Changeset 10073
- Timestamp:
- 01/04/11 10:03:04 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib
- Files:
-
- 25 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd
r9912 r10073 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 0:49:24 30.08.20105 -- at - 14:00:25 01.10.2010 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 41 41 -- Created: 42 42 -- by - dneise.UNKNOWN (E5B-LABOR6) 43 -- at - 1 0:49:25 30.08.201043 -- at - 14:00:25 01.10.2010 44 44 -- 45 45 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd
r9912 r10073 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 09:42:04 30.07.20105 -- at - 17:00:23 03.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 23 23 config_data_valid : OUT std_logic; 24 24 config_ready : OUT std_logic; 25 -- -- 26 config_rw_ack : OUT std_logic := '0'; 27 -- -- 28 config_rw_ready : OUT std_logic := '0'; 25 29 config_started : OUT std_logic := '0'; 26 30 dac_array : OUT dac_array_type; 27 drs_address : OUT std_logic_vector (3 DOWNTO 0);28 drs_address_mode : OUT std_logic;29 31 roi_array : OUT roi_array_type; 30 32 config_data : INOUT std_logic_vector (15 DOWNTO 0) … … 40 42 -- Created: 41 43 -- by - dneise.UNKNOWN (E5B-LABOR6) 42 -- at - 09:42:04 30.07.201044 -- at - 17:00:23 03.01.2011 43 45 -- 44 46 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 91 93 config_data_valid : OUT std_logic := '0'; 92 94 config_busy : OUT std_logic := '0'; 95 -- -- 96 config_rw_ack : OUT std_logic := '0'; 97 -- -- 98 config_rw_ready : OUT std_logic := '0'; 99 -- -- 93 100 ram_addr : OUT std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0); 94 101 ram_data_in : OUT std_logic_vector (15 DOWNTO 0); 95 102 ram_write_en : OUT std_logic_vector (0 DOWNTO 0); 96 103 dac_array : OUT dac_array_type ; 97 roi_array : OUT roi_array_type ; 98 drs_address : OUT std_logic_vector (3 DOWNTO 0); 99 drs_address_mode : OUT std_logic 104 roi_array : OUT roi_array_type 100 105 ); 101 106 END COMPONENT; … … 137 142 config_data_valid => config_data_valid, 138 143 config_busy => config_busy, 144 config_rw_ack => config_rw_ack, 145 config_rw_ready => config_rw_ready, 139 146 ram_addr => ram_addr, 140 147 ram_data_in => ram_data_in, 141 148 ram_write_en => ram_wren, 142 149 dac_array => dac_array, 143 roi_array => roi_array, 144 drs_address => drs_address, 145 drs_address_mode => drs_address_mode 150 roi_array => roi_array 146 151 ); 147 152 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10072 r10073 142 142 when CONFIG4 => 143 143 drs_channel_id <= DRS_WRITE_SHIFT_REG; 144 drs_srin_data <= "1 0101010";144 drs_srin_data <= "11111111"; 145 145 drs_srin_write_8b <= '1'; 146 146 if (drs_srin_write_ack = '1') then -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak
r10072 r10073 25 25 ); 26 26 port( 27 -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 28 27 29 clk : in std_logic; 28 30 data_out : out std_logic_vector (63 downto 0); … … 32 34 ram_write_ea : in std_logic; 33 35 ram_write_ready : out std_logic := '0'; 36 -- -- 37 ram_write_ready_ack : IN std_logic; 38 -- -- 34 39 config_start_mm, config_start_cm, config_start_spi : out std_logic := '0'; 35 40 config_ready_mm, config_ready_cm, config_ready_spi : in std_logic; … … 45 50 trigger_id : in std_logic_vector (47 downto 0); 46 51 trigger : in std_logic; 47 s_trigger : in std_logic;52 -- s_trigger : in std_logic; 48 53 new_config : in std_logic; 49 54 config_started : out std_logic := '0'; … … 55 60 drs_dwrite : out std_logic := '1'; 56 61 drs_clk_en, drs_read_s_cell : out std_logic := '0'; 62 63 drs_srin_write_8b : out std_logic := '0'; 64 drs_srin_write_ack : in std_logic; 65 drs_srin_data : out std_logic_vector (7 downto 0) := (others => '0'); 66 drs_srin_write_ready : in std_logic; 67 57 68 drs_read_s_cell_ready : in std_logic; 58 69 drs_s_cell_array : in drs_s_cell_array_type … … 62 73 architecture Behavioral of data_generator is 63 74 64 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,75 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES, 65 76 WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT, 66 77 WRITE_END_FLAG, WRITE_DATA_STOP, … … 76 87 signal adc_wait_cnt : integer range 0 to 7 := 0; 77 88 78 signal trigger_flag : std_logic := '0'; 79 89 signal trigger_flag :std_logic := '0'; 90 signal ram_write_ea_flag : std_logic := '0'; 91 signal new_config_int : std_logic := '0'; 92 93 signal roi_max_int : roi_max_type; 80 94 81 95 begin … … 95 109 when CONFIG => 96 110 config_started <= '1'; 97 -- config config manager 98 config_start_cm <= '1'; 99 if (config_started_cm = '1') then 100 state_generate <= CONFIG1; 111 if (new_config = '0') then 112 config_started <= '0'; 113 -- config config manager 114 config_start_cm <= '1'; 115 if (config_started_cm = '1') then 116 config_start_cm <= '0'; 117 state_generate <= CONFIG1; 118 end if; 101 119 end if; 102 120 when CONFIG1 => 103 121 if (config_ready_cm = '1') then 104 config_started <= '0';105 config_start_cm <= '0';106 122 config_start_mm <= '1'; 107 123 end if; 108 124 if (config_started_mm = '1') then 125 config_start_mm <= '0'; 109 126 state_generate <= CONFIG2; 110 127 end if; 111 128 when CONFIG2 => 112 129 if (config_ready_mm = '1') then 113 config_start_mm <= '0';114 130 config_start_spi <= '1'; 115 131 end if; 116 132 if (config_started_spi = '1') then 133 config_start_spi <= '0'; 117 134 state_generate <= CONFIG3; 118 135 end if; 119 136 when CONFIG3 => 120 137 if (config_ready_spi = '1') then 121 config_start_spi <= '0'; 138 state_generate <= CONFIG4; 139 -- state_generate <= WRITE_DATA_IDLE; 140 end if; 141 -- configure DRS 142 when CONFIG4 => 143 drs_channel_id <= DRS_WRITE_SHIFT_REG; 144 drs_srin_data <= "10101010"; 145 drs_srin_write_8b <= '1'; 146 if (drs_srin_write_ack = '1') then 147 drs_srin_write_8b <= '0'; 148 state_generate <= CONFIG5; 149 end if; 150 when CONFIG5 => 151 if (drs_srin_write_ready = '1') then 152 roi_max_int <= roi_max; 122 153 state_generate <= WRITE_DATA_IDLE; 123 154 end if; 155 -- end configure DRS 124 156 125 157 when WRITE_DATA_IDLE => … … 127 159 state_generate <= CONFIG; 128 160 end if; 129 if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then 161 -- if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then 162 if (ram_write_ea = '1' and trigger_flag = '1') then 130 163 -- stop drs, dwrite low 131 164 drs_dwrite <= '0'; … … 248 281 when WRITE_EXTERNAL_TRIGGER => -- external trigger ID 249 282 addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH); 250 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); 283 -- data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); 284 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); 251 285 state_generate <= WRITE_INTERNAL_TRIGGER; 252 286 when WRITE_INTERNAL_TRIGGER => -- internal trigger ID … … 263 297 state_generate <= WRITE_DATA_END_WAIT; 264 298 when WRITE_DATA_END_WAIT => 265 state_generate <= WRITE_DATA_STOP; 299 -- -- 300 if (ram_write_ready_ack = '1') then 301 state_generate <= WRITE_DATA_STOP; 302 -- -- 303 ram_write_ready <= '0'; 304 -- -- 305 end if; 306 -- -- 266 307 when WRITE_DATA_STOP => 267 drs_dwrite <= '1'; 268 data_cntr <= 0; 269 addr_cntr <= 0; 270 channel_id <= 0; 271 ram_write_ready <= '0'; 272 state_generate <= WRITE_DATA_IDLE; 273 308 -- -- 309 if (ram_write_ready_ack = '0') then 310 -- -- 311 drs_dwrite <= '1'; 312 data_cntr <= 0; 313 addr_cntr <= 0; 314 channel_id <= 0; 315 state_generate <= WRITE_DATA_IDLE; 316 -- -- 317 end if; 318 -- -- 274 319 when others => 275 320 null; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf
r9912 r10073 25 25 NET RS485_C_DE LOC = C5 | IOSTANDARD=LVCMOS33; #ok 26 26 NET RS485_C_RE LOC = C6 | IOSTANDARD=LVCMOS33; #ok 27 #NET RS485_C_DO LOC = C7 | IOSTANDARD=LVCMOS33; #ok28 #NET RS485_C_DI LOC = C8 | IOSTANDARD=LVCMOS33; #ok27 NET RS485_C_DO LOC = C7 | IOSTANDARD=LVCMOS33; #ok 28 NET RS485_C_DI LOC = C8 | IOSTANDARD=LVCMOS33; #ok 29 29 30 30 NET RS485_E_DE LOC = D20 | IOSTANDARD=LVCMOS33; #ok 31 31 NET RS485_E_RE LOC = D21 | IOSTANDARD=LVCMOS33; #ok 32 #NET RS485_E_DO LOC = D22 | IOSTANDARD=LVCMOS33; #ok33 #NET RS485_E_DI LOC = D23 | IOSTANDARD=LVCMOS33; #ok32 NET RS485_E_DO LOC = D22 | IOSTANDARD=LVCMOS33; #ok 33 NET RS485_E_DI LOC = D23 | IOSTANDARD=LVCMOS33; #ok 34 34 35 35 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r9912 r10073 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 0:49:29 30.08.20105 -- at - 17:00:27 03.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 23 23 D3_SROUT : IN std_logic; 24 24 D_PLLLCK : IN std_logic_vector (3 DOWNTO 0); 25 RS485_C_DI : IN std_logic; 26 RS485_E_DI : IN std_logic; 27 RS485_E_DO : IN std_logic; 25 28 TRG : IN STD_LOGIC; 26 29 W_INT : IN std_logic; … … 44 47 OE_ADC : OUT STD_LOGIC; 45 48 RS485_C_DE : OUT std_logic; 49 RS485_C_DO : OUT std_logic; 46 50 RS485_C_RE : OUT std_logic; 47 51 RS485_E_DE : OUT std_logic; 48 52 RS485_E_RE : OUT std_logic; 49 53 RSRLOAD : OUT std_logic := '0'; 50 SRIN : OUT std_logic ;54 SRIN : OUT std_logic := '0'; 51 55 S_CLK : OUT std_logic; 52 56 T0_CS : OUT std_logic; … … 73 77 -- Created: 74 78 -- by - dneise.UNKNOWN (E5B-LABOR6) 75 -- at - 1 0:49:29 30.08.201079 -- at - 17:00:27 03.01.2011 76 80 -- 77 81 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 152 156 RSRLOAD : OUT std_logic := '0'; 153 157 SRCLK : OUT std_logic := '0'; 158 SRIN_out : OUT std_logic := '0'; 154 159 adc_clk_en : OUT std_logic := '0'; 155 160 adc_oeb : OUT std_logic := '1'; … … 220 225 -- MISC 6 221 226 TRG_V <= '0'; 222 RS485_C_RE <= ' 1';227 RS485_C_RE <= '0'; 223 228 RS485_C_DE <= '0'; 224 RS485_E_RE <= '1'; 229 RS485_C_DO <= RS485_C_DI; 230 231 RS485_E_RE <= '0'; 225 232 RS485_E_DE <= '0'; 233 --RS485_E_DO <= RS485_E_DI; 226 234 227 235 -- DENABLE <= '0'; -- domino wave stopped 228 236 -- DENABLE <= '1'; -- domino wave running 229 237 230 SRIN <= '1';238 231 239 EE_CS <= '1'; 232 240 -- LEDs are low active … … 305 313 RSRLOAD => RSRLOAD, 306 314 SRCLK => SRCLK, 315 SRIN_out => SRIN, 307 316 adc_clk_en => adc_clk_en, 308 317 adc_oeb => OE_ADC, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r9912 r10073 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 0:49:27 30.08.20105 -- at - 17:00:23 03.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 44 44 RSRLOAD : OUT std_logic := '0'; 45 45 SRCLK : OUT std_logic := '0'; 46 SRIN_out : OUT std_logic := '0'; 46 47 adc_clk_en : OUT std_logic := '0'; 47 48 adc_oeb : OUT std_logic := '1'; … … 76 77 -- Created: 77 78 -- by - dneise.UNKNOWN (E5B-LABOR6) 78 -- at - 1 0:49:28 30.08.201079 -- at - 17:00:24 03.01.2011 79 80 -- 80 81 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 113 114 SIGNAL config_ready_cm : std_logic; 114 115 SIGNAL config_ready_spi : std_logic; 116 -- -- 117 SIGNAL config_rw_ack : std_logic := '0'; 118 -- -- 119 SIGNAL config_rw_ready : std_logic := '0'; 115 120 SIGNAL config_start : std_logic := '0'; 116 121 SIGNAL config_start_cm : std_logic; … … 130 135 SIGNAL drs_read_s_cell_ready : std_logic; 131 136 SIGNAL drs_s_cell_array : drs_s_cell_array_type; 137 SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0'); 132 138 SIGNAL dwrite : std_logic := '1'; 133 139 SIGNAL dwrite_enable : std_logic := '1'; … … 142 148 SIGNAL ram_write_ea : std_logic; 143 149 SIGNAL ram_write_ready : std_logic := '0'; 150 -- -- 151 SIGNAL ram_write_ready_ack : std_logic := '0'; 144 152 SIGNAL roi_array : roi_array_type; 145 153 SIGNAL roi_max : roi_max_type; 146 SIGNAL s_trigger : std_logic := '0';154 SIGNAL s_trigger : std_logic; 147 155 SIGNAL sclk1 : std_logic; 148 156 SIGNAL sclk_enable : std_logic; … … 150 158 SIGNAL sensor_ready : std_logic; 151 159 SIGNAL srclk_enable : std_logic := '0'; 160 SIGNAL srin_write_ack : std_logic := '0'; 161 SIGNAL srin_write_ready : std_logic := '0'; 162 SIGNAL start_srin_write_8b : std_logic; 152 163 SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0); 164 SIGNAL trigger_out : std_logic; 153 165 SIGNAL wiz_ack : std_logic; 154 166 SIGNAL wiz_busy : std_logic; … … 207 219 config_data_valid : OUT std_logic ; 208 220 config_ready : OUT std_logic ; 221 -- -- 222 config_rw_ack : OUT std_logic := '0'; 223 -- -- 224 config_rw_ready : OUT std_logic := '0'; 209 225 config_started : OUT std_logic := '0'; 210 226 dac_array : OUT dac_array_type ; 211 drs_address : OUT std_logic_vector (3 DOWNTO 0);212 drs_address_mode : OUT std_logic ;213 227 roi_array : OUT roi_array_type ; 214 228 config_data : INOUT std_logic_vector (15 DOWNTO 0) … … 231 245 ); 232 246 PORT ( 247 -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 233 248 clk : IN std_logic ; 234 249 data_out : OUT std_logic_vector (63 DOWNTO 0); … … 238 253 ram_write_ea : IN std_logic ; 239 254 ram_write_ready : OUT std_logic := '0'; 255 -- -- 256 ram_write_ready_ack : IN std_logic ; 257 -- -- 240 258 config_start_mm : OUT std_logic := '0'; 259 -- -- 241 260 config_start_cm : OUT std_logic := '0'; 261 -- -- 242 262 config_start_spi : OUT std_logic := '0'; 243 263 config_ready_mm : IN std_logic ; … … 257 277 trigger_id : IN std_logic_vector (47 DOWNTO 0); 258 278 trigger : IN std_logic ; 259 s_trigger : IN std_logic;279 -- s_trigger : in std_logic; 260 280 new_config : IN std_logic ; 261 281 config_started : OUT std_logic := '0'; … … 268 288 drs_clk_en : OUT std_logic := '0'; 269 289 drs_read_s_cell : OUT std_logic := '0'; 290 drs_srin_write_8b : OUT std_logic := '0'; 291 drs_srin_write_ack : IN std_logic ; 292 drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 293 drs_srin_write_ready : IN std_logic ; 270 294 drs_read_s_cell_ready : IN std_logic ; 271 295 drs_s_cell_array : IN drs_s_cell_array_type … … 279 303 SROUT_in_2 : IN std_logic; 280 304 SROUT_in_3 : IN std_logic; 305 srin_data : IN std_logic_vector (7 DOWNTO 0); 281 306 start_endless_mode : IN std_logic; 282 307 start_read_stop_pos_mode : IN std_logic; 308 start_srin_write_8b : IN std_logic; 283 309 RSRLOAD : OUT std_logic := '0'; 284 310 SRCLK : OUT std_logic := '0'; 311 SRIN_out : OUT std_logic := '0'; 312 srin_write_ack : OUT std_logic := '0'; 313 srin_write_ready : OUT std_logic := '0'; 285 314 stop_pos : OUT drs_s_cell_array_type; 286 315 stop_pos_valid : OUT std_logic := '0' … … 296 325 config_start : IN std_logic ; 297 326 ram_write_ready : IN std_logic ; 327 -- -- 328 ram_write_ready_ack : OUT std_logic := '0'; 329 -- -- 298 330 roi_array : IN roi_array_type ; 299 331 ram_write_ea : OUT std_logic := '0'; … … 367 399 config_wr_en : OUT std_logic := '0'; 368 400 config_rd_en : OUT std_logic := '0'; 401 -- -- 402 config_rw_ack : IN std_logic ; 403 -- -- 404 config_rw_ready : IN std_logic ; 405 -- -- 369 406 config_busy : IN std_logic ; 370 407 denable : OUT std_logic := '0'; -- default domino wave off … … 429 466 END CASE; 430 467 END PROCESS u_0combo_proc; 468 469 -- ModuleWare code(v1.9) for instance 'U_9' of 'or' 470 trigger_out <= s_trigger OR trigger; 431 471 432 472 -- Instance port mappings. … … 468 508 config_data_valid => config_data_valid, 469 509 config_ready => config_ready_cm, 510 config_rw_ack => config_rw_ack, 511 config_rw_ready => config_rw_ready, 470 512 config_started => config_started_cu, 471 513 dac_array => dac_array, 472 drs_address => drs_address,473 drs_address_mode => drs_address_mode,474 514 roi_array => roi_array, 475 515 config_data => config_data … … 497 537 ram_write_ea => ram_write_ea, 498 538 ram_write_ready => ram_write_ready, 539 ram_write_ready_ack => ram_write_ready_ack, 499 540 config_start_mm => config_start, 500 541 config_start_cm => config_start_cm, … … 515 556 crate_id => crate_id, 516 557 trigger_id => trigger_id, 517 trigger => trigger, 518 s_trigger => s_trigger, 558 trigger => trigger_out, 519 559 new_config => new_config, 520 560 config_started => config_started, … … 527 567 drs_clk_en => drs_clk_en, 528 568 drs_read_s_cell => drs_read_s_cell, 569 drs_srin_write_8b => start_srin_write_8b, 570 drs_srin_write_ack => srin_write_ack, 571 drs_srin_data => drs_srin_data, 572 drs_srin_write_ready => srin_write_ready, 529 573 drs_read_s_cell_ready => drs_read_s_cell_ready, 530 574 drs_s_cell_array => drs_s_cell_array … … 541 585 stop_pos => drs_s_cell_array, 542 586 stop_pos_valid => drs_read_s_cell_ready, 587 start_srin_write_8b => start_srin_write_8b, 588 srin_write_ready => srin_write_ready, 589 srin_write_ack => srin_write_ack, 590 srin_data => drs_srin_data, 591 SRIN_out => SRIN_out, 543 592 RSRLOAD => RSRLOAD, 544 593 SRCLK => SRCLK1 … … 553 602 config_start => config_start, 554 603 ram_write_ready => ram_write_ready, 604 ram_write_ready_ack => ram_write_ready_ack, 555 605 roi_array => roi_array, 556 606 ram_write_ea => ram_write_ea, … … 587 637 PORT MAP ( 588 638 trigger_id => trigger_id, 589 trigger => trigger ,639 trigger => trigger_out, 590 640 clk => CLK_25_PS_internal 591 641 ); … … 621 671 config_wr_en => config_wr_en, 622 672 config_rd_en => config_rd_en, 673 config_rw_ack => config_rw_ack, 674 config_rw_ready => config_rw_ready, 623 675 config_busy => config_busy, 624 676 denable => denable, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd
r9912 r10073 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 09:42:04 30.07.20105 -- at - 14:00:24 01.10.2010 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 38 38 -- Created: 39 39 -- by - dneise.UNKNOWN (E5B-LABOR6) 40 -- at - 09:42:04 30.07.201040 -- at - 14:00:25 01.10.2010 41 41 -- 42 42 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/control_unit_struct.xrf
r9912 r10073 31 31 DESIGN control_unit 32 32 VIEW symbol.sb 33 GRAPHIC 350,0 24034 DESIGN control_unit 35 VIEW symbol.sb 36 GRAPHIC 165,0 25037 DESIGN control_unit 38 VIEW symbol.sb 39 GRAPHIC 521,0 26040 DESIGN control_unit 41 VIEW symbol.sb 42 GRAPHIC 526,0 27043 DESIGN control_unit 44 VIEW symbol.sb 45 GRAPHIC 155,0 28046 DESIGN control_unit 47 VIEW symbol.sb 48 GRAPHIC 150,0 29049 DESIGN control_unit 50 VIEW symbol.sb 51 GRAPHIC 1,0 3 2052 DESIGN control_unit 53 VIEW symbol.sb 54 GRAPHIC 1,0 3 3055 DESIGN control_unit 56 VIEW struct.bd 57 NO_GRAPHIC 3 658 DESIGN control_unit 59 VIEW struct.bd 60 GRAPHIC 41,0 4 5061 DESIGN control_unit 62 VIEW struct.bd 63 NO_GRAPHIC 5 064 DESIGN control_unit 65 VIEW struct.bd 66 GRAPHIC 0,0 5 3267 DESIGN control_unit 68 VIEW struct.bd 69 GRAPHIC 345,0 58070 DESIGN control_unit 71 VIEW struct.bd 72 GRAPHIC 333,0 59073 DESIGN control_unit 74 VIEW struct.bd 75 GRAPHIC 349,0 6 0076 DESIGN control_unit 77 VIEW struct.bd 78 GRAPHIC 329,0 6 1079 DESIGN control_unit 80 VIEW struct.bd 81 NO_GRAPHIC 6 282 DESIGN control_unit 83 VIEW struct.bd 84 NO_GRAPHIC 6 333 GRAPHIC 558,0 25 0 34 DESIGN control_unit 35 VIEW symbol.sb 36 GRAPHIC 564,0 27 0 37 DESIGN control_unit 38 VIEW symbol.sb 39 GRAPHIC 350,0 28 0 40 DESIGN control_unit 41 VIEW symbol.sb 42 GRAPHIC 165,0 29 0 43 DESIGN control_unit 44 VIEW symbol.sb 45 GRAPHIC 155,0 30 0 46 DESIGN control_unit 47 VIEW symbol.sb 48 GRAPHIC 150,0 31 0 49 DESIGN control_unit 50 VIEW symbol.sb 51 GRAPHIC 1,0 34 0 52 DESIGN control_unit 53 VIEW symbol.sb 54 GRAPHIC 1,0 35 0 55 DESIGN control_unit 56 VIEW struct.bd 57 NO_GRAPHIC 38 58 DESIGN control_unit 59 VIEW struct.bd 60 GRAPHIC 41,0 47 0 61 DESIGN control_unit 62 VIEW struct.bd 63 NO_GRAPHIC 52 64 DESIGN control_unit 65 VIEW struct.bd 66 GRAPHIC 0,0 55 2 67 DESIGN control_unit 68 VIEW struct.bd 69 GRAPHIC 345,0 60 0 70 DESIGN control_unit 71 VIEW struct.bd 72 GRAPHIC 333,0 61 0 73 DESIGN control_unit 74 VIEW struct.bd 75 GRAPHIC 349,0 62 0 76 DESIGN control_unit 77 VIEW struct.bd 78 GRAPHIC 329,0 63 0 79 DESIGN control_unit 80 VIEW struct.bd 81 NO_GRAPHIC 64 82 DESIGN control_unit 83 VIEW struct.bd 84 NO_GRAPHIC 65 85 85 LIBRARY FACT_FAD_lib 86 86 DESIGN control@r@a@m_16bit_x256 87 87 VIEW control@r@a@m_16bit_x256_a 88 GRAPHIC 993,0 6 5089 DESIGN control@r@a@m_16bit_x256 90 VIEW control@r@a@m_16bit_x256_a 91 GRAPHIC 48,0 6 7092 DESIGN control@r@a@m_16bit_x256 93 VIEW control@r@a@m_16bit_x256_a 94 GRAPHIC 53,0 68095 DESIGN control@r@a@m_16bit_x256 96 VIEW control@r@a@m_16bit_x256_a 97 GRAPHIC 58,0 69098 DESIGN control@r@a@m_16bit_x256 99 VIEW control@r@a@m_16bit_x256_a 100 GRAPHIC 63,0 7 00101 DESIGN control@r@a@m_16bit_x256 102 VIEW control@r@a@m_16bit_x256_a 103 GRAPHIC 68,0 7 10104 DESIGN control_unit 105 VIEW struct.bd 106 GRAPHIC 960,0 7 40107 DESIGN control_manager 108 VIEW symbol.sb 109 GRAPHIC 14,0 7 51110 DESIGN control_manager 111 VIEW beha 112 GRAPHIC 48,0 8 10113 DESIGN control_manager 114 VIEW beha 115 GRAPHIC 310,0 8 20116 DESIGN control_manager 117 VIEW beha 118 GRAPHIC 58,0 8 30119 DESIGN control_manager 120 VIEW beha 121 GRAPHIC 492,0 8 40122 DESIGN control_manager 123 VIEW beha 124 GRAPHIC 63,0 8 50125 DESIGN control_manager 126 VIEW beha 127 GRAPHIC 68,0 8 60128 DESIGN control_manager 129 VIEW beha 130 GRAPHIC 73,0 8 70131 DESIGN control_manager 132 VIEW beha 133 GRAPHIC 78,0 880134 DESIGN control_manager 135 VIEW beha 136 GRAPHIC 83,0 890137 DESIGN control_manager 138 VIEW beha 139 GRAPHIC 88,0 9 00140 DESIGN control_manager 141 VIEW beha 142 GRAPHIC 93,0 9 10143 DESIGN control_manager 144 VIEW beha 145 GRAPHIC 346,0 920146 DESIGN control_manager 147 VIEW beha 148 GRAPHIC 263,0 930149 DESIGN control_manager 150 VIEW beha 151 GRAPHIC 268,0 940152 DESIGN control_manager 153 VIEW beha 154 GRAPHIC 118,0 950155 DESIGN control_manager 156 VIEW beha 157 GRAPHIC 123,0 960158 DESIGN control_manager 159 VIEW beha 160 GRAPHIC 528,0 970161 DESIGN control_manager 162 VIEW beha 163 GRAPHIC 533,0 98088 GRAPHIC 993,0 67 0 89 DESIGN control@r@a@m_16bit_x256 90 VIEW control@r@a@m_16bit_x256_a 91 GRAPHIC 48,0 69 0 92 DESIGN control@r@a@m_16bit_x256 93 VIEW control@r@a@m_16bit_x256_a 94 GRAPHIC 53,0 70 0 95 DESIGN control@r@a@m_16bit_x256 96 VIEW control@r@a@m_16bit_x256_a 97 GRAPHIC 58,0 71 0 98 DESIGN control@r@a@m_16bit_x256 99 VIEW control@r@a@m_16bit_x256_a 100 GRAPHIC 63,0 72 0 101 DESIGN control@r@a@m_16bit_x256 102 VIEW control@r@a@m_16bit_x256_a 103 GRAPHIC 68,0 73 0 104 DESIGN control_unit 105 VIEW struct.bd 106 GRAPHIC 960,0 76 0 107 DESIGN control_manager 108 VIEW symbol.sb 109 GRAPHIC 14,0 77 1 110 DESIGN control_manager 111 VIEW beha 112 GRAPHIC 48,0 83 0 113 DESIGN control_manager 114 VIEW beha 115 GRAPHIC 310,0 84 0 116 DESIGN control_manager 117 VIEW beha 118 GRAPHIC 58,0 85 0 119 DESIGN control_manager 120 VIEW beha 121 GRAPHIC 492,0 86 0 122 DESIGN control_manager 123 VIEW beha 124 GRAPHIC 63,0 87 0 125 DESIGN control_manager 126 VIEW beha 127 GRAPHIC 68,0 88 0 128 DESIGN control_manager 129 VIEW beha 130 GRAPHIC 73,0 89 0 131 DESIGN control_manager 132 VIEW beha 133 GRAPHIC 78,0 90 0 134 DESIGN control_manager 135 VIEW beha 136 GRAPHIC 83,0 91 0 137 DESIGN control_manager 138 VIEW beha 139 GRAPHIC 88,0 92 0 140 DESIGN control_manager 141 VIEW beha 142 GRAPHIC 93,0 93 0 143 DESIGN control_manager 144 VIEW beha 145 GRAPHIC 571,0 94 0 146 DESIGN control_manager 147 VIEW beha 148 GRAPHIC 576,0 96 0 149 DESIGN control_manager 150 VIEW beha 151 GRAPHIC 346,0 98 0 152 DESIGN control_manager 153 VIEW beha 154 GRAPHIC 263,0 100 0 155 DESIGN control_manager 156 VIEW beha 157 GRAPHIC 268,0 101 0 158 DESIGN control_manager 159 VIEW beha 160 GRAPHIC 118,0 102 0 161 DESIGN control_manager 162 VIEW beha 163 GRAPHIC 123,0 103 0 164 164 LIBRARY FACT_FAD_lib 165 165 DESIGN control_unit 166 166 VIEW struct.bd 167 NO_GRAPHIC 10 1168 DESIGN control_unit 169 VIEW struct.bd 170 GRAPHIC 993,0 10 40171 DESIGN control_unit 172 VIEW struct.bd 173 GRAPHIC 960,0 1 050174 DESIGN control_unit 175 VIEW struct.bd 176 NO_GRAPHIC 1 08177 DESIGN control_unit 178 VIEW struct.bd 179 NO_GRAPHIC 11 0180 DESIGN control_unit 181 VIEW struct.bd 182 GRAPHIC 993,0 11 20183 DESIGN control_unit 184 VIEW struct.bd 185 GRAPHIC 279,0 11 40186 DESIGN control_unit 187 VIEW struct.bd 188 GRAPHIC 237,0 1 150189 DESIGN control_unit 190 VIEW struct.bd 191 GRAPHIC 285,0 1 160192 DESIGN control_unit 193 VIEW struct.bd 194 GRAPHIC 233,0 1 170195 DESIGN control_unit 196 VIEW struct.bd 197 GRAPHIC 301,0 1 180198 DESIGN control_unit 199 VIEW struct.bd 200 GRAPHIC 960,0 12 00201 DESIGN control_unit 202 VIEW struct.bd 203 GRAPHIC 967,0 12 11204 DESIGN control_unit 205 VIEW struct.bd 206 GRAPHIC 241,0 1 270207 DESIGN control_unit 208 VIEW struct.bd 209 GRAPHIC 301,0 1 280210 DESIGN control_unit 211 VIEW struct.bd 212 GRAPHIC 321,0 1 290213 DESIGN control_unit 214 VIEW struct.bd 215 GRAPHIC 1084,0 13 00216 DESIGN control_unit 217 VIEW struct.bd 218 GRAPHIC 289,0 13 10219 DESIGN control_unit 220 VIEW struct.bd 221 GRAPHIC 267,0 13 20222 DESIGN control_unit 223 VIEW struct.bd 224 GRAPHIC 227,0 13 30225 DESIGN control_unit 226 VIEW struct.bd 227 GRAPHIC 295,0 13 40228 DESIGN control_unit 229 VIEW struct.bd 230 GRAPHIC 311,0 1 350231 DESIGN control_unit 232 VIEW struct.bd 233 GRAPHIC 255,0 1 360234 DESIGN control_unit 235 VIEW struct.bd 236 GRAPHIC 261,0 1 370237 DESIGN control_unit 238 VIEW struct.bd 239 GRAPHIC 285,0 1380240 DESIGN control_unit 241 VIEW struct.bd 242 GRAPHIC 237,0 1390243 DESIGN control_unit 244 VIEW struct.bd 245 GRAPHIC 2 33,0 1400246 DESIGN control_unit 247 VIEW struct.bd 248 GRAPHIC 305,0 1410249 DESIGN control_unit 250 VIEW struct.bd 251 GRAPHIC 2 73,0 1420252 DESIGN control_unit 253 VIEW struct.bd 254 GRAPHIC 1208,0 1430255 DESIGN control_unit 256 VIEW struct.bd 257 GRAPHIC 1222,0 1440258 DESIGN control_unit 259 VIEW struct.bd 260 NO_GRAPHIC 1 47167 NO_GRAPHIC 106 168 DESIGN control_unit 169 VIEW struct.bd 170 GRAPHIC 993,0 109 0 171 DESIGN control_unit 172 VIEW struct.bd 173 GRAPHIC 960,0 110 0 174 DESIGN control_unit 175 VIEW struct.bd 176 NO_GRAPHIC 113 177 DESIGN control_unit 178 VIEW struct.bd 179 NO_GRAPHIC 115 180 DESIGN control_unit 181 VIEW struct.bd 182 GRAPHIC 993,0 117 0 183 DESIGN control_unit 184 VIEW struct.bd 185 GRAPHIC 279,0 119 0 186 DESIGN control_unit 187 VIEW struct.bd 188 GRAPHIC 237,0 120 0 189 DESIGN control_unit 190 VIEW struct.bd 191 GRAPHIC 285,0 121 0 192 DESIGN control_unit 193 VIEW struct.bd 194 GRAPHIC 233,0 122 0 195 DESIGN control_unit 196 VIEW struct.bd 197 GRAPHIC 301,0 123 0 198 DESIGN control_unit 199 VIEW struct.bd 200 GRAPHIC 960,0 125 0 201 DESIGN control_unit 202 VIEW struct.bd 203 GRAPHIC 967,0 126 1 204 DESIGN control_unit 205 VIEW struct.bd 206 GRAPHIC 241,0 132 0 207 DESIGN control_unit 208 VIEW struct.bd 209 GRAPHIC 301,0 133 0 210 DESIGN control_unit 211 VIEW struct.bd 212 GRAPHIC 321,0 134 0 213 DESIGN control_unit 214 VIEW struct.bd 215 GRAPHIC 1084,0 135 0 216 DESIGN control_unit 217 VIEW struct.bd 218 GRAPHIC 289,0 136 0 219 DESIGN control_unit 220 VIEW struct.bd 221 GRAPHIC 267,0 137 0 222 DESIGN control_unit 223 VIEW struct.bd 224 GRAPHIC 227,0 138 0 225 DESIGN control_unit 226 VIEW struct.bd 227 GRAPHIC 295,0 139 0 228 DESIGN control_unit 229 VIEW struct.bd 230 GRAPHIC 311,0 140 0 231 DESIGN control_unit 232 VIEW struct.bd 233 GRAPHIC 255,0 141 0 234 DESIGN control_unit 235 VIEW struct.bd 236 GRAPHIC 261,0 142 0 237 DESIGN control_unit 238 VIEW struct.bd 239 GRAPHIC 1281,0 143 0 240 DESIGN control_unit 241 VIEW struct.bd 242 GRAPHIC 1295,0 144 0 243 DESIGN control_unit 244 VIEW struct.bd 245 GRAPHIC 285,0 145 0 246 DESIGN control_unit 247 VIEW struct.bd 248 GRAPHIC 237,0 146 0 249 DESIGN control_unit 250 VIEW struct.bd 251 GRAPHIC 233,0 147 0 252 DESIGN control_unit 253 VIEW struct.bd 254 GRAPHIC 305,0 148 0 255 DESIGN control_unit 256 VIEW struct.bd 257 GRAPHIC 273,0 149 0 258 DESIGN control_unit 259 VIEW struct.bd 260 NO_GRAPHIC 152 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf
r9912 r10073 37 37 DESIGN @f@a@d_@board 38 38 VIEW symbol.sb 39 GRAPHIC 1121,0 24 0 40 DESIGN @f@a@d_@board 41 VIEW symbol.sb 42 GRAPHIC 1421,0 25 0 43 DESIGN @f@a@d_@board 44 VIEW symbol.sb 45 GRAPHIC 1116,0 26 0 46 DESIGN @f@a@d_@board 47 VIEW symbol.sb 48 GRAPHIC 3456,0 27 0 49 DESIGN @f@a@d_@board 50 VIEW symbol.sb 51 GRAPHIC 3026,0 28 0 52 DESIGN @f@a@d_@board 53 VIEW symbol.sb 54 GRAPHIC 1126,0 29 0 55 DESIGN @f@a@d_@board 56 VIEW symbol.sb 57 GRAPHIC 1227,0 30 0 58 DESIGN @f@a@d_@board 59 VIEW symbol.sb 60 GRAPHIC 1232,0 31 0 61 DESIGN @f@a@d_@board 62 VIEW symbol.sb 63 GRAPHIC 1237,0 32 0 64 DESIGN @f@a@d_@board 65 VIEW symbol.sb 66 GRAPHIC 1242,0 33 0 67 DESIGN @f@a@d_@board 68 VIEW symbol.sb 69 GRAPHIC 1363,0 34 0 70 DESIGN @f@a@d_@board 71 VIEW symbol.sb 72 GRAPHIC 1701,0 35 0 73 DESIGN @f@a@d_@board 74 VIEW symbol.sb 75 GRAPHIC 1308,0 36 0 76 DESIGN @f@a@d_@board 77 VIEW symbol.sb 78 GRAPHIC 1302,0 37 0 79 DESIGN @f@a@d_@board 80 VIEW symbol.sb 81 GRAPHIC 2068,0 38 0 82 DESIGN @f@a@d_@board 83 VIEW symbol.sb 84 GRAPHIC 2949,0 39 0 85 DESIGN @f@a@d_@board 86 VIEW symbol.sb 87 GRAPHIC 1711,0 40 0 88 DESIGN @f@a@d_@board 89 VIEW symbol.sb 90 GRAPHIC 2375,0 41 0 91 DESIGN @f@a@d_@board 92 VIEW symbol.sb 93 GRAPHIC 1620,0 42 0 94 DESIGN @f@a@d_@board 95 VIEW symbol.sb 96 GRAPHIC 1166,0 43 0 97 DESIGN @f@a@d_@board 98 VIEW symbol.sb 99 GRAPHIC 1686,0 44 0 100 DESIGN @f@a@d_@board 101 VIEW symbol.sb 102 GRAPHIC 1681,0 45 0 103 DESIGN @f@a@d_@board 104 VIEW symbol.sb 105 GRAPHIC 1696,0 46 0 106 DESIGN @f@a@d_@board 107 VIEW symbol.sb 108 GRAPHIC 1691,0 47 0 109 DESIGN @f@a@d_@board 110 VIEW symbol.sb 111 GRAPHIC 693,0 48 0 112 DESIGN @f@a@d_@board 113 VIEW symbol.sb 114 GRAPHIC 1706,0 49 0 115 DESIGN @f@a@d_@board 116 VIEW symbol.sb 117 GRAPHIC 1388,0 50 0 118 DESIGN @f@a@d_@board 119 VIEW symbol.sb 120 GRAPHIC 1368,0 51 0 121 DESIGN @f@a@d_@board 122 VIEW symbol.sb 123 GRAPHIC 1373,0 52 0 124 DESIGN @f@a@d_@board 125 VIEW symbol.sb 126 GRAPHIC 1378,0 53 0 127 DESIGN @f@a@d_@board 128 VIEW symbol.sb 129 GRAPHIC 1383,0 54 0 130 DESIGN @f@a@d_@board 131 VIEW symbol.sb 132 GRAPHIC 1676,0 55 0 133 DESIGN @f@a@d_@board 134 VIEW symbol.sb 135 GRAPHIC 1393,0 56 0 136 DESIGN @f@a@d_@board 137 VIEW symbol.sb 138 GRAPHIC 1426,0 57 0 139 DESIGN @f@a@d_@board 140 VIEW symbol.sb 141 GRAPHIC 1409,0 58 0 142 DESIGN @f@a@d_@board 143 VIEW symbol.sb 144 GRAPHIC 1403,0 59 0 145 DESIGN @f@a@d_@board 146 VIEW symbol.sb 147 GRAPHIC 1415,0 60 0 148 DESIGN @f@a@d_@board 149 VIEW symbol.sb 150 GRAPHIC 1626,0 61 0 151 DESIGN @f@a@d_@board 152 VIEW symbol.sb 153 GRAPHIC 1398,0 62 0 154 DESIGN @f@a@d_@board 155 VIEW symbol.sb 156 GRAPHIC 1,0 65 0 157 DESIGN @f@a@d_@board 158 VIEW symbol.sb 159 GRAPHIC 1,0 66 0 160 DESIGN @f@a@d_@board 161 VIEW struct.bd 162 NO_GRAPHIC 69 163 DESIGN @f@a@d_@board 164 VIEW struct.bd 165 GRAPHIC 41,0 78 0 166 DESIGN @f@a@d_@board 167 VIEW struct.bd 168 NO_GRAPHIC 86 169 DESIGN @f@a@d_@board 170 VIEW struct.bd 171 GRAPHIC 0,0 89 2 172 DESIGN @f@a@d_@board 173 VIEW struct.bd 174 GRAPHIC 10504,0 94 0 175 DESIGN @f@a@d_@board 176 VIEW struct.bd 177 GRAPHIC 10512,0 95 0 178 DESIGN @f@a@d_@board 179 VIEW struct.bd 180 GRAPHIC 10496,0 96 0 181 DESIGN @f@a@d_@board 182 VIEW struct.bd 183 GRAPHIC 3268,0 97 0 184 DESIGN @f@a@d_@board 185 VIEW struct.bd 186 GRAPHIC 10032,0 98 0 187 DESIGN @f@a@d_@board 188 VIEW struct.bd 189 GRAPHIC 9500,0 99 0 190 DESIGN @f@a@d_@board 191 VIEW struct.bd 192 GRAPHIC 10552,0 100 0 193 DESIGN @f@a@d_@board 194 VIEW struct.bd 195 GRAPHIC 10592,0 101 0 196 DESIGN @f@a@d_@board 197 VIEW struct.bd 198 GRAPHIC 10584,0 102 0 199 DESIGN @f@a@d_@board 200 VIEW struct.bd 201 GRAPHIC 10576,0 103 0 202 DESIGN @f@a@d_@board 203 VIEW struct.bd 204 GRAPHIC 10536,0 104 0 205 DESIGN @f@a@d_@board 206 VIEW struct.bd 207 GRAPHIC 10544,0 105 0 208 DESIGN @f@a@d_@board 209 VIEW struct.bd 210 GRAPHIC 10520,0 106 0 211 DESIGN @f@a@d_@board 212 VIEW struct.bd 213 GRAPHIC 10528,0 107 0 214 DESIGN @f@a@d_@board 215 VIEW struct.bd 216 GRAPHIC 2421,0 108 0 217 DESIGN @f@a@d_@board 218 VIEW struct.bd 219 GRAPHIC 10050,0 109 0 220 DESIGN @f@a@d_@board 221 VIEW struct.bd 222 GRAPHIC 1465,0 110 0 223 DESIGN @f@a@d_@board 224 VIEW struct.bd 225 GRAPHIC 275,0 111 0 226 DESIGN @f@a@d_@board 227 VIEW struct.bd 228 GRAPHIC 283,0 112 0 229 DESIGN @f@a@d_@board 230 VIEW struct.bd 231 GRAPHIC 8851,0 113 0 232 DESIGN @f@a@d_@board 233 VIEW struct.bd 234 GRAPHIC 7485,0 114 0 235 DESIGN @f@a@d_@board 236 VIEW struct.bd 237 GRAPHIC 10560,0 115 0 238 DESIGN @f@a@d_@board 239 VIEW struct.bd 240 GRAPHIC 3019,0 116 0 241 DESIGN @f@a@d_@board 242 VIEW struct.bd 243 GRAPHIC 10568,0 118 0 244 DESIGN @f@a@d_@board 245 VIEW struct.bd 246 NO_GRAPHIC 119 247 DESIGN @f@a@d_@board 248 VIEW struct.bd 249 NO_GRAPHIC 120 39 GRAPHIC 3581,0 24 0 40 DESIGN @f@a@d_@board 41 VIEW symbol.sb 42 GRAPHIC 3687,0 25 0 43 DESIGN @f@a@d_@board 44 VIEW symbol.sb 45 GRAPHIC 3692,0 26 0 46 DESIGN @f@a@d_@board 47 VIEW symbol.sb 48 GRAPHIC 1121,0 27 0 49 DESIGN @f@a@d_@board 50 VIEW symbol.sb 51 GRAPHIC 1421,0 28 0 52 DESIGN @f@a@d_@board 53 VIEW symbol.sb 54 GRAPHIC 1116,0 29 0 55 DESIGN @f@a@d_@board 56 VIEW symbol.sb 57 GRAPHIC 3456,0 30 0 58 DESIGN @f@a@d_@board 59 VIEW symbol.sb 60 GRAPHIC 3026,0 31 0 61 DESIGN @f@a@d_@board 62 VIEW symbol.sb 63 GRAPHIC 1126,0 32 0 64 DESIGN @f@a@d_@board 65 VIEW symbol.sb 66 GRAPHIC 1227,0 33 0 67 DESIGN @f@a@d_@board 68 VIEW symbol.sb 69 GRAPHIC 1232,0 34 0 70 DESIGN @f@a@d_@board 71 VIEW symbol.sb 72 GRAPHIC 1237,0 35 0 73 DESIGN @f@a@d_@board 74 VIEW symbol.sb 75 GRAPHIC 1242,0 36 0 76 DESIGN @f@a@d_@board 77 VIEW symbol.sb 78 GRAPHIC 1363,0 37 0 79 DESIGN @f@a@d_@board 80 VIEW symbol.sb 81 GRAPHIC 1701,0 38 0 82 DESIGN @f@a@d_@board 83 VIEW symbol.sb 84 GRAPHIC 1308,0 39 0 85 DESIGN @f@a@d_@board 86 VIEW symbol.sb 87 GRAPHIC 1302,0 40 0 88 DESIGN @f@a@d_@board 89 VIEW symbol.sb 90 GRAPHIC 2068,0 41 0 91 DESIGN @f@a@d_@board 92 VIEW symbol.sb 93 GRAPHIC 2949,0 42 0 94 DESIGN @f@a@d_@board 95 VIEW symbol.sb 96 GRAPHIC 1711,0 43 0 97 DESIGN @f@a@d_@board 98 VIEW symbol.sb 99 GRAPHIC 2375,0 44 0 100 DESIGN @f@a@d_@board 101 VIEW symbol.sb 102 GRAPHIC 1620,0 45 0 103 DESIGN @f@a@d_@board 104 VIEW symbol.sb 105 GRAPHIC 1166,0 46 0 106 DESIGN @f@a@d_@board 107 VIEW symbol.sb 108 GRAPHIC 1686,0 47 0 109 DESIGN @f@a@d_@board 110 VIEW symbol.sb 111 GRAPHIC 3586,0 48 0 112 DESIGN @f@a@d_@board 113 VIEW symbol.sb 114 GRAPHIC 1681,0 49 0 115 DESIGN @f@a@d_@board 116 VIEW symbol.sb 117 GRAPHIC 1696,0 50 0 118 DESIGN @f@a@d_@board 119 VIEW symbol.sb 120 GRAPHIC 1691,0 51 0 121 DESIGN @f@a@d_@board 122 VIEW symbol.sb 123 GRAPHIC 693,0 52 0 124 DESIGN @f@a@d_@board 125 VIEW symbol.sb 126 GRAPHIC 1706,0 53 0 127 DESIGN @f@a@d_@board 128 VIEW symbol.sb 129 GRAPHIC 1388,0 54 0 130 DESIGN @f@a@d_@board 131 VIEW symbol.sb 132 GRAPHIC 1368,0 55 0 133 DESIGN @f@a@d_@board 134 VIEW symbol.sb 135 GRAPHIC 1373,0 56 0 136 DESIGN @f@a@d_@board 137 VIEW symbol.sb 138 GRAPHIC 1378,0 57 0 139 DESIGN @f@a@d_@board 140 VIEW symbol.sb 141 GRAPHIC 1383,0 58 0 142 DESIGN @f@a@d_@board 143 VIEW symbol.sb 144 GRAPHIC 1676,0 59 0 145 DESIGN @f@a@d_@board 146 VIEW symbol.sb 147 GRAPHIC 1393,0 60 0 148 DESIGN @f@a@d_@board 149 VIEW symbol.sb 150 GRAPHIC 1426,0 61 0 151 DESIGN @f@a@d_@board 152 VIEW symbol.sb 153 GRAPHIC 1409,0 62 0 154 DESIGN @f@a@d_@board 155 VIEW symbol.sb 156 GRAPHIC 1403,0 63 0 157 DESIGN @f@a@d_@board 158 VIEW symbol.sb 159 GRAPHIC 1415,0 64 0 160 DESIGN @f@a@d_@board 161 VIEW symbol.sb 162 GRAPHIC 1626,0 65 0 163 DESIGN @f@a@d_@board 164 VIEW symbol.sb 165 GRAPHIC 1398,0 66 0 166 DESIGN @f@a@d_@board 167 VIEW symbol.sb 168 GRAPHIC 1,0 69 0 169 DESIGN @f@a@d_@board 170 VIEW symbol.sb 171 GRAPHIC 1,0 70 0 172 DESIGN @f@a@d_@board 173 VIEW struct.bd 174 NO_GRAPHIC 73 175 DESIGN @f@a@d_@board 176 VIEW struct.bd 177 GRAPHIC 41,0 82 0 178 DESIGN @f@a@d_@board 179 VIEW struct.bd 180 NO_GRAPHIC 90 181 DESIGN @f@a@d_@board 182 VIEW struct.bd 183 GRAPHIC 0,0 93 2 184 DESIGN @f@a@d_@board 185 VIEW struct.bd 186 GRAPHIC 10504,0 98 0 187 DESIGN @f@a@d_@board 188 VIEW struct.bd 189 GRAPHIC 10512,0 99 0 190 DESIGN @f@a@d_@board 191 VIEW struct.bd 192 GRAPHIC 10496,0 100 0 193 DESIGN @f@a@d_@board 194 VIEW struct.bd 195 GRAPHIC 3268,0 101 0 196 DESIGN @f@a@d_@board 197 VIEW struct.bd 198 GRAPHIC 10032,0 102 0 199 DESIGN @f@a@d_@board 200 VIEW struct.bd 201 GRAPHIC 9500,0 103 0 202 DESIGN @f@a@d_@board 203 VIEW struct.bd 204 GRAPHIC 10552,0 104 0 205 DESIGN @f@a@d_@board 206 VIEW struct.bd 207 GRAPHIC 10592,0 105 0 208 DESIGN @f@a@d_@board 209 VIEW struct.bd 210 GRAPHIC 10584,0 106 0 211 DESIGN @f@a@d_@board 212 VIEW struct.bd 213 GRAPHIC 10576,0 107 0 214 DESIGN @f@a@d_@board 215 VIEW struct.bd 216 GRAPHIC 10536,0 108 0 217 DESIGN @f@a@d_@board 218 VIEW struct.bd 219 GRAPHIC 10544,0 109 0 220 DESIGN @f@a@d_@board 221 VIEW struct.bd 222 GRAPHIC 10520,0 110 0 223 DESIGN @f@a@d_@board 224 VIEW struct.bd 225 GRAPHIC 10528,0 111 0 226 DESIGN @f@a@d_@board 227 VIEW struct.bd 228 GRAPHIC 2421,0 112 0 229 DESIGN @f@a@d_@board 230 VIEW struct.bd 231 GRAPHIC 10050,0 113 0 232 DESIGN @f@a@d_@board 233 VIEW struct.bd 234 GRAPHIC 1465,0 114 0 235 DESIGN @f@a@d_@board 236 VIEW struct.bd 237 GRAPHIC 275,0 115 0 238 DESIGN @f@a@d_@board 239 VIEW struct.bd 240 GRAPHIC 283,0 116 0 241 DESIGN @f@a@d_@board 242 VIEW struct.bd 243 GRAPHIC 8851,0 117 0 244 DESIGN @f@a@d_@board 245 VIEW struct.bd 246 GRAPHIC 7485,0 118 0 247 DESIGN @f@a@d_@board 248 VIEW struct.bd 249 GRAPHIC 10560,0 119 0 250 DESIGN @f@a@d_@board 251 VIEW struct.bd 252 GRAPHIC 3019,0 120 0 253 DESIGN @f@a@d_@board 254 VIEW struct.bd 255 GRAPHIC 10568,0 122 0 256 DESIGN @f@a@d_@board 257 VIEW struct.bd 258 NO_GRAPHIC 123 259 DESIGN @f@a@d_@board 260 VIEW struct.bd 261 NO_GRAPHIC 124 250 262 LIBRARY FACT_FAD_lib 251 263 DESIGN @f@a@d_main 252 264 VIEW struct 253 GRAPHIC 169,0 122 0 254 DESIGN @f@a@d_main 255 VIEW symbol.sb 256 GRAPHIC 14,0 123 1 257 DESIGN @f@a@d_main 258 VIEW symbol.sb 259 GRAPHIC 1755,0 127 0 260 DESIGN @f@a@d_main 261 VIEW symbol.sb 262 GRAPHIC 2710,0 128 0 263 DESIGN @f@a@d_main 264 VIEW symbol.sb 265 GRAPHIC 2715,0 129 0 266 DESIGN @f@a@d_main 267 VIEW symbol.sb 268 GRAPHIC 2720,0 130 0 269 DESIGN @f@a@d_main 270 VIEW symbol.sb 271 GRAPHIC 2725,0 131 0 272 DESIGN @f@a@d_main 273 VIEW symbol.sb 274 GRAPHIC 2282,0 132 0 275 DESIGN @f@a@d_main 276 VIEW symbol.sb 277 GRAPHIC 1976,0 133 0 278 DESIGN @f@a@d_main 279 VIEW symbol.sb 280 GRAPHIC 923,0 134 0 281 DESIGN @f@a@d_main 282 VIEW symbol.sb 283 GRAPHIC 928,0 135 0 284 DESIGN @f@a@d_main 285 VIEW symbol.sb 286 GRAPHIC 464,0 136 0 287 DESIGN @f@a@d_main 288 VIEW symbol.sb 289 GRAPHIC 1062,0 137 0 290 DESIGN @f@a@d_main 291 VIEW symbol.sb 292 GRAPHIC 4584,0 138 0 293 DESIGN @f@a@d_main 294 VIEW symbol.sb 295 GRAPHIC 4589,0 139 0 296 DESIGN @f@a@d_main 297 VIEW symbol.sb 298 GRAPHIC 4579,0 140 0 299 DESIGN @f@a@d_main 300 VIEW symbol.sb 301 GRAPHIC 1389,0 141 0 302 DESIGN @f@a@d_main 303 VIEW symbol.sb 304 GRAPHIC 1725,0 142 0 305 DESIGN @f@a@d_main 306 VIEW symbol.sb 307 GRAPHIC 4497,0 143 0 308 DESIGN @f@a@d_main 309 VIEW symbol.sb 310 GRAPHIC 4467,0 144 0 311 DESIGN @f@a@d_main 312 VIEW symbol.sb 313 GRAPHIC 4487,0 145 0 314 DESIGN @f@a@d_main 315 VIEW symbol.sb 316 GRAPHIC 4472,0 146 0 317 DESIGN @f@a@d_main 318 VIEW symbol.sb 319 GRAPHIC 4482,0 147 0 320 DESIGN @f@a@d_main 321 VIEW symbol.sb 322 GRAPHIC 4477,0 148 0 323 DESIGN @f@a@d_main 324 VIEW symbol.sb 325 GRAPHIC 4517,0 149 0 326 DESIGN @f@a@d_main 327 VIEW symbol.sb 328 GRAPHIC 4522,0 150 0 329 DESIGN @f@a@d_main 330 VIEW symbol.sb 331 GRAPHIC 2987,0 151 0 332 DESIGN @f@a@d_main 333 VIEW symbol.sb 334 GRAPHIC 2992,0 152 0 335 DESIGN @f@a@d_main 336 VIEW symbol.sb 337 GRAPHIC 4323,0 153 0 338 DESIGN @f@a@d_main 339 VIEW symbol.sb 340 GRAPHIC 833,0 154 0 341 DESIGN @f@a@d_main 342 VIEW symbol.sb 343 GRAPHIC 3641,0 155 0 344 DESIGN @f@a@d_main 345 VIEW symbol.sb 346 GRAPHIC 4144,0 156 0 347 DESIGN @f@a@d_main 348 VIEW symbol.sb 349 GRAPHIC 2448,0 157 0 350 DESIGN @f@a@d_main 351 VIEW symbol.sb 352 GRAPHIC 2453,0 158 0 353 DESIGN @f@a@d_main 354 VIEW symbol.sb 355 GRAPHIC 163,0 159 0 356 DESIGN @f@a@d_main 357 VIEW symbol.sb 358 GRAPHIC 4067,0 160 0 359 DESIGN @f@a@d_main 360 VIEW symbol.sb 361 GRAPHIC 4502,0 161 0 362 DESIGN @f@a@d_main 363 VIEW symbol.sb 364 GRAPHIC 4512,0 162 0 365 DESIGN @f@a@d_main 366 VIEW symbol.sb 367 GRAPHIC 3631,0 163 0 368 DESIGN @f@a@d_main 369 VIEW symbol.sb 370 GRAPHIC 3646,0 164 0 371 DESIGN @f@a@d_main 372 VIEW symbol.sb 373 GRAPHIC 4507,0 165 0 374 DESIGN @f@a@d_main 375 VIEW symbol.sb 376 GRAPHIC 1037,0 167 0 377 DESIGN @f@a@d_main 378 VIEW symbol.sb 379 GRAPHIC 1047,0 168 0 380 DESIGN @f@a@d_main 381 VIEW symbol.sb 382 GRAPHIC 1057,0 169 0 383 DESIGN @f@a@d_main 384 VIEW symbol.sb 385 GRAPHIC 135,0 170 0 386 DESIGN @f@a@d_main 387 VIEW symbol.sb 388 GRAPHIC 1052,0 171 0 389 DESIGN @f@a@d_main 390 VIEW symbol.sb 391 GRAPHIC 3636,0 172 0 392 DESIGN @f@a@d_main 393 VIEW symbol.sb 394 GRAPHIC 1042,0 173 0 265 GRAPHIC 169,0 126 0 266 DESIGN @f@a@d_main 267 VIEW symbol.sb 268 GRAPHIC 14,0 127 1 269 DESIGN @f@a@d_main 270 VIEW symbol.sb 271 GRAPHIC 1755,0 131 0 272 DESIGN @f@a@d_main 273 VIEW symbol.sb 274 GRAPHIC 2710,0 132 0 275 DESIGN @f@a@d_main 276 VIEW symbol.sb 277 GRAPHIC 2715,0 133 0 278 DESIGN @f@a@d_main 279 VIEW symbol.sb 280 GRAPHIC 2720,0 134 0 281 DESIGN @f@a@d_main 282 VIEW symbol.sb 283 GRAPHIC 2725,0 135 0 284 DESIGN @f@a@d_main 285 VIEW symbol.sb 286 GRAPHIC 2282,0 136 0 287 DESIGN @f@a@d_main 288 VIEW symbol.sb 289 GRAPHIC 1976,0 137 0 290 DESIGN @f@a@d_main 291 VIEW symbol.sb 292 GRAPHIC 923,0 138 0 293 DESIGN @f@a@d_main 294 VIEW symbol.sb 295 GRAPHIC 928,0 139 0 296 DESIGN @f@a@d_main 297 VIEW symbol.sb 298 GRAPHIC 464,0 140 0 299 DESIGN @f@a@d_main 300 VIEW symbol.sb 301 GRAPHIC 1062,0 141 0 302 DESIGN @f@a@d_main 303 VIEW symbol.sb 304 GRAPHIC 4584,0 142 0 305 DESIGN @f@a@d_main 306 VIEW symbol.sb 307 GRAPHIC 4589,0 143 0 308 DESIGN @f@a@d_main 309 VIEW symbol.sb 310 GRAPHIC 4579,0 144 0 311 DESIGN @f@a@d_main 312 VIEW symbol.sb 313 GRAPHIC 1389,0 145 0 314 DESIGN @f@a@d_main 315 VIEW symbol.sb 316 GRAPHIC 1725,0 146 0 317 DESIGN @f@a@d_main 318 VIEW symbol.sb 319 GRAPHIC 4497,0 147 0 320 DESIGN @f@a@d_main 321 VIEW symbol.sb 322 GRAPHIC 4467,0 148 0 323 DESIGN @f@a@d_main 324 VIEW symbol.sb 325 GRAPHIC 4487,0 149 0 326 DESIGN @f@a@d_main 327 VIEW symbol.sb 328 GRAPHIC 4472,0 150 0 329 DESIGN @f@a@d_main 330 VIEW symbol.sb 331 GRAPHIC 4482,0 151 0 332 DESIGN @f@a@d_main 333 VIEW symbol.sb 334 GRAPHIC 4477,0 152 0 335 DESIGN @f@a@d_main 336 VIEW symbol.sb 337 GRAPHIC 4517,0 153 0 338 DESIGN @f@a@d_main 339 VIEW symbol.sb 340 GRAPHIC 4522,0 154 0 341 DESIGN @f@a@d_main 342 VIEW symbol.sb 343 GRAPHIC 2987,0 155 0 344 DESIGN @f@a@d_main 345 VIEW symbol.sb 346 GRAPHIC 2992,0 156 0 347 DESIGN @f@a@d_main 348 VIEW symbol.sb 349 GRAPHIC 4780,0 157 0 350 DESIGN @f@a@d_main 351 VIEW symbol.sb 352 GRAPHIC 4323,0 158 0 353 DESIGN @f@a@d_main 354 VIEW symbol.sb 355 GRAPHIC 833,0 159 0 356 DESIGN @f@a@d_main 357 VIEW symbol.sb 358 GRAPHIC 3641,0 160 0 359 DESIGN @f@a@d_main 360 VIEW symbol.sb 361 GRAPHIC 4144,0 161 0 362 DESIGN @f@a@d_main 363 VIEW symbol.sb 364 GRAPHIC 2448,0 162 0 365 DESIGN @f@a@d_main 366 VIEW symbol.sb 367 GRAPHIC 2453,0 163 0 368 DESIGN @f@a@d_main 369 VIEW symbol.sb 370 GRAPHIC 163,0 164 0 371 DESIGN @f@a@d_main 372 VIEW symbol.sb 373 GRAPHIC 4067,0 165 0 374 DESIGN @f@a@d_main 375 VIEW symbol.sb 376 GRAPHIC 4502,0 166 0 377 DESIGN @f@a@d_main 378 VIEW symbol.sb 379 GRAPHIC 4512,0 167 0 380 DESIGN @f@a@d_main 381 VIEW symbol.sb 382 GRAPHIC 3631,0 168 0 383 DESIGN @f@a@d_main 384 VIEW symbol.sb 385 GRAPHIC 3646,0 169 0 386 DESIGN @f@a@d_main 387 VIEW symbol.sb 388 GRAPHIC 4507,0 170 0 389 DESIGN @f@a@d_main 390 VIEW symbol.sb 391 GRAPHIC 1037,0 172 0 392 DESIGN @f@a@d_main 393 VIEW symbol.sb 394 GRAPHIC 1047,0 173 0 395 DESIGN @f@a@d_main 396 VIEW symbol.sb 397 GRAPHIC 1057,0 174 0 398 DESIGN @f@a@d_main 399 VIEW symbol.sb 400 GRAPHIC 135,0 175 0 401 DESIGN @f@a@d_main 402 VIEW symbol.sb 403 GRAPHIC 1052,0 176 0 404 DESIGN @f@a@d_main 405 VIEW symbol.sb 406 GRAPHIC 3636,0 177 0 407 DESIGN @f@a@d_main 408 VIEW symbol.sb 409 GRAPHIC 1042,0 178 0 395 410 LIBRARY FACT_FAD_lib 396 411 DESIGN @f@a@d_@board 397 412 VIEW struct.bd 398 NO_GRAPHIC 176 399 DESIGN @f@a@d_@board 400 VIEW struct.bd 401 GRAPHIC 169,0 179 0 402 DESIGN @f@a@d_@board 403 VIEW struct.bd 404 NO_GRAPHIC 182 405 DESIGN @f@a@d_@board 406 VIEW struct.bd 407 GRAPHIC 265,0 185 0 408 DESIGN @f@a@d_@board 409 VIEW struct.bd 410 NO_GRAPHIC 189 411 DESIGN @f@a@d_@board 412 VIEW struct.bd 413 GRAPHIC 3248,0 190 0 414 DESIGN @f@a@d_@board 415 VIEW struct.bd 416 NO_GRAPHIC 196 417 DESIGN @f@a@d_@board 418 VIEW struct.bd 419 GRAPHIC 3300,0 197 0 420 DESIGN @f@a@d_@board 421 VIEW struct.bd 422 NO_GRAPHIC 203 423 DESIGN @f@a@d_@board 424 VIEW struct.bd 425 GRAPHIC 3394,0 204 0 426 DESIGN @f@a@d_@board 427 VIEW struct.bd 428 NO_GRAPHIC 210 429 DESIGN @f@a@d_@board 430 VIEW struct.bd 431 GRAPHIC 3542,0 211 0 432 DESIGN @f@a@d_@board 433 VIEW struct.bd 434 NO_GRAPHIC 217 435 DESIGN @f@a@d_@board 436 VIEW struct.bd 437 GRAPHIC 3700,0 218 0 438 DESIGN @f@a@d_@board 439 VIEW struct.bd 440 NO_GRAPHIC 238 441 DESIGN @f@a@d_@board 442 VIEW struct.bd 443 GRAPHIC 6888,0 239 0 444 DESIGN @f@a@d_@board 445 VIEW struct.bd 446 NO_GRAPHIC 241 447 DESIGN @f@a@d_@board 448 VIEW struct.bd 449 GRAPHIC 7092,0 242 0 450 DESIGN @f@a@d_@board 451 VIEW struct.bd 452 NO_GRAPHIC 245 453 DESIGN @f@a@d_@board 454 VIEW struct.bd 455 GRAPHIC 10310,0 246 0 456 DESIGN @f@a@d_@board 457 VIEW struct.bd 458 NO_GRAPHIC 266 459 DESIGN @f@a@d_@board 460 VIEW struct.bd 461 GRAPHIC 10023,0 267 0 462 DESIGN @f@a@d_@board 463 VIEW struct.bd 464 GRAPHIC 7652,0 270 0 465 DESIGN @f@a@d_@board 466 VIEW struct.bd 467 NO_GRAPHIC 273 468 DESIGN @f@a@d_@board 469 VIEW struct.bd 470 GRAPHIC 169,0 275 0 471 DESIGN @f@a@d_@board 472 VIEW struct.bd 473 GRAPHIC 176,0 276 1 474 DESIGN @f@a@d_@board 475 VIEW struct.bd 476 GRAPHIC 245,0 280 0 477 DESIGN @f@a@d_@board 478 VIEW struct.bd 479 GRAPHIC 1865,0 281 0 480 DESIGN @f@a@d_@board 481 VIEW struct.bd 482 GRAPHIC 1873,0 282 0 483 DESIGN @f@a@d_@board 484 VIEW struct.bd 485 GRAPHIC 1881,0 283 0 486 DESIGN @f@a@d_@board 487 VIEW struct.bd 488 GRAPHIC 1889,0 284 0 489 DESIGN @f@a@d_@board 490 VIEW struct.bd 491 GRAPHIC 1467,0 285 0 492 DESIGN @f@a@d_@board 493 VIEW struct.bd 494 GRAPHIC 1730,0 286 0 495 DESIGN @f@a@d_@board 496 VIEW struct.bd 497 GRAPHIC 277,0 287 0 498 DESIGN @f@a@d_@board 499 VIEW struct.bd 500 GRAPHIC 285,0 288 0 501 DESIGN @f@a@d_@board 502 VIEW struct.bd 503 GRAPHIC 3218,0 289 0 504 DESIGN @f@a@d_@board 505 VIEW struct.bd 506 GRAPHIC 450,0 290 0 507 DESIGN @f@a@d_@board 508 VIEW struct.bd 509 GRAPHIC 10506,0 291 0 510 DESIGN @f@a@d_@board 511 VIEW struct.bd 512 GRAPHIC 10514,0 292 0 513 DESIGN @f@a@d_@board 514 VIEW struct.bd 515 GRAPHIC 10498,0 293 0 516 DESIGN @f@a@d_@board 517 VIEW struct.bd 518 GRAPHIC 10034,0 294 0 519 DESIGN @f@a@d_@board 520 VIEW struct.bd 521 GRAPHIC 9502,0 295 0 522 DESIGN @f@a@d_@board 523 VIEW struct.bd 524 GRAPHIC 10554,0 296 0 525 DESIGN @f@a@d_@board 526 VIEW struct.bd 527 GRAPHIC 10594,0 297 0 528 DESIGN @f@a@d_@board 529 VIEW struct.bd 530 GRAPHIC 10586,0 298 0 531 DESIGN @f@a@d_@board 532 VIEW struct.bd 533 GRAPHIC 10578,0 299 0 534 DESIGN @f@a@d_@board 535 VIEW struct.bd 536 GRAPHIC 10538,0 300 0 537 DESIGN @f@a@d_@board 538 VIEW struct.bd 539 GRAPHIC 10546,0 301 0 540 DESIGN @f@a@d_@board 541 VIEW struct.bd 542 GRAPHIC 10522,0 302 0 543 DESIGN @f@a@d_@board 544 VIEW struct.bd 545 GRAPHIC 10530,0 303 0 546 DESIGN @f@a@d_@board 547 VIEW struct.bd 548 GRAPHIC 2409,0 304 0 549 DESIGN @f@a@d_@board 550 VIEW struct.bd 551 GRAPHIC 2423,0 305 0 552 DESIGN @f@a@d_@board 553 VIEW struct.bd 554 GRAPHIC 10052,0 306 0 555 DESIGN @f@a@d_@board 556 VIEW struct.bd 557 GRAPHIC 362,0 307 0 558 DESIGN @f@a@d_@board 559 VIEW struct.bd 560 GRAPHIC 7477,0 308 0 561 DESIGN @f@a@d_@board 562 VIEW struct.bd 563 GRAPHIC 6431,0 309 0 564 DESIGN @f@a@d_@board 565 VIEW struct.bd 566 GRAPHIC 8853,0 310 0 567 DESIGN @f@a@d_@board 568 VIEW struct.bd 569 GRAPHIC 1841,0 311 0 570 DESIGN @f@a@d_@board 571 VIEW struct.bd 572 GRAPHIC 4942,0 312 0 573 DESIGN @f@a@d_@board 574 VIEW struct.bd 575 GRAPHIC 3682,0 313 0 576 DESIGN @f@a@d_@board 577 VIEW struct.bd 578 GRAPHIC 10562,0 315 0 579 DESIGN @f@a@d_@board 580 VIEW struct.bd 581 GRAPHIC 3009,0 316 0 582 DESIGN @f@a@d_@board 583 VIEW struct.bd 584 GRAPHIC 3021,0 317 0 585 DESIGN @f@a@d_@board 586 VIEW struct.bd 587 GRAPHIC 10570,0 318 0 588 DESIGN @f@a@d_@board 589 VIEW struct.bd 590 GRAPHIC 426,0 319 0 591 DESIGN @f@a@d_@board 592 VIEW struct.bd 593 GRAPHIC 434,0 320 0 594 DESIGN @f@a@d_@board 595 VIEW struct.bd 596 GRAPHIC 458,0 321 0 597 DESIGN @f@a@d_@board 598 VIEW struct.bd 599 GRAPHIC 418,0 322 0 600 DESIGN @f@a@d_@board 601 VIEW struct.bd 602 GRAPHIC 466,0 323 0 603 DESIGN @f@a@d_@board 604 VIEW struct.bd 605 GRAPHIC 3015,0 324 0 606 DESIGN @f@a@d_@board 607 VIEW struct.bd 608 GRAPHIC 442,0 325 0 609 DESIGN @f@a@d_@board 610 VIEW struct.bd 611 NO_GRAPHIC 328 413 NO_GRAPHIC 181 414 DESIGN @f@a@d_@board 415 VIEW struct.bd 416 GRAPHIC 169,0 184 0 417 DESIGN @f@a@d_@board 418 VIEW struct.bd 419 NO_GRAPHIC 187 420 DESIGN @f@a@d_@board 421 VIEW struct.bd 422 GRAPHIC 265,0 190 0 423 DESIGN @f@a@d_@board 424 VIEW struct.bd 425 NO_GRAPHIC 194 426 DESIGN @f@a@d_@board 427 VIEW struct.bd 428 GRAPHIC 3248,0 195 0 429 DESIGN @f@a@d_@board 430 VIEW struct.bd 431 NO_GRAPHIC 201 432 DESIGN @f@a@d_@board 433 VIEW struct.bd 434 GRAPHIC 3300,0 202 0 435 DESIGN @f@a@d_@board 436 VIEW struct.bd 437 NO_GRAPHIC 208 438 DESIGN @f@a@d_@board 439 VIEW struct.bd 440 GRAPHIC 3394,0 209 0 441 DESIGN @f@a@d_@board 442 VIEW struct.bd 443 NO_GRAPHIC 215 444 DESIGN @f@a@d_@board 445 VIEW struct.bd 446 GRAPHIC 3542,0 216 0 447 DESIGN @f@a@d_@board 448 VIEW struct.bd 449 NO_GRAPHIC 222 450 DESIGN @f@a@d_@board 451 VIEW struct.bd 452 GRAPHIC 3700,0 223 0 453 DESIGN @f@a@d_@board 454 VIEW struct.bd 455 NO_GRAPHIC 246 456 DESIGN @f@a@d_@board 457 VIEW struct.bd 458 GRAPHIC 6888,0 247 0 459 DESIGN @f@a@d_@board 460 VIEW struct.bd 461 NO_GRAPHIC 249 462 DESIGN @f@a@d_@board 463 VIEW struct.bd 464 GRAPHIC 7092,0 250 0 465 DESIGN @f@a@d_@board 466 VIEW struct.bd 467 NO_GRAPHIC 253 468 DESIGN @f@a@d_@board 469 VIEW struct.bd 470 GRAPHIC 10310,0 254 0 471 DESIGN @f@a@d_@board 472 VIEW struct.bd 473 NO_GRAPHIC 274 474 DESIGN @f@a@d_@board 475 VIEW struct.bd 476 GRAPHIC 10023,0 275 0 477 DESIGN @f@a@d_@board 478 VIEW struct.bd 479 GRAPHIC 7652,0 278 0 480 DESIGN @f@a@d_@board 481 VIEW struct.bd 482 NO_GRAPHIC 281 483 DESIGN @f@a@d_@board 484 VIEW struct.bd 485 GRAPHIC 169,0 283 0 486 DESIGN @f@a@d_@board 487 VIEW struct.bd 488 GRAPHIC 176,0 284 1 489 DESIGN @f@a@d_@board 490 VIEW struct.bd 491 GRAPHIC 245,0 288 0 492 DESIGN @f@a@d_@board 493 VIEW struct.bd 494 GRAPHIC 1865,0 289 0 495 DESIGN @f@a@d_@board 496 VIEW struct.bd 497 GRAPHIC 1873,0 290 0 498 DESIGN @f@a@d_@board 499 VIEW struct.bd 500 GRAPHIC 1881,0 291 0 501 DESIGN @f@a@d_@board 502 VIEW struct.bd 503 GRAPHIC 1889,0 292 0 504 DESIGN @f@a@d_@board 505 VIEW struct.bd 506 GRAPHIC 1467,0 293 0 507 DESIGN @f@a@d_@board 508 VIEW struct.bd 509 GRAPHIC 1730,0 294 0 510 DESIGN @f@a@d_@board 511 VIEW struct.bd 512 GRAPHIC 277,0 295 0 513 DESIGN @f@a@d_@board 514 VIEW struct.bd 515 GRAPHIC 285,0 296 0 516 DESIGN @f@a@d_@board 517 VIEW struct.bd 518 GRAPHIC 3218,0 297 0 519 DESIGN @f@a@d_@board 520 VIEW struct.bd 521 GRAPHIC 450,0 298 0 522 DESIGN @f@a@d_@board 523 VIEW struct.bd 524 GRAPHIC 10506,0 299 0 525 DESIGN @f@a@d_@board 526 VIEW struct.bd 527 GRAPHIC 10514,0 300 0 528 DESIGN @f@a@d_@board 529 VIEW struct.bd 530 GRAPHIC 10498,0 301 0 531 DESIGN @f@a@d_@board 532 VIEW struct.bd 533 GRAPHIC 10034,0 302 0 534 DESIGN @f@a@d_@board 535 VIEW struct.bd 536 GRAPHIC 9502,0 303 0 537 DESIGN @f@a@d_@board 538 VIEW struct.bd 539 GRAPHIC 10554,0 304 0 540 DESIGN @f@a@d_@board 541 VIEW struct.bd 542 GRAPHIC 10594,0 305 0 543 DESIGN @f@a@d_@board 544 VIEW struct.bd 545 GRAPHIC 10586,0 306 0 546 DESIGN @f@a@d_@board 547 VIEW struct.bd 548 GRAPHIC 10578,0 307 0 549 DESIGN @f@a@d_@board 550 VIEW struct.bd 551 GRAPHIC 10538,0 308 0 552 DESIGN @f@a@d_@board 553 VIEW struct.bd 554 GRAPHIC 10546,0 309 0 555 DESIGN @f@a@d_@board 556 VIEW struct.bd 557 GRAPHIC 10522,0 310 0 558 DESIGN @f@a@d_@board 559 VIEW struct.bd 560 GRAPHIC 10530,0 311 0 561 DESIGN @f@a@d_@board 562 VIEW struct.bd 563 GRAPHIC 2409,0 312 0 564 DESIGN @f@a@d_@board 565 VIEW struct.bd 566 GRAPHIC 2423,0 313 0 567 DESIGN @f@a@d_@board 568 VIEW struct.bd 569 GRAPHIC 12320,0 314 0 570 DESIGN @f@a@d_@board 571 VIEW struct.bd 572 GRAPHIC 10052,0 315 0 573 DESIGN @f@a@d_@board 574 VIEW struct.bd 575 GRAPHIC 362,0 316 0 576 DESIGN @f@a@d_@board 577 VIEW struct.bd 578 GRAPHIC 7477,0 317 0 579 DESIGN @f@a@d_@board 580 VIEW struct.bd 581 GRAPHIC 6431,0 318 0 582 DESIGN @f@a@d_@board 583 VIEW struct.bd 584 GRAPHIC 8853,0 319 0 585 DESIGN @f@a@d_@board 586 VIEW struct.bd 587 GRAPHIC 1841,0 320 0 588 DESIGN @f@a@d_@board 589 VIEW struct.bd 590 GRAPHIC 4942,0 321 0 591 DESIGN @f@a@d_@board 592 VIEW struct.bd 593 GRAPHIC 3682,0 322 0 594 DESIGN @f@a@d_@board 595 VIEW struct.bd 596 GRAPHIC 10562,0 324 0 597 DESIGN @f@a@d_@board 598 VIEW struct.bd 599 GRAPHIC 3009,0 325 0 600 DESIGN @f@a@d_@board 601 VIEW struct.bd 602 GRAPHIC 3021,0 326 0 603 DESIGN @f@a@d_@board 604 VIEW struct.bd 605 GRAPHIC 10570,0 327 0 606 DESIGN @f@a@d_@board 607 VIEW struct.bd 608 GRAPHIC 426,0 328 0 609 DESIGN @f@a@d_@board 610 VIEW struct.bd 611 GRAPHIC 434,0 329 0 612 DESIGN @f@a@d_@board 613 VIEW struct.bd 614 GRAPHIC 458,0 330 0 615 DESIGN @f@a@d_@board 616 VIEW struct.bd 617 GRAPHIC 418,0 331 0 618 DESIGN @f@a@d_@board 619 VIEW struct.bd 620 GRAPHIC 466,0 332 0 621 DESIGN @f@a@d_@board 622 VIEW struct.bd 623 GRAPHIC 3015,0 333 0 624 DESIGN @f@a@d_@board 625 VIEW struct.bd 626 GRAPHIC 442,0 334 0 627 DESIGN @f@a@d_@board 628 VIEW struct.bd 629 NO_GRAPHIC 337 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf
r9912 r10073 88 88 DESIGN @f@a@d_main 89 89 VIEW symbol.sb 90 GRAPHIC 4 323,0 45 091 DESIGN @f@a@d_main 92 VIEW symbol.sb 93 GRAPHIC 833,0 46 094 DESIGN @f@a@d_main 95 VIEW symbol.sb 96 GRAPHIC 3641,0 47 097 DESIGN @f@a@d_main 98 VIEW symbol.sb 99 GRAPHIC 4144,0 48 0100 DESIGN @f@a@d_main 101 VIEW symbol.sb 102 GRAPHIC 2448,0 49 0103 DESIGN @f@a@d_main 104 VIEW symbol.sb 105 GRAPHIC 24 53,0 50 0106 DESIGN @f@a@d_main 107 VIEW symbol.sb 108 GRAPHIC 163,0 51 0109 DESIGN @f@a@d_main 110 VIEW symbol.sb 111 GRAPHIC 4067,0 52 0112 DESIGN @f@a@d_main 113 VIEW symbol.sb 114 GRAPHIC 4 502,0 53 0115 DESIGN @f@a@d_main 116 VIEW symbol.sb 117 GRAPHIC 45 12,0 54 0118 DESIGN @f@a@d_main 119 VIEW symbol.sb 120 GRAPHIC 3631,0 55 0121 DESIGN @f@a@d_main 122 VIEW symbol.sb 123 GRAPHIC 36 46,0 56 0124 DESIGN @f@a@d_main 125 VIEW symbol.sb 126 GRAPHIC 4507,0 580127 DESIGN @f@a@d_main 128 VIEW symbol.sb 129 GRAPHIC 1037,0 59 0130 DESIGN @f@a@d_main 131 VIEW symbol.sb 132 GRAPHIC 10 47,0 60 0133 DESIGN @f@a@d_main 134 VIEW symbol.sb 135 GRAPHIC 10 57,0 61 0136 DESIGN @f@a@d_main 137 VIEW symbol.sb 138 GRAPHIC 1 35,0 62 0139 DESIGN @f@a@d_main 140 VIEW symbol.sb 141 GRAPHIC 1 052,0 63 0142 DESIGN @f@a@d_main 143 VIEW symbol.sb 144 GRAPHIC 3636,0 64 0145 DESIGN @f@a@d_main 146 VIEW symbol.sb 147 GRAPHIC 1042,0 65 0148 DESIGN @f@a@d_main 149 VIEW symbol.sb 150 GRAPHIC 1 ,0 68090 GRAPHIC 4780,0 45 0 91 DESIGN @f@a@d_main 92 VIEW symbol.sb 93 GRAPHIC 4323,0 46 0 94 DESIGN @f@a@d_main 95 VIEW symbol.sb 96 GRAPHIC 833,0 47 0 97 DESIGN @f@a@d_main 98 VIEW symbol.sb 99 GRAPHIC 3641,0 48 0 100 DESIGN @f@a@d_main 101 VIEW symbol.sb 102 GRAPHIC 4144,0 49 0 103 DESIGN @f@a@d_main 104 VIEW symbol.sb 105 GRAPHIC 2448,0 50 0 106 DESIGN @f@a@d_main 107 VIEW symbol.sb 108 GRAPHIC 2453,0 51 0 109 DESIGN @f@a@d_main 110 VIEW symbol.sb 111 GRAPHIC 163,0 52 0 112 DESIGN @f@a@d_main 113 VIEW symbol.sb 114 GRAPHIC 4067,0 53 0 115 DESIGN @f@a@d_main 116 VIEW symbol.sb 117 GRAPHIC 4502,0 54 0 118 DESIGN @f@a@d_main 119 VIEW symbol.sb 120 GRAPHIC 4512,0 55 0 121 DESIGN @f@a@d_main 122 VIEW symbol.sb 123 GRAPHIC 3631,0 56 0 124 DESIGN @f@a@d_main 125 VIEW symbol.sb 126 GRAPHIC 3646,0 57 0 127 DESIGN @f@a@d_main 128 VIEW symbol.sb 129 GRAPHIC 4507,0 59 0 130 DESIGN @f@a@d_main 131 VIEW symbol.sb 132 GRAPHIC 1037,0 60 0 133 DESIGN @f@a@d_main 134 VIEW symbol.sb 135 GRAPHIC 1047,0 61 0 136 DESIGN @f@a@d_main 137 VIEW symbol.sb 138 GRAPHIC 1057,0 62 0 139 DESIGN @f@a@d_main 140 VIEW symbol.sb 141 GRAPHIC 135,0 63 0 142 DESIGN @f@a@d_main 143 VIEW symbol.sb 144 GRAPHIC 1052,0 64 0 145 DESIGN @f@a@d_main 146 VIEW symbol.sb 147 GRAPHIC 3636,0 65 0 148 DESIGN @f@a@d_main 149 VIEW symbol.sb 150 GRAPHIC 1042,0 66 0 151 151 DESIGN @f@a@d_main 152 152 VIEW symbol.sb 153 153 GRAPHIC 1,0 69 0 154 154 DESIGN @f@a@d_main 155 VIEW struct.bd 156 NO_GRAPHIC 72 157 DESIGN @f@a@d_main 158 VIEW struct.bd 159 GRAPHIC 41,0 81 0 160 DESIGN @f@a@d_main 161 VIEW struct.bd 162 NO_GRAPHIC 93 163 DESIGN @f@a@d_main 164 VIEW struct.bd 165 GRAPHIC 0,0 96 2 166 DESIGN @f@a@d_main 167 VIEW struct.bd 168 GRAPHIC 4204,0 101 0 169 DESIGN @f@a@d_main 170 VIEW struct.bd 171 GRAPHIC 10008,0 102 0 172 DESIGN @f@a@d_main 173 VIEW struct.bd 174 GRAPHIC 5640,0 103 0 175 DESIGN @f@a@d_main 176 VIEW struct.bd 177 GRAPHIC 5632,0 104 0 178 DESIGN @f@a@d_main 179 VIEW struct.bd 180 GRAPHIC 326,0 105 0 181 DESIGN @f@a@d_main 182 VIEW struct.bd 183 GRAPHIC 5088,0 106 0 184 DESIGN @f@a@d_main 185 VIEW struct.bd 186 GRAPHIC 5104,0 107 0 187 DESIGN @f@a@d_main 188 VIEW struct.bd 189 GRAPHIC 5112,0 108 0 190 DESIGN @f@a@d_main 191 VIEW struct.bd 192 GRAPHIC 5096,0 109 0 193 DESIGN @f@a@d_main 194 VIEW struct.bd 195 GRAPHIC 5128,0 110 0 196 DESIGN @f@a@d_main 197 VIEW struct.bd 198 GRAPHIC 2592,0 111 0 199 DESIGN @f@a@d_main 200 VIEW struct.bd 201 GRAPHIC 5196,0 112 0 202 DESIGN @f@a@d_main 203 VIEW struct.bd 204 GRAPHIC 5588,0 113 0 205 DESIGN @f@a@d_main 206 VIEW struct.bd 207 GRAPHIC 2586,0 114 0 208 DESIGN @f@a@d_main 209 VIEW struct.bd 210 GRAPHIC 5194,0 115 0 211 DESIGN @f@a@d_main 212 VIEW struct.bd 213 GRAPHIC 5743,0 116 0 214 DESIGN @f@a@d_main 215 VIEW struct.bd 216 GRAPHIC 5960,0 117 0 217 DESIGN @f@a@d_main 218 VIEW struct.bd 219 GRAPHIC 6014,0 118 0 220 DESIGN @f@a@d_main 221 VIEW struct.bd 222 GRAPHIC 6016,0 119 0 223 DESIGN @f@a@d_main 224 VIEW struct.bd 225 GRAPHIC 6012,0 120 0 226 DESIGN @f@a@d_main 227 VIEW struct.bd 228 GRAPHIC 5120,0 121 0 229 DESIGN @f@a@d_main 230 VIEW struct.bd 231 GRAPHIC 5144,0 122 0 232 DESIGN @f@a@d_main 233 VIEW struct.bd 234 GRAPHIC 332,0 123 0 235 DESIGN @f@a@d_main 236 VIEW struct.bd 237 GRAPHIC 8508,0 124 0 238 DESIGN @f@a@d_main 239 VIEW struct.bd 240 GRAPHIC 8516,0 125 0 241 DESIGN @f@a@d_main 242 VIEW struct.bd 243 GRAPHIC 8583,0 126 0 244 DESIGN @f@a@d_main 245 VIEW struct.bd 246 GRAPHIC 4399,0 127 0 247 DESIGN @f@a@d_main 248 VIEW struct.bd 249 GRAPHIC 4417,0 128 0 250 DESIGN @f@a@d_main 251 VIEW struct.bd 252 GRAPHIC 4741,0 129 0 253 DESIGN @f@a@d_main 254 VIEW struct.bd 255 GRAPHIC 4405,0 130 0 256 DESIGN @f@a@d_main 257 VIEW struct.bd 258 GRAPHIC 6544,0 131 0 259 DESIGN @f@a@d_main 260 VIEW struct.bd 261 GRAPHIC 6450,0 132 0 262 DESIGN @f@a@d_main 263 VIEW struct.bd 264 GRAPHIC 5948,0 133 0 265 DESIGN @f@a@d_main 266 VIEW struct.bd 267 GRAPHIC 2640,0 134 0 268 DESIGN @f@a@d_main 269 VIEW struct.bd 270 GRAPHIC 9231,0 135 0 271 DESIGN @f@a@d_main 272 VIEW struct.bd 273 GRAPHIC 9239,0 136 0 274 DESIGN @f@a@d_main 275 VIEW struct.bd 276 GRAPHIC 9941,0 137 0 277 DESIGN @f@a@d_main 278 VIEW struct.bd 279 GRAPHIC 362,0 138 0 280 DESIGN @f@a@d_main 281 VIEW struct.bd 282 GRAPHIC 368,0 139 0 283 DESIGN @f@a@d_main 284 VIEW struct.bd 285 GRAPHIC 2297,0 140 0 286 DESIGN @f@a@d_main 287 VIEW struct.bd 288 GRAPHIC 2574,0 141 0 289 DESIGN @f@a@d_main 290 VIEW struct.bd 291 GRAPHIC 2580,0 142 0 292 DESIGN @f@a@d_main 293 VIEW struct.bd 294 GRAPHIC 2924,0 143 0 295 DESIGN @f@a@d_main 296 VIEW struct.bd 297 GRAPHIC 2598,0 144 0 298 DESIGN @f@a@d_main 299 VIEW struct.bd 300 GRAPHIC 5279,0 145 0 301 DESIGN @f@a@d_main 302 VIEW struct.bd 303 GRAPHIC 8730,0 146 0 304 DESIGN @f@a@d_main 305 VIEW struct.bd 306 GRAPHIC 8746,0 147 0 307 DESIGN @f@a@d_main 308 VIEW struct.bd 309 GRAPHIC 5478,0 148 0 310 DESIGN @f@a@d_main 311 VIEW struct.bd 312 GRAPHIC 5472,0 149 0 313 DESIGN @f@a@d_main 314 VIEW struct.bd 315 GRAPHIC 9949,0 150 0 316 DESIGN @f@a@d_main 317 VIEW struct.bd 318 GRAPHIC 1981,0 151 0 319 DESIGN @f@a@d_main 320 VIEW struct.bd 321 GRAPHIC 8414,0 152 0 322 DESIGN @f@a@d_main 323 VIEW struct.bd 324 GRAPHIC 2468,0 153 0 325 DESIGN @f@a@d_main 326 VIEW struct.bd 327 GRAPHIC 2492,0 154 0 328 DESIGN @f@a@d_main 329 VIEW struct.bd 330 GRAPHIC 2486,0 155 0 331 DESIGN @f@a@d_main 332 VIEW struct.bd 333 GRAPHIC 2474,0 156 0 334 DESIGN @f@a@d_main 335 VIEW struct.bd 336 GRAPHIC 2498,0 157 0 337 DESIGN @f@a@d_main 338 VIEW struct.bd 339 GRAPHIC 2504,0 158 0 340 DESIGN @f@a@d_main 341 VIEW struct.bd 342 GRAPHIC 2480,0 159 0 343 DESIGN @f@a@d_main 344 VIEW struct.bd 345 GRAPHIC 320,0 160 0 346 DESIGN @f@a@d_main 347 VIEW struct.bd 348 NO_GRAPHIC 161 349 DESIGN @f@a@d_main 350 VIEW struct.bd 351 GRAPHIC 6276,0 163 0 352 DESIGN @f@a@d_main 353 VIEW struct.bd 354 GRAPHIC 3888,0 164 0 355 DESIGN @f@a@d_main 356 VIEW struct.bd 357 NO_GRAPHIC 166 155 VIEW symbol.sb 156 GRAPHIC 1,0 70 0 157 DESIGN @f@a@d_main 158 VIEW struct.bd 159 NO_GRAPHIC 73 160 DESIGN @f@a@d_main 161 VIEW struct.bd 162 GRAPHIC 41,0 82 0 163 DESIGN @f@a@d_main 164 VIEW struct.bd 165 NO_GRAPHIC 94 166 DESIGN @f@a@d_main 167 VIEW struct.bd 168 GRAPHIC 0,0 97 2 169 DESIGN @f@a@d_main 170 VIEW struct.bd 171 GRAPHIC 4204,0 102 0 172 DESIGN @f@a@d_main 173 VIEW struct.bd 174 GRAPHIC 10008,0 103 0 175 DESIGN @f@a@d_main 176 VIEW struct.bd 177 GRAPHIC 5640,0 104 0 178 DESIGN @f@a@d_main 179 VIEW struct.bd 180 GRAPHIC 5632,0 105 0 181 DESIGN @f@a@d_main 182 VIEW struct.bd 183 GRAPHIC 326,0 106 0 184 DESIGN @f@a@d_main 185 VIEW struct.bd 186 GRAPHIC 5088,0 107 0 187 DESIGN @f@a@d_main 188 VIEW struct.bd 189 GRAPHIC 5104,0 108 0 190 DESIGN @f@a@d_main 191 VIEW struct.bd 192 GRAPHIC 5112,0 109 0 193 DESIGN @f@a@d_main 194 VIEW struct.bd 195 GRAPHIC 5096,0 110 0 196 DESIGN @f@a@d_main 197 VIEW struct.bd 198 GRAPHIC 5128,0 111 0 199 DESIGN @f@a@d_main 200 VIEW struct.bd 201 GRAPHIC 2592,0 112 0 202 DESIGN @f@a@d_main 203 VIEW struct.bd 204 GRAPHIC 5196,0 113 0 205 DESIGN @f@a@d_main 206 VIEW struct.bd 207 GRAPHIC 5588,0 114 0 208 DESIGN @f@a@d_main 209 VIEW struct.bd 210 GRAPHIC 10192,0 116 0 211 DESIGN @f@a@d_main 212 VIEW struct.bd 213 GRAPHIC 10200,0 118 0 214 DESIGN @f@a@d_main 215 VIEW struct.bd 216 GRAPHIC 2586,0 119 0 217 DESIGN @f@a@d_main 218 VIEW struct.bd 219 GRAPHIC 5194,0 120 0 220 DESIGN @f@a@d_main 221 VIEW struct.bd 222 GRAPHIC 5743,0 121 0 223 DESIGN @f@a@d_main 224 VIEW struct.bd 225 GRAPHIC 5960,0 122 0 226 DESIGN @f@a@d_main 227 VIEW struct.bd 228 GRAPHIC 6014,0 123 0 229 DESIGN @f@a@d_main 230 VIEW struct.bd 231 GRAPHIC 6016,0 124 0 232 DESIGN @f@a@d_main 233 VIEW struct.bd 234 GRAPHIC 6012,0 125 0 235 DESIGN @f@a@d_main 236 VIEW struct.bd 237 GRAPHIC 5120,0 126 0 238 DESIGN @f@a@d_main 239 VIEW struct.bd 240 GRAPHIC 5144,0 127 0 241 DESIGN @f@a@d_main 242 VIEW struct.bd 243 GRAPHIC 332,0 128 0 244 DESIGN @f@a@d_main 245 VIEW struct.bd 246 GRAPHIC 8508,0 129 0 247 DESIGN @f@a@d_main 248 VIEW struct.bd 249 GRAPHIC 8516,0 130 0 250 DESIGN @f@a@d_main 251 VIEW struct.bd 252 GRAPHIC 8583,0 131 0 253 DESIGN @f@a@d_main 254 VIEW struct.bd 255 GRAPHIC 4399,0 132 0 256 DESIGN @f@a@d_main 257 VIEW struct.bd 258 GRAPHIC 4417,0 133 0 259 DESIGN @f@a@d_main 260 VIEW struct.bd 261 GRAPHIC 4741,0 134 0 262 DESIGN @f@a@d_main 263 VIEW struct.bd 264 GRAPHIC 4405,0 135 0 265 DESIGN @f@a@d_main 266 VIEW struct.bd 267 GRAPHIC 10314,0 136 0 268 DESIGN @f@a@d_main 269 VIEW struct.bd 270 GRAPHIC 6544,0 137 0 271 DESIGN @f@a@d_main 272 VIEW struct.bd 273 GRAPHIC 6450,0 138 0 274 DESIGN @f@a@d_main 275 VIEW struct.bd 276 GRAPHIC 5948,0 139 0 277 DESIGN @f@a@d_main 278 VIEW struct.bd 279 GRAPHIC 2640,0 140 0 280 DESIGN @f@a@d_main 281 VIEW struct.bd 282 GRAPHIC 9231,0 141 0 283 DESIGN @f@a@d_main 284 VIEW struct.bd 285 GRAPHIC 9239,0 142 0 286 DESIGN @f@a@d_main 287 VIEW struct.bd 288 GRAPHIC 9941,0 143 0 289 DESIGN @f@a@d_main 290 VIEW struct.bd 291 GRAPHIC 362,0 144 0 292 DESIGN @f@a@d_main 293 VIEW struct.bd 294 GRAPHIC 368,0 145 0 295 DESIGN @f@a@d_main 296 VIEW struct.bd 297 GRAPHIC 2297,0 146 0 298 DESIGN @f@a@d_main 299 VIEW struct.bd 300 GRAPHIC 2574,0 147 0 301 DESIGN @f@a@d_main 302 VIEW struct.bd 303 GRAPHIC 2580,0 148 0 304 DESIGN @f@a@d_main 305 VIEW struct.bd 306 GRAPHIC 10465,0 150 0 307 DESIGN @f@a@d_main 308 VIEW struct.bd 309 GRAPHIC 2924,0 151 0 310 DESIGN @f@a@d_main 311 VIEW struct.bd 312 GRAPHIC 2598,0 152 0 313 DESIGN @f@a@d_main 314 VIEW struct.bd 315 GRAPHIC 10264,0 153 0 316 DESIGN @f@a@d_main 317 VIEW struct.bd 318 GRAPHIC 8730,0 154 0 319 DESIGN @f@a@d_main 320 VIEW struct.bd 321 GRAPHIC 8746,0 155 0 322 DESIGN @f@a@d_main 323 VIEW struct.bd 324 GRAPHIC 5478,0 156 0 325 DESIGN @f@a@d_main 326 VIEW struct.bd 327 GRAPHIC 5472,0 157 0 328 DESIGN @f@a@d_main 329 VIEW struct.bd 330 GRAPHIC 9949,0 158 0 331 DESIGN @f@a@d_main 332 VIEW struct.bd 333 GRAPHIC 10302,0 159 0 334 DESIGN @f@a@d_main 335 VIEW struct.bd 336 GRAPHIC 10308,0 160 0 337 DESIGN @f@a@d_main 338 VIEW struct.bd 339 GRAPHIC 10296,0 161 0 340 DESIGN @f@a@d_main 341 VIEW struct.bd 342 GRAPHIC 1981,0 162 0 343 DESIGN @f@a@d_main 344 VIEW struct.bd 345 GRAPHIC 10449,0 163 0 346 DESIGN @f@a@d_main 347 VIEW struct.bd 348 GRAPHIC 8414,0 164 0 349 DESIGN @f@a@d_main 350 VIEW struct.bd 351 GRAPHIC 2468,0 165 0 352 DESIGN @f@a@d_main 353 VIEW struct.bd 354 GRAPHIC 2492,0 166 0 355 DESIGN @f@a@d_main 356 VIEW struct.bd 357 GRAPHIC 2486,0 167 0 358 DESIGN @f@a@d_main 359 VIEW struct.bd 360 GRAPHIC 2474,0 168 0 361 DESIGN @f@a@d_main 362 VIEW struct.bd 363 GRAPHIC 2498,0 169 0 364 DESIGN @f@a@d_main 365 VIEW struct.bd 366 GRAPHIC 2504,0 170 0 367 DESIGN @f@a@d_main 368 VIEW struct.bd 369 GRAPHIC 2480,0 171 0 370 DESIGN @f@a@d_main 371 VIEW struct.bd 372 GRAPHIC 320,0 172 0 373 DESIGN @f@a@d_main 374 VIEW struct.bd 375 NO_GRAPHIC 173 376 DESIGN @f@a@d_main 377 VIEW struct.bd 378 GRAPHIC 6276,0 175 0 379 DESIGN @f@a@d_main 380 VIEW struct.bd 381 GRAPHIC 3888,0 176 0 382 DESIGN @f@a@d_main 383 VIEW struct.bd 384 NO_GRAPHIC 178 358 385 LIBRARY FACT_FAD_lib 359 386 DESIGN adc_buffer 360 387 VIEW beha 361 GRAPHIC 5678,0 1 680362 DESIGN @f@a@d_main 363 VIEW struct.bd 364 NO_GRAPHIC 1 75365 DESIGN @f@a@d_main 366 VIEW struct.bd 367 GRAPHIC 9175,0 1 770388 GRAPHIC 5678,0 180 0 389 DESIGN @f@a@d_main 390 VIEW struct.bd 391 NO_GRAPHIC 187 392 DESIGN @f@a@d_main 393 VIEW struct.bd 394 GRAPHIC 9175,0 189 0 368 395 DESIGN clock_generator_var_ps 369 396 VIEW symbol.sb 370 GRAPHIC 168,0 1 790397 GRAPHIC 168,0 191 0 371 398 DESIGN clock_generator_var_ps 372 399 VIEW symbol.sb 373 GRAPHIC 848,0 1 800400 GRAPHIC 848,0 192 0 374 401 DESIGN clock_generator_var_ps 375 402 VIEW symbol.sb 376 GRAPHIC 703,0 1 810403 GRAPHIC 703,0 193 0 377 404 DESIGN clock_generator_var_ps 378 405 VIEW symbol.sb 379 GRAPHIC 698,0 1 820406 GRAPHIC 698,0 194 0 380 407 DESIGN clock_generator_var_ps 381 408 VIEW symbol.sb 382 GRAPHIC 126,0 1 830409 GRAPHIC 126,0 195 0 383 410 DESIGN clock_generator_var_ps 384 411 VIEW symbol.sb 385 GRAPHIC 643,0 1 840412 GRAPHIC 643,0 196 0 386 413 DESIGN clock_generator_var_ps 387 414 VIEW symbol.sb 388 GRAPHIC 121,0 1 850415 GRAPHIC 121,0 197 0 389 416 DESIGN clock_generator_var_ps 390 417 VIEW symbol.sb 391 GRAPHIC 481,0 1 860418 GRAPHIC 481,0 198 0 392 419 DESIGN clock_generator_var_ps 393 420 VIEW symbol.sb 394 GRAPHIC 544,0 1 870421 GRAPHIC 544,0 199 0 395 422 DESIGN clock_generator_var_ps 396 423 VIEW symbol.sb 397 GRAPHIC 524,0 1880424 GRAPHIC 524,0 200 0 398 425 DESIGN clock_generator_var_ps 399 426 VIEW symbol.sb 400 GRAPHIC 539,0 1890427 GRAPHIC 539,0 201 0 401 428 DESIGN clock_generator_var_ps 402 429 VIEW symbol.sb 403 GRAPHIC 529,0 1900430 GRAPHIC 529,0 202 0 404 431 DESIGN clock_generator_var_ps 405 432 VIEW symbol.sb 406 GRAPHIC 534,0 1910433 GRAPHIC 534,0 203 0 407 434 DESIGN clock_generator_var_ps 408 435 VIEW symbol.sb 409 GRAPHIC 475,0 1920436 GRAPHIC 475,0 204 0 410 437 DESIGN clock_generator_var_ps 411 438 VIEW symbol.sb 412 GRAPHIC 463,0 1930439 GRAPHIC 463,0 205 0 413 440 DESIGN clock_generator_var_ps 414 441 VIEW symbol.sb 415 GRAPHIC 469,0 1940416 DESIGN @f@a@d_main 417 VIEW struct.bd 418 GRAPHIC 5072,0 1980442 GRAPHIC 469,0 206 0 443 DESIGN @f@a@d_main 444 VIEW struct.bd 445 GRAPHIC 5072,0 210 0 419 446 DESIGN control_unit 420 447 VIEW symbol.sb 421 GRAPHIC 130,0 2 000448 GRAPHIC 130,0 212 0 422 449 DESIGN control_unit 423 450 VIEW symbol.sb 424 GRAPHIC 135,0 2 010451 GRAPHIC 135,0 213 0 425 452 DESIGN control_unit 426 453 VIEW symbol.sb 427 GRAPHIC 170,0 2 020454 GRAPHIC 170,0 214 0 428 455 DESIGN control_unit 429 456 VIEW symbol.sb 430 GRAPHIC 175,0 2 030457 GRAPHIC 175,0 215 0 431 458 DESIGN control_unit 432 459 VIEW symbol.sb 433 GRAPHIC 160,0 2 040460 GRAPHIC 160,0 216 0 434 461 DESIGN control_unit 435 462 VIEW symbol.sb 436 GRAPHIC 145,0 2 050463 GRAPHIC 145,0 217 0 437 464 DESIGN control_unit 438 465 VIEW symbol.sb 439 GRAPHIC 140,0 2 060466 GRAPHIC 140,0 218 0 440 467 DESIGN control_unit 441 468 VIEW symbol.sb 442 GRAPHIC 180,0 2 070469 GRAPHIC 180,0 219 0 443 470 DESIGN control_unit 444 471 VIEW symbol.sb 445 GRAPHIC 350,0 2080472 GRAPHIC 558,0 220 0 446 473 DESIGN control_unit 447 474 VIEW symbol.sb 448 GRAPHIC 165,0 2090475 GRAPHIC 564,0 222 0 449 476 DESIGN control_unit 450 477 VIEW symbol.sb 451 GRAPHIC 521,0 2100478 GRAPHIC 350,0 224 0 452 479 DESIGN control_unit 453 480 VIEW symbol.sb 454 GRAPHIC 526,0 2110481 GRAPHIC 165,0 225 0 455 482 DESIGN control_unit 456 483 VIEW symbol.sb 457 GRAPHIC 155,0 2 120484 GRAPHIC 155,0 226 0 458 485 DESIGN control_unit 459 486 VIEW symbol.sb 460 GRAPHIC 150,0 2 130461 DESIGN @f@a@d_main 462 VIEW struct.bd 463 GRAPHIC 8277,0 2 160487 GRAPHIC 150,0 227 0 488 DESIGN @f@a@d_main 489 VIEW struct.bd 490 GRAPHIC 8277,0 230 0 464 491 DESIGN data@r@a@m_64b_16b_width14_5 465 492 VIEW data@r@a@m_64b_16b_width14_5_a 466 GRAPHIC 48,0 2 180493 GRAPHIC 48,0 232 0 467 494 DESIGN data@r@a@m_64b_16b_width14_5 468 495 VIEW data@r@a@m_64b_16b_width14_5_a 469 GRAPHIC 53,0 2 190496 GRAPHIC 53,0 233 0 470 497 DESIGN data@r@a@m_64b_16b_width14_5 471 498 VIEW data@r@a@m_64b_16b_width14_5_a 472 GRAPHIC 58,0 2 200499 GRAPHIC 58,0 234 0 473 500 DESIGN data@r@a@m_64b_16b_width14_5 474 501 VIEW data@r@a@m_64b_16b_width14_5_a 475 GRAPHIC 63,0 2 210502 GRAPHIC 63,0 235 0 476 503 DESIGN data@r@a@m_64b_16b_width14_5 477 504 VIEW data@r@a@m_64b_16b_width14_5_a 478 GRAPHIC 68,0 2 220505 GRAPHIC 68,0 236 0 479 506 DESIGN data@r@a@m_64b_16b_width14_5 480 507 VIEW data@r@a@m_64b_16b_width14_5_a 481 GRAPHIC 73,0 2 230508 GRAPHIC 73,0 237 0 482 509 DESIGN data@r@a@m_64b_16b_width14_5 483 510 VIEW data@r@a@m_64b_16b_width14_5_a 484 GRAPHIC 78,0 224 0 485 DESIGN @f@a@d_main 486 VIEW struct.bd 487 GRAPHIC 1399,0 227 0 488 DESIGN data_generator 489 VIEW symbol.sb 490 GRAPHIC 14,0 228 1 491 DESIGN data_generator 492 VIEW @behavioral 493 GRAPHIC 48,0 232 0 494 DESIGN data_generator 495 VIEW @behavioral 496 GRAPHIC 53,0 233 0 497 DESIGN data_generator 498 VIEW @behavioral 499 GRAPHIC 58,0 234 0 500 DESIGN data_generator 501 VIEW @behavioral 502 GRAPHIC 73,0 235 0 503 DESIGN data_generator 504 VIEW @behavioral 505 GRAPHIC 78,0 236 0 506 DESIGN data_generator 507 VIEW @behavioral 508 GRAPHIC 402,0 237 0 509 DESIGN data_generator 510 VIEW @behavioral 511 GRAPHIC 407,0 238 0 512 DESIGN data_generator 513 VIEW @behavioral 514 GRAPHIC 1122,0 239 0 515 DESIGN data_generator 516 VIEW @behavioral 517 GRAPHIC 963,0 240 0 518 DESIGN data_generator 519 VIEW @behavioral 520 GRAPHIC 1127,0 241 0 521 DESIGN data_generator 522 VIEW @behavioral 523 GRAPHIC 1048,0 242 0 524 DESIGN data_generator 525 VIEW @behavioral 526 GRAPHIC 958,0 243 0 527 DESIGN data_generator 528 VIEW @behavioral 529 GRAPHIC 1053,0 244 0 530 DESIGN data_generator 531 VIEW @behavioral 532 GRAPHIC 1201,0 245 0 533 DESIGN data_generator 534 VIEW @behavioral 535 GRAPHIC 1196,0 246 0 536 DESIGN data_generator 537 VIEW @behavioral 538 GRAPHIC 1206,0 247 0 539 DESIGN data_generator 540 VIEW @behavioral 541 GRAPHIC 473,0 248 0 542 DESIGN data_generator 543 VIEW @behavioral 544 GRAPHIC 412,0 249 0 545 DESIGN data_generator 546 VIEW @behavioral 547 GRAPHIC 1085,0 250 0 548 DESIGN data_generator 549 VIEW @behavioral 550 GRAPHIC 1090,0 251 0 551 DESIGN data_generator 552 VIEW @behavioral 553 GRAPHIC 1240,0 252 0 554 DESIGN data_generator 555 VIEW @behavioral 556 GRAPHIC 526,0 253 0 557 DESIGN data_generator 558 VIEW @behavioral 559 GRAPHIC 88,0 254 0 560 DESIGN data_generator 561 VIEW @behavioral 562 GRAPHIC 285,0 255 0 563 DESIGN data_generator 564 VIEW @behavioral 565 GRAPHIC 93,0 256 0 566 DESIGN data_generator 567 VIEW @behavioral 568 GRAPHIC 98,0 257 0 569 DESIGN data_generator 570 VIEW @behavioral 571 GRAPHIC 1018,0 258 0 572 DESIGN data_generator 573 VIEW @behavioral 574 GRAPHIC 1164,0 259 0 575 DESIGN data_generator 576 VIEW @behavioral 577 GRAPHIC 1159,0 260 0 578 DESIGN data_generator 579 VIEW @behavioral 580 GRAPHIC 898,0 261 0 581 DESIGN data_generator 582 VIEW @behavioral 583 GRAPHIC 637,0 262 0 584 DESIGN data_generator 585 VIEW @behavioral 586 GRAPHIC 1395,0 263 0 587 DESIGN data_generator 588 VIEW @behavioral 589 GRAPHIC 1427,0 264 0 590 DESIGN data_generator 591 VIEW @behavioral 592 GRAPHIC 676,0 265 0 593 DESIGN data_generator 594 VIEW @behavioral 595 GRAPHIC 845,0 266 0 596 DESIGN data_generator 597 VIEW @behavioral 598 GRAPHIC 681,0 267 0 599 DESIGN data_generator 600 VIEW @behavioral 601 GRAPHIC 801,0 268 0 602 DESIGN data_generator 603 VIEW @behavioral 604 GRAPHIC 806,0 269 0 605 DESIGN data_generator 606 VIEW @behavioral 607 GRAPHIC 811,0 270 0 608 DESIGN @f@a@d_main 609 VIEW struct.bd 610 GRAPHIC 4903,0 273 0 611 DESIGN @f@a@d_main 612 VIEW struct.bd 613 NO_GRAPHIC 286 614 DESIGN @f@a@d_main 615 VIEW struct.bd 616 GRAPHIC 2311,0 288 0 617 DESIGN memory_manager 618 VIEW symbol.sb 619 GRAPHIC 14,0 289 1 620 DESIGN memory_manager 621 VIEW beha 622 GRAPHIC 138,0 294 0 623 DESIGN memory_manager 624 VIEW beha 625 GRAPHIC 194,0 295 0 626 DESIGN memory_manager 627 VIEW beha 628 GRAPHIC 349,0 296 0 629 DESIGN memory_manager 630 VIEW beha 631 GRAPHIC 569,0 297 0 632 DESIGN memory_manager 633 VIEW beha 634 GRAPHIC 224,0 298 0 635 DESIGN memory_manager 636 VIEW beha 637 GRAPHIC 254,0 299 0 638 DESIGN memory_manager 639 VIEW beha 640 GRAPHIC 804,0 300 0 641 DESIGN memory_manager 642 VIEW beha 643 GRAPHIC 433,0 301 0 644 DESIGN memory_manager 645 VIEW beha 646 GRAPHIC 622,0 302 0 647 DESIGN memory_manager 648 VIEW beha 649 GRAPHIC 289,0 303 0 650 DESIGN memory_manager 651 VIEW beha 652 GRAPHIC 309,0 304 0 653 DESIGN memory_manager 654 VIEW beha 655 GRAPHIC 284,0 305 0 656 DESIGN memory_manager 657 VIEW beha 658 GRAPHIC 294,0 306 0 659 DESIGN memory_manager 660 VIEW beha 661 GRAPHIC 304,0 307 0 662 DESIGN memory_manager 663 VIEW beha 664 GRAPHIC 299,0 308 0 665 DESIGN memory_manager 666 VIEW beha 667 GRAPHIC 379,0 309 0 668 DESIGN memory_manager 669 VIEW beha 670 GRAPHIC 915,0 310 0 671 DESIGN memory_manager 672 VIEW beha 673 GRAPHIC 51,0 311 0 674 DESIGN @f@a@d_main 675 VIEW struct.bd 676 GRAPHIC 5793,0 314 0 511 GRAPHIC 78,0 238 0 512 DESIGN @f@a@d_main 513 VIEW struct.bd 514 GRAPHIC 1399,0 241 0 515 DESIGN data_generator 516 VIEW symbol.sb 517 GRAPHIC 14,0 242 1 518 DESIGN data_generator 519 VIEW @behavioral 520 GRAPHIC 48,0 246 0 521 DESIGN data_generator 522 VIEW @behavioral 523 GRAPHIC 53,0 248 0 524 DESIGN data_generator 525 VIEW @behavioral 526 GRAPHIC 58,0 249 0 527 DESIGN data_generator 528 VIEW @behavioral 529 GRAPHIC 73,0 250 0 530 DESIGN data_generator 531 VIEW @behavioral 532 GRAPHIC 78,0 251 0 533 DESIGN data_generator 534 VIEW @behavioral 535 GRAPHIC 402,0 252 0 536 DESIGN data_generator 537 VIEW @behavioral 538 GRAPHIC 407,0 253 0 539 DESIGN data_generator 540 VIEW @behavioral 541 GRAPHIC 1479,0 254 0 542 DESIGN data_generator 543 VIEW @behavioral 544 GRAPHIC 1122,0 256 0 545 DESIGN data_generator 546 VIEW @behavioral 547 GRAPHIC 963,0 258 0 548 DESIGN data_generator 549 VIEW @behavioral 550 GRAPHIC 1127,0 260 0 551 DESIGN data_generator 552 VIEW @behavioral 553 GRAPHIC 1048,0 262 0 554 DESIGN data_generator 555 VIEW @behavioral 556 GRAPHIC 958,0 263 0 557 DESIGN data_generator 558 VIEW @behavioral 559 GRAPHIC 1053,0 264 0 560 DESIGN data_generator 561 VIEW @behavioral 562 GRAPHIC 1201,0 265 0 563 DESIGN data_generator 564 VIEW @behavioral 565 GRAPHIC 1196,0 266 0 566 DESIGN data_generator 567 VIEW @behavioral 568 GRAPHIC 1206,0 267 0 569 DESIGN data_generator 570 VIEW @behavioral 571 GRAPHIC 473,0 268 0 572 DESIGN data_generator 573 VIEW @behavioral 574 GRAPHIC 412,0 269 0 575 DESIGN data_generator 576 VIEW @behavioral 577 GRAPHIC 1085,0 270 0 578 DESIGN data_generator 579 VIEW @behavioral 580 GRAPHIC 1090,0 271 0 581 DESIGN data_generator 582 VIEW @behavioral 583 GRAPHIC 1240,0 272 0 584 DESIGN data_generator 585 VIEW @behavioral 586 GRAPHIC 526,0 273 0 587 DESIGN data_generator 588 VIEW @behavioral 589 GRAPHIC 88,0 274 0 590 DESIGN data_generator 591 VIEW @behavioral 592 GRAPHIC 285,0 275 0 593 DESIGN data_generator 594 VIEW @behavioral 595 GRAPHIC 93,0 276 0 596 DESIGN data_generator 597 VIEW @behavioral 598 GRAPHIC 98,0 277 0 599 DESIGN data_generator 600 VIEW @behavioral 601 GRAPHIC 1164,0 278 0 602 DESIGN data_generator 603 VIEW @behavioral 604 GRAPHIC 1159,0 280 0 605 DESIGN data_generator 606 VIEW @behavioral 607 GRAPHIC 898,0 281 0 608 DESIGN data_generator 609 VIEW @behavioral 610 GRAPHIC 637,0 282 0 611 DESIGN data_generator 612 VIEW @behavioral 613 GRAPHIC 1395,0 283 0 614 DESIGN data_generator 615 VIEW @behavioral 616 GRAPHIC 1427,0 284 0 617 DESIGN data_generator 618 VIEW @behavioral 619 GRAPHIC 676,0 285 0 620 DESIGN data_generator 621 VIEW @behavioral 622 GRAPHIC 845,0 286 0 623 DESIGN data_generator 624 VIEW @behavioral 625 GRAPHIC 681,0 287 0 626 DESIGN data_generator 627 VIEW @behavioral 628 GRAPHIC 801,0 288 0 629 DESIGN data_generator 630 VIEW @behavioral 631 GRAPHIC 1464,0 289 0 632 DESIGN data_generator 633 VIEW @behavioral 634 GRAPHIC 1469,0 290 0 635 DESIGN data_generator 636 VIEW @behavioral 637 GRAPHIC 1459,0 291 0 638 DESIGN data_generator 639 VIEW @behavioral 640 GRAPHIC 1474,0 292 0 641 DESIGN data_generator 642 VIEW @behavioral 643 GRAPHIC 806,0 293 0 644 DESIGN data_generator 645 VIEW @behavioral 646 GRAPHIC 811,0 294 0 647 DESIGN @f@a@d_main 648 VIEW struct.bd 649 GRAPHIC 4903,0 297 0 650 DESIGN @f@a@d_main 651 VIEW struct.bd 652 NO_GRAPHIC 315 653 DESIGN @f@a@d_main 654 VIEW struct.bd 655 GRAPHIC 2311,0 317 0 656 DESIGN memory_manager 657 VIEW symbol.sb 658 GRAPHIC 14,0 318 1 659 DESIGN memory_manager 660 VIEW beha 661 GRAPHIC 138,0 323 0 662 DESIGN memory_manager 663 VIEW beha 664 GRAPHIC 194,0 324 0 665 DESIGN memory_manager 666 VIEW beha 667 GRAPHIC 349,0 325 0 668 DESIGN memory_manager 669 VIEW beha 670 GRAPHIC 949,0 326 0 671 DESIGN memory_manager 672 VIEW beha 673 GRAPHIC 569,0 328 0 674 DESIGN memory_manager 675 VIEW beha 676 GRAPHIC 224,0 330 0 677 DESIGN memory_manager 678 VIEW beha 679 GRAPHIC 254,0 331 0 680 DESIGN memory_manager 681 VIEW beha 682 GRAPHIC 804,0 332 0 683 DESIGN memory_manager 684 VIEW beha 685 GRAPHIC 433,0 333 0 686 DESIGN memory_manager 687 VIEW beha 688 GRAPHIC 622,0 334 0 689 DESIGN memory_manager 690 VIEW beha 691 GRAPHIC 289,0 335 0 692 DESIGN memory_manager 693 VIEW beha 694 GRAPHIC 309,0 336 0 695 DESIGN memory_manager 696 VIEW beha 697 GRAPHIC 284,0 337 0 698 DESIGN memory_manager 699 VIEW beha 700 GRAPHIC 294,0 338 0 701 DESIGN memory_manager 702 VIEW beha 703 GRAPHIC 304,0 339 0 704 DESIGN memory_manager 705 VIEW beha 706 GRAPHIC 299,0 340 0 707 DESIGN memory_manager 708 VIEW beha 709 GRAPHIC 379,0 341 0 710 DESIGN memory_manager 711 VIEW beha 712 GRAPHIC 915,0 342 0 713 DESIGN memory_manager 714 VIEW beha 715 GRAPHIC 51,0 343 0 716 DESIGN @f@a@d_main 717 VIEW struct.bd 718 GRAPHIC 5793,0 346 0 677 719 DESIGN spi_interface 678 720 VIEW symbol.sb 679 GRAPHIC 1121,0 3 160721 GRAPHIC 1121,0 348 0 680 722 DESIGN spi_interface 681 723 VIEW symbol.sb 682 GRAPHIC 326,0 3 170724 GRAPHIC 326,0 349 0 683 725 DESIGN spi_interface 684 726 VIEW symbol.sb 685 GRAPHIC 197,0 3 180727 GRAPHIC 197,0 350 0 686 728 DESIGN spi_interface 687 729 VIEW symbol.sb 688 GRAPHIC 321,0 3 190730 GRAPHIC 321,0 351 0 689 731 DESIGN spi_interface 690 732 VIEW symbol.sb 691 GRAPHIC 1198,0 3 200733 GRAPHIC 1198,0 352 0 692 734 DESIGN spi_interface 693 735 VIEW symbol.sb 694 GRAPHIC 1017,0 3 210736 GRAPHIC 1017,0 353 0 695 737 DESIGN spi_interface 696 738 VIEW symbol.sb 697 GRAPHIC 1229,0 3 220739 GRAPHIC 1229,0 354 0 698 740 DESIGN spi_interface 699 741 VIEW symbol.sb 700 GRAPHIC 126,0 3 230742 GRAPHIC 126,0 355 0 701 743 DESIGN spi_interface 702 744 VIEW symbol.sb 703 GRAPHIC 819,0 3 240745 GRAPHIC 819,0 356 0 704 746 DESIGN spi_interface 705 747 VIEW symbol.sb 706 GRAPHIC 1022,0 3 250748 GRAPHIC 1022,0 357 0 707 749 DESIGN spi_interface 708 750 VIEW symbol.sb 709 GRAPHIC 824,0 3 260751 GRAPHIC 824,0 358 0 710 752 DESIGN spi_interface 711 753 VIEW symbol.sb 712 GRAPHIC 1283,0 3 270713 DESIGN @f@a@d_main 714 VIEW struct.bd 715 GRAPHIC 1768,0 3 300754 GRAPHIC 1283,0 359 0 755 DESIGN @f@a@d_main 756 VIEW struct.bd 757 GRAPHIC 1768,0 362 0 716 758 DESIGN trigger_counter 717 759 VIEW beha 718 GRAPHIC 48,0 3 320760 GRAPHIC 48,0 364 0 719 761 DESIGN trigger_counter 720 762 VIEW beha 721 GRAPHIC 53,0 3 330763 GRAPHIC 53,0 365 0 722 764 DESIGN trigger_counter 723 765 VIEW beha 724 GRAPHIC 148,0 334 0 725 DESIGN @f@a@d_main 726 VIEW struct.bd 727 GRAPHIC 1606,0 337 0 728 DESIGN w5300_modul 729 VIEW symbol.sb 730 GRAPHIC 14,0 338 1 731 DESIGN w5300_modul 732 VIEW @behavioral 733 GRAPHIC 48,0 342 0 734 DESIGN w5300_modul 735 VIEW @behavioral 736 GRAPHIC 53,0 343 0 737 DESIGN w5300_modul 738 VIEW @behavioral 739 GRAPHIC 58,0 344 0 740 DESIGN w5300_modul 741 VIEW @behavioral 742 GRAPHIC 63,0 345 0 743 DESIGN w5300_modul 744 VIEW @behavioral 745 GRAPHIC 68,0 346 0 746 DESIGN w5300_modul 747 VIEW @behavioral 748 GRAPHIC 73,0 347 0 749 DESIGN w5300_modul 750 VIEW @behavioral 751 GRAPHIC 491,0 348 0 752 DESIGN w5300_modul 753 VIEW @behavioral 754 GRAPHIC 83,0 349 0 755 DESIGN w5300_modul 756 VIEW @behavioral 757 GRAPHIC 88,0 350 0 758 DESIGN w5300_modul 759 VIEW @behavioral 760 GRAPHIC 93,0 351 0 761 DESIGN w5300_modul 762 VIEW @behavioral 763 GRAPHIC 98,0 352 0 764 DESIGN w5300_modul 765 VIEW @behavioral 766 GRAPHIC 103,0 353 0 767 DESIGN w5300_modul 768 VIEW @behavioral 769 GRAPHIC 108,0 354 0 770 DESIGN w5300_modul 771 VIEW @behavioral 772 GRAPHIC 113,0 355 0 773 DESIGN w5300_modul 774 VIEW @behavioral 775 GRAPHIC 885,0 356 0 776 DESIGN w5300_modul 777 VIEW @behavioral 778 GRAPHIC 118,0 357 0 779 DESIGN w5300_modul 780 VIEW @behavioral 781 GRAPHIC 353,0 358 0 782 DESIGN w5300_modul 783 VIEW @behavioral 784 GRAPHIC 348,0 359 0 785 DESIGN w5300_modul 786 VIEW @behavioral 787 GRAPHIC 385,0 360 0 788 DESIGN w5300_modul 789 VIEW @behavioral 790 GRAPHIC 521,0 361 0 791 DESIGN w5300_modul 792 VIEW @behavioral 793 GRAPHIC 576,0 362 0 794 DESIGN w5300_modul 795 VIEW @behavioral 796 GRAPHIC 566,0 363 0 797 DESIGN w5300_modul 798 VIEW @behavioral 799 GRAPHIC 551,0 364 0 800 DESIGN w5300_modul 801 VIEW @behavioral 802 GRAPHIC 561,0 365 0 803 DESIGN w5300_modul 804 VIEW @behavioral 805 GRAPHIC 571,0 366 0 806 DESIGN w5300_modul 807 VIEW @behavioral 808 GRAPHIC 640,0 367 0 809 DESIGN w5300_modul 810 VIEW @behavioral 811 GRAPHIC 556,0 368 0 812 DESIGN w5300_modul 813 VIEW @behavioral 814 GRAPHIC 670,0 369 0 815 DESIGN w5300_modul 816 VIEW @behavioral 817 GRAPHIC 723,0 370 0 818 DESIGN w5300_modul 819 VIEW @behavioral 820 GRAPHIC 917,0 371 0 821 DESIGN w5300_modul 822 VIEW @behavioral 823 GRAPHIC 949,0 372 0 824 DESIGN w5300_modul 825 VIEW @behavioral 826 GRAPHIC 954,0 373 0 827 DESIGN w5300_modul 828 VIEW @behavioral 829 GRAPHIC 988,0 374 0 830 DESIGN w5300_modul 831 VIEW @behavioral 832 GRAPHIC 1020,0 375 0 766 GRAPHIC 148,0 366 0 767 DESIGN @f@a@d_main 768 VIEW struct.bd 769 GRAPHIC 1606,0 369 0 770 DESIGN w5300_modul 771 VIEW symbol.sb 772 GRAPHIC 14,0 370 1 773 DESIGN w5300_modul 774 VIEW @behavioral 775 GRAPHIC 48,0 374 0 776 DESIGN w5300_modul 777 VIEW @behavioral 778 GRAPHIC 53,0 375 0 779 DESIGN w5300_modul 780 VIEW @behavioral 781 GRAPHIC 58,0 376 0 782 DESIGN w5300_modul 783 VIEW @behavioral 784 GRAPHIC 63,0 377 0 785 DESIGN w5300_modul 786 VIEW @behavioral 787 GRAPHIC 68,0 378 0 788 DESIGN w5300_modul 789 VIEW @behavioral 790 GRAPHIC 73,0 379 0 791 DESIGN w5300_modul 792 VIEW @behavioral 793 GRAPHIC 491,0 380 0 794 DESIGN w5300_modul 795 VIEW @behavioral 796 GRAPHIC 83,0 381 0 797 DESIGN w5300_modul 798 VIEW @behavioral 799 GRAPHIC 88,0 382 0 800 DESIGN w5300_modul 801 VIEW @behavioral 802 GRAPHIC 93,0 383 0 803 DESIGN w5300_modul 804 VIEW @behavioral 805 GRAPHIC 98,0 384 0 806 DESIGN w5300_modul 807 VIEW @behavioral 808 GRAPHIC 103,0 385 0 809 DESIGN w5300_modul 810 VIEW @behavioral 811 GRAPHIC 108,0 386 0 812 DESIGN w5300_modul 813 VIEW @behavioral 814 GRAPHIC 113,0 387 0 815 DESIGN w5300_modul 816 VIEW @behavioral 817 GRAPHIC 885,0 388 0 818 DESIGN w5300_modul 819 VIEW @behavioral 820 GRAPHIC 118,0 389 0 821 DESIGN w5300_modul 822 VIEW @behavioral 823 GRAPHIC 353,0 390 0 824 DESIGN w5300_modul 825 VIEW @behavioral 826 GRAPHIC 348,0 391 0 827 DESIGN w5300_modul 828 VIEW @behavioral 829 GRAPHIC 385,0 392 0 830 DESIGN w5300_modul 831 VIEW @behavioral 832 GRAPHIC 521,0 393 0 833 DESIGN w5300_modul 834 VIEW @behavioral 835 GRAPHIC 576,0 394 0 836 DESIGN w5300_modul 837 VIEW @behavioral 838 GRAPHIC 566,0 395 0 839 DESIGN w5300_modul 840 VIEW @behavioral 841 GRAPHIC 551,0 396 0 842 DESIGN w5300_modul 843 VIEW @behavioral 844 GRAPHIC 561,0 397 0 845 DESIGN w5300_modul 846 VIEW @behavioral 847 GRAPHIC 571,0 398 0 848 DESIGN w5300_modul 849 VIEW @behavioral 850 GRAPHIC 640,0 399 0 851 DESIGN w5300_modul 852 VIEW @behavioral 853 GRAPHIC 1052,0 400 0 854 DESIGN w5300_modul 855 VIEW @behavioral 856 GRAPHIC 1057,0 402 0 857 DESIGN w5300_modul 858 VIEW @behavioral 859 GRAPHIC 556,0 404 0 860 DESIGN w5300_modul 861 VIEW @behavioral 862 GRAPHIC 670,0 406 0 863 DESIGN w5300_modul 864 VIEW @behavioral 865 GRAPHIC 723,0 407 0 866 DESIGN w5300_modul 867 VIEW @behavioral 868 GRAPHIC 917,0 408 0 869 DESIGN w5300_modul 870 VIEW @behavioral 871 GRAPHIC 949,0 409 0 872 DESIGN w5300_modul 873 VIEW @behavioral 874 GRAPHIC 954,0 410 0 875 DESIGN w5300_modul 876 VIEW @behavioral 877 GRAPHIC 988,0 411 0 878 DESIGN w5300_modul 879 VIEW @behavioral 880 GRAPHIC 1020,0 412 0 833 881 LIBRARY FACT_FAD_lib 834 882 DESIGN @f@a@d_main 835 883 VIEW struct.bd 836 NO_GRAPHIC 378 837 DESIGN @f@a@d_main 838 VIEW struct.bd 839 GRAPHIC 5678,0 381 0 840 DESIGN @f@a@d_main 841 VIEW struct.bd 842 GRAPHIC 9175,0 382 0 843 DESIGN @f@a@d_main 844 VIEW struct.bd 845 GRAPHIC 5072,0 383 0 846 DESIGN @f@a@d_main 847 VIEW struct.bd 848 GRAPHIC 8277,0 384 0 849 DESIGN @f@a@d_main 850 VIEW struct.bd 851 GRAPHIC 1399,0 385 0 852 DESIGN @f@a@d_main 853 VIEW struct.bd 854 GRAPHIC 4903,0 386 0 855 DESIGN @f@a@d_main 856 VIEW struct.bd 857 GRAPHIC 2311,0 387 0 858 DESIGN @f@a@d_main 859 VIEW struct.bd 860 GRAPHIC 5793,0 388 0 861 DESIGN @f@a@d_main 862 VIEW struct.bd 863 GRAPHIC 1768,0 389 0 864 DESIGN @f@a@d_main 865 VIEW struct.bd 866 GRAPHIC 1606,0 390 0 867 DESIGN @f@a@d_main 868 VIEW struct.bd 869 NO_GRAPHIC 393 870 DESIGN @f@a@d_main 871 VIEW struct.bd 872 GRAPHIC 6529,0 395 0 873 DESIGN @f@a@d_main 874 VIEW struct.bd 875 GRAPHIC 9957,0 398 0 876 DESIGN @f@a@d_main 877 VIEW struct.bd 878 GRAPHIC 8721,0 401 0 879 DESIGN @f@a@d_main 880 VIEW struct.bd 881 GRAPHIC 9430,0 404 0 882 DESIGN @f@a@d_main 883 VIEW struct.bd 884 GRAPHIC 9472,0 407 0 885 DESIGN @f@a@d_main 886 VIEW struct.bd 887 GRAPHIC 9662,0 410 0 888 DESIGN @f@a@d_main 889 VIEW struct.bd 890 GRAPHIC 9679,0 413 0 891 DESIGN @f@a@d_main 892 VIEW struct.bd 893 GRAPHIC 9710,0 416 0 894 DESIGN @f@a@d_main 895 VIEW struct.bd 896 GRAPHIC 8562,0 419 0 884 NO_GRAPHIC 415 885 DESIGN @f@a@d_main 886 VIEW struct.bd 887 GRAPHIC 5678,0 418 0 888 DESIGN @f@a@d_main 889 VIEW struct.bd 890 GRAPHIC 9175,0 419 0 891 DESIGN @f@a@d_main 892 VIEW struct.bd 893 GRAPHIC 5072,0 420 0 894 DESIGN @f@a@d_main 895 VIEW struct.bd 896 GRAPHIC 8277,0 421 0 897 DESIGN @f@a@d_main 898 VIEW struct.bd 899 GRAPHIC 1399,0 422 0 900 DESIGN @f@a@d_main 901 VIEW struct.bd 902 GRAPHIC 4903,0 423 0 903 DESIGN @f@a@d_main 904 VIEW struct.bd 905 GRAPHIC 2311,0 424 0 906 DESIGN @f@a@d_main 907 VIEW struct.bd 908 GRAPHIC 5793,0 425 0 909 DESIGN @f@a@d_main 910 VIEW struct.bd 911 GRAPHIC 1768,0 426 0 912 DESIGN @f@a@d_main 913 VIEW struct.bd 914 GRAPHIC 1606,0 427 0 897 915 DESIGN @f@a@d_main 898 916 VIEW struct.bd … … 900 918 DESIGN @f@a@d_main 901 919 VIEW struct.bd 902 GRAPHIC 5678,0 432 0 903 DESIGN @f@a@d_main 904 VIEW struct.bd 905 GRAPHIC 5646,0 434 0 906 DESIGN @f@a@d_main 907 VIEW struct.bd 908 GRAPHIC 4272,0 435 0 909 DESIGN @f@a@d_main 910 VIEW struct.bd 911 GRAPHIC 2786,0 436 0 912 DESIGN @f@a@d_main 913 VIEW struct.bd 914 GRAPHIC 5626,0 437 0 915 DESIGN @f@a@d_main 916 VIEW struct.bd 917 GRAPHIC 5634,0 438 0 918 DESIGN @f@a@d_main 919 VIEW struct.bd 920 GRAPHIC 9175,0 440 0 921 DESIGN @f@a@d_main 922 VIEW struct.bd 923 GRAPHIC 4042,0 442 0 924 DESIGN @f@a@d_main 925 VIEW struct.bd 926 GRAPHIC 10036,0 443 0 927 DESIGN @f@a@d_main 928 VIEW struct.bd 929 GRAPHIC 9253,0 444 0 930 DESIGN @f@a@d_main 931 VIEW struct.bd 932 GRAPHIC 9261,0 445 0 933 DESIGN @f@a@d_main 934 VIEW struct.bd 935 GRAPHIC 6072,0 446 0 936 DESIGN @f@a@d_main 937 VIEW struct.bd 938 GRAPHIC 3984,0 447 0 939 DESIGN @f@a@d_main 940 VIEW struct.bd 941 GRAPHIC 3888,0 448 0 942 DESIGN @f@a@d_main 943 VIEW struct.bd 944 GRAPHIC 9353,0 449 0 945 DESIGN @f@a@d_main 946 VIEW struct.bd 947 GRAPHIC 9269,0 450 0 948 DESIGN @f@a@d_main 949 VIEW struct.bd 950 GRAPHIC 9325,0 451 0 951 DESIGN @f@a@d_main 952 VIEW struct.bd 953 GRAPHIC 9283,0 452 0 954 DESIGN @f@a@d_main 955 VIEW struct.bd 956 GRAPHIC 9311,0 453 0 957 DESIGN @f@a@d_main 958 VIEW struct.bd 959 GRAPHIC 9297,0 454 0 960 DESIGN @f@a@d_main 961 VIEW struct.bd 962 GRAPHIC 9367,0 455 0 963 DESIGN @f@a@d_main 964 VIEW struct.bd 965 GRAPHIC 9397,0 456 0 966 DESIGN @f@a@d_main 967 VIEW struct.bd 968 GRAPHIC 9382,0 457 0 969 DESIGN @f@a@d_main 970 VIEW struct.bd 971 GRAPHIC 5072,0 459 0 972 DESIGN @f@a@d_main 973 VIEW struct.bd 974 GRAPHIC 5582,0 461 0 975 DESIGN @f@a@d_main 976 VIEW struct.bd 977 GRAPHIC 5090,0 462 0 978 DESIGN @f@a@d_main 979 VIEW struct.bd 980 GRAPHIC 5130,0 463 0 981 DESIGN @f@a@d_main 982 VIEW struct.bd 983 GRAPHIC 5184,0 464 0 984 DESIGN @f@a@d_main 985 VIEW struct.bd 986 GRAPHIC 5122,0 465 0 987 DESIGN @f@a@d_main 988 VIEW struct.bd 989 GRAPHIC 5106,0 466 0 990 DESIGN @f@a@d_main 991 VIEW struct.bd 992 GRAPHIC 5098,0 467 0 993 DESIGN @f@a@d_main 994 VIEW struct.bd 995 GRAPHIC 5190,0 468 0 996 DESIGN @f@a@d_main 997 VIEW struct.bd 998 GRAPHIC 6002,0 469 0 999 DESIGN @f@a@d_main 1000 VIEW struct.bd 1001 GRAPHIC 5146,0 470 0 1002 DESIGN @f@a@d_main 1003 VIEW struct.bd 1004 GRAPHIC 8510,0 471 0 1005 DESIGN @f@a@d_main 1006 VIEW struct.bd 1007 GRAPHIC 8518,0 472 0 1008 DESIGN @f@a@d_main 1009 VIEW struct.bd 1010 GRAPHIC 5138,0 473 0 1011 DESIGN @f@a@d_main 1012 VIEW struct.bd 1013 GRAPHIC 5114,0 474 0 1014 DESIGN @f@a@d_main 1015 VIEW struct.bd 1016 GRAPHIC 8277,0 476 0 1017 DESIGN @f@a@d_main 1018 VIEW struct.bd 1019 GRAPHIC 5602,0 478 0 1020 DESIGN @f@a@d_main 1021 VIEW struct.bd 1022 GRAPHIC 334,0 479 0 1023 DESIGN @f@a@d_main 1024 VIEW struct.bd 1025 GRAPHIC 328,0 480 0 1026 DESIGN @f@a@d_main 1027 VIEW struct.bd 1028 GRAPHIC 322,0 481 0 1029 DESIGN @f@a@d_main 1030 VIEW struct.bd 1031 GRAPHIC 4240,0 482 0 1032 DESIGN @f@a@d_main 1033 VIEW struct.bd 1034 GRAPHIC 364,0 483 0 1035 DESIGN @f@a@d_main 1036 VIEW struct.bd 1037 GRAPHIC 370,0 484 0 1038 DESIGN @f@a@d_main 1039 VIEW struct.bd 1040 GRAPHIC 1399,0 486 0 1041 DESIGN @f@a@d_main 1042 VIEW struct.bd 1043 GRAPHIC 1406,0 487 1 1044 DESIGN @f@a@d_main 1045 VIEW struct.bd 1046 GRAPHIC 5602,0 491 0 1047 DESIGN @f@a@d_main 1048 VIEW struct.bd 1049 GRAPHIC 334,0 492 0 1050 DESIGN @f@a@d_main 1051 VIEW struct.bd 1052 GRAPHIC 328,0 493 0 1053 DESIGN @f@a@d_main 1054 VIEW struct.bd 1055 GRAPHIC 322,0 494 0 1056 DESIGN @f@a@d_main 1057 VIEW struct.bd 1058 GRAPHIC 2299,0 495 0 1059 DESIGN @f@a@d_main 1060 VIEW struct.bd 1061 GRAPHIC 2576,0 496 0 1062 DESIGN @f@a@d_main 1063 VIEW struct.bd 1064 GRAPHIC 2582,0 497 0 1065 DESIGN @f@a@d_main 1066 VIEW struct.bd 1067 GRAPHIC 2588,0 498 0 1068 DESIGN @f@a@d_main 1069 VIEW struct.bd 1070 GRAPHIC 5184,0 499 0 1071 DESIGN @f@a@d_main 1072 VIEW struct.bd 1073 GRAPHIC 5745,0 500 0 1074 DESIGN @f@a@d_main 1075 VIEW struct.bd 1076 GRAPHIC 2594,0 501 0 1077 DESIGN @f@a@d_main 1078 VIEW struct.bd 1079 GRAPHIC 5190,0 502 0 1080 DESIGN @f@a@d_main 1081 VIEW struct.bd 1082 GRAPHIC 5404,0 503 0 1083 DESIGN @f@a@d_main 1084 VIEW struct.bd 1085 GRAPHIC 6018,0 504 0 1086 DESIGN @f@a@d_main 1087 VIEW struct.bd 1088 GRAPHIC 6002,0 505 0 1089 DESIGN @f@a@d_main 1090 VIEW struct.bd 1091 GRAPHIC 6008,0 506 0 1092 DESIGN @f@a@d_main 1093 VIEW struct.bd 1094 GRAPHIC 5138,0 507 0 1095 DESIGN @f@a@d_main 1096 VIEW struct.bd 1097 GRAPHIC 2600,0 508 0 1098 DESIGN @f@a@d_main 1099 VIEW struct.bd 1100 GRAPHIC 5480,0 509 0 1101 DESIGN @f@a@d_main 1102 VIEW struct.bd 1103 GRAPHIC 5474,0 510 0 1104 DESIGN @f@a@d_main 1105 VIEW struct.bd 1106 GRAPHIC 6064,0 511 0 1107 DESIGN @f@a@d_main 1108 VIEW struct.bd 1109 GRAPHIC 2642,0 512 0 1110 DESIGN @f@a@d_main 1111 VIEW struct.bd 1112 GRAPHIC 1411,0 513 0 1113 DESIGN @f@a@d_main 1114 VIEW struct.bd 1115 GRAPHIC 1682,0 514 0 1116 DESIGN @f@a@d_main 1117 VIEW struct.bd 1118 GRAPHIC 1983,0 515 0 1119 DESIGN @f@a@d_main 1120 VIEW struct.bd 1121 GRAPHIC 1425,0 516 0 1122 DESIGN @f@a@d_main 1123 VIEW struct.bd 1124 GRAPHIC 5281,0 517 0 1125 DESIGN @f@a@d_main 1126 VIEW struct.bd 1127 GRAPHIC 5950,0 518 0 1128 DESIGN @f@a@d_main 1129 VIEW struct.bd 1130 GRAPHIC 5962,0 519 0 1131 DESIGN @f@a@d_main 1132 VIEW struct.bd 1133 GRAPHIC 5626,0 520 0 1134 DESIGN @f@a@d_main 1135 VIEW struct.bd 1136 GRAPHIC 2778,0 521 0 1137 DESIGN @f@a@d_main 1138 VIEW struct.bd 1139 GRAPHIC 9006,0 522 0 1140 DESIGN @f@a@d_main 1141 VIEW struct.bd 1142 GRAPHIC 5634,0 523 0 1143 DESIGN @f@a@d_main 1144 VIEW struct.bd 1145 GRAPHIC 8577,0 524 0 1146 DESIGN @f@a@d_main 1147 VIEW struct.bd 1148 GRAPHIC 6540,0 525 0 1149 DESIGN @f@a@d_main 1150 VIEW struct.bd 1151 GRAPHIC 4401,0 526 0 1152 DESIGN @f@a@d_main 1153 VIEW struct.bd 1154 GRAPHIC 4419,0 527 0 1155 DESIGN @f@a@d_main 1156 VIEW struct.bd 1157 GRAPHIC 4743,0 528 0 1158 DESIGN @f@a@d_main 1159 VIEW struct.bd 1160 GRAPHIC 4407,0 529 0 1161 DESIGN @f@a@d_main 1162 VIEW struct.bd 1163 GRAPHIC 4903,0 531 0 1164 DESIGN @f@a@d_main 1165 VIEW struct.bd 1166 GRAPHIC 4757,0 533 0 1167 DESIGN @f@a@d_main 1168 VIEW struct.bd 1169 GRAPHIC 4401,0 534 0 1170 DESIGN @f@a@d_main 1171 VIEW struct.bd 1172 GRAPHIC 4419,0 535 0 1173 DESIGN @f@a@d_main 1174 VIEW struct.bd 1175 GRAPHIC 4671,0 536 0 1176 DESIGN @f@a@d_main 1177 VIEW struct.bd 1178 GRAPHIC 4679,0 537 0 1179 DESIGN @f@a@d_main 1180 VIEW struct.bd 1181 GRAPHIC 4687,0 538 0 1182 DESIGN @f@a@d_main 1183 VIEW struct.bd 1184 GRAPHIC 4695,0 539 0 1185 DESIGN @f@a@d_main 1186 VIEW struct.bd 1187 GRAPHIC 4407,0 540 0 1188 DESIGN @f@a@d_main 1189 VIEW struct.bd 1190 GRAPHIC 4743,0 541 0 1191 DESIGN @f@a@d_main 1192 VIEW struct.bd 1193 GRAPHIC 4948,0 542 0 1194 DESIGN @f@a@d_main 1195 VIEW struct.bd 1196 GRAPHIC 10010,0 543 0 1197 DESIGN @f@a@d_main 1198 VIEW struct.bd 1199 GRAPHIC 2311,0 545 0 1200 DESIGN @f@a@d_main 1201 VIEW struct.bd 1202 GRAPHIC 2318,0 546 1 1203 DESIGN @f@a@d_main 1204 VIEW struct.bd 1205 GRAPHIC 6082,0 551 0 1206 DESIGN @f@a@d_main 1207 VIEW struct.bd 1208 GRAPHIC 2588,0 552 0 1209 DESIGN @f@a@d_main 1210 VIEW struct.bd 1211 GRAPHIC 2582,0 553 0 1212 DESIGN @f@a@d_main 1213 VIEW struct.bd 1214 GRAPHIC 5168,0 554 0 1215 DESIGN @f@a@d_main 1216 VIEW struct.bd 1217 GRAPHIC 2576,0 555 0 1218 DESIGN @f@a@d_main 1219 VIEW struct.bd 1220 GRAPHIC 2594,0 556 0 1221 DESIGN @f@a@d_main 1222 VIEW struct.bd 1223 GRAPHIC 6018,0 557 0 1224 DESIGN @f@a@d_main 1225 VIEW struct.bd 1226 GRAPHIC 2600,0 558 0 1227 DESIGN @f@a@d_main 1228 VIEW struct.bd 1229 GRAPHIC 2642,0 559 0 1230 DESIGN @f@a@d_main 1231 VIEW struct.bd 1232 GRAPHIC 2488,0 560 0 1233 DESIGN @f@a@d_main 1234 VIEW struct.bd 1235 GRAPHIC 2482,0 561 0 1236 DESIGN @f@a@d_main 1237 VIEW struct.bd 1238 GRAPHIC 2494,0 562 0 1239 DESIGN @f@a@d_main 1240 VIEW struct.bd 1241 GRAPHIC 2476,0 563 0 1242 DESIGN @f@a@d_main 1243 VIEW struct.bd 1244 GRAPHIC 2506,0 564 0 1245 DESIGN @f@a@d_main 1246 VIEW struct.bd 1247 GRAPHIC 2500,0 565 0 1248 DESIGN @f@a@d_main 1249 VIEW struct.bd 1250 GRAPHIC 2470,0 566 0 1251 DESIGN @f@a@d_main 1252 VIEW struct.bd 1253 GRAPHIC 8416,0 567 0 1254 DESIGN @f@a@d_main 1255 VIEW struct.bd 1256 GRAPHIC 2299,0 568 0 1257 DESIGN @f@a@d_main 1258 VIEW struct.bd 1259 GRAPHIC 5793,0 570 0 1260 DESIGN @f@a@d_main 1261 VIEW struct.bd 1262 GRAPHIC 5805,0 572 0 1263 DESIGN @f@a@d_main 1264 VIEW struct.bd 1265 GRAPHIC 5745,0 573 0 1266 DESIGN @f@a@d_main 1267 VIEW struct.bd 1268 GRAPHIC 5146,0 574 0 1269 DESIGN @f@a@d_main 1270 VIEW struct.bd 1271 GRAPHIC 5404,0 575 0 1272 DESIGN @f@a@d_main 1273 VIEW struct.bd 1274 GRAPHIC 6008,0 576 0 1275 DESIGN @f@a@d_main 1276 VIEW struct.bd 1277 GRAPHIC 5829,0 577 0 1278 DESIGN @f@a@d_main 1279 VIEW struct.bd 1280 GRAPHIC 6160,0 578 0 1281 DESIGN @f@a@d_main 1282 VIEW struct.bd 1283 GRAPHIC 8732,0 579 0 1284 DESIGN @f@a@d_main 1285 VIEW struct.bd 1286 GRAPHIC 5480,0 580 0 1287 DESIGN @f@a@d_main 1288 VIEW struct.bd 1289 GRAPHIC 5837,0 581 0 1290 DESIGN @f@a@d_main 1291 VIEW struct.bd 1292 GRAPHIC 5474,0 582 0 1293 DESIGN @f@a@d_main 1294 VIEW struct.bd 1295 GRAPHIC 5821,0 583 0 1296 DESIGN @f@a@d_main 1297 VIEW struct.bd 1298 GRAPHIC 1768,0 585 0 1299 DESIGN @f@a@d_main 1300 VIEW struct.bd 1301 GRAPHIC 1983,0 587 0 1302 DESIGN @f@a@d_main 1303 VIEW struct.bd 1304 GRAPHIC 2876,0 588 0 1305 DESIGN @f@a@d_main 1306 VIEW struct.bd 1307 GRAPHIC 6276,0 589 0 1308 DESIGN @f@a@d_main 1309 VIEW struct.bd 1310 GRAPHIC 1606,0 591 0 1311 DESIGN @f@a@d_main 1312 VIEW struct.bd 1313 GRAPHIC 1613,0 592 1 1314 DESIGN @f@a@d_main 1315 VIEW struct.bd 1316 GRAPHIC 3888,0 596 0 1317 DESIGN @f@a@d_main 1318 VIEW struct.bd 1319 GRAPHIC 376,0 597 0 1320 DESIGN @f@a@d_main 1321 VIEW struct.bd 1322 GRAPHIC 384,0 598 0 1323 DESIGN @f@a@d_main 1324 VIEW struct.bd 1325 GRAPHIC 392,0 599 0 1326 DESIGN @f@a@d_main 1327 VIEW struct.bd 1328 GRAPHIC 400,0 600 0 1329 DESIGN @f@a@d_main 1330 VIEW struct.bd 1331 GRAPHIC 408,0 601 0 1332 DESIGN @f@a@d_main 1333 VIEW struct.bd 1334 GRAPHIC 5222,0 602 0 1335 DESIGN @f@a@d_main 1336 VIEW struct.bd 1337 GRAPHIC 424,0 603 0 1338 DESIGN @f@a@d_main 1339 VIEW struct.bd 1340 GRAPHIC 432,0 604 0 1341 DESIGN @f@a@d_main 1342 VIEW struct.bd 1343 GRAPHIC 2482,0 605 0 1344 DESIGN @f@a@d_main 1345 VIEW struct.bd 1346 GRAPHIC 2488,0 606 0 1347 DESIGN @f@a@d_main 1348 VIEW struct.bd 1349 GRAPHIC 370,0 607 0 1350 DESIGN @f@a@d_main 1351 VIEW struct.bd 1352 GRAPHIC 364,0 608 0 1353 DESIGN @f@a@d_main 1354 VIEW struct.bd 1355 GRAPHIC 2476,0 609 0 1356 DESIGN @f@a@d_main 1357 VIEW struct.bd 1358 GRAPHIC 8416,0 610 0 1359 DESIGN @f@a@d_main 1360 VIEW struct.bd 1361 GRAPHIC 2470,0 611 0 1362 DESIGN @f@a@d_main 1363 VIEW struct.bd 1364 GRAPHIC 2506,0 612 0 1365 DESIGN @f@a@d_main 1366 VIEW struct.bd 1367 GRAPHIC 2500,0 613 0 1368 DESIGN @f@a@d_main 1369 VIEW struct.bd 1370 GRAPHIC 2494,0 614 0 1371 DESIGN @f@a@d_main 1372 VIEW struct.bd 1373 GRAPHIC 5281,0 615 0 1374 DESIGN @f@a@d_main 1375 VIEW struct.bd 1376 GRAPHIC 5950,0 616 0 1377 DESIGN @f@a@d_main 1378 VIEW struct.bd 1379 GRAPHIC 5962,0 617 0 1380 DESIGN @f@a@d_main 1381 VIEW struct.bd 1382 GRAPHIC 5090,0 618 0 1383 DESIGN @f@a@d_main 1384 VIEW struct.bd 1385 GRAPHIC 5114,0 619 0 1386 DESIGN @f@a@d_main 1387 VIEW struct.bd 1388 GRAPHIC 5122,0 620 0 1389 DESIGN @f@a@d_main 1390 VIEW struct.bd 1391 GRAPHIC 5130,0 621 0 1392 DESIGN @f@a@d_main 1393 VIEW struct.bd 1394 GRAPHIC 5106,0 622 0 1395 DESIGN @f@a@d_main 1396 VIEW struct.bd 1397 GRAPHIC 6362,0 623 0 1398 DESIGN @f@a@d_main 1399 VIEW struct.bd 1400 GRAPHIC 6452,0 624 0 1401 DESIGN @f@a@d_main 1402 VIEW struct.bd 1403 GRAPHIC 8752,0 625 0 1404 DESIGN @f@a@d_main 1405 VIEW struct.bd 1406 GRAPHIC 9233,0 626 0 1407 DESIGN @f@a@d_main 1408 VIEW struct.bd 1409 GRAPHIC 9241,0 627 0 1410 DESIGN @f@a@d_main 1411 VIEW struct.bd 1412 GRAPHIC 9943,0 628 0 1413 DESIGN @f@a@d_main 1414 VIEW struct.bd 1415 GRAPHIC 9951,0 629 0 1416 DESIGN @f@a@d_main 1417 VIEW struct.bd 1418 GRAPHIC 6276,0 633 0 1419 DESIGN @f@a@d_main 1420 VIEW struct.bd 1421 GRAPHIC 3888,0 634 0 1422 DESIGN @f@a@d_main 1423 VIEW struct.bd 1424 NO_GRAPHIC 636 920 GRAPHIC 6529,0 432 0 921 DESIGN @f@a@d_main 922 VIEW struct.bd 923 GRAPHIC 9957,0 435 0 924 DESIGN @f@a@d_main 925 VIEW struct.bd 926 GRAPHIC 8721,0 438 0 927 DESIGN @f@a@d_main 928 VIEW struct.bd 929 GRAPHIC 9430,0 441 0 930 DESIGN @f@a@d_main 931 VIEW struct.bd 932 GRAPHIC 9472,0 444 0 933 DESIGN @f@a@d_main 934 VIEW struct.bd 935 GRAPHIC 9662,0 447 0 936 DESIGN @f@a@d_main 937 VIEW struct.bd 938 GRAPHIC 9679,0 450 0 939 DESIGN @f@a@d_main 940 VIEW struct.bd 941 GRAPHIC 9710,0 453 0 942 DESIGN @f@a@d_main 943 VIEW struct.bd 944 GRAPHIC 8562,0 456 0 945 DESIGN @f@a@d_main 946 VIEW struct.bd 947 GRAPHIC 10380,0 467 0 948 DESIGN @f@a@d_main 949 VIEW struct.bd 950 NO_GRAPHIC 470 951 DESIGN @f@a@d_main 952 VIEW struct.bd 953 GRAPHIC 5678,0 472 0 954 DESIGN @f@a@d_main 955 VIEW struct.bd 956 GRAPHIC 5646,0 474 0 957 DESIGN @f@a@d_main 958 VIEW struct.bd 959 GRAPHIC 4272,0 475 0 960 DESIGN @f@a@d_main 961 VIEW struct.bd 962 GRAPHIC 2786,0 476 0 963 DESIGN @f@a@d_main 964 VIEW struct.bd 965 GRAPHIC 5626,0 477 0 966 DESIGN @f@a@d_main 967 VIEW struct.bd 968 GRAPHIC 5634,0 478 0 969 DESIGN @f@a@d_main 970 VIEW struct.bd 971 GRAPHIC 9175,0 480 0 972 DESIGN @f@a@d_main 973 VIEW struct.bd 974 GRAPHIC 4042,0 482 0 975 DESIGN @f@a@d_main 976 VIEW struct.bd 977 GRAPHIC 10036,0 483 0 978 DESIGN @f@a@d_main 979 VIEW struct.bd 980 GRAPHIC 9253,0 484 0 981 DESIGN @f@a@d_main 982 VIEW struct.bd 983 GRAPHIC 9261,0 485 0 984 DESIGN @f@a@d_main 985 VIEW struct.bd 986 GRAPHIC 6072,0 486 0 987 DESIGN @f@a@d_main 988 VIEW struct.bd 989 GRAPHIC 3984,0 487 0 990 DESIGN @f@a@d_main 991 VIEW struct.bd 992 GRAPHIC 3888,0 488 0 993 DESIGN @f@a@d_main 994 VIEW struct.bd 995 GRAPHIC 9353,0 489 0 996 DESIGN @f@a@d_main 997 VIEW struct.bd 998 GRAPHIC 9269,0 490 0 999 DESIGN @f@a@d_main 1000 VIEW struct.bd 1001 GRAPHIC 9325,0 491 0 1002 DESIGN @f@a@d_main 1003 VIEW struct.bd 1004 GRAPHIC 9283,0 492 0 1005 DESIGN @f@a@d_main 1006 VIEW struct.bd 1007 GRAPHIC 9311,0 493 0 1008 DESIGN @f@a@d_main 1009 VIEW struct.bd 1010 GRAPHIC 9297,0 494 0 1011 DESIGN @f@a@d_main 1012 VIEW struct.bd 1013 GRAPHIC 9367,0 495 0 1014 DESIGN @f@a@d_main 1015 VIEW struct.bd 1016 GRAPHIC 9397,0 496 0 1017 DESIGN @f@a@d_main 1018 VIEW struct.bd 1019 GRAPHIC 9382,0 497 0 1020 DESIGN @f@a@d_main 1021 VIEW struct.bd 1022 GRAPHIC 5072,0 499 0 1023 DESIGN @f@a@d_main 1024 VIEW struct.bd 1025 GRAPHIC 5582,0 501 0 1026 DESIGN @f@a@d_main 1027 VIEW struct.bd 1028 GRAPHIC 5090,0 502 0 1029 DESIGN @f@a@d_main 1030 VIEW struct.bd 1031 GRAPHIC 5130,0 503 0 1032 DESIGN @f@a@d_main 1033 VIEW struct.bd 1034 GRAPHIC 5184,0 504 0 1035 DESIGN @f@a@d_main 1036 VIEW struct.bd 1037 GRAPHIC 5122,0 505 0 1038 DESIGN @f@a@d_main 1039 VIEW struct.bd 1040 GRAPHIC 5106,0 506 0 1041 DESIGN @f@a@d_main 1042 VIEW struct.bd 1043 GRAPHIC 5098,0 507 0 1044 DESIGN @f@a@d_main 1045 VIEW struct.bd 1046 GRAPHIC 5190,0 508 0 1047 DESIGN @f@a@d_main 1048 VIEW struct.bd 1049 GRAPHIC 10194,0 509 0 1050 DESIGN @f@a@d_main 1051 VIEW struct.bd 1052 GRAPHIC 10202,0 510 0 1053 DESIGN @f@a@d_main 1054 VIEW struct.bd 1055 GRAPHIC 6002,0 511 0 1056 DESIGN @f@a@d_main 1057 VIEW struct.bd 1058 GRAPHIC 5146,0 512 0 1059 DESIGN @f@a@d_main 1060 VIEW struct.bd 1061 GRAPHIC 5138,0 513 0 1062 DESIGN @f@a@d_main 1063 VIEW struct.bd 1064 GRAPHIC 5114,0 514 0 1065 DESIGN @f@a@d_main 1066 VIEW struct.bd 1067 GRAPHIC 8277,0 516 0 1068 DESIGN @f@a@d_main 1069 VIEW struct.bd 1070 GRAPHIC 5602,0 518 0 1071 DESIGN @f@a@d_main 1072 VIEW struct.bd 1073 GRAPHIC 334,0 519 0 1074 DESIGN @f@a@d_main 1075 VIEW struct.bd 1076 GRAPHIC 328,0 520 0 1077 DESIGN @f@a@d_main 1078 VIEW struct.bd 1079 GRAPHIC 322,0 521 0 1080 DESIGN @f@a@d_main 1081 VIEW struct.bd 1082 GRAPHIC 4240,0 522 0 1083 DESIGN @f@a@d_main 1084 VIEW struct.bd 1085 GRAPHIC 364,0 523 0 1086 DESIGN @f@a@d_main 1087 VIEW struct.bd 1088 GRAPHIC 370,0 524 0 1089 DESIGN @f@a@d_main 1090 VIEW struct.bd 1091 GRAPHIC 1399,0 526 0 1092 DESIGN @f@a@d_main 1093 VIEW struct.bd 1094 GRAPHIC 1406,0 527 1 1095 DESIGN @f@a@d_main 1096 VIEW struct.bd 1097 GRAPHIC 5602,0 531 0 1098 DESIGN @f@a@d_main 1099 VIEW struct.bd 1100 GRAPHIC 334,0 532 0 1101 DESIGN @f@a@d_main 1102 VIEW struct.bd 1103 GRAPHIC 328,0 533 0 1104 DESIGN @f@a@d_main 1105 VIEW struct.bd 1106 GRAPHIC 322,0 534 0 1107 DESIGN @f@a@d_main 1108 VIEW struct.bd 1109 GRAPHIC 2299,0 535 0 1110 DESIGN @f@a@d_main 1111 VIEW struct.bd 1112 GRAPHIC 2576,0 536 0 1113 DESIGN @f@a@d_main 1114 VIEW struct.bd 1115 GRAPHIC 2582,0 537 0 1116 DESIGN @f@a@d_main 1117 VIEW struct.bd 1118 GRAPHIC 10467,0 538 0 1119 DESIGN @f@a@d_main 1120 VIEW struct.bd 1121 GRAPHIC 2588,0 539 0 1122 DESIGN @f@a@d_main 1123 VIEW struct.bd 1124 GRAPHIC 5184,0 540 0 1125 DESIGN @f@a@d_main 1126 VIEW struct.bd 1127 GRAPHIC 5745,0 541 0 1128 DESIGN @f@a@d_main 1129 VIEW struct.bd 1130 GRAPHIC 2594,0 542 0 1131 DESIGN @f@a@d_main 1132 VIEW struct.bd 1133 GRAPHIC 5190,0 543 0 1134 DESIGN @f@a@d_main 1135 VIEW struct.bd 1136 GRAPHIC 5404,0 544 0 1137 DESIGN @f@a@d_main 1138 VIEW struct.bd 1139 GRAPHIC 6018,0 545 0 1140 DESIGN @f@a@d_main 1141 VIEW struct.bd 1142 GRAPHIC 6002,0 546 0 1143 DESIGN @f@a@d_main 1144 VIEW struct.bd 1145 GRAPHIC 6008,0 547 0 1146 DESIGN @f@a@d_main 1147 VIEW struct.bd 1148 GRAPHIC 5138,0 548 0 1149 DESIGN @f@a@d_main 1150 VIEW struct.bd 1151 GRAPHIC 2600,0 549 0 1152 DESIGN @f@a@d_main 1153 VIEW struct.bd 1154 GRAPHIC 5480,0 550 0 1155 DESIGN @f@a@d_main 1156 VIEW struct.bd 1157 GRAPHIC 5474,0 551 0 1158 DESIGN @f@a@d_main 1159 VIEW struct.bd 1160 GRAPHIC 6064,0 552 0 1161 DESIGN @f@a@d_main 1162 VIEW struct.bd 1163 GRAPHIC 2642,0 553 0 1164 DESIGN @f@a@d_main 1165 VIEW struct.bd 1166 GRAPHIC 1411,0 554 0 1167 DESIGN @f@a@d_main 1168 VIEW struct.bd 1169 GRAPHIC 1682,0 555 0 1170 DESIGN @f@a@d_main 1171 VIEW struct.bd 1172 GRAPHIC 1983,0 556 0 1173 DESIGN @f@a@d_main 1174 VIEW struct.bd 1175 GRAPHIC 10439,0 557 0 1176 DESIGN @f@a@d_main 1177 VIEW struct.bd 1178 GRAPHIC 5950,0 558 0 1179 DESIGN @f@a@d_main 1180 VIEW struct.bd 1181 GRAPHIC 5962,0 559 0 1182 DESIGN @f@a@d_main 1183 VIEW struct.bd 1184 GRAPHIC 5626,0 560 0 1185 DESIGN @f@a@d_main 1186 VIEW struct.bd 1187 GRAPHIC 2778,0 561 0 1188 DESIGN @f@a@d_main 1189 VIEW struct.bd 1190 GRAPHIC 9006,0 562 0 1191 DESIGN @f@a@d_main 1192 VIEW struct.bd 1193 GRAPHIC 5634,0 563 0 1194 DESIGN @f@a@d_main 1195 VIEW struct.bd 1196 GRAPHIC 8577,0 564 0 1197 DESIGN @f@a@d_main 1198 VIEW struct.bd 1199 GRAPHIC 6540,0 565 0 1200 DESIGN @f@a@d_main 1201 VIEW struct.bd 1202 GRAPHIC 4401,0 566 0 1203 DESIGN @f@a@d_main 1204 VIEW struct.bd 1205 GRAPHIC 4419,0 567 0 1206 DESIGN @f@a@d_main 1207 VIEW struct.bd 1208 GRAPHIC 10298,0 568 0 1209 DESIGN @f@a@d_main 1210 VIEW struct.bd 1211 GRAPHIC 10304,0 569 0 1212 DESIGN @f@a@d_main 1213 VIEW struct.bd 1214 GRAPHIC 10316,0 570 0 1215 DESIGN @f@a@d_main 1216 VIEW struct.bd 1217 GRAPHIC 10310,0 571 0 1218 DESIGN @f@a@d_main 1219 VIEW struct.bd 1220 GRAPHIC 4743,0 572 0 1221 DESIGN @f@a@d_main 1222 VIEW struct.bd 1223 GRAPHIC 4407,0 573 0 1224 DESIGN @f@a@d_main 1225 VIEW struct.bd 1226 GRAPHIC 4903,0 575 0 1227 DESIGN @f@a@d_main 1228 VIEW struct.bd 1229 GRAPHIC 4757,0 577 0 1230 DESIGN @f@a@d_main 1231 VIEW struct.bd 1232 GRAPHIC 4401,0 578 0 1233 DESIGN @f@a@d_main 1234 VIEW struct.bd 1235 GRAPHIC 4419,0 579 0 1236 DESIGN @f@a@d_main 1237 VIEW struct.bd 1238 GRAPHIC 4671,0 580 0 1239 DESIGN @f@a@d_main 1240 VIEW struct.bd 1241 GRAPHIC 4679,0 581 0 1242 DESIGN @f@a@d_main 1243 VIEW struct.bd 1244 GRAPHIC 4687,0 582 0 1245 DESIGN @f@a@d_main 1246 VIEW struct.bd 1247 GRAPHIC 4695,0 583 0 1248 DESIGN @f@a@d_main 1249 VIEW struct.bd 1250 GRAPHIC 4407,0 584 0 1251 DESIGN @f@a@d_main 1252 VIEW struct.bd 1253 GRAPHIC 4743,0 585 0 1254 DESIGN @f@a@d_main 1255 VIEW struct.bd 1256 GRAPHIC 10298,0 586 0 1257 DESIGN @f@a@d_main 1258 VIEW struct.bd 1259 GRAPHIC 10310,0 587 0 1260 DESIGN @f@a@d_main 1261 VIEW struct.bd 1262 GRAPHIC 10304,0 588 0 1263 DESIGN @f@a@d_main 1264 VIEW struct.bd 1265 GRAPHIC 10316,0 589 0 1266 DESIGN @f@a@d_main 1267 VIEW struct.bd 1268 GRAPHIC 10322,0 590 0 1269 DESIGN @f@a@d_main 1270 VIEW struct.bd 1271 GRAPHIC 4948,0 591 0 1272 DESIGN @f@a@d_main 1273 VIEW struct.bd 1274 GRAPHIC 10010,0 592 0 1275 DESIGN @f@a@d_main 1276 VIEW struct.bd 1277 GRAPHIC 2311,0 594 0 1278 DESIGN @f@a@d_main 1279 VIEW struct.bd 1280 GRAPHIC 2318,0 595 1 1281 DESIGN @f@a@d_main 1282 VIEW struct.bd 1283 GRAPHIC 6082,0 600 0 1284 DESIGN @f@a@d_main 1285 VIEW struct.bd 1286 GRAPHIC 2588,0 601 0 1287 DESIGN @f@a@d_main 1288 VIEW struct.bd 1289 GRAPHIC 2582,0 602 0 1290 DESIGN @f@a@d_main 1291 VIEW struct.bd 1292 GRAPHIC 10467,0 603 0 1293 DESIGN @f@a@d_main 1294 VIEW struct.bd 1295 GRAPHIC 5168,0 604 0 1296 DESIGN @f@a@d_main 1297 VIEW struct.bd 1298 GRAPHIC 2576,0 605 0 1299 DESIGN @f@a@d_main 1300 VIEW struct.bd 1301 GRAPHIC 2594,0 606 0 1302 DESIGN @f@a@d_main 1303 VIEW struct.bd 1304 GRAPHIC 6018,0 607 0 1305 DESIGN @f@a@d_main 1306 VIEW struct.bd 1307 GRAPHIC 2600,0 608 0 1308 DESIGN @f@a@d_main 1309 VIEW struct.bd 1310 GRAPHIC 2642,0 609 0 1311 DESIGN @f@a@d_main 1312 VIEW struct.bd 1313 GRAPHIC 2488,0 610 0 1314 DESIGN @f@a@d_main 1315 VIEW struct.bd 1316 GRAPHIC 2482,0 611 0 1317 DESIGN @f@a@d_main 1318 VIEW struct.bd 1319 GRAPHIC 2494,0 612 0 1320 DESIGN @f@a@d_main 1321 VIEW struct.bd 1322 GRAPHIC 2476,0 613 0 1323 DESIGN @f@a@d_main 1324 VIEW struct.bd 1325 GRAPHIC 2506,0 614 0 1326 DESIGN @f@a@d_main 1327 VIEW struct.bd 1328 GRAPHIC 2500,0 615 0 1329 DESIGN @f@a@d_main 1330 VIEW struct.bd 1331 GRAPHIC 2470,0 616 0 1332 DESIGN @f@a@d_main 1333 VIEW struct.bd 1334 GRAPHIC 8416,0 617 0 1335 DESIGN @f@a@d_main 1336 VIEW struct.bd 1337 GRAPHIC 2299,0 618 0 1338 DESIGN @f@a@d_main 1339 VIEW struct.bd 1340 GRAPHIC 5793,0 620 0 1341 DESIGN @f@a@d_main 1342 VIEW struct.bd 1343 GRAPHIC 5805,0 622 0 1344 DESIGN @f@a@d_main 1345 VIEW struct.bd 1346 GRAPHIC 5745,0 623 0 1347 DESIGN @f@a@d_main 1348 VIEW struct.bd 1349 GRAPHIC 5146,0 624 0 1350 DESIGN @f@a@d_main 1351 VIEW struct.bd 1352 GRAPHIC 5404,0 625 0 1353 DESIGN @f@a@d_main 1354 VIEW struct.bd 1355 GRAPHIC 6008,0 626 0 1356 DESIGN @f@a@d_main 1357 VIEW struct.bd 1358 GRAPHIC 5829,0 627 0 1359 DESIGN @f@a@d_main 1360 VIEW struct.bd 1361 GRAPHIC 6160,0 628 0 1362 DESIGN @f@a@d_main 1363 VIEW struct.bd 1364 GRAPHIC 8732,0 629 0 1365 DESIGN @f@a@d_main 1366 VIEW struct.bd 1367 GRAPHIC 5480,0 630 0 1368 DESIGN @f@a@d_main 1369 VIEW struct.bd 1370 GRAPHIC 5837,0 631 0 1371 DESIGN @f@a@d_main 1372 VIEW struct.bd 1373 GRAPHIC 5474,0 632 0 1374 DESIGN @f@a@d_main 1375 VIEW struct.bd 1376 GRAPHIC 5821,0 633 0 1377 DESIGN @f@a@d_main 1378 VIEW struct.bd 1379 GRAPHIC 1768,0 635 0 1380 DESIGN @f@a@d_main 1381 VIEW struct.bd 1382 GRAPHIC 1983,0 637 0 1383 DESIGN @f@a@d_main 1384 VIEW struct.bd 1385 GRAPHIC 10443,0 638 0 1386 DESIGN @f@a@d_main 1387 VIEW struct.bd 1388 GRAPHIC 6276,0 639 0 1389 DESIGN @f@a@d_main 1390 VIEW struct.bd 1391 GRAPHIC 1606,0 641 0 1392 DESIGN @f@a@d_main 1393 VIEW struct.bd 1394 GRAPHIC 1613,0 642 1 1395 DESIGN @f@a@d_main 1396 VIEW struct.bd 1397 GRAPHIC 3888,0 646 0 1398 DESIGN @f@a@d_main 1399 VIEW struct.bd 1400 GRAPHIC 376,0 647 0 1401 DESIGN @f@a@d_main 1402 VIEW struct.bd 1403 GRAPHIC 384,0 648 0 1404 DESIGN @f@a@d_main 1405 VIEW struct.bd 1406 GRAPHIC 392,0 649 0 1407 DESIGN @f@a@d_main 1408 VIEW struct.bd 1409 GRAPHIC 400,0 650 0 1410 DESIGN @f@a@d_main 1411 VIEW struct.bd 1412 GRAPHIC 408,0 651 0 1413 DESIGN @f@a@d_main 1414 VIEW struct.bd 1415 GRAPHIC 5222,0 652 0 1416 DESIGN @f@a@d_main 1417 VIEW struct.bd 1418 GRAPHIC 424,0 653 0 1419 DESIGN @f@a@d_main 1420 VIEW struct.bd 1421 GRAPHIC 432,0 654 0 1422 DESIGN @f@a@d_main 1423 VIEW struct.bd 1424 GRAPHIC 2482,0 655 0 1425 DESIGN @f@a@d_main 1426 VIEW struct.bd 1427 GRAPHIC 2488,0 656 0 1428 DESIGN @f@a@d_main 1429 VIEW struct.bd 1430 GRAPHIC 370,0 657 0 1431 DESIGN @f@a@d_main 1432 VIEW struct.bd 1433 GRAPHIC 364,0 658 0 1434 DESIGN @f@a@d_main 1435 VIEW struct.bd 1436 GRAPHIC 2476,0 659 0 1437 DESIGN @f@a@d_main 1438 VIEW struct.bd 1439 GRAPHIC 8416,0 660 0 1440 DESIGN @f@a@d_main 1441 VIEW struct.bd 1442 GRAPHIC 2470,0 661 0 1443 DESIGN @f@a@d_main 1444 VIEW struct.bd 1445 GRAPHIC 2506,0 662 0 1446 DESIGN @f@a@d_main 1447 VIEW struct.bd 1448 GRAPHIC 2500,0 663 0 1449 DESIGN @f@a@d_main 1450 VIEW struct.bd 1451 GRAPHIC 2494,0 664 0 1452 DESIGN @f@a@d_main 1453 VIEW struct.bd 1454 GRAPHIC 10266,0 665 0 1455 DESIGN @f@a@d_main 1456 VIEW struct.bd 1457 GRAPHIC 5950,0 666 0 1458 DESIGN @f@a@d_main 1459 VIEW struct.bd 1460 GRAPHIC 5962,0 667 0 1461 DESIGN @f@a@d_main 1462 VIEW struct.bd 1463 GRAPHIC 5090,0 668 0 1464 DESIGN @f@a@d_main 1465 VIEW struct.bd 1466 GRAPHIC 5114,0 669 0 1467 DESIGN @f@a@d_main 1468 VIEW struct.bd 1469 GRAPHIC 5122,0 670 0 1470 DESIGN @f@a@d_main 1471 VIEW struct.bd 1472 GRAPHIC 5130,0 671 0 1473 DESIGN @f@a@d_main 1474 VIEW struct.bd 1475 GRAPHIC 10194,0 672 0 1476 DESIGN @f@a@d_main 1477 VIEW struct.bd 1478 GRAPHIC 10202,0 673 0 1479 DESIGN @f@a@d_main 1480 VIEW struct.bd 1481 GRAPHIC 5106,0 674 0 1482 DESIGN @f@a@d_main 1483 VIEW struct.bd 1484 GRAPHIC 6362,0 675 0 1485 DESIGN @f@a@d_main 1486 VIEW struct.bd 1487 GRAPHIC 6452,0 676 0 1488 DESIGN @f@a@d_main 1489 VIEW struct.bd 1490 GRAPHIC 8752,0 677 0 1491 DESIGN @f@a@d_main 1492 VIEW struct.bd 1493 GRAPHIC 9233,0 678 0 1494 DESIGN @f@a@d_main 1495 VIEW struct.bd 1496 GRAPHIC 9241,0 679 0 1497 DESIGN @f@a@d_main 1498 VIEW struct.bd 1499 GRAPHIC 9943,0 680 0 1500 DESIGN @f@a@d_main 1501 VIEW struct.bd 1502 GRAPHIC 9951,0 681 0 1503 DESIGN @f@a@d_main 1504 VIEW struct.bd 1505 GRAPHIC 6276,0 685 0 1506 DESIGN @f@a@d_main 1507 VIEW struct.bd 1508 GRAPHIC 3888,0 686 0 1509 DESIGN @f@a@d_main 1510 VIEW struct.bd 1511 NO_GRAPHIC 688 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd
r9912 r10073 109 109 (vvPair 110 110 variable "HDLDir" 111 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"111 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" 112 112 ) 113 113 (vvPair 114 114 variable "HDSDir" 115 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"115 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 116 116 ) 117 117 (vvPair 118 118 variable "SideDataDesignDir" 119 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"119 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info" 120 120 ) 121 121 (vvPair 122 122 variable "SideDataUserDir" 123 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"123 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user" 124 124 ) 125 125 (vvPair 126 126 variable "SourceDir" 127 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"127 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 128 128 ) 129 129 (vvPair … … 141 141 (vvPair 142 142 variable "d" 143 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board"143 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board" 144 144 ) 145 145 (vvPair 146 146 variable "d_logical" 147 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board"147 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board" 148 148 ) 149 149 (vvPair 150 150 variable "date" 151 value " 27.08.2010"151 value "03.01.2011" 152 152 ) 153 153 (vvPair 154 154 variable "day" 155 value " Fr"155 value "Mo" 156 156 ) 157 157 (vvPair 158 158 variable "day_long" 159 value " Freitag"159 value "Montag" 160 160 ) 161 161 (vvPair 162 162 variable "dd" 163 value " 27"163 value "03" 164 164 ) 165 165 (vvPair … … 221 221 (vvPair 222 222 variable "mm" 223 value "0 8"223 value "01" 224 224 ) 225 225 (vvPair … … 229 229 (vvPair 230 230 variable "month" 231 value " Aug"231 value "Jan" 232 232 ) 233 233 (vvPair 234 234 variable "month_long" 235 value " August"235 value "Januar" 236 236 ) 237 237 (vvPair 238 238 variable "p" 239 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"239 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd" 240 240 ) 241 241 (vvPair 242 242 variable "p_logical" 243 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"243 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd" 244 244 ) 245 245 (vvPair … … 297 297 (vvPair 298 298 variable "time" 299 value "1 7:10:56"299 value "16:58:24" 300 300 ) 301 301 (vvPair … … 317 317 (vvPair 318 318 variable "year" 319 value "201 0"319 value "2011" 320 320 ) 321 321 (vvPair 322 322 variable "yy" 323 value "1 0"323 value "11" 324 324 ) 325 325 ] … … 349 349 bg "0,0,32768" 350 350 ) 351 xt "99200,4000,108 900,5000"351 xt "99200,4000,108700,5000" 352 352 st " 353 353 by %user on %dd %month %year … … 688 688 n "wiz_reset" 689 689 t "std_logic" 690 o 4 3690 o 44 691 691 suid 2,0 692 692 i "'1'" … … 727 727 b "(7 DOWNTO 0)" 728 728 posAdd 0 729 o 3 3729 o 34 730 730 suid 7,0 731 731 i "(OTHERS => '0')" … … 799 799 n "adc_oeb" 800 800 t "std_logic" 801 o 2 8801 o 29 802 802 suid 21,0 803 803 i "'1'" … … 909 909 t "std_logic_vector" 910 910 b "(9 DOWNTO 0)" 911 o 4 0911 o 41 912 912 suid 26,0 913 913 ) … … 945 945 n "wiz_cs" 946 946 t "std_logic" 947 o 4 1947 o 42 948 948 suid 28,0 949 949 i "'1'" … … 983 983 t "std_logic_vector" 984 984 b "(15 DOWNTO 0)" 985 o 4 6985 o 47 986 986 suid 27,0 987 987 ) … … 1054 1054 n "wiz_rd" 1055 1055 t "std_logic" 1056 o 4 21056 o 43 1057 1057 suid 30,0 1058 1058 i "'1'" … … 1091 1091 n "wiz_wr" 1092 1092 t "std_logic" 1093 o 4 41093 o 45 1094 1094 suid 29,0 1095 1095 i "'1'" … … 1301 1301 t "std_logic_vector" 1302 1302 b "(3 downto 0)" 1303 o 3 11303 o 32 1304 1304 suid 48,0 1305 1305 i "(others => '0')" … … 1337 1337 n "drs_dwrite" 1338 1338 t "std_logic" 1339 o 3 21339 o 33 1340 1340 suid 49,0 1341 1341 i "'1'" … … 1582 1582 n "dac_cs" 1583 1583 t "std_logic" 1584 o 291584 o 30 1585 1585 suid 64,0 1586 1586 ) … … 1618 1618 n "sclk" 1619 1619 t "std_logic" 1620 o 3 71620 o 38 1621 1621 suid 62,0 1622 1622 ) … … 1655 1655 t "std_logic_vector" 1656 1656 b "(3 DOWNTO 0)" 1657 o 3 81657 o 39 1658 1658 suid 65,0 1659 1659 ) … … 1693 1693 preAdd 0 1694 1694 posAdd 0 1695 o 4 51695 o 46 1696 1696 suid 63,0 1697 1697 ) … … 1729 1729 n "mosi" 1730 1730 t "std_logic" 1731 o 3 41731 o 35 1732 1732 suid 66,0 1733 1733 i "'0'" … … 1768 1768 eolc "-- default domino wave off" 1769 1769 posAdd 0 1770 o 3 01770 o 31 1771 1771 suid 67,0 1772 1772 i "'0'" … … 1804 1804 n "adc_clk_en" 1805 1805 t "std_logic" 1806 o 2 71806 o 28 1807 1807 suid 69,0 1808 1808 i "'0'" … … 1918 1918 preAdd 0 1919 1919 posAdd 0 1920 o 3 51920 o 36 1921 1921 suid 77,0 1922 1922 i "(OTHERS => '0')" … … 2173 2173 preAdd 0 2174 2174 posAdd 0 2175 o 3 62175 o 37 2176 2176 suid 79,0 2177 2177 i "'0'" … … 2213 2213 preAdd 0 2214 2214 posAdd 0 2215 o 392215 o 40 2216 2216 suid 78,0 2217 2217 i "'0'" … … 2327 2327 ) 2328 2328 ) 2329 *59 (CptPort 2330 uid 12314,0 2331 ps "OnEdgeStrategy" 2332 shape (Triangle 2333 uid 12315,0 2334 ro 90 2335 va (VaSet 2336 vasetType 1 2337 fg "0,65535,0" 2338 ) 2339 xt "80000,139625,80750,140375" 2340 ) 2341 tg (CPTG 2342 uid 12316,0 2343 ps "CptPortTextPlaceStrategy" 2344 stg "RightVerticalLayoutStrategy" 2345 f (Text 2346 uid 12317,0 2347 va (VaSet 2348 ) 2349 xt "75300,139500,79000,140500" 2350 st "SRIN_out" 2351 ju 2 2352 blo "79000,140300" 2353 ) 2354 ) 2355 thePort (LogicalPort 2356 m 1 2357 decl (Decl 2358 n "SRIN_out" 2359 t "std_logic" 2360 o 27 2361 suid 85,0 2362 i "'0'" 2363 ) 2364 ) 2365 ) 2329 2366 ] 2330 2367 shape (Rectangle … … 2336 2373 lineWidth 2 2337 2374 ) 2338 xt "52000,66000,80000,14 0000"2375 xt "52000,66000,80000,141000" 2339 2376 ) 2340 2377 oxt "15000,-1000,43000,27000" … … 2344 2381 stg "VerticalLayoutStrategy" 2345 2382 textVec [ 2346 * 59(Text2383 *60 (Text 2347 2384 uid 172,0 2348 2385 va (VaSet … … 2354 2391 tm "BdLibraryNameMgr" 2355 2392 ) 2356 *6 0(Text2393 *61 (Text 2357 2394 uid 173,0 2358 2395 va (VaSet … … 2364 2401 tm "CptNameMgr" 2365 2402 ) 2366 *6 1(Text2403 *62 (Text 2367 2404 uid 174,0 2368 2405 va (VaSet … … 2406 2443 fg "49152,49152,49152" 2407 2444 ) 2408 xt "52250,13 8250,53750,139750"2445 xt "52250,139250,53750,140750" 2409 2446 iconName "BlockDiagram.png" 2410 2447 iconMaskName "BlockDiagram.msk" … … 2416 2453 archFileType "UNKNOWN" 2417 2454 ) 2418 *6 2(PortIoIn2455 *63 (PortIoIn 2419 2456 uid 231,0 2420 2457 shape (CompositeShape … … 2461 2498 ) 2462 2499 ) 2463 *6 3(PortIoIn2500 *64 (PortIoIn 2464 2501 uid 251,0 2465 2502 shape (CompositeShape … … 2506 2543 ) 2507 2544 ) 2508 *6 4(HdlText2545 *65 (HdlText 2509 2546 uid 265,0 2510 2547 optionalChildren [ 2511 *6 5(EmbeddedText2548 *66 (EmbeddedText 2512 2549 uid 271,0 2513 2550 commentText (CommentText … … 2559 2596 stg "VerticalLayoutStrategy" 2560 2597 textVec [ 2561 *6 6(Text2598 *67 (Text 2562 2599 uid 268,0 2563 2600 va (VaSet … … 2569 2606 tm "HdlTextNameMgr" 2570 2607 ) 2571 *6 7(Text2608 *68 (Text 2572 2609 uid 269,0 2573 2610 va (VaSet … … 2595 2632 viewiconposition 0 2596 2633 ) 2597 *6 8(Net2634 *69 (Net 2598 2635 uid 275,0 2599 2636 decl (Decl … … 2603 2640 preAdd 0 2604 2641 posAdd 0 2605 o 552642 o 69 2606 2643 suid 5,0 2607 2644 ) … … 2611 2648 font "Courier New,8,0" 2612 2649 ) 2613 xt "39000, 57600,67500,58400"2650 xt "39000,60800,67500,61600" 2614 2651 st "SIGNAL board_id : std_logic_vector(3 downto 0) 2615 2652 " 2616 2653 ) 2617 2654 ) 2618 * 69(Net2655 *70 (Net 2619 2656 uid 283,0 2620 2657 decl (Decl … … 2622 2659 t "std_logic_vector" 2623 2660 b "(1 downto 0)" 2624 o 562661 o 70 2625 2662 suid 6,0 2626 2663 ) … … 2630 2667 font "Courier New,8,0" 2631 2668 ) 2632 xt "39000, 58400,67500,59200"2669 xt "39000,61600,67500,62400" 2633 2670 st "SIGNAL crate_id : std_logic_vector(1 downto 0) 2634 2671 " 2635 2672 ) 2636 2673 ) 2637 *7 0(PortIoOut2674 *71 (PortIoOut 2638 2675 uid 472,0 2639 2676 shape (CompositeShape … … 2679 2716 ) 2680 2717 ) 2681 *7 1(PortIoOut2718 *72 (PortIoOut 2682 2719 uid 478,0 2683 2720 shape (CompositeShape … … 2723 2760 ) 2724 2761 ) 2725 *7 2(PortIoOut2762 *73 (PortIoOut 2726 2763 uid 484,0 2727 2764 shape (CompositeShape … … 2767 2804 ) 2768 2805 ) 2769 *7 3(PortIoInOut2806 *74 (PortIoInOut 2770 2807 uid 490,0 2771 2808 shape (CompositeShape … … 2809 2846 ) 2810 2847 ) 2811 *7 4(PortIoIn2848 *75 (PortIoIn 2812 2849 uid 496,0 2813 2850 shape (CompositeShape … … 2853 2890 ) 2854 2891 ) 2855 *7 5(PortIoOut2892 *76 (PortIoOut 2856 2893 uid 502,0 2857 2894 shape (CompositeShape … … 2897 2934 ) 2898 2935 ) 2899 *7 6(PortIoOut2936 *77 (PortIoOut 2900 2937 uid 508,0 2901 2938 shape (CompositeShape … … 2941 2978 ) 2942 2979 ) 2943 *7 7(Net2980 *78 (Net 2944 2981 uid 1465,0 2945 2982 decl (Decl 2946 2983 n "adc_data_array" 2947 2984 t "adc_data_array_type" 2948 o 542985 o 68 2949 2986 suid 29,0 2950 2987 ) … … 2954 2991 font "Courier New,8,0" 2955 2992 ) 2956 xt "39000, 56800,63000,57600"2993 xt "39000,60000,63000,60800" 2957 2994 st "SIGNAL adc_data_array : adc_data_array_type 2958 2995 " 2959 2996 ) 2960 2997 ) 2961 *7 8(Net2998 *79 (Net 2962 2999 uid 2407,0 2963 3000 decl (Decl 2964 3001 n "RSRLOAD" 2965 3002 t "std_logic" 2966 o 3 53003 o 37 2967 3004 suid 57,0 2968 3005 i "'0'" … … 2973 3010 font "Courier New,8,0" 2974 3011 ) 2975 xt "39000,3 1000,68500,31800"3012 xt "39000,34200,68500,35000" 2976 3013 st "RSRLOAD : std_logic := '0' 2977 3014 " 2978 3015 ) 2979 3016 ) 2980 * 79(PortIoOut3017 *80 (PortIoOut 2981 3018 uid 2415,0 2982 3019 shape (CompositeShape … … 3023 3060 ) 3024 3061 ) 3025 *8 0(Net3062 *81 (Net 3026 3063 uid 2421,0 3027 3064 decl (Decl 3028 3065 n "SRCLK" 3029 3066 t "std_logic" 3030 o 523067 o 66 3031 3068 suid 58,0 3032 3069 i "'0'" … … 3037 3074 font "Courier New,8,0" 3038 3075 ) 3039 xt "39000,5 5200,72000,56000"3076 xt "39000,58400,72000,59200" 3040 3077 st "SIGNAL SRCLK : std_logic := '0' 3041 3078 " 3042 3079 ) 3043 3080 ) 3044 *8 1(Net3081 *82 (Net 3045 3082 uid 3019,0 3046 3083 decl (Decl … … 3048 3085 t "std_logic_vector" 3049 3086 b "(3 DOWNTO 0)" 3050 o 593087 o 74 3051 3088 suid 65,0 3052 3089 ) … … 3056 3093 font "Courier New,8,0" 3057 3094 ) 3058 xt "39000,6 1600,67500,62400"3095 xt "39000,64800,67500,65600" 3059 3096 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0) 3060 3097 " 3061 3098 ) 3062 3099 ) 3063 *8 2(Net3100 *83 (Net 3064 3101 uid 3025,0 3065 3102 decl (Decl 3066 3103 n "DAC_CS" 3067 3104 t "std_logic" 3068 o 2 13105 o 22 3069 3106 suid 66,0 3070 3107 ) … … 3074 3111 font "Courier New,8,0" 3075 3112 ) 3076 xt "39000, 19800,54000,20600"3113 xt "39000,22200,54000,23000" 3077 3114 st "DAC_CS : std_logic 3078 3115 " 3079 3116 ) 3080 3117 ) 3081 *8 3(PortIoOut3118 *84 (PortIoOut 3082 3119 uid 3153,0 3083 3120 shape (CompositeShape … … 3124 3161 ) 3125 3162 ) 3126 *8 4(Net3163 *85 (Net 3127 3164 uid 3216,0 3128 3165 decl (Decl … … 3139 3176 font "Courier New,8,0" 3140 3177 ) 3141 xt "39000,1 3400,54000,14200"3178 xt "39000,15800,54000,16600" 3142 3179 st "X_50M : STD_LOGIC 3143 3180 " 3144 3181 ) 3145 3182 ) 3146 *8 5(Net3183 *86 (Net 3147 3184 uid 3226,0 3148 3185 decl (Decl … … 3157 3194 font "Courier New,8,0" 3158 3195 ) 3159 xt "39000,1 1800,54000,12600"3196 xt "39000,14200,54000,15000" 3160 3197 st "TRG : STD_LOGIC 3161 3198 " 3162 3199 ) 3163 3200 ) 3164 *8 6(HdlText3201 *87 (HdlText 3165 3202 uid 3248,0 3166 3203 optionalChildren [ 3167 *8 7(EmbeddedText3204 *88 (EmbeddedText 3168 3205 uid 3254,0 3169 3206 commentText (CommentText … … 3217 3254 stg "VerticalLayoutStrategy" 3218 3255 textVec [ 3219 *8 8(Text3256 *89 (Text 3220 3257 uid 3251,0 3221 3258 va (VaSet … … 3227 3264 tm "HdlTextNameMgr" 3228 3265 ) 3229 * 89(Text3266 *90 (Text 3230 3267 uid 3252,0 3231 3268 va (VaSet … … 3253 3290 viewiconposition 0 3254 3291 ) 3255 *9 0(Net3292 *91 (Net 3256 3293 uid 3266,0 3257 3294 decl (Decl … … 3259 3296 t "std_logic_vector" 3260 3297 b "(3 downto 0)" 3261 o 1 63298 o 17 3262 3299 suid 71,0 3263 3300 ) … … 3267 3304 font "Courier New,8,0" 3268 3305 ) 3269 xt "39000,1 5800,64000,16600"3306 xt "39000,18200,64000,19000" 3270 3307 st "A_CLK : std_logic_vector(3 downto 0) 3271 3308 " 3272 3309 ) 3273 3310 ) 3274 *9 1(Net3311 *92 (Net 3275 3312 uid 3268,0 3276 3313 decl (Decl 3277 3314 n "CLK_25_PS" 3278 3315 t "std_logic" 3279 o 5 03316 o 55 3280 3317 suid 72,0 3281 3318 ) … … 3285 3322 font "Courier New,8,0" 3286 3323 ) 3287 xt "39000,4 6400,57500,47200"3324 xt "39000,49600,57500,50400" 3288 3325 st "SIGNAL CLK_25_PS : std_logic 3289 3326 " 3290 3327 ) 3291 3328 ) 3292 *9 2(PortIoOut3329 *93 (PortIoOut 3293 3330 uid 3284,0 3294 3331 shape (CompositeShape … … 3335 3372 ) 3336 3373 ) 3337 *9 3(Net3374 *94 (Net 3338 3375 uid 3290,0 3339 3376 decl (Decl … … 3342 3379 preAdd 0 3343 3380 posAdd 0 3344 o 3 03381 o 31 3345 3382 suid 73,0 3346 3383 ) … … 3350 3387 font "Courier New,8,0" 3351 3388 ) 3352 xt "39000,2 7000,54000,27800"3389 xt "39000,29400,54000,30200" 3353 3390 st "OE_ADC : STD_LOGIC 3354 3391 " 3355 3392 ) 3356 3393 ) 3357 *9 4(PortIoIn3394 *95 (PortIoIn 3358 3395 uid 3292,0 3359 3396 shape (CompositeShape … … 3400 3437 ) 3401 3438 ) 3402 *9 5(Net3439 *96 (Net 3403 3440 uid 3298,0 3404 3441 decl (Decl … … 3419 3456 ) 3420 3457 ) 3421 *9 6(HdlText3458 *97 (HdlText 3422 3459 uid 3300,0 3423 3460 optionalChildren [ 3424 *9 7(EmbeddedText3461 *98 (EmbeddedText 3425 3462 uid 3306,0 3426 3463 commentText (CommentText … … 3474 3511 stg "VerticalLayoutStrategy" 3475 3512 textVec [ 3476 *9 8(Text3513 *99 (Text 3477 3514 uid 3303,0 3478 3515 va (VaSet … … 3484 3521 tm "HdlTextNameMgr" 3485 3522 ) 3486 * 99(Text3523 *100 (Text 3487 3524 uid 3304,0 3488 3525 va (VaSet … … 3510 3547 viewiconposition 0 3511 3548 ) 3512 *10 0(PortIoIn3549 *101 (PortIoIn 3513 3550 uid 3310,0 3514 3551 shape (CompositeShape … … 3555 3592 ) 3556 3593 ) 3557 *10 1(PortIoIn3594 *102 (PortIoIn 3558 3595 uid 3332,0 3559 3596 shape (CompositeShape … … 3600 3637 ) 3601 3638 ) 3602 *10 2(PortIoIn3639 *103 (PortIoIn 3603 3640 uid 3338,0 3604 3641 shape (CompositeShape … … 3645 3682 ) 3646 3683 ) 3647 *10 3(PortIoIn3684 *104 (PortIoIn 3648 3685 uid 3344,0 3649 3686 shape (CompositeShape … … 3690 3727 ) 3691 3728 ) 3692 *10 4(Net3729 *105 (Net 3693 3730 uid 3374,0 3694 3731 decl (Decl … … 3709 3746 ) 3710 3747 ) 3711 *10 5(Net3748 *106 (Net 3712 3749 uid 3376,0 3713 3750 decl (Decl … … 3728 3765 ) 3729 3766 ) 3730 *10 6(Net3767 *107 (Net 3731 3768 uid 3378,0 3732 3769 decl (Decl … … 3747 3784 ) 3748 3785 ) 3749 *10 7(Net3786 *108 (Net 3750 3787 uid 3380,0 3751 3788 decl (Decl … … 3766 3803 ) 3767 3804 ) 3768 *10 8(HdlText3805 *109 (HdlText 3769 3806 uid 3394,0 3770 3807 optionalChildren [ 3771 *1 09(EmbeddedText3808 *110 (EmbeddedText 3772 3809 uid 3400,0 3773 3810 commentText (CommentText … … 3821 3858 stg "VerticalLayoutStrategy" 3822 3859 textVec [ 3823 *11 0(Text3860 *111 (Text 3824 3861 uid 3397,0 3825 3862 va (VaSet … … 3831 3868 tm "HdlTextNameMgr" 3832 3869 ) 3833 *11 1(Text3870 *112 (Text 3834 3871 uid 3398,0 3835 3872 va (VaSet … … 3857 3894 viewiconposition 0 3858 3895 ) 3859 *11 2(Net3896 *113 (Net 3860 3897 uid 3460,0 3861 3898 decl (Decl 3862 3899 n "D0_SRCLK" 3863 3900 t "STD_LOGIC" 3864 o 1 73901 o 18 3865 3902 suid 87,0 3866 3903 ) … … 3870 3907 font "Courier New,8,0" 3871 3908 ) 3872 xt "39000,1 6600,54000,17400"3909 xt "39000,19000,54000,19800" 3873 3910 st "D0_SRCLK : STD_LOGIC 3874 3911 " 3875 3912 ) 3876 3913 ) 3877 *11 3(Net3914 *114 (Net 3878 3915 uid 3462,0 3879 3916 decl (Decl 3880 3917 n "D1_SRCLK" 3881 3918 t "STD_LOGIC" 3882 o 1 83919 o 19 3883 3920 suid 88,0 3884 3921 ) … … 3888 3925 font "Courier New,8,0" 3889 3926 ) 3890 xt "39000,1 7400,54000,18200"3927 xt "39000,19800,54000,20600" 3891 3928 st "D1_SRCLK : STD_LOGIC 3892 3929 " 3893 3930 ) 3894 3931 ) 3895 *11 4(Net3932 *115 (Net 3896 3933 uid 3464,0 3897 3934 decl (Decl 3898 3935 n "D2_SRCLK" 3899 3936 t "STD_LOGIC" 3900 o 193937 o 20 3901 3938 suid 89,0 3902 3939 ) … … 3906 3943 font "Courier New,8,0" 3907 3944 ) 3908 xt "39000, 18200,54000,19000"3945 xt "39000,20600,54000,21400" 3909 3946 st "D2_SRCLK : STD_LOGIC 3910 3947 " 3911 3948 ) 3912 3949 ) 3913 *11 5(Net3950 *116 (Net 3914 3951 uid 3466,0 3915 3952 decl (Decl 3916 3953 n "D3_SRCLK" 3917 3954 t "STD_LOGIC" 3918 o 2 03955 o 21 3919 3956 suid 90,0 3920 3957 ) … … 3924 3961 font "Courier New,8,0" 3925 3962 ) 3926 xt "39000, 19000,54000,19800"3963 xt "39000,21400,54000,22200" 3927 3964 st "D3_SRCLK : STD_LOGIC 3928 3965 " 3929 3966 ) 3930 3967 ) 3931 *11 6(PortIoIn3968 *117 (PortIoIn 3932 3969 uid 3476,0 3933 3970 shape (CompositeShape … … 3974 4011 ) 3975 4012 ) 3976 *11 7(PortIoIn4013 *118 (PortIoIn 3977 4014 uid 3482,0 3978 4015 shape (CompositeShape … … 4019 4056 ) 4020 4057 ) 4021 *11 8(PortIoIn4058 *119 (PortIoIn 4022 4059 uid 3488,0 4023 4060 shape (CompositeShape … … 4064 4101 ) 4065 4102 ) 4066 *1 19(PortIoIn4103 *120 (PortIoIn 4067 4104 uid 3494,0 4068 4105 shape (CompositeShape … … 4109 4146 ) 4110 4147 ) 4111 *12 0(Net4148 *121 (Net 4112 4149 uid 3500,0 4113 4150 decl (Decl … … 4127 4164 ) 4128 4165 ) 4129 *12 1(Net4166 *122 (Net 4130 4167 uid 3502,0 4131 4168 decl (Decl … … 4145 4182 ) 4146 4183 ) 4147 *12 2(Net4184 *123 (Net 4148 4185 uid 3504,0 4149 4186 decl (Decl … … 4163 4200 ) 4164 4201 ) 4165 *12 3(Net4202 *124 (Net 4166 4203 uid 3506,0 4167 4204 decl (Decl … … 4181 4218 ) 4182 4219 ) 4183 *12 4(PortIoOut4220 *125 (PortIoOut 4184 4221 uid 3508,0 4185 4222 shape (CompositeShape … … 4226 4263 ) 4227 4264 ) 4228 *12 5(Net4265 *126 (Net 4229 4266 uid 3514,0 4230 4267 decl (Decl … … 4232 4269 t "std_logic_vector" 4233 4270 b "(3 DOWNTO 0)" 4234 o 2 44271 o 25 4235 4272 suid 95,0 4236 4273 i "(others => '0')" … … 4241 4278 font "Courier New,8,0" 4242 4279 ) 4243 xt "39000,2 2200,74500,23000"4280 xt "39000,24600,74500,25400" 4244 4281 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0') 4245 4282 " 4246 4283 ) 4247 4284 ) 4248 *12 6(PortIoOut4285 *127 (PortIoOut 4249 4286 uid 3516,0 4250 4287 shape (CompositeShape … … 4291 4328 ) 4292 4329 ) 4293 *12 7(Net4330 *128 (Net 4294 4331 uid 3522,0 4295 4332 decl (Decl 4296 4333 n "DWRITE" 4297 4334 t "std_logic" 4298 o 2 34335 o 24 4299 4336 suid 96,0 4300 4337 i "'0'" … … 4305 4342 font "Courier New,8,0" 4306 4343 ) 4307 xt "39000,2 1400,68500,22200"4344 xt "39000,23800,68500,24600" 4308 4345 st "DWRITE : std_logic := '0' 4309 4346 " 4310 4347 ) 4311 4348 ) 4312 *12 8(PortIoOut4349 *129 (PortIoOut 4313 4350 uid 3536,0 4314 4351 shape (CompositeShape … … 4354 4391 ) 4355 4392 ) 4356 *1 29(HdlText4393 *130 (HdlText 4357 4394 uid 3542,0 4358 4395 optionalChildren [ 4359 *13 0(EmbeddedText4396 *131 (EmbeddedText 4360 4397 uid 3612,0 4361 4398 commentText (CommentText … … 4409 4446 stg "VerticalLayoutStrategy" 4410 4447 textVec [ 4411 *13 1(Text4448 *132 (Text 4412 4449 uid 3545,0 4413 4450 va (VaSet … … 4419 4456 tm "HdlTextNameMgr" 4420 4457 ) 4421 *13 2(Text4458 *133 (Text 4422 4459 uid 3546,0 4423 4460 va (VaSet … … 4445 4482 viewiconposition 0 4446 4483 ) 4447 *13 3(PortIoOut4484 *134 (PortIoOut 4448 4485 uid 3548,0 4449 4486 shape (CompositeShape … … 4489 4526 ) 4490 4527 ) 4491 *13 4(PortIoOut4528 *135 (PortIoOut 4492 4529 uid 3554,0 4493 4530 shape (CompositeShape … … 4533 4570 ) 4534 4571 ) 4535 *13 5(PortIoOut4572 *136 (PortIoOut 4536 4573 uid 3560,0 4537 4574 shape (CompositeShape … … 4577 4614 ) 4578 4615 ) 4579 *13 6(PortIoOut4616 *137 (PortIoOut 4580 4617 uid 3566,0 4581 4618 shape (CompositeShape … … 4621 4658 ) 4622 4659 ) 4623 *13 7(Net4660 *138 (Net 4624 4661 uid 3604,0 4625 4662 decl (Decl 4626 4663 n "T0_CS" 4627 4664 t "std_logic" 4628 o 384665 o 40 4629 4666 suid 101,0 4630 4667 ) … … 4634 4671 font "Courier New,8,0" 4635 4672 ) 4636 xt "39000,3 3400,54000,34200"4673 xt "39000,36600,54000,37400" 4637 4674 st "T0_CS : std_logic 4638 4675 " 4639 4676 ) 4640 4677 ) 4641 *13 8(Net4678 *139 (Net 4642 4679 uid 3606,0 4643 4680 decl (Decl 4644 4681 n "T1_CS" 4645 4682 t "std_logic" 4646 o 394683 o 41 4647 4684 suid 102,0 4648 4685 ) … … 4652 4689 font "Courier New,8,0" 4653 4690 ) 4654 xt "39000,3 4200,54000,35000"4691 xt "39000,37400,54000,38200" 4655 4692 st "T1_CS : std_logic 4656 4693 " 4657 4694 ) 4658 4695 ) 4659 *1 39(Net4696 *140 (Net 4660 4697 uid 3608,0 4661 4698 decl (Decl 4662 4699 n "T2_CS" 4663 4700 t "std_logic" 4664 o 4 04701 o 42 4665 4702 suid 103,0 4666 4703 ) … … 4670 4707 font "Courier New,8,0" 4671 4708 ) 4672 xt "39000,3 5000,54000,35800"4709 xt "39000,38200,54000,39000" 4673 4710 st "T2_CS : std_logic 4674 4711 " 4675 4712 ) 4676 4713 ) 4677 *14 0(Net4714 *141 (Net 4678 4715 uid 3610,0 4679 4716 decl (Decl 4680 4717 n "T3_CS" 4681 4718 t "std_logic" 4682 o 4 14719 o 43 4683 4720 suid 104,0 4684 4721 ) … … 4688 4725 font "Courier New,8,0" 4689 4726 ) 4690 xt "39000,3 5800,54000,36600"4727 xt "39000,39000,54000,39800" 4691 4728 st "T3_CS : std_logic 4692 4729 " 4693 4730 ) 4694 4731 ) 4695 *14 1(PortIoOut4732 *142 (PortIoOut 4696 4733 uid 3624,0 4697 4734 shape (CompositeShape … … 4737 4774 ) 4738 4775 ) 4739 *14 2(Net4776 *143 (Net 4740 4777 uid 3630,0 4741 4778 decl (Decl 4742 4779 n "S_CLK" 4743 4780 t "std_logic" 4744 o 3 74781 o 39 4745 4782 suid 105,0 4746 4783 ) … … 4750 4787 font "Courier New,8,0" 4751 4788 ) 4752 xt "39000,3 2600,54000,33400"4789 xt "39000,35800,54000,36600" 4753 4790 st "S_CLK : std_logic 4754 4791 " 4755 4792 ) 4756 4793 ) 4757 *14 3(Net4794 *144 (Net 4758 4795 uid 3632,0 4759 4796 decl (Decl … … 4761 4798 t "std_logic_vector" 4762 4799 b "(9 DOWNTO 0)" 4763 o 4 34800 o 45 4764 4801 suid 106,0 4765 4802 ) … … 4769 4806 font "Courier New,8,0" 4770 4807 ) 4771 xt "39000, 37400,64000,38200"4808 xt "39000,40600,64000,41400" 4772 4809 st "W_A : std_logic_vector(9 DOWNTO 0) 4773 4810 " 4774 4811 ) 4775 4812 ) 4776 *14 4(Net4813 *145 (Net 4777 4814 uid 3634,0 4778 4815 decl (Decl … … 4780 4817 t "std_logic_vector" 4781 4818 b "(15 DOWNTO 0)" 4782 o 494819 o 51 4783 4820 suid 107,0 4784 4821 ) … … 4788 4825 font "Courier New,8,0" 4789 4826 ) 4790 xt "39000,4 2200,64500,43000"4827 xt "39000,45400,64500,46200" 4791 4828 st "W_D : std_logic_vector(15 DOWNTO 0) 4792 4829 " 4793 4830 ) 4794 4831 ) 4795 *14 5(Net4832 *146 (Net 4796 4833 uid 3636,0 4797 4834 decl (Decl 4798 4835 n "W_RES" 4799 4836 t "std_logic" 4800 o 4 64837 o 48 4801 4838 suid 108,0 4802 4839 i "'1'" … … 4807 4844 font "Courier New,8,0" 4808 4845 ) 4809 xt "39000, 39800,68500,40600"4846 xt "39000,43000,68500,43800" 4810 4847 st "W_RES : std_logic := '1' 4811 4848 " 4812 4849 ) 4813 4850 ) 4814 *14 6(Net4851 *147 (Net 4815 4852 uid 3638,0 4816 4853 decl (Decl 4817 4854 n "W_RD" 4818 4855 t "std_logic" 4819 o 4 54856 o 47 4820 4857 suid 109,0 4821 4858 i "'1'" … … 4826 4863 font "Courier New,8,0" 4827 4864 ) 4828 xt "39000, 39000,68500,39800"4865 xt "39000,42200,68500,43000" 4829 4866 st "W_RD : std_logic := '1' 4830 4867 " 4831 4868 ) 4832 4869 ) 4833 *14 7(Net4870 *148 (Net 4834 4871 uid 3640,0 4835 4872 decl (Decl 4836 4873 n "W_WR" 4837 4874 t "std_logic" 4838 o 4 74875 o 49 4839 4876 suid 110,0 4840 4877 i "'1'" … … 4845 4882 font "Courier New,8,0" 4846 4883 ) 4847 xt "39000,4 0600,68500,41400"4884 xt "39000,43800,68500,44600" 4848 4885 st "W_WR : std_logic := '1' 4849 4886 " 4850 4887 ) 4851 4888 ) 4852 *14 8(Net4889 *149 (Net 4853 4890 uid 3642,0 4854 4891 decl (Decl … … 4863 4900 font "Courier New,8,0" 4864 4901 ) 4865 xt "39000,1 2600,54000,13400"4902 xt "39000,15000,54000,15800" 4866 4903 st "W_INT : std_logic 4867 4904 " 4868 4905 ) 4869 4906 ) 4870 *1 49(Net4907 *150 (Net 4871 4908 uid 3644,0 4872 4909 decl (Decl 4873 4910 n "W_CS" 4874 4911 t "std_logic" 4875 o 4 44912 o 46 4876 4913 suid 112,0 4877 4914 i "'1'" … … 4882 4919 font "Courier New,8,0" 4883 4920 ) 4884 xt "39000, 38200,68500,39000"4921 xt "39000,41400,68500,42200" 4885 4922 st "W_CS : std_logic := '1' 4886 4923 " 4887 4924 ) 4888 4925 ) 4889 *15 0(PortIoInOut4926 *151 (PortIoInOut 4890 4927 uid 3674,0 4891 4928 shape (CompositeShape … … 4929 4966 ) 4930 4967 ) 4931 *15 1(Net4968 *152 (Net 4932 4969 uid 3680,0 4933 4970 decl (Decl 4934 4971 n "MOSI" 4935 4972 t "std_logic" 4936 o 294973 o 30 4937 4974 suid 113,0 4938 4975 i "'0'" … … 4943 4980 font "Courier New,8,0" 4944 4981 ) 4945 xt "39000,2 6200,68500,27000"4982 xt "39000,28600,68500,29400" 4946 4983 st "MOSI : std_logic := '0' 4947 4984 " 4948 4985 ) 4949 4986 ) 4950 *15 2(PortIoOut4987 *153 (PortIoOut 4951 4988 uid 3688,0 4952 4989 shape (CompositeShape … … 4992 5029 ) 4993 5030 ) 4994 *15 3(Net5031 *154 (Net 4995 5032 uid 3694,0 4996 5033 decl (Decl … … 4999 5036 preAdd 0 5000 5037 posAdd 0 5001 o 485038 o 50 5002 5039 suid 114,0 5003 5040 ) … … 5007 5044 font "Courier New,8,0" 5008 5045 ) 5009 xt "39000,4 1400,54000,42200"5046 xt "39000,44600,54000,45400" 5010 5047 st "MISO : std_logic 5011 5048 " 5012 5049 ) 5013 5050 ) 5014 *15 4(HdlText5051 *155 (HdlText 5015 5052 uid 3700,0 5016 5053 optionalChildren [ 5017 *15 5(EmbeddedText5054 *156 (EmbeddedText 5018 5055 uid 3706,0 5019 5056 commentText (CommentText … … 5028 5065 lineWidth 2 5029 5066 ) 5030 xt "82000,10 2000,100000,118000"5067 xt "82000,106000,99000,118000" 5031 5068 ) 5032 5069 oxt "0,0,18000,5000" … … 5035 5072 va (VaSet 5036 5073 ) 5037 xt "82200,10 2200,98600,118200"5074 xt "82200,106200,98600,118200" 5038 5075 st " 5039 5076 -- MISC 6 5040 5077 TRG_V <= '0'; 5041 RS485_C_RE <= ' 1';5078 RS485_C_RE <= '0'; 5042 5079 RS485_C_DE <= '0'; 5043 RS485_E_RE <= '1'; 5080 RS485_C_DO <= RS485_C_DI; 5081 5082 RS485_E_RE <= '0'; 5044 5083 RS485_E_DE <= '0'; 5084 --RS485_E_DO <= RS485_E_DI; 5045 5085 5046 5086 -- DENABLE <= '0'; -- domino wave stopped 5047 5087 -- DENABLE <= '1'; -- domino wave running 5048 5088 5049 SRIN <= '1'; 5089 5050 5090 EE_CS <= '1'; 5051 5091 -- LEDs are low active … … 5060 5100 tm "HdlTextMgr" 5061 5101 wrapOption 3 5062 visibleHeight 1 60005063 visibleWidth 1 80005102 visibleHeight 12000 5103 visibleWidth 17000 5064 5104 ) 5065 5105 ) … … 5082 5122 stg "VerticalLayoutStrategy" 5083 5123 textVec [ 5084 *15 6(Text5124 *157 (Text 5085 5125 uid 3703,0 5086 5126 va (VaSet … … 5092 5132 tm "HdlTextNameMgr" 5093 5133 ) 5094 *15 7(Text5134 *158 (Text 5095 5135 uid 3704,0 5096 5136 va (VaSet … … 5118 5158 viewiconposition 0 5119 5159 ) 5120 *15 8(PortIoOut5160 *159 (PortIoOut 5121 5161 uid 3710,0 5122 5162 shape (CompositeShape … … 5162 5202 ) 5163 5203 ) 5164 *1 59(PortIoOut5204 *160 (PortIoOut 5165 5205 uid 3716,0 5166 5206 shape (CompositeShape … … 5206 5246 ) 5207 5247 ) 5208 *16 0(PortIoOut5248 *161 (PortIoOut 5209 5249 uid 3722,0 5210 5250 shape (CompositeShape … … 5250 5290 ) 5251 5291 ) 5252 *16 1(PortIoOut5292 *162 (PortIoOut 5253 5293 uid 3728,0 5254 5294 shape (CompositeShape … … 5294 5334 ) 5295 5335 ) 5296 *16 2(PortIoOut5336 *163 (PortIoOut 5297 5337 uid 3734,0 5298 5338 shape (CompositeShape … … 5338 5378 ) 5339 5379 ) 5340 *16 3(PortIoOut5380 *164 (PortIoOut 5341 5381 uid 3740,0 5342 5382 shape (CompositeShape … … 5378 5418 st "DENABLE" 5379 5419 blo "114000,121300" 5380 tm "WireNameMgr"5381 )5382 )5383 )5384 *164 (PortIoOut5385 uid 3746,05386 shape (CompositeShape5387 uid 3747,05388 va (VaSet5389 vasetType 15390 fg "0,0,32768"5391 )5392 optionalChildren [5393 (Pentagon5394 uid 3748,05395 sl 05396 ro 2705397 xt "111500,108625,113000,109375"5398 )5399 (Line5400 uid 3749,05401 sl 05402 ro 2705403 xt "111000,109000,111500,109000"5404 pts [5405 "111000,109000"5406 "111500,109000"5407 ]5408 )5409 ]5410 )5411 stc 05412 sf 15413 tg (WTG5414 uid 3750,05415 ps "PortIoTextPlaceStrategy"5416 stg "STSignalDisplayStrategy"5417 f (Text5418 uid 3751,05419 va (VaSet5420 )5421 xt "114000,108500,116300,109500"5422 st "SRIN"5423 blo "114000,109300"5424 5420 tm "WireNameMgr" 5425 5421 ) … … 5519 5515 n "TRG_V" 5520 5516 t "std_logic" 5521 o 4 25517 o 44 5522 5518 suid 126,0 5523 5519 ) … … 5527 5523 font "Courier New,8,0" 5528 5524 ) 5529 xt "39000,3 6600,54000,37400"5525 xt "39000,39800,54000,40600" 5530 5526 st "TRG_V : std_logic 5531 5527 " … … 5537 5533 n "RS485_C_RE" 5538 5534 t "std_logic" 5539 o 3 25535 o 34 5540 5536 suid 127,0 5541 5537 ) … … 5545 5541 font "Courier New,8,0" 5546 5542 ) 5547 xt "39000, 28600,54000,29400"5543 xt "39000,31800,54000,32600" 5548 5544 st "RS485_C_RE : std_logic 5549 5545 " … … 5555 5551 n "RS485_C_DE" 5556 5552 t "std_logic" 5557 o 3 15553 o 32 5558 5554 suid 128,0 5559 5555 ) … … 5563 5559 font "Courier New,8,0" 5564 5560 ) 5565 xt "39000, 27800,54000,28600"5561 xt "39000,30200,54000,31000" 5566 5562 st "RS485_C_DE : std_logic 5567 5563 " … … 5573 5569 n "RS485_E_RE" 5574 5570 t "std_logic" 5575 o 3 45571 o 36 5576 5572 suid 129,0 5577 5573 ) … … 5581 5577 font "Courier New,8,0" 5582 5578 ) 5583 xt "39000,3 0200,54000,31000"5579 xt "39000,33400,54000,34200" 5584 5580 st "RS485_E_RE : std_logic 5585 5581 " … … 5591 5587 n "RS485_E_DE" 5592 5588 t "std_logic" 5593 o 3 35589 o 35 5594 5590 suid 130,0 5595 5591 ) … … 5599 5595 font "Courier New,8,0" 5600 5596 ) 5601 xt "39000, 29400,54000,30200"5597 xt "39000,32600,54000,33400" 5602 5598 st "RS485_E_DE : std_logic 5603 5599 " … … 5609 5605 n "DENABLE" 5610 5606 t "std_logic" 5611 o 2 25607 o 23 5612 5608 suid 131,0 5613 5609 i "'0'" … … 5618 5614 font "Courier New,8,0" 5619 5615 ) 5620 xt "39000,2 0600,68500,21400"5616 xt "39000,23000,68500,23800" 5621 5617 st "DENABLE : std_logic := '0' 5622 5618 " … … 5624 5620 ) 5625 5621 *173 (Net 5626 uid 3876,05627 decl (Decl5628 n "SRIN"5629 t "std_logic"5630 o 365631 suid 132,05632 )5633 declText (MLText5634 uid 3877,05635 va (VaSet5636 font "Courier New,8,0"5637 )5638 xt "39000,31800,54000,32600"5639 st "SRIN : std_logic5640 "5641 )5642 )5643 *174 (Net5644 5622 uid 3878,0 5645 5623 decl (Decl 5646 5624 n "EE_CS" 5647 5625 t "std_logic" 5648 o 2 75626 o 28 5649 5627 suid 133,0 5650 5628 ) … … 5654 5632 font "Courier New,8,0" 5655 5633 ) 5656 xt "39000,2 4600,54000,25400"5634 xt "39000,27000,54000,27800" 5657 5635 st "EE_CS : std_logic 5658 5636 " 5659 5637 ) 5660 5638 ) 5661 *17 5(Net5639 *174 (Net 5662 5640 uid 3880,0 5663 5641 decl (Decl … … 5665 5643 t "std_logic_vector" 5666 5644 b "( 2 DOWNTO 0 )" 5667 o 2 85645 o 29 5668 5646 suid 134,0 5669 5647 i "(others => '1')" … … 5674 5652 font "Courier New,8,0" 5675 5653 ) 5676 xt "39000,2 5400,74500,26200"5654 xt "39000,27800,74500,28600" 5677 5655 st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1') 5678 5656 " 5679 5657 ) 5680 5658 ) 5681 *17 6(PortIoOut5659 *175 (PortIoOut 5682 5660 uid 3995,0 5683 5661 shape (CompositeShape … … 5724 5702 ) 5725 5703 ) 5726 *17 7(PortIoOut5704 *176 (PortIoOut 5727 5705 uid 4001,0 5728 5706 shape (CompositeShape … … 5769 5747 ) 5770 5748 ) 5771 *17 8(PortIoOut5749 *177 (PortIoOut 5772 5750 uid 4007,0 5773 5751 shape (CompositeShape … … 5814 5792 ) 5815 5793 ) 5816 *17 9(PortIoOut5794 *178 (PortIoOut 5817 5795 uid 4013,0 5818 5796 shape (CompositeShape … … 5859 5837 ) 5860 5838 ) 5861 *1 80(PortIoOut5839 *179 (PortIoOut 5862 5840 uid 4916,0 5863 5841 shape (CompositeShape … … 5903 5881 ) 5904 5882 ) 5905 *18 1(Net5883 *180 (Net 5906 5884 uid 5320,0 5907 5885 decl (Decl … … 5909 5887 t "std_logic_vector" 5910 5888 b "(7 DOWNTO 0)" 5911 o 2 55889 o 26 5912 5890 suid 141,0 5913 5891 i "(OTHERS => '0')" … … 5918 5896 font "Courier New,8,0" 5919 5897 ) 5920 xt "39000,2 3000,74500,23800"5898 xt "39000,25400,74500,26200" 5921 5899 st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 5922 5900 " 5923 5901 ) 5924 5902 ) 5925 *18 2(PortIoIn5903 *181 (PortIoIn 5926 5904 uid 6781,0 5927 5905 shape (CompositeShape … … 5968 5946 ) 5969 5947 ) 5970 *18 3(Net5948 *182 (Net 5971 5949 uid 6793,0 5972 5950 decl (Decl … … 5987 5965 ) 5988 5966 ) 5989 *18 4(PortIoOut5967 *183 (PortIoOut 5990 5968 uid 6874,0 5991 5969 shape (CompositeShape … … 6031 6009 ) 6032 6010 ) 6033 *18 5(Net6011 *184 (Net 6034 6012 uid 6886,0 6035 6013 decl (Decl … … 6037 6015 t "std_logic_vector" 6038 6016 b "(3 DOWNTO 0)" 6039 o 2 66017 o 27 6040 6018 suid 154,0 6041 6019 i "(others => '0')" … … 6046 6024 font "Courier New,8,0" 6047 6025 ) 6048 xt "39000,2 3800,74500,24600"6026 xt "39000,26200,74500,27000" 6049 6027 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0') 6050 6028 " 6051 6029 ) 6052 6030 ) 6053 *18 6(HdlText6031 *185 (HdlText 6054 6032 uid 6888,0 6055 6033 optionalChildren [ 6056 *18 7(EmbeddedText6034 *186 (EmbeddedText 6057 6035 uid 6894,0 6058 6036 commentText (CommentText … … 6102 6080 stg "VerticalLayoutStrategy" 6103 6081 textVec [ 6104 *18 8(Text6082 *187 (Text 6105 6083 uid 6891,0 6106 6084 va (VaSet … … 6112 6090 tm "HdlTextNameMgr" 6113 6091 ) 6114 *18 9(Text6092 *188 (Text 6115 6093 uid 6892,0 6116 6094 va (VaSet … … 6138 6116 viewiconposition 0 6139 6117 ) 6140 *1 90(HdlText6118 *189 (HdlText 6141 6119 uid 7092,0 6142 6120 optionalChildren [ 6143 *19 1(EmbeddedText6121 *190 (EmbeddedText 6144 6122 uid 7098,0 6145 6123 commentText (CommentText … … 6191 6169 stg "VerticalLayoutStrategy" 6192 6170 textVec [ 6193 *19 2(Text6171 *191 (Text 6194 6172 uid 7095,0 6195 6173 va (VaSet … … 6201 6179 tm "HdlTextNameMgr" 6202 6180 ) 6203 *19 3(Text6181 *192 (Text 6204 6182 uid 7096,0 6205 6183 va (VaSet … … 6227 6205 viewiconposition 0 6228 6206 ) 6229 *19 4(PortIoOut6207 *193 (PortIoOut 6230 6208 uid 7138,0 6231 6209 shape (CompositeShape … … 6271 6249 ) 6272 6250 ) 6273 *19 5(Net6251 *194 (Net 6274 6252 uid 7150,0 6275 6253 decl (Decl … … 6277 6255 t "std_logic_vector" 6278 6256 b "(7 DOWNTO 0)" 6279 o 1 56257 o 16 6280 6258 suid 155,0 6281 6259 i "(OTHERS => '0')" … … 6286 6264 font "Courier New,8,0" 6287 6265 ) 6288 xt "39000,1 5000,74500,15800"6266 xt "39000,17400,74500,18200" 6289 6267 st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 6290 6268 " 6291 6269 ) 6292 6270 ) 6293 *19 6(Net6271 *195 (Net 6294 6272 uid 7485,0 6295 6273 decl (Decl 6296 6274 n "dummy" 6297 6275 t "std_logic" 6298 o 586276 o 72 6299 6277 suid 157,0 6300 6278 ) … … 6304 6282 font "Courier New,8,0" 6305 6283 ) 6306 xt "39000,6 0000,57500,60800"6284 xt "39000,63200,57500,64000" 6307 6285 st "SIGNAL dummy : std_logic 6308 6286 " 6309 6287 ) 6310 6288 ) 6311 *19 7(MWC6289 *196 (MWC 6312 6290 uid 7652,0 6313 6291 optionalChildren [ 6314 *19 8(CptPort6292 *197 (CptPort 6315 6293 uid 7632,0 6316 6294 optionalChildren [ 6317 *19 9(Line6295 *198 (Line 6318 6296 uid 7636,0 6319 6297 layer 5 … … 6369 6347 n "s" 6370 6348 t "std_logic" 6371 o 586349 o 72 6372 6350 suid 1,0 6373 6351 ) 6374 6352 ) 6375 6353 ) 6376 * 200(CptPort6354 *199 (CptPort 6377 6355 uid 7637,0 6378 6356 optionalChildren [ 6379 *20 1(Line6357 *200 (Line 6380 6358 uid 7641,0 6381 6359 layer 5 … … 6434 6412 n "t" 6435 6413 t "std_logic" 6436 o 2 16414 o 22 6437 6415 suid 2,0 6438 6416 ) 6439 6417 ) 6440 6418 ) 6441 *20 2(CommentGraphic6419 *201 (CommentGraphic 6442 6420 uid 7642,0 6443 6421 shape (PolyLine2D … … 6460 6438 oxt "6000,6000,7000,7000" 6461 6439 ) 6462 *20 3(CommentGraphic6440 *202 (CommentGraphic 6463 6441 uid 7644,0 6464 6442 shape (PolyLine2D … … 6481 6459 oxt "6000,7000,7000,8000" 6482 6460 ) 6483 *20 4(CommentGraphic6461 *203 (CommentGraphic 6484 6462 uid 7646,0 6485 6463 shape (PolyLine2D … … 6502 6480 oxt "6988,7329,7988,7329" 6503 6481 ) 6504 *20 5(CommentGraphic6482 *204 (CommentGraphic 6505 6483 uid 7648,0 6506 6484 shape (PolyLine2D … … 6521 6499 oxt "8000,7000,9000,7000" 6522 6500 ) 6523 *20 6(CommentGraphic6501 *205 (CommentGraphic 6524 6502 uid 7650,0 6525 6503 shape (PolyLine2D … … 6562 6540 stg "VerticalLayoutStrategy" 6563 6541 textVec [ 6564 *20 7(Text6542 *206 (Text 6565 6543 uid 7655,0 6566 6544 va (VaSet … … 6572 6550 blo "90350,83900" 6573 6551 ) 6574 *20 8(Text6552 *207 (Text 6575 6553 uid 7656,0 6576 6554 va (VaSet … … 6581 6559 blo "90350,84900" 6582 6560 ) 6583 *20 9(Text6561 *208 (Text 6584 6562 uid 7657,0 6585 6563 va (VaSet … … 6626 6604 ) 6627 6605 ) 6628 *2 10(Net6606 *209 (Net 6629 6607 uid 8851,0 6630 6608 decl (Decl … … 6632 6610 t "std_logic_vector" 6633 6611 b "(3 downto 0)" 6634 o 576612 o 71 6635 6613 suid 159,0 6636 6614 i "(others => '0')" … … 6641 6619 font "Courier New,8,0" 6642 6620 ) 6643 xt "39000, 59200,78000,60000"6621 xt "39000,62400,78000,63200" 6644 6622 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6645 6623 " 6646 6624 ) 6647 6625 ) 6648 *21 1(Net6626 *210 (Net 6649 6627 uid 9500,0 6650 6628 decl (Decl 6651 6629 n "CLK_50" 6652 6630 t "std_logic" 6653 o 5 16631 o 57 6654 6632 suid 163,0 6655 6633 ) … … 6659 6637 font "Courier New,8,0" 6660 6638 ) 6661 xt "39000, 48000,57500,48800"6639 xt "39000,51200,57500,52000" 6662 6640 st "SIGNAL CLK_50 : std_logic 6663 6641 " 6664 6642 ) 6665 6643 ) 6666 *21 2(MWC6644 *211 (MWC 6667 6645 uid 10023,0 6668 6646 optionalChildren [ 6669 *21 3(CptPort6647 *212 (CptPort 6670 6648 uid 9995,0 6671 6649 optionalChildren [ 6672 *21 4(Line6650 *213 (Line 6673 6651 uid 9999,0 6674 6652 layer 5 … … 6683 6661 ] 6684 6662 ) 6685 *21 5(Property6663 *214 (Property 6686 6664 uid 10000,0 6687 6665 pclass "_MW_GEOM_" … … 6722 6700 n "dout" 6723 6701 t "std_logic" 6724 o 5 06702 o 55 6725 6703 suid 1,0 6726 6704 ) 6727 6705 ) 6728 6706 ) 6729 *21 6(CptPort6707 *215 (CptPort 6730 6708 uid 10001,0 6731 6709 optionalChildren [ 6732 *21 7(Line6710 *216 (Line 6733 6711 uid 10005,0 6734 6712 layer 5 … … 6776 6754 n "din0" 6777 6755 t "std_logic" 6778 o 596756 o 67 6779 6757 suid 2,0 6780 6758 i "'0'" … … 6782 6760 ) 6783 6761 ) 6784 *21 8(CptPort6762 *217 (CptPort 6785 6763 uid 10006,0 6786 6764 optionalChildren [ 6787 *21 9(Line6765 *218 (Line 6788 6766 uid 10010,0 6789 6767 layer 5 … … 6831 6809 n "din1" 6832 6810 t "std_logic" 6833 o 5 86811 o 56 6834 6812 suid 3,0 6835 6813 ) 6836 6814 ) 6837 6815 ) 6838 *2 20(CommentGraphic6816 *219 (CommentGraphic 6839 6817 uid 10011,0 6840 6818 optionalChildren [ 6841 *22 1(Property6819 *220 (Property 6842 6820 uid 10013,0 6843 6821 pclass "_MW_GEOM_" … … 6863 6841 oxt "11000,6000,11000,6000" 6864 6842 ) 6865 *22 2(CommentGraphic6843 *221 (CommentGraphic 6866 6844 uid 10014,0 6867 6845 optionalChildren [ 6868 *22 3(Property6846 *222 (Property 6869 6847 uid 10016,0 6870 6848 pclass "_MW_GEOM_" … … 6890 6868 oxt "11000,10000,11000,10000" 6891 6869 ) 6892 *22 4(Grouping6870 *223 (Grouping 6893 6871 uid 10017,0 6894 6872 optionalChildren [ 6895 *22 5(CommentGraphic6873 *224 (CommentGraphic 6896 6874 uid 10019,0 6897 6875 shape (PolyLine2D … … 6914 6892 oxt "9000,6000,11000,10000" 6915 6893 ) 6916 *22 6(CommentGraphic6894 *225 (CommentGraphic 6917 6895 uid 10021,0 6918 6896 shape (Arc2D … … 6967 6945 stg "VerticalLayoutStrategy" 6968 6946 textVec [ 6969 *22 7(Text6947 *226 (Text 6970 6948 uid 10026,0 6971 6949 va (VaSet … … 6977 6955 blo "44500,73300" 6978 6956 ) 6979 *22 8(Text6957 *227 (Text 6980 6958 uid 10027,0 6981 6959 va (VaSet … … 6986 6964 blo "44500,74300" 6987 6965 ) 6988 *22 9(Text6966 *228 (Text 6989 6967 uid 10028,0 6990 6968 va (VaSet … … 7031 7009 ) 7032 7010 ) 7033 *2 30(Net7011 *229 (Net 7034 7012 uid 10032,0 7035 7013 decl (Decl 7036 7014 n "CLK_25_PS1" 7037 7015 t "std_logic" 7038 o 5 87016 o 56 7039 7017 suid 164,0 7040 7018 ) … … 7044 7022 font "Courier New,8,0" 7045 7023 ) 7046 xt "39000, 47200,57500,48000"7024 xt "39000,50400,57500,51200" 7047 7025 st "SIGNAL CLK_25_PS1 : std_logic 7048 7026 " 7049 7027 ) 7050 7028 ) 7051 *23 1(Net7029 *230 (Net 7052 7030 uid 10050,0 7053 7031 decl (Decl 7054 7032 n "adc_clk_en" 7055 7033 t "std_logic" 7056 o 597034 o 67 7057 7035 suid 165,0 7058 7036 i "'0'" … … 7063 7041 font "Courier New,8,0" 7064 7042 ) 7065 xt "39000,5 6000,72000,56800"7043 xt "39000,59200,72000,60000" 7066 7044 st "SIGNAL adc_clk_en : std_logic := '0' 7067 7045 " 7068 7046 ) 7069 7047 ) 7070 *23 2(PortIoOut7048 *231 (PortIoOut 7071 7049 uid 10296,0 7072 7050 shape (CompositeShape … … 7112 7090 ) 7113 7091 ) 7114 *23 3(Net7092 *232 (Net 7115 7093 uid 10308,0 7116 7094 decl (Decl … … 7118 7096 t "std_logic_vector" 7119 7097 b "(7 DOWNTO 0)" 7120 o 607098 o 15 7121 7099 suid 166,0 7122 7100 i "(others => '0')" … … 7127 7105 font "Courier New,8,0" 7128 7106 ) 7129 xt "39000,1 4200,74500,15000"7107 xt "39000,16600,74500,17400" 7130 7108 st "A0_T : std_logic_vector(7 DOWNTO 0) := (others => '0') 7131 7109 " 7132 7110 ) 7133 7111 ) 7134 *23 4(HdlText7112 *233 (HdlText 7135 7113 uid 10310,0 7136 7114 optionalChildren [ 7137 *23 5(EmbeddedText7115 *234 (EmbeddedText 7138 7116 uid 10316,0 7139 7117 commentText (CommentText … … 7201 7179 stg "VerticalLayoutStrategy" 7202 7180 textVec [ 7203 *23 6(Text7181 *235 (Text 7204 7182 uid 10313,0 7205 7183 va (VaSet … … 7211 7189 tm "HdlTextNameMgr" 7212 7190 ) 7213 *23 7(Text7191 *236 (Text 7214 7192 uid 10314,0 7215 7193 va (VaSet … … 7237 7215 viewiconposition 0 7238 7216 ) 7239 *23 8(Net7217 *237 (Net 7240 7218 uid 10496,0 7241 7219 decl (Decl 7242 7220 n "CLK50_OUT" 7243 7221 t "std_logic" 7244 o 617222 o 54 7245 7223 suid 184,0 7246 7224 ) … … 7250 7228 font "Courier New,8,0" 7251 7229 ) 7252 xt "39000,4 5600,57500,46400"7230 xt "39000,48800,57500,49600" 7253 7231 st "SIGNAL CLK50_OUT : std_logic 7254 7232 " 7255 7233 ) 7256 7234 ) 7257 *23 9(Net7235 *238 (Net 7258 7236 uid 10504,0 7259 7237 decl (Decl 7260 7238 n "CLK25_OUT" 7261 7239 t "std_logic" 7262 o 627240 o 52 7263 7241 suid 185,0 7264 7242 ) … … 7268 7246 font "Courier New,8,0" 7269 7247 ) 7270 xt "39000,4 4000,57500,44800"7248 xt "39000,47200,57500,48000" 7271 7249 st "SIGNAL CLK25_OUT : std_logic 7272 7250 " 7273 7251 ) 7274 7252 ) 7275 *2 40(Net7253 *239 (Net 7276 7254 uid 10512,0 7277 7255 decl (Decl 7278 7256 n "CLK25_PSOUT" 7279 7257 t "std_logic" 7280 o 637258 o 53 7281 7259 suid 186,0 7282 7260 ) … … 7286 7264 font "Courier New,8,0" 7287 7265 ) 7288 xt "39000,4 4800,57500,45600"7266 xt "39000,48000,57500,48800" 7289 7267 st "SIGNAL CLK25_PSOUT : std_logic 7290 7268 " 7291 7269 ) 7292 7270 ) 7293 *24 1(Net7271 *240 (Net 7294 7272 uid 10520,0 7295 7273 decl (Decl … … 7304 7282 font "Courier New,8,0" 7305 7283 ) 7306 xt "39000,5 3600,57500,54400"7284 xt "39000,56800,57500,57600" 7307 7285 st "SIGNAL PS_DIR_IN : std_logic 7308 7286 " 7309 7287 ) 7310 7288 ) 7311 *24 2(Net7289 *241 (Net 7312 7290 uid 10528,0 7313 7291 decl (Decl … … 7322 7300 font "Courier New,8,0" 7323 7301 ) 7324 xt "39000,5 4400,57500,55200"7302 xt "39000,57600,57500,58400" 7325 7303 st "SIGNAL PS_DO_IN : std_logic 7326 7304 " 7327 7305 ) 7328 7306 ) 7329 *24 3(Net7307 *242 (Net 7330 7308 uid 10536,0 7331 7309 decl (Decl 7332 7310 n "PSEN_OUT" 7333 7311 t "std_logic" 7334 o 6 67312 o 62 7335 7313 suid 189,0 7336 7314 ) … … 7340 7318 font "Courier New,8,0" 7341 7319 ) 7342 xt "39000,5 2000,57500,52800"7320 xt "39000,55200,57500,56000" 7343 7321 st "SIGNAL PSEN_OUT : std_logic 7344 7322 " 7345 7323 ) 7346 7324 ) 7347 *24 4(Net7325 *243 (Net 7348 7326 uid 10544,0 7349 7327 decl (Decl 7350 7328 n "PSINCDEC_OUT" 7351 7329 t "std_logic" 7352 o 6 77330 o 63 7353 7331 suid 190,0 7354 7332 ) … … 7358 7336 font "Courier New,8,0" 7359 7337 ) 7360 xt "39000,5 2800,57500,53600"7338 xt "39000,56000,57500,56800" 7361 7339 st "SIGNAL PSINCDEC_OUT : std_logic 7362 7340 " 7363 7341 ) 7364 7342 ) 7365 *24 5(Net7343 *244 (Net 7366 7344 uid 10552,0 7367 7345 decl (Decl … … 7370 7348 preAdd 0 7371 7349 posAdd 0 7372 o 687350 o 58 7373 7351 suid 191,0 7374 7352 ) … … 7378 7356 font "Courier New,8,0" 7379 7357 ) 7380 xt "39000, 48800,57500,49600"7358 xt "39000,52000,57500,52800" 7381 7359 st "SIGNAL DCM_locked : std_logic 7382 7360 " 7383 7361 ) 7384 7362 ) 7385 *24 6(Net7363 *245 (Net 7386 7364 uid 10560,0 7387 7365 decl (Decl … … 7390 7368 preAdd 0 7391 7369 posAdd 0 7392 o 697370 o 73 7393 7371 suid 192,0 7394 7372 i "'0'" … … 7399 7377 font "Courier New,8,0" 7400 7378 ) 7401 xt "39000,6 0800,72000,61600"7379 xt "39000,64000,72000,64800" 7402 7380 st "SIGNAL ready : std_logic := '0' 7403 7381 " 7404 7382 ) 7405 7383 ) 7406 *24 7(Net7384 *246 (Net 7407 7385 uid 10568,0 7408 7386 decl (Decl … … 7412 7390 preAdd 0 7413 7391 posAdd 0 7414 o 7 07392 o 75 7415 7393 suid 193,0 7416 7394 i "'0'" … … 7421 7399 font "Courier New,8,0" 7422 7400 ) 7423 xt "39000,6 2400,72000,64000"7401 xt "39000,65600,72000,67200" 7424 7402 st "-- status: 7425 7403 SIGNAL shifting : std_logic := '0' … … 7427 7405 ) 7428 7406 ) 7429 *24 8(Net7407 *247 (Net 7430 7408 uid 10576,0 7431 7409 decl (Decl 7432 7410 n "PSDONE_extraOUT" 7433 7411 t "std_logic" 7434 o 717412 o 61 7435 7413 suid 194,0 7436 7414 ) … … 7440 7418 font "Courier New,8,0" 7441 7419 ) 7442 xt "39000,5 1200,57500,52000"7420 xt "39000,54400,57500,55200" 7443 7421 st "SIGNAL PSDONE_extraOUT : std_logic 7444 7422 " 7445 7423 ) 7446 7424 ) 7447 *24 9(Net7425 *248 (Net 7448 7426 uid 10584,0 7449 7427 decl (Decl 7450 7428 n "PSCLK_OUT" 7451 7429 t "std_logic" 7452 o 727430 o 60 7453 7431 suid 195,0 7454 7432 ) … … 7458 7436 font "Courier New,8,0" 7459 7437 ) 7460 xt "39000,5 0400,57500,51200"7438 xt "39000,53600,57500,54400" 7461 7439 st "SIGNAL PSCLK_OUT : std_logic 7462 7440 " 7463 7441 ) 7464 7442 ) 7465 *2 50(Net7443 *249 (Net 7466 7444 uid 10592,0 7467 7445 decl (Decl 7468 7446 n "LOCKED_extraOUT" 7469 7447 t "std_logic" 7470 o 737448 o 59 7471 7449 suid 196,0 7472 7450 ) … … 7476 7454 font "Courier New,8,0" 7477 7455 ) 7478 xt "39000, 49600,57500,50400"7456 xt "39000,52800,57500,53600" 7479 7457 st "SIGNAL LOCKED_extraOUT : std_logic 7480 7458 " 7481 7459 ) 7482 7460 ) 7483 *251 (Wire 7461 *250 (PortIoIn 7462 uid 11090,0 7463 shape (CompositeShape 7464 uid 11091,0 7465 va (VaSet 7466 vasetType 1 7467 fg "0,0,32768" 7468 ) 7469 optionalChildren [ 7470 (Pentagon 7471 uid 11092,0 7472 sl 0 7473 ro 270 7474 xt "94000,102625,95500,103375" 7475 ) 7476 (Line 7477 uid 11093,0 7478 sl 0 7479 ro 270 7480 xt "95500,103000,96000,103000" 7481 pts [ 7482 "95500,103000" 7483 "96000,103000" 7484 ] 7485 ) 7486 ] 7487 ) 7488 stc 0 7489 sf 1 7490 tg (WTG 7491 uid 11094,0 7492 ps "PortIoTextPlaceStrategy" 7493 stg "STSignalDisplayStrategy" 7494 f (Text 7495 uid 11095,0 7496 va (VaSet 7497 ) 7498 xt "87700,102500,93000,103500" 7499 st "RS485_C_DI" 7500 ju 2 7501 blo "93000,103300" 7502 tm "WireNameMgr" 7503 ) 7504 ) 7505 ) 7506 *251 (Net 7507 uid 11102,0 7508 decl (Decl 7509 n "RS485_C_DI" 7510 t "std_logic" 7511 o 74 7512 suid 197,0 7513 ) 7514 declText (MLText 7515 uid 11103,0 7516 va (VaSet 7517 font "Courier New,8,0" 7518 ) 7519 xt "39000,11800,54000,12600" 7520 st "RS485_C_DI : std_logic 7521 " 7522 ) 7523 ) 7524 *252 (PortIoOut 7525 uid 11104,0 7526 shape (CompositeShape 7527 uid 11105,0 7528 va (VaSet 7529 vasetType 1 7530 fg "0,0,32768" 7531 ) 7532 optionalChildren [ 7533 (Pentagon 7534 uid 11106,0 7535 sl 0 7536 ro 270 7537 xt "111500,111625,113000,112375" 7538 ) 7539 (Line 7540 uid 11107,0 7541 sl 0 7542 ro 270 7543 xt "111000,112000,111500,112000" 7544 pts [ 7545 "111000,112000" 7546 "111500,112000" 7547 ] 7548 ) 7549 ] 7550 ) 7551 stc 0 7552 sf 1 7553 tg (WTG 7554 uid 11108,0 7555 ps "PortIoTextPlaceStrategy" 7556 stg "STSignalDisplayStrategy" 7557 f (Text 7558 uid 11109,0 7559 va (VaSet 7560 ) 7561 xt "114000,111500,119700,112500" 7562 st "RS485_C_DO" 7563 blo "114000,112300" 7564 tm "WireNameMgr" 7565 ) 7566 ) 7567 ) 7568 *253 (Net 7569 uid 11116,0 7570 decl (Decl 7571 n "RS485_C_DO" 7572 t "std_logic" 7573 o 75 7574 suid 198,0 7575 ) 7576 declText (MLText 7577 uid 11117,0 7578 va (VaSet 7579 font "Courier New,8,0" 7580 ) 7581 xt "39000,31000,54000,31800" 7582 st "RS485_C_DO : std_logic 7583 " 7584 ) 7585 ) 7586 *254 (PortIoIn 7587 uid 11508,0 7588 shape (CompositeShape 7589 uid 11509,0 7590 va (VaSet 7591 vasetType 1 7592 fg "0,0,32768" 7593 ) 7594 optionalChildren [ 7595 (Pentagon 7596 uid 11510,0 7597 sl 0 7598 ro 270 7599 xt "121000,115625,122500,116375" 7600 ) 7601 (Line 7602 uid 11511,0 7603 sl 0 7604 ro 270 7605 xt "122500,116000,123000,116000" 7606 pts [ 7607 "122500,116000" 7608 "123000,116000" 7609 ] 7610 ) 7611 ] 7612 ) 7613 stc 0 7614 sf 1 7615 tg (WTG 7616 uid 11512,0 7617 ps "PortIoTextPlaceStrategy" 7618 stg "STSignalDisplayStrategy" 7619 f (Text 7620 uid 11513,0 7621 va (VaSet 7622 ) 7623 xt "114800,115500,120000,116500" 7624 st "RS485_E_DI" 7625 ju 2 7626 blo "120000,116300" 7627 tm "WireNameMgr" 7628 ) 7629 ) 7630 ) 7631 *255 (Net 7632 uid 11520,0 7633 decl (Decl 7634 n "RS485_E_DI" 7635 t "std_logic" 7636 o 76 7637 suid 200,0 7638 ) 7639 declText (MLText 7640 uid 11521,0 7641 va (VaSet 7642 font "Courier New,8,0" 7643 ) 7644 xt "39000,12600,54000,13400" 7645 st "RS485_E_DI : std_logic 7646 " 7647 ) 7648 ) 7649 *256 (Net 7650 uid 11534,0 7651 decl (Decl 7652 n "RS485_E_DO" 7653 t "std_logic" 7654 o 77 7655 suid 201,0 7656 ) 7657 declText (MLText 7658 uid 11535,0 7659 va (VaSet 7660 font "Courier New,8,0" 7661 ) 7662 xt "39000,13400,54000,14200" 7663 st "RS485_E_DO : std_logic 7664 " 7665 ) 7666 ) 7667 *257 (PortIoIn 7668 uid 11922,0 7669 shape (CompositeShape 7670 uid 11923,0 7671 va (VaSet 7672 vasetType 1 7673 fg "0,0,32768" 7674 ) 7675 optionalChildren [ 7676 (Pentagon 7677 uid 11924,0 7678 sl 0 7679 ro 90 7680 xt "126500,113625,128000,114375" 7681 ) 7682 (Line 7683 uid 11925,0 7684 sl 0 7685 ro 90 7686 xt "126000,114000,126500,114000" 7687 pts [ 7688 "126500,114000" 7689 "126000,114000" 7690 ] 7691 ) 7692 ] 7693 ) 7694 stc 0 7695 sf 1 7696 tg (WTG 7697 uid 11926,0 7698 ps "PortIoTextPlaceStrategy" 7699 stg "STSignalDisplayStrategy" 7700 f (Text 7701 uid 11927,0 7702 va (VaSet 7703 ) 7704 xt "129000,113500,134600,114500" 7705 st "RS485_E_DO" 7706 blo "129000,114300" 7707 tm "WireNameMgr" 7708 ) 7709 ) 7710 ) 7711 *258 (PortIoOut 7712 uid 12326,0 7713 shape (CompositeShape 7714 uid 12327,0 7715 va (VaSet 7716 vasetType 1 7717 fg "0,0,32768" 7718 ) 7719 optionalChildren [ 7720 (Pentagon 7721 uid 12328,0 7722 sl 0 7723 ro 270 7724 xt "87500,139625,89000,140375" 7725 ) 7726 (Line 7727 uid 12329,0 7728 sl 0 7729 ro 270 7730 xt "87000,140000,87500,140000" 7731 pts [ 7732 "87000,140000" 7733 "87500,140000" 7734 ] 7735 ) 7736 ] 7737 ) 7738 stc 0 7739 sf 1 7740 tg (WTG 7741 uid 12330,0 7742 ps "PortIoTextPlaceStrategy" 7743 stg "STSignalDisplayStrategy" 7744 f (Text 7745 uid 12331,0 7746 va (VaSet 7747 ) 7748 xt "90000,139500,92300,140500" 7749 st "SRIN" 7750 blo "90000,140300" 7751 tm "WireNameMgr" 7752 ) 7753 ) 7754 ) 7755 *259 (Net 7756 uid 12334,0 7757 decl (Decl 7758 n "SRIN" 7759 t "std_logic" 7760 o 78 7761 suid 203,0 7762 i "'0'" 7763 ) 7764 declText (MLText 7765 uid 12335,0 7766 va (VaSet 7767 font "Courier New,8,0" 7768 ) 7769 xt "39000,35000,68500,35800" 7770 st "SRIN : std_logic := '0' 7771 " 7772 ) 7773 ) 7774 *260 (Wire 7484 7775 uid 245,0 7485 7776 shape (OrthoPolyLine … … 7495 7786 ) 7496 7787 start &27 7497 end &6 37788 end &64 7498 7789 ss 0 7499 7790 sat 32 … … 7518 7809 ) 7519 7810 ) 7520 on &8 47521 ) 7522 *2 52(Wire7811 on &85 7812 ) 7813 *261 (Wire 7523 7814 uid 277,0 7524 7815 shape (OrthoPolyLine … … 7535 7826 ) 7536 7827 start &17 7537 end &6 47828 end &65 7538 7829 sat 32 7539 7830 eat 2 … … 7556 7847 ) 7557 7848 ) 7558 on &6 87559 ) 7560 *2 53(Wire7849 on &69 7850 ) 7851 *262 (Wire 7561 7852 uid 285,0 7562 7853 shape (OrthoPolyLine … … 7573 7864 ) 7574 7865 start &18 7575 end &6 47866 end &65 7576 7867 sat 32 7577 7868 eat 2 … … 7594 7885 ) 7595 7886 ) 7596 on & 697597 ) 7598 *2 54(Wire7887 on &70 7888 ) 7889 *263 (Wire 7599 7890 uid 362,0 7600 7891 shape (OrthoPolyLine … … 7609 7900 ] 7610 7901 ) 7611 start &9 27902 start &93 7612 7903 end &16 7613 7904 sat 32 … … 7632 7923 ) 7633 7924 ) 7634 on &9 37635 ) 7636 *2 55(Wire7925 on &94 7926 ) 7927 *264 (Wire 7637 7928 uid 418,0 7638 7929 shape (OrthoPolyLine … … 7648 7939 ) 7649 7940 start &13 7650 end &7 07941 end &71 7651 7942 sat 32 7652 7943 eat 32 … … 7670 7961 ) 7671 7962 ) 7672 on &14 57673 ) 7674 *2 56(Wire7963 on &146 7964 ) 7965 *265 (Wire 7675 7966 uid 426,0 7676 7967 shape (OrthoPolyLine … … 7687 7978 ) 7688 7979 start &19 7689 end &7 17980 end &72 7690 7981 sat 32 7691 7982 eat 32 … … 7710 8001 ) 7711 8002 ) 7712 on &14 37713 ) 7714 *2 57(Wire8003 on &144 8004 ) 8005 *266 (Wire 7715 8006 uid 434,0 7716 8007 shape (OrthoPolyLine … … 7726 8017 ) 7727 8018 start &20 7728 end &7 28019 end &73 7729 8020 sat 32 7730 8021 eat 32 … … 7748 8039 ) 7749 8040 ) 7750 on &1 497751 ) 7752 *2 58(Wire8041 on &150 8042 ) 8043 *267 (Wire 7753 8044 uid 442,0 7754 8045 shape (OrthoPolyLine … … 7765 8056 ) 7766 8057 start &21 7767 end &7 38058 end &74 7768 8059 sat 32 7769 8060 eat 32 … … 7788 8079 ) 7789 8080 ) 7790 on &14 47791 ) 7792 *2 59(Wire8081 on &145 8082 ) 8083 *268 (Wire 7793 8084 uid 450,0 7794 8085 shape (OrthoPolyLine … … 7803 8094 ] 7804 8095 ) 7805 start &7 48096 start &75 7806 8097 end &22 7807 8098 sat 32 … … 7826 8117 ) 7827 8118 ) 7828 on &14 87829 ) 7830 *26 0(Wire8119 on &149 8120 ) 8121 *269 (Wire 7831 8122 uid 458,0 7832 8123 shape (OrthoPolyLine … … 7842 8133 ) 7843 8134 start &23 7844 end &757845 sat 327846 eat 327847 stc 07848 st 07849 sf 17850 si 07851 tg (WTG7852 uid 462,07853 ps "ConnStartEndStrategy"7854 stg "STSignalDisplayStrategy"7855 f (Text7856 uid 463,07857 va (VaSet7858 isHidden 17859 )7860 xt "82000,71000,84700,72000"7861 st "W_RD"7862 blo "82000,71800"7863 tm "WireNameMgr"7864 )7865 )7866 on &1467867 )7868 *261 (Wire7869 uid 466,07870 shape (OrthoPolyLine7871 uid 467,07872 va (VaSet7873 vasetType 37874 )7875 xt "80750,73000,111000,73000"7876 pts [7877 "80750,73000"7878 "111000,73000"7879 ]7880 )7881 start &247882 8135 end &76 7883 8136 sat 32 … … 7888 8141 si 0 7889 8142 tg (WTG 8143 uid 462,0 8144 ps "ConnStartEndStrategy" 8145 stg "STSignalDisplayStrategy" 8146 f (Text 8147 uid 463,0 8148 va (VaSet 8149 isHidden 1 8150 ) 8151 xt "82000,71000,84700,72000" 8152 st "W_RD" 8153 blo "82000,71800" 8154 tm "WireNameMgr" 8155 ) 8156 ) 8157 on &147 8158 ) 8159 *270 (Wire 8160 uid 466,0 8161 shape (OrthoPolyLine 8162 uid 467,0 8163 va (VaSet 8164 vasetType 3 8165 ) 8166 xt "80750,73000,111000,73000" 8167 pts [ 8168 "80750,73000" 8169 "111000,73000" 8170 ] 8171 ) 8172 start &24 8173 end &77 8174 sat 32 8175 eat 32 8176 stc 0 8177 st 0 8178 sf 1 8179 si 0 8180 tg (WTG 7890 8181 uid 470,0 7891 8182 ps "ConnStartEndStrategy" … … 7902 8193 ) 7903 8194 ) 7904 on &14 77905 ) 7906 *2 62(Wire8195 on &148 8196 ) 8197 *271 (Wire 7907 8198 uid 1467,0 7908 8199 shape (OrthoPolyLine … … 7917 8208 ] 7918 8209 ) 7919 start &9 68210 start &97 7920 8211 end &28 7921 8212 sat 2 … … 7938 8229 ) 7939 8230 ) 7940 on &7 77941 ) 7942 *2 63(Wire8231 on &78 8232 ) 8233 *272 (Wire 7943 8234 uid 1730,0 7944 8235 shape (OrthoPolyLine … … 7954 8245 ] 7955 8246 ) 7956 start &9 48247 start &95 7957 8248 end &29 7958 8249 sat 32 … … 7978 8269 ) 7979 8270 ) 7980 on &9 57981 ) 7982 *2 64(Wire8271 on &96 8272 ) 8273 *273 (Wire 7983 8274 uid 1833,0 7984 8275 shape (OrthoPolyLine … … 7994 8285 ] 7995 8286 ) 7996 start &1 907997 end &12 48287 start &189 8288 end &125 7998 8289 sat 2 7999 8290 eat 32 … … 8018 8309 ) 8019 8310 ) 8020 on &12 58021 ) 8022 *2 65(Wire8311 on &126 8312 ) 8313 *274 (Wire 8023 8314 uid 1841,0 8024 8315 shape (OrthoPolyLine … … 8034 8325 ) 8035 8326 start &31 8036 end &12 68327 end &127 8037 8328 sat 32 8038 8329 eat 32 … … 8056 8347 ) 8057 8348 ) 8058 on &12 78059 ) 8060 *2 66(Wire8349 on &128 8350 ) 8351 *275 (Wire 8061 8352 uid 1865,0 8062 8353 shape (OrthoPolyLine … … 8071 8362 ] 8072 8363 ) 8073 start &11 68364 start &117 8074 8365 end &32 8075 8366 sat 32 … … 8094 8385 ) 8095 8386 ) 8096 on &12 08097 ) 8098 *2 67(Wire8387 on &121 8388 ) 8389 *276 (Wire 8099 8390 uid 1873,0 8100 8391 shape (OrthoPolyLine … … 8109 8400 ] 8110 8401 ) 8111 start &11 78402 start &118 8112 8403 end &33 8113 8404 sat 32 … … 8132 8423 ) 8133 8424 ) 8134 on &12 18135 ) 8136 *2 68(Wire8425 on &122 8426 ) 8427 *277 (Wire 8137 8428 uid 1881,0 8138 8429 shape (OrthoPolyLine … … 8147 8438 ] 8148 8439 ) 8149 start &11 88440 start &119 8150 8441 end &34 8151 8442 sat 32 … … 8170 8461 ) 8171 8462 ) 8172 on &12 28173 ) 8174 *2 69(Wire8463 on &123 8464 ) 8465 *278 (Wire 8175 8466 uid 1889,0 8176 8467 shape (OrthoPolyLine … … 8185 8476 ] 8186 8477 ) 8187 start &1 198478 start &120 8188 8479 end &35 8189 8480 sat 32 … … 8208 8499 ) 8209 8500 ) 8210 on &12 38211 ) 8212 *27 0(Wire8501 on &124 8502 ) 8503 *279 (Wire 8213 8504 uid 2409,0 8214 8505 shape (OrthoPolyLine … … 8224 8515 ) 8225 8516 start &36 8226 end & 798517 end &80 8227 8518 sat 32 8228 8519 eat 32 … … 8246 8537 ) 8247 8538 ) 8248 on &7 88249 ) 8250 *2 71(Wire8539 on &79 8540 ) 8541 *280 (Wire 8251 8542 uid 2423,0 8252 8543 shape (OrthoPolyLine … … 8262 8553 ) 8263 8554 start &37 8264 end &10 88555 end &109 8265 8556 sat 32 8266 8557 eat 1 … … 8284 8575 ) 8285 8576 ) 8286 on &8 08287 ) 8288 *2 72(Wire8577 on &81 8578 ) 8579 *281 (Wire 8289 8580 uid 3009,0 8290 8581 shape (OrthoPolyLine … … 8300 8591 ) 8301 8592 start &39 8302 end &14 18593 end &142 8303 8594 sat 32 8304 8595 eat 32 … … 8322 8613 ) 8323 8614 ) 8324 on &14 28325 ) 8326 *2 73(Wire8615 on &143 8616 ) 8617 *282 (Wire 8327 8618 uid 3015,0 8328 8619 shape (OrthoPolyLine … … 8338 8629 ) 8339 8630 start &41 8340 end &15 08631 end &151 8341 8632 sat 32 8342 8633 eat 32 … … 8360 8651 ) 8361 8652 ) 8362 on &15 38363 ) 8364 *2 74(Wire8653 on &154 8654 ) 8655 *283 (Wire 8365 8656 uid 3021,0 8366 8657 shape (OrthoPolyLine … … 8377 8668 ) 8378 8669 start &40 8379 end &1 298670 end &130 8380 8671 sat 32 8381 8672 eat 1 … … 8398 8689 ) 8399 8690 ) 8400 on &8 18401 ) 8402 *2 75(Wire8691 on &82 8692 ) 8693 *284 (Wire 8403 8694 uid 3027,0 8404 8695 shape (OrthoPolyLine … … 8413 8704 ] 8414 8705 ) 8415 start & 2008416 end &12 88706 start &199 8707 end &129 8417 8708 ss 0 8418 8709 sat 32 … … 8437 8728 ) 8438 8729 ) 8439 on &8 28440 ) 8441 *2 76(Wire8730 on &83 8731 ) 8732 *285 (Wire 8442 8733 uid 3218,0 8443 8734 shape (OrthoPolyLine … … 8452 8743 ] 8453 8744 ) 8454 start &6 28745 start &63 8455 8746 end &15 8456 8747 sat 32 … … 8475 8766 ) 8476 8767 ) 8477 on &8 58478 ) 8479 *2 77(Wire8768 on &86 8769 ) 8770 *286 (Wire 8480 8771 uid 3260,0 8481 8772 shape (OrthoPolyLine … … 8491 8782 ] 8492 8783 ) 8493 start &8 38494 end &8 68784 start &84 8785 end &87 8495 8786 sat 32 8496 8787 eat 2 … … 8515 8806 ) 8516 8807 ) 8517 on &9 08518 ) 8519 *2 78(Wire8808 on &91 8809 ) 8810 *287 (Wire 8520 8811 uid 3270,0 8521 8812 shape (OrthoPolyLine … … 8532 8823 ] 8533 8824 ) 8534 start &21 38535 end &8 68825 start &212 8826 end &87 8536 8827 sat 32 8537 8828 eat 1 … … 8553 8844 ) 8554 8845 ) 8555 on &9 18556 ) 8557 *2 79(Wire8846 on &92 8847 ) 8848 *288 (Wire 8558 8849 uid 3318,0 8559 8850 shape (OrthoPolyLine … … 8569 8860 ] 8570 8861 ) 8571 start &10 08572 end &9 68862 start &101 8863 end &97 8573 8864 sat 32 8574 8865 eat 1 … … 8593 8884 ) 8594 8885 ) 8595 on &10 48596 ) 8597 *28 0(Wire8886 on &105 8887 ) 8888 *289 (Wire 8598 8889 uid 3352,0 8599 8890 shape (OrthoPolyLine … … 8609 8900 ] 8610 8901 ) 8611 start &10 18612 end &9 68902 start &102 8903 end &97 8613 8904 sat 32 8614 8905 eat 1 … … 8633 8924 ) 8634 8925 ) 8635 on &10 58636 ) 8637 *2 81(Wire8926 on &106 8927 ) 8928 *290 (Wire 8638 8929 uid 3360,0 8639 8930 shape (OrthoPolyLine … … 8649 8940 ] 8650 8941 ) 8651 start &10 28652 end &9 68942 start &103 8943 end &97 8653 8944 sat 32 8654 8945 eat 1 … … 8673 8964 ) 8674 8965 ) 8675 on &10 68676 ) 8677 *2 82(Wire8966 on &107 8967 ) 8968 *291 (Wire 8678 8969 uid 3368,0 8679 8970 shape (OrthoPolyLine … … 8689 8980 ] 8690 8981 ) 8691 start &10 38692 end &9 68982 start &104 8983 end &97 8693 8984 sat 32 8694 8985 eat 1 … … 8713 9004 ) 8714 9005 ) 8715 on &10 78716 ) 8717 *2 83(Wire9006 on &108 9007 ) 9008 *292 (Wire 8718 9009 uid 3430,0 8719 9010 shape (OrthoPolyLine … … 8728 9019 ] 8729 9020 ) 8730 start &17 68731 end &10 89021 start &175 9022 end &109 8732 9023 sat 32 8733 9024 eat 2 … … 8751 9042 ) 8752 9043 ) 8753 on &11 28754 ) 8755 *2 84(Wire9044 on &113 9045 ) 9046 *293 (Wire 8756 9047 uid 3438,0 8757 9048 shape (OrthoPolyLine … … 8766 9057 ] 8767 9058 ) 8768 start &17 78769 end &10 89059 start &176 9060 end &109 8770 9061 sat 32 8771 9062 eat 2 … … 8789 9080 ) 8790 9081 ) 8791 on &11 38792 ) 8793 *2 85(Wire9082 on &114 9083 ) 9084 *294 (Wire 8794 9085 uid 3446,0 8795 9086 shape (OrthoPolyLine … … 8804 9095 ] 8805 9096 ) 8806 start &17 88807 end &10 89097 start &177 9098 end &109 8808 9099 sat 32 8809 9100 eat 2 … … 8827 9118 ) 8828 9119 ) 8829 on &11 48830 ) 8831 *2 86(Wire9120 on &115 9121 ) 9122 *295 (Wire 8832 9123 uid 3454,0 8833 9124 shape (OrthoPolyLine … … 8842 9133 ] 8843 9134 ) 8844 start &17 98845 end &10 89135 start &178 9136 end &109 8846 9137 sat 32 8847 9138 eat 2 … … 8865 9156 ) 8866 9157 ) 8867 on &11 58868 ) 8869 *2 87(Wire9158 on &116 9159 ) 9160 *296 (Wire 8870 9161 uid 3574,0 8871 9162 shape (OrthoPolyLine … … 8880 9171 ] 8881 9172 ) 8882 start &13 38883 end &1 299173 start &134 9174 end &130 8884 9175 sat 32 8885 9176 eat 2 … … 8903 9194 ) 8904 9195 ) 8905 on &13 78906 ) 8907 *2 88(Wire9196 on &138 9197 ) 9198 *297 (Wire 8908 9199 uid 3582,0 8909 9200 shape (OrthoPolyLine … … 8918 9209 ] 8919 9210 ) 8920 start &13 48921 end &1 299211 start &135 9212 end &130 8922 9213 sat 32 8923 9214 eat 2 … … 8941 9232 ) 8942 9233 ) 8943 on &13 88944 ) 8945 *2 89(Wire9234 on &139 9235 ) 9236 *298 (Wire 8946 9237 uid 3590,0 8947 9238 shape (OrthoPolyLine … … 8956 9247 ] 8957 9248 ) 8958 start &13 58959 end &1 299249 start &136 9250 end &130 8960 9251 sat 32 8961 9252 eat 2 … … 8979 9270 ) 8980 9271 ) 8981 on &1 398982 ) 8983 *29 0(Wire9272 on &140 9273 ) 9274 *299 (Wire 8984 9275 uid 3598,0 8985 9276 shape (OrthoPolyLine … … 8994 9285 ] 8995 9286 ) 8996 start &13 68997 end &1 299287 start &137 9288 end &130 8998 9289 sat 32 8999 9290 eat 2 … … 9017 9308 ) 9018 9309 ) 9019 on &14 09020 ) 9021 * 291(Wire9310 on &141 9311 ) 9312 *300 (Wire 9022 9313 uid 3682,0 9023 9314 shape (OrthoPolyLine … … 9033 9324 ) 9034 9325 start &42 9035 end &15 29326 end &153 9036 9327 sat 32 9037 9328 eat 32 … … 9055 9346 ) 9056 9347 ) 9057 on &15 19058 ) 9059 * 292(Wire9348 on &152 9349 ) 9350 *301 (Wire 9060 9351 uid 3778,0 9061 9352 shape (OrthoPolyLine … … 9070 9361 ] 9071 9362 ) 9072 start &15 89073 end &15 49363 start &159 9364 end &155 9074 9365 sat 32 9075 9366 eat 2 … … 9095 9386 on &167 9096 9387 ) 9097 * 293(Wire9388 *302 (Wire 9098 9389 uid 3786,0 9099 9390 shape (OrthoPolyLine … … 9108 9399 ] 9109 9400 ) 9110 start &1 599111 end &15 49401 start &160 9402 end &155 9112 9403 sat 32 9113 9404 eat 2 … … 9133 9424 on &168 9134 9425 ) 9135 * 294(Wire9426 *303 (Wire 9136 9427 uid 3794,0 9137 9428 shape (OrthoPolyLine … … 9146 9437 ] 9147 9438 ) 9148 start &16 09149 end &15 49439 start &161 9440 end &155 9150 9441 sat 32 9151 9442 eat 2 … … 9171 9462 on &169 9172 9463 ) 9173 * 295(Wire9464 *304 (Wire 9174 9465 uid 3802,0 9175 9466 shape (OrthoPolyLine … … 9184 9475 ] 9185 9476 ) 9186 start &16 19187 end &15 49477 start &162 9478 end &155 9188 9479 sat 32 9189 9480 eat 2 … … 9209 9500 on &170 9210 9501 ) 9211 * 296(Wire9502 *305 (Wire 9212 9503 uid 3810,0 9213 9504 shape (OrthoPolyLine … … 9222 9513 ] 9223 9514 ) 9224 start &16 29225 end &15 49515 start &163 9516 end &155 9226 9517 sat 32 9227 9518 eat 2 … … 9247 9538 on &171 9248 9539 ) 9249 * 297(Wire9250 uid 38 26,09540 *306 (Wire 9541 uid 3834,0 9251 9542 shape (OrthoPolyLine 9252 uid 38 27,09543 uid 3835,0 9253 9544 va (VaSet 9254 9545 vasetType 3 9255 9546 ) 9256 xt "108000,1 09000,111000,109000"9257 pts [ 9258 "111000,1 09000"9259 "108000,1 09000"9260 ] 9261 ) 9262 start &16 49263 end &15 49547 xt "108000,110000,111000,110000" 9548 pts [ 9549 "111000,110000" 9550 "108000,110000" 9551 ] 9552 ) 9553 start &165 9554 end &155 9264 9555 sat 32 9265 9556 eat 2 … … 9269 9560 si 0 9270 9561 tg (WTG 9271 uid 3830,09272 ps "ConnStartEndStrategy"9273 stg "STSignalDisplayStrategy"9274 f (Text9275 uid 3831,09276 va (VaSet9277 isHidden 19278 )9279 xt "108000,108000,110300,109000"9280 st "SRIN"9281 blo "108000,108800"9282 tm "WireNameMgr"9283 )9284 )9285 on &1739286 )9287 *298 (Wire9288 uid 3834,09289 shape (OrthoPolyLine9290 uid 3835,09291 va (VaSet9292 vasetType 39293 )9294 xt "108000,110000,111000,110000"9295 pts [9296 "111000,110000"9297 "108000,110000"9298 ]9299 )9300 start &1659301 end &1549302 sat 329303 eat 29304 stc 09305 st 09306 sf 19307 si 09308 tg (WTG9309 9562 uid 3838,0 9310 9563 ps "ConnStartEndStrategy" … … 9321 9574 ) 9322 9575 ) 9323 on &17 49324 ) 9325 * 299(Wire9576 on &173 9577 ) 9578 *307 (Wire 9326 9579 uid 3842,0 9327 9580 shape (OrthoPolyLine … … 9338 9591 ) 9339 9592 start &166 9340 end &15 49593 end &155 9341 9594 sat 32 9342 9595 eat 2 … … 9361 9614 ) 9362 9615 ) 9363 on &17 59364 ) 9365 *30 0(Wire9616 on &174 9617 ) 9618 *308 (Wire 9366 9619 uid 4942,0 9367 9620 shape (OrthoPolyLine … … 9378 9631 ) 9379 9632 start &14 9380 end &1 809633 end &179 9381 9634 sat 32 9382 9635 eat 32 … … 9401 9654 ) 9402 9655 ) 9403 on &18 19404 ) 9405 *30 1(Wire9656 on &180 9657 ) 9658 *309 (Wire 9406 9659 uid 6431,0 9407 9660 shape (OrthoPolyLine … … 9417 9670 ) 9418 9671 start &43 9419 end &16 39672 end &164 9420 9673 sat 32 9421 9674 eat 32 … … 9441 9694 on &172 9442 9695 ) 9443 *3 02(Wire9696 *310 (Wire 9444 9697 uid 6787,0 9445 9698 shape (OrthoPolyLine … … 9455 9708 ] 9456 9709 ) 9457 start &18 29458 end &18 69710 start &181 9711 end &185 9459 9712 sat 32 9460 9713 eat 1 … … 9478 9731 ) 9479 9732 ) 9480 on &18 39481 ) 9482 *3 03(Wire9733 on &182 9734 ) 9735 *311 (Wire 9483 9736 uid 6880,0 9484 9737 shape (OrthoPolyLine … … 9494 9747 ] 9495 9748 ) 9496 start &18 69497 end &18 49749 start &185 9750 end &183 9498 9751 sat 2 9499 9752 eat 32 … … 9517 9770 ) 9518 9771 ) 9519 on &18 59520 ) 9521 *3 04(Wire9772 on &184 9773 ) 9774 *312 (Wire 9522 9775 uid 7144,0 9523 9776 shape (OrthoPolyLine … … 9533 9786 ] 9534 9787 ) 9535 end &19 49788 end &193 9536 9789 sat 16 9537 9790 eat 32 … … 9555 9808 ) 9556 9809 ) 9557 on &19 59558 ) 9559 *3 05(Wire9810 on &194 9811 ) 9812 *313 (Wire 9560 9813 uid 7477,0 9561 9814 shape (OrthoPolyLine … … 9571 9824 ) 9572 9825 start &38 9573 end &19 89826 end &197 9574 9827 es 0 9575 9828 sat 32 … … 9592 9845 ) 9593 9846 ) 9594 on &19 69595 ) 9596 *3 06(Wire9847 on &195 9848 ) 9849 *314 (Wire 9597 9850 uid 8853,0 9598 9851 shape (OrthoPolyLine … … 9611 9864 ) 9612 9865 start &30 9613 end &1 909866 end &189 9614 9867 sat 32 9615 9868 eat 1 … … 9632 9885 ) 9633 9886 ) 9634 on &2 109635 ) 9636 *3 07(Wire9887 on &209 9888 ) 9889 *315 (Wire 9637 9890 uid 9502,0 9638 9891 shape (OrthoPolyLine … … 9667 9920 ) 9668 9921 ) 9669 on &21 19670 ) 9671 *3 08(Wire9922 on &210 9923 ) 9924 *316 (Wire 9672 9925 uid 10034,0 9673 9926 shape (OrthoPolyLine … … 9684 9937 ) 9685 9938 start &25 9686 end &21 89939 end &217 9687 9940 sat 32 9688 9941 eat 32 … … 9705 9958 ) 9706 9959 ) 9707 on &2 309708 ) 9709 *3 09(Wire9960 on &229 9961 ) 9962 *317 (Wire 9710 9963 uid 10052,0 9711 9964 shape (OrthoPolyLine … … 9721 9974 ) 9722 9975 start &44 9723 end &21 69976 end &215 9724 9977 sat 32 9725 9978 eat 32 … … 9742 9995 ) 9743 9996 ) 9744 on &23 19745 ) 9746 *31 0(Wire9997 on &230 9998 ) 9999 *318 (Wire 9747 10000 uid 10302,0 9748 10001 shape (OrthoPolyLine … … 9758 10011 ] 9759 10012 ) 9760 end &23 210013 end &231 9761 10014 sat 16 9762 10015 eat 32 … … 9780 10033 ) 9781 10034 ) 9782 on &23 39783 ) 9784 *31 1(Wire10035 on &232 10036 ) 10037 *319 (Wire 9785 10038 uid 10452,0 9786 10039 shape (OrthoPolyLine … … 9788 10041 va (VaSet 9789 10042 vasetType 3 10043 lineWidth 2 9790 10044 ) 9791 10045 xt "112000,126000,122000,126000" … … 9795 10049 ] 9796 10050 ) 9797 start &23 410051 start &233 9798 10052 sat 2 9799 10053 eat 16 10054 sty 1 9800 10055 st 0 9801 10056 sf 1 … … 9815 10070 ) 9816 10071 ) 9817 on &23 39818 ) 9819 *3 12(Wire10072 on &232 10073 ) 10074 *320 (Wire 9820 10075 uid 10460,0 9821 10076 shape (OrthoPolyLine … … 9823 10078 va (VaSet 9824 10079 vasetType 3 10080 lineWidth 2 9825 10081 ) 9826 10082 xt "112000,127000,122000,127000" … … 9830 10086 ] 9831 10087 ) 9832 start &23 410088 start &233 9833 10089 sat 2 9834 10090 eat 16 10091 sty 1 9835 10092 st 0 9836 10093 sf 1 … … 9850 10107 ) 9851 10108 ) 9852 on &19 59853 ) 9854 *3 13(Wire10109 on &194 10110 ) 10111 *321 (Wire 9855 10112 uid 10498,0 9856 10113 shape (OrthoPolyLine … … 9885 10142 ) 9886 10143 ) 9887 on &23 89888 ) 9889 *3 14(Wire10144 on &237 10145 ) 10146 *322 (Wire 9890 10147 uid 10506,0 9891 10148 shape (OrthoPolyLine … … 9920 10177 ) 9921 10178 ) 9922 on &23 99923 ) 9924 *3 15(Wire10179 on &238 10180 ) 10181 *323 (Wire 9925 10182 uid 10514,0 9926 10183 shape (OrthoPolyLine … … 9955 10212 ) 9956 10213 ) 9957 on &2 409958 ) 9959 *3 16(Wire10214 on &239 10215 ) 10216 *324 (Wire 9960 10217 uid 10522,0 9961 10218 shape (OrthoPolyLine … … 9990 10247 ) 9991 10248 ) 9992 on &24 19993 ) 9994 *3 17(Wire10249 on &240 10250 ) 10251 *325 (Wire 9995 10252 uid 10530,0 9996 10253 shape (OrthoPolyLine … … 10025 10282 ) 10026 10283 ) 10027 on &24 210028 ) 10029 *3 18(Wire10284 on &241 10285 ) 10286 *326 (Wire 10030 10287 uid 10538,0 10031 10288 shape (OrthoPolyLine … … 10060 10317 ) 10061 10318 ) 10062 on &24 310063 ) 10064 *3 19(Wire10319 on &242 10320 ) 10321 *327 (Wire 10065 10322 uid 10546,0 10066 10323 shape (OrthoPolyLine … … 10095 10352 ) 10096 10353 ) 10097 on &24 410098 ) 10099 *32 0(Wire10354 on &243 10355 ) 10356 *328 (Wire 10100 10357 uid 10554,0 10101 10358 shape (OrthoPolyLine … … 10130 10387 ) 10131 10388 ) 10132 on &24 510133 ) 10134 *32 1(Wire10389 on &244 10390 ) 10391 *329 (Wire 10135 10392 uid 10562,0 10136 10393 shape (OrthoPolyLine … … 10165 10422 ) 10166 10423 ) 10167 on &24 610168 ) 10169 *3 22(Wire10424 on &245 10425 ) 10426 *330 (Wire 10170 10427 uid 10570,0 10171 10428 shape (OrthoPolyLine … … 10200 10457 ) 10201 10458 ) 10202 on &24 710203 ) 10204 *3 23(Wire10459 on &246 10460 ) 10461 *331 (Wire 10205 10462 uid 10578,0 10206 10463 shape (OrthoPolyLine … … 10235 10492 ) 10236 10493 ) 10237 on &24 810238 ) 10239 *3 24(Wire10494 on &247 10495 ) 10496 *332 (Wire 10240 10497 uid 10586,0 10241 10498 shape (OrthoPolyLine … … 10270 10527 ) 10271 10528 ) 10272 on &24 910273 ) 10274 *3 25(Wire10529 on &248 10530 ) 10531 *333 (Wire 10275 10532 uid 10594,0 10276 10533 shape (OrthoPolyLine … … 10305 10562 ) 10306 10563 ) 10307 on &2 5010308 ) 10309 *3 26(Wire10564 on &249 10565 ) 10566 *334 (Wire 10310 10567 uid 10600,0 10311 10568 shape (OrthoPolyLine … … 10320 10577 ] 10321 10578 ) 10322 end &23 410579 end &233 10323 10580 sat 16 10324 10581 eat 1 … … 10340 10597 ) 10341 10598 ) 10342 on &23 910343 ) 10344 *3 27(Wire10599 on &238 10600 ) 10601 *335 (Wire 10345 10602 uid 10608,0 10346 10603 shape (OrthoPolyLine … … 10355 10612 ] 10356 10613 ) 10357 end &23 410614 end &233 10358 10615 sat 16 10359 10616 eat 1 … … 10375 10632 ) 10376 10633 ) 10377 on &2 4010378 ) 10379 *3 28(Wire10634 on &239 10635 ) 10636 *336 (Wire 10380 10637 uid 10616,0 10381 10638 shape (OrthoPolyLine … … 10390 10647 ] 10391 10648 ) 10392 end &23 410649 end &233 10393 10650 sat 16 10394 10651 eat 1 … … 10410 10667 ) 10411 10668 ) 10412 on &23 810413 ) 10414 *3 29(Wire10669 on &237 10670 ) 10671 *337 (Wire 10415 10672 uid 10624,0 10416 10673 shape (OrthoPolyLine … … 10425 10682 ] 10426 10683 ) 10427 end &23 410684 end &233 10428 10685 sat 16 10429 10686 eat 1 … … 10445 10702 ) 10446 10703 ) 10447 on &24 510448 ) 10449 *33 0(Wire10704 on &244 10705 ) 10706 *338 (Wire 10450 10707 uid 10632,0 10451 10708 shape (OrthoPolyLine … … 10460 10717 ] 10461 10718 ) 10462 end &23 410719 end &233 10463 10720 sat 16 10464 10721 eat 1 … … 10480 10737 ) 10481 10738 ) 10482 on &2 5010483 ) 10484 *33 1(Wire10739 on &249 10740 ) 10741 *339 (Wire 10485 10742 uid 10640,0 10486 10743 shape (OrthoPolyLine … … 10495 10752 ] 10496 10753 ) 10497 end &23 410754 end &233 10498 10755 sat 16 10499 10756 eat 1 … … 10515 10772 ) 10516 10773 ) 10517 on &24 910518 ) 10519 *3 32(Wire10774 on &248 10775 ) 10776 *340 (Wire 10520 10777 uid 10648,0 10521 10778 shape (OrthoPolyLine … … 10530 10787 ] 10531 10788 ) 10532 end &23 410789 end &233 10533 10790 sat 16 10534 10791 eat 1 … … 10550 10807 ) 10551 10808 ) 10552 on &24 810553 ) 10554 *3 33(Wire10809 on &247 10810 ) 10811 *341 (Wire 10555 10812 uid 10656,0 10556 10813 shape (OrthoPolyLine … … 10565 10822 ] 10566 10823 ) 10567 end &23 410824 end &233 10568 10825 sat 16 10569 10826 eat 1 … … 10585 10842 ) 10586 10843 ) 10587 on &24 310588 ) 10589 *3 34(Wire10844 on &242 10845 ) 10846 *342 (Wire 10590 10847 uid 10664,0 10591 10848 shape (OrthoPolyLine … … 10600 10857 ] 10601 10858 ) 10602 end &23 410859 end &233 10603 10860 sat 16 10604 10861 eat 1 … … 10620 10877 ) 10621 10878 ) 10622 on &24 410623 ) 10624 *3 35(Wire10879 on &243 10880 ) 10881 *343 (Wire 10625 10882 uid 10672,0 10626 10883 shape (OrthoPolyLine … … 10635 10892 ] 10636 10893 ) 10637 end &23 410894 end &233 10638 10895 sat 16 10639 10896 eat 1 … … 10655 10912 ) 10656 10913 ) 10657 on &24 110658 ) 10659 *3 36(Wire10914 on &240 10915 ) 10916 *344 (Wire 10660 10917 uid 10680,0 10661 10918 shape (OrthoPolyLine … … 10670 10927 ] 10671 10928 ) 10672 end &23 410929 end &233 10673 10930 sat 16 10674 10931 eat 1 … … 10690 10947 ) 10691 10948 ) 10692 on &24 210693 ) 10694 *3 37(Wire10949 on &241 10950 ) 10951 *345 (Wire 10695 10952 uid 10688,0 10696 10953 shape (OrthoPolyLine … … 10705 10962 ] 10706 10963 ) 10707 end &23 410964 end &233 10708 10965 sat 16 10709 10966 eat 1 … … 10725 10982 ) 10726 10983 ) 10727 on &24 610728 ) 10729 *3 38(Wire10984 on &245 10985 ) 10986 *346 (Wire 10730 10987 uid 10696,0 10731 10988 shape (OrthoPolyLine … … 10740 10997 ] 10741 10998 ) 10742 end &23 410999 end &233 10743 11000 sat 16 10744 11001 eat 1 … … 10760 11017 ) 10761 11018 ) 10762 on &247 11019 on &246 11020 ) 11021 *347 (Wire 11022 uid 11096,0 11023 shape (OrthoPolyLine 11024 uid 11097,0 11025 va (VaSet 11026 vasetType 3 11027 ) 11028 xt "96000,103000,100000,103000" 11029 pts [ 11030 "96000,103000" 11031 "100000,103000" 11032 ] 11033 ) 11034 start &250 11035 end &155 11036 sat 32 11037 eat 1 11038 st 0 11039 sf 1 11040 si 0 11041 tg (WTG 11042 uid 11100,0 11043 ps "ConnStartEndStrategy" 11044 stg "STSignalDisplayStrategy" 11045 f (Text 11046 uid 11101,0 11047 va (VaSet 11048 isHidden 1 11049 ) 11050 xt "126000,96000,131300,97000" 11051 st "RS485_C_DI" 11052 blo "126000,96800" 11053 tm "WireNameMgr" 11054 ) 11055 ) 11056 on &251 11057 ) 11058 *348 (Wire 11059 uid 11110,0 11060 shape (OrthoPolyLine 11061 uid 11111,0 11062 va (VaSet 11063 vasetType 3 11064 ) 11065 xt "108000,112000,111000,112000" 11066 pts [ 11067 "108000,112000" 11068 "111000,112000" 11069 ] 11070 ) 11071 start &155 11072 end &252 11073 sat 2 11074 eat 32 11075 st 0 11076 sf 1 11077 si 0 11078 tg (WTG 11079 uid 11114,0 11080 ps "ConnStartEndStrategy" 11081 stg "STSignalDisplayStrategy" 11082 f (Text 11083 uid 11115,0 11084 va (VaSet 11085 isHidden 1 11086 ) 11087 xt "110000,111000,115700,112000" 11088 st "RS485_C_DO" 11089 blo "110000,111800" 11090 tm "WireNameMgr" 11091 ) 11092 ) 11093 on &253 11094 ) 11095 *349 (Wire 11096 uid 11514,0 11097 shape (OrthoPolyLine 11098 uid 11515,0 11099 va (VaSet 11100 vasetType 3 11101 ) 11102 xt "123000,116000,127000,116000" 11103 pts [ 11104 "123000,116000" 11105 "127000,116000" 11106 ] 11107 ) 11108 start &254 11109 sat 32 11110 eat 16 11111 st 0 11112 sf 1 11113 si 0 11114 tg (WTG 11115 uid 11518,0 11116 ps "ConnStartEndStrategy" 11117 stg "STSignalDisplayStrategy" 11118 f (Text 11119 uid 11519,0 11120 va (VaSet 11121 isHidden 1 11122 ) 11123 xt "125000,115000,130200,116000" 11124 st "RS485_E_DI" 11125 blo "125000,115800" 11126 tm "WireNameMgr" 11127 ) 11128 ) 11129 on &255 11130 ) 11131 *350 (Wire 11132 uid 11528,0 11133 shape (OrthoPolyLine 11134 uid 11529,0 11135 va (VaSet 11136 vasetType 3 11137 ) 11138 xt "123000,114000,126000,114000" 11139 pts [ 11140 "123000,114000" 11141 "126000,114000" 11142 ] 11143 ) 11144 end &257 11145 sat 16 11146 eat 32 11147 st 0 11148 sf 1 11149 si 0 11150 tg (WTG 11151 uid 11532,0 11152 ps "ConnStartEndStrategy" 11153 stg "STSignalDisplayStrategy" 11154 f (Text 11155 uid 11533,0 11156 va (VaSet 11157 isHidden 1 11158 ) 11159 xt "125000,113000,130600,114000" 11160 st "RS485_E_DO" 11161 blo "125000,113800" 11162 tm "WireNameMgr" 11163 ) 11164 ) 11165 on &256 11166 ) 11167 *351 (Wire 11168 uid 12320,0 11169 shape (OrthoPolyLine 11170 uid 12321,0 11171 va (VaSet 11172 vasetType 3 11173 ) 11174 xt "80750,140000,87000,140000" 11175 pts [ 11176 "80750,140000" 11177 "87000,140000" 11178 ] 11179 ) 11180 start &59 11181 end &258 11182 sat 32 11183 eat 32 11184 stc 0 11185 st 0 11186 sf 1 11187 si 0 11188 tg (WTG 11189 uid 12324,0 11190 ps "ConnStartEndStrategy" 11191 stg "STSignalDisplayStrategy" 11192 f (Text 11193 uid 12325,0 11194 va (VaSet 11195 isHidden 1 11196 ) 11197 xt "82000,139000,84300,140000" 11198 st "SRIN" 11199 blo "82000,139800" 11200 tm "WireNameMgr" 11201 ) 11202 ) 11203 on &259 10763 11204 ) 10764 11205 ] … … 10774 11215 color "26368,26368,26368" 10775 11216 ) 10776 packageList *3 39(PackageList11217 packageList *352 (PackageList 10777 11218 uid 41,0 10778 11219 stg "VerticalLayoutStrategy" 10779 11220 textVec [ 10780 *3 40(Text11221 *353 (Text 10781 11222 uid 42,0 10782 11223 va (VaSet … … 10787 11228 blo "0,800" 10788 11229 ) 10789 *3 41(MLText11230 *354 (MLText 10790 11231 uid 43,0 10791 11232 va (VaSet … … 10808 11249 stg "VerticalLayoutStrategy" 10809 11250 textVec [ 10810 *3 42(Text11251 *355 (Text 10811 11252 uid 45,0 10812 11253 va (VaSet … … 10818 11259 blo "20000,800" 10819 11260 ) 10820 *3 43(Text11261 *356 (Text 10821 11262 uid 46,0 10822 11263 va (VaSet … … 10828 11269 blo "20000,1800" 10829 11270 ) 10830 *3 44(MLText11271 *357 (MLText 10831 11272 uid 47,0 10832 11273 va (VaSet … … 10838 11279 tm "BdCompilerDirectivesTextMgr" 10839 11280 ) 10840 *3 45(Text11281 *358 (Text 10841 11282 uid 48,0 10842 11283 va (VaSet … … 10848 11289 blo "20000,4800" 10849 11290 ) 10850 *3 46(MLText11291 *359 (MLText 10851 11292 uid 49,0 10852 11293 va (VaSet … … 10856 11297 tm "BdCompilerDirectivesTextMgr" 10857 11298 ) 10858 *3 47(Text11299 *360 (Text 10859 11300 uid 50,0 10860 11301 va (VaSet … … 10866 11307 blo "20000,5800" 10867 11308 ) 10868 *3 48(MLText11309 *361 (MLText 10869 11310 uid 51,0 10870 11311 va (VaSet … … 10877 11318 associable 1 10878 11319 ) 10879 windowSize " 1280,0,2561,1024"10880 viewArea " 33652,91254,117471,160379"11320 windowSize "0,0,1281,1002" 11321 viewArea "48828,78798,132010,145674" 10881 11322 cachedDiagramExtent "0,0,699000,450107" 10882 11323 pageSetupInfo (PageSetupInfo … … 10891 11332 hasePageBreakOrigin 1 10892 11333 pageBreakOrigin "0,0" 10893 lastUid 1 0906,011334 lastUid 12337,0 10894 11335 defaultCommentText (CommentText 10895 11336 shape (Rectangle … … 10953 11394 stg "VerticalLayoutStrategy" 10954 11395 textVec [ 10955 *3 49(Text11396 *362 (Text 10956 11397 va (VaSet 10957 11398 font "Arial,8,1" … … 10962 11403 tm "BdLibraryNameMgr" 10963 11404 ) 10964 *3 50(Text11405 *363 (Text 10965 11406 va (VaSet 10966 11407 font "Arial,8,1" … … 10971 11412 tm "BlkNameMgr" 10972 11413 ) 10973 *3 51(Text11414 *364 (Text 10974 11415 va (VaSet 10975 11416 font "Arial,8,1" … … 11022 11463 stg "VerticalLayoutStrategy" 11023 11464 textVec [ 11024 *3 52(Text11465 *365 (Text 11025 11466 va (VaSet 11026 11467 font "Arial,8,1" … … 11030 11471 blo "550,4300" 11031 11472 ) 11032 *3 53(Text11473 *366 (Text 11033 11474 va (VaSet 11034 11475 font "Arial,8,1" … … 11038 11479 blo "550,5300" 11039 11480 ) 11040 *3 54(Text11481 *367 (Text 11041 11482 va (VaSet 11042 11483 font "Arial,8,1" … … 11087 11528 stg "VerticalLayoutStrategy" 11088 11529 textVec [ 11089 *3 55(Text11530 *368 (Text 11090 11531 va (VaSet 11091 11532 font "Arial,8,1" … … 11096 11537 tm "BdLibraryNameMgr" 11097 11538 ) 11098 *3 56(Text11539 *369 (Text 11099 11540 va (VaSet 11100 11541 font "Arial,8,1" … … 11105 11546 tm "CptNameMgr" 11106 11547 ) 11107 *3 57(Text11548 *370 (Text 11108 11549 va (VaSet 11109 11550 font "Arial,8,1" … … 11159 11600 stg "VerticalLayoutStrategy" 11160 11601 textVec [ 11161 *3 58(Text11602 *371 (Text 11162 11603 va (VaSet 11163 11604 font "Arial,8,1" … … 11167 11608 blo "500,4300" 11168 11609 ) 11169 *3 59(Text11610 *372 (Text 11170 11611 va (VaSet 11171 11612 font "Arial,8,1" … … 11175 11616 blo "500,5300" 11176 11617 ) 11177 *3 60(Text11618 *373 (Text 11178 11619 va (VaSet 11179 11620 font "Arial,8,1" … … 11220 11661 stg "VerticalLayoutStrategy" 11221 11662 textVec [ 11222 *3 61(Text11663 *374 (Text 11223 11664 va (VaSet 11224 11665 font "Arial,8,1" … … 11228 11669 blo "50,4300" 11229 11670 ) 11230 *3 62(Text11671 *375 (Text 11231 11672 va (VaSet 11232 11673 font "Arial,8,1" … … 11236 11677 blo "50,5300" 11237 11678 ) 11238 *3 63(Text11679 *376 (Text 11239 11680 va (VaSet 11240 11681 font "Arial,8,1" … … 11277 11718 stg "VerticalLayoutStrategy" 11278 11719 textVec [ 11279 *3 64(Text11720 *377 (Text 11280 11721 va (VaSet 11281 11722 font "Arial,8,1" … … 11286 11727 tm "HdlTextNameMgr" 11287 11728 ) 11288 *3 65(Text11729 *378 (Text 11289 11730 va (VaSet 11290 11731 font "Arial,8,1" … … 11689 12130 stg "VerticalLayoutStrategy" 11690 12131 textVec [ 11691 *3 66(Text12132 *379 (Text 11692 12133 va (VaSet 11693 12134 font "Arial,8,1" … … 11697 12138 blo "14100,20800" 11698 12139 ) 11699 *3 67(MLText12140 *380 (MLText 11700 12141 va (VaSet 11701 12142 ) … … 11749 12190 stg "VerticalLayoutStrategy" 11750 12191 textVec [ 11751 *3 68(Text12192 *381 (Text 11752 12193 va (VaSet 11753 12194 font "Arial,8,1" … … 11757 12198 blo "14100,20800" 11758 12199 ) 11759 *3 69(MLText12200 *382 (MLText 11760 12201 va (VaSet 11761 12202 ) … … 11875 12316 font "Arial,8,1" 11876 12317 ) 11877 xt "37000,4 3000,44100,44000"12318 xt "37000,46200,44100,47200" 11878 12319 st "Diagram Signals:" 11879 blo "37000,4 3800"12320 blo "37000,47000" 11880 12321 ) 11881 12322 postUserLabel (Text … … 11901 12342 commonDM (CommonDM 11902 12343 ldm (LogicalDM 11903 suid 196,012344 suid 203,0 11904 12345 usingSuid 1 11905 emptyRow *3 70(LEmptyRow12346 emptyRow *383 (LEmptyRow 11906 12347 ) 11907 12348 uid 54,0 11908 12349 optionalChildren [ 11909 *3 71(RefLabelRowHdr11910 ) 11911 *3 72(TitleRowHdr11912 ) 11913 *3 73(FilterRowHdr11914 ) 11915 *3 74(RefLabelColHdr12350 *384 (RefLabelRowHdr 12351 ) 12352 *385 (TitleRowHdr 12353 ) 12354 *386 (FilterRowHdr 12355 ) 12356 *387 (RefLabelColHdr 11916 12357 tm "RefLabelColHdrMgr" 11917 12358 ) 11918 *3 75(RowExpandColHdr12359 *388 (RowExpandColHdr 11919 12360 tm "RowExpandColHdrMgr" 11920 12361 ) 11921 *3 76(GroupColHdr12362 *389 (GroupColHdr 11922 12363 tm "GroupColHdrMgr" 11923 12364 ) 11924 *3 77(NameColHdr12365 *390 (NameColHdr 11925 12366 tm "BlockDiagramNameColHdrMgr" 11926 12367 ) 11927 *3 78(ModeColHdr12368 *391 (ModeColHdr 11928 12369 tm "BlockDiagramModeColHdrMgr" 11929 12370 ) 11930 *3 79(TypeColHdr12371 *392 (TypeColHdr 11931 12372 tm "BlockDiagramTypeColHdrMgr" 11932 12373 ) 11933 *3 80(BoundsColHdr12374 *393 (BoundsColHdr 11934 12375 tm "BlockDiagramBoundsColHdrMgr" 11935 12376 ) 11936 *3 81(InitColHdr12377 *394 (InitColHdr 11937 12378 tm "BlockDiagramInitColHdrMgr" 11938 12379 ) 11939 *3 82(EolColHdr12380 *395 (EolColHdr 11940 12381 tm "BlockDiagramEolColHdrMgr" 11941 12382 ) 11942 *3 83(LeafLogPort12383 *396 (LeafLogPort 11943 12384 port (LogicalPort 11944 12385 m 4 … … 11949 12390 preAdd 0 11950 12391 posAdd 0 11951 o 5512392 o 69 11952 12393 suid 5,0 11953 12394 ) … … 11955 12396 uid 327,0 11956 12397 ) 11957 *3 84(LeafLogPort12398 *397 (LeafLogPort 11958 12399 port (LogicalPort 11959 12400 m 4 … … 11962 12403 t "std_logic_vector" 11963 12404 b "(1 downto 0)" 11964 o 5612405 o 70 11965 12406 suid 6,0 11966 12407 ) … … 11968 12409 uid 329,0 11969 12410 ) 11970 *3 85(LeafLogPort12411 *398 (LeafLogPort 11971 12412 port (LogicalPort 11972 12413 m 4 … … 11974 12415 n "adc_data_array" 11975 12416 t "adc_data_array_type" 11976 o 5412417 o 68 11977 12418 suid 29,0 11978 12419 ) … … 11980 12421 uid 1491,0 11981 12422 ) 11982 *3 86(LeafLogPort12423 *399 (LeafLogPort 11983 12424 port (LogicalPort 11984 12425 m 1 … … 11986 12427 n "RSRLOAD" 11987 12428 t "std_logic" 11988 o 3 512429 o 37 11989 12430 suid 57,0 11990 12431 i "'0'" … … 11993 12434 uid 2435,0 11994 12435 ) 11995 * 387(LeafLogPort12436 *400 (LeafLogPort 11996 12437 port (LogicalPort 11997 12438 m 4 … … 11999 12440 n "SRCLK" 12000 12441 t "std_logic" 12001 o 5212442 o 66 12002 12443 suid 58,0 12003 12444 i "'0'" … … 12006 12447 uid 2437,0 12007 12448 ) 12008 * 388(LeafLogPort12449 *401 (LeafLogPort 12009 12450 port (LogicalPort 12010 12451 m 4 … … 12013 12454 t "std_logic_vector" 12014 12455 b "(3 DOWNTO 0)" 12015 o 5912456 o 74 12016 12457 suid 65,0 12017 12458 ) … … 12019 12460 uid 3037,0 12020 12461 ) 12021 * 389(LeafLogPort12462 *402 (LeafLogPort 12022 12463 port (LogicalPort 12023 12464 m 1 … … 12025 12466 n "DAC_CS" 12026 12467 t "std_logic" 12027 o 2 112468 o 22 12028 12469 suid 66,0 12029 12470 ) … … 12031 12472 uid 3039,0 12032 12473 ) 12033 * 390(LeafLogPort12474 *403 (LeafLogPort 12034 12475 port (LogicalPort 12035 12476 decl (Decl … … 12044 12485 uid 3276,0 12045 12486 ) 12046 * 391(LeafLogPort12487 *404 (LeafLogPort 12047 12488 port (LogicalPort 12048 12489 decl (Decl … … 12055 12496 uid 3278,0 12056 12497 ) 12057 * 392(LeafLogPort12498 *405 (LeafLogPort 12058 12499 port (LogicalPort 12059 12500 m 1 … … 12062 12503 t "std_logic_vector" 12063 12504 b "(3 downto 0)" 12064 o 1 612505 o 17 12065 12506 suid 71,0 12066 12507 ) … … 12068 12509 uid 3280,0 12069 12510 ) 12070 * 393(LeafLogPort12511 *406 (LeafLogPort 12071 12512 port (LogicalPort 12072 12513 m 4 … … 12074 12515 n "CLK_25_PS" 12075 12516 t "std_logic" 12076 o 5 012517 o 55 12077 12518 suid 72,0 12078 12519 ) … … 12080 12521 uid 3282,0 12081 12522 ) 12082 * 394(LeafLogPort12523 *407 (LeafLogPort 12083 12524 port (LogicalPort 12084 12525 m 1 … … 12088 12529 preAdd 0 12089 12530 posAdd 0 12090 o 3 012531 o 31 12091 12532 suid 73,0 12092 12533 ) … … 12094 12535 uid 3382,0 12095 12536 ) 12096 * 395(LeafLogPort12537 *408 (LeafLogPort 12097 12538 port (LogicalPort 12098 12539 decl (Decl … … 12106 12547 uid 3384,0 12107 12548 ) 12108 * 396(LeafLogPort12549 *409 (LeafLogPort 12109 12550 port (LogicalPort 12110 12551 decl (Decl … … 12118 12559 uid 3386,0 12119 12560 ) 12120 * 397(LeafLogPort12561 *410 (LeafLogPort 12121 12562 port (LogicalPort 12122 12563 decl (Decl … … 12130 12571 uid 3388,0 12131 12572 ) 12132 * 398(LeafLogPort12573 *411 (LeafLogPort 12133 12574 port (LogicalPort 12134 12575 decl (Decl … … 12142 12583 uid 3390,0 12143 12584 ) 12144 * 399(LeafLogPort12585 *412 (LeafLogPort 12145 12586 port (LogicalPort 12146 12587 decl (Decl … … 12154 12595 uid 3392,0 12155 12596 ) 12156 *4 00(LeafLogPort12597 *413 (LeafLogPort 12157 12598 port (LogicalPort 12158 12599 m 1 … … 12160 12601 n "D0_SRCLK" 12161 12602 t "STD_LOGIC" 12162 o 1 712603 o 18 12163 12604 suid 87,0 12164 12605 ) … … 12166 12607 uid 3468,0 12167 12608 ) 12168 *4 01(LeafLogPort12609 *414 (LeafLogPort 12169 12610 port (LogicalPort 12170 12611 m 1 … … 12172 12613 n "D1_SRCLK" 12173 12614 t "STD_LOGIC" 12174 o 1 812615 o 19 12175 12616 suid 88,0 12176 12617 ) … … 12178 12619 uid 3470,0 12179 12620 ) 12180 *4 02(LeafLogPort12621 *415 (LeafLogPort 12181 12622 port (LogicalPort 12182 12623 m 1 … … 12184 12625 n "D2_SRCLK" 12185 12626 t "STD_LOGIC" 12186 o 1912627 o 20 12187 12628 suid 89,0 12188 12629 ) … … 12190 12631 uid 3472,0 12191 12632 ) 12192 *4 03(LeafLogPort12633 *416 (LeafLogPort 12193 12634 port (LogicalPort 12194 12635 m 1 … … 12196 12637 n "D3_SRCLK" 12197 12638 t "STD_LOGIC" 12198 o 2 012639 o 21 12199 12640 suid 90,0 12200 12641 ) … … 12202 12643 uid 3474,0 12203 12644 ) 12204 *4 04(LeafLogPort12645 *417 (LeafLogPort 12205 12646 port (LogicalPort 12206 12647 decl (Decl … … 12213 12654 uid 3524,0 12214 12655 ) 12215 *4 05(LeafLogPort12656 *418 (LeafLogPort 12216 12657 port (LogicalPort 12217 12658 decl (Decl … … 12224 12665 uid 3526,0 12225 12666 ) 12226 *4 06(LeafLogPort12667 *419 (LeafLogPort 12227 12668 port (LogicalPort 12228 12669 decl (Decl … … 12235 12676 uid 3528,0 12236 12677 ) 12237 *4 07(LeafLogPort12678 *420 (LeafLogPort 12238 12679 port (LogicalPort 12239 12680 decl (Decl … … 12246 12687 uid 3530,0 12247 12688 ) 12248 *4 08(LeafLogPort12689 *421 (LeafLogPort 12249 12690 port (LogicalPort 12250 12691 m 1 … … 12253 12694 t "std_logic_vector" 12254 12695 b "(3 DOWNTO 0)" 12255 o 2 412696 o 25 12256 12697 suid 95,0 12257 12698 i "(others => '0')" … … 12260 12701 uid 3532,0 12261 12702 ) 12262 *4 09(LeafLogPort12703 *422 (LeafLogPort 12263 12704 port (LogicalPort 12264 12705 m 1 … … 12266 12707 n "DWRITE" 12267 12708 t "std_logic" 12268 o 2 312709 o 24 12269 12710 suid 96,0 12270 12711 i "'0'" … … 12273 12714 uid 3534,0 12274 12715 ) 12275 *4 10(LeafLogPort12716 *423 (LeafLogPort 12276 12717 port (LogicalPort 12277 12718 m 1 … … 12279 12720 n "T0_CS" 12280 12721 t "std_logic" 12281 o 3812722 o 40 12282 12723 suid 101,0 12283 12724 ) … … 12285 12726 uid 3646,0 12286 12727 ) 12287 *4 11(LeafLogPort12728 *424 (LeafLogPort 12288 12729 port (LogicalPort 12289 12730 m 1 … … 12291 12732 n "T1_CS" 12292 12733 t "std_logic" 12293 o 3912734 o 41 12294 12735 suid 102,0 12295 12736 ) … … 12297 12738 uid 3648,0 12298 12739 ) 12299 *4 12(LeafLogPort12740 *425 (LeafLogPort 12300 12741 port (LogicalPort 12301 12742 m 1 … … 12303 12744 n "T2_CS" 12304 12745 t "std_logic" 12305 o 4 012746 o 42 12306 12747 suid 103,0 12307 12748 ) … … 12309 12750 uid 3650,0 12310 12751 ) 12311 *4 13(LeafLogPort12752 *426 (LeafLogPort 12312 12753 port (LogicalPort 12313 12754 m 1 … … 12315 12756 n "T3_CS" 12316 12757 t "std_logic" 12317 o 4 112758 o 43 12318 12759 suid 104,0 12319 12760 ) … … 12321 12762 uid 3652,0 12322 12763 ) 12323 *4 14(LeafLogPort12764 *427 (LeafLogPort 12324 12765 port (LogicalPort 12325 12766 m 1 … … 12327 12768 n "S_CLK" 12328 12769 t "std_logic" 12329 o 3 712770 o 39 12330 12771 suid 105,0 12331 12772 ) … … 12333 12774 uid 3654,0 12334 12775 ) 12335 *4 15(LeafLogPort12776 *428 (LeafLogPort 12336 12777 port (LogicalPort 12337 12778 m 1 … … 12340 12781 t "std_logic_vector" 12341 12782 b "(9 DOWNTO 0)" 12342 o 4 312783 o 45 12343 12784 suid 106,0 12344 12785 ) … … 12346 12787 uid 3656,0 12347 12788 ) 12348 *4 16(LeafLogPort12789 *429 (LeafLogPort 12349 12790 port (LogicalPort 12350 12791 m 2 … … 12353 12794 t "std_logic_vector" 12354 12795 b "(15 DOWNTO 0)" 12355 o 4912796 o 51 12356 12797 suid 107,0 12357 12798 ) 12358 12799 ) 12359 12800 uid 3658,0 12360 )12361 *417 (LeafLogPort12362 port (LogicalPort12363 m 112364 decl (Decl12365 n "W_RES"12366 t "std_logic"12367 o 4612368 suid 108,012369 i "'1'"12370 )12371 )12372 uid 3660,012373 )12374 *418 (LeafLogPort12375 port (LogicalPort12376 m 112377 decl (Decl12378 n "W_RD"12379 t "std_logic"12380 o 4512381 suid 109,012382 i "'1'"12383 )12384 )12385 uid 3662,012386 )12387 *419 (LeafLogPort12388 port (LogicalPort12389 m 112390 decl (Decl12391 n "W_WR"12392 t "std_logic"12393 o 4712394 suid 110,012395 i "'1'"12396 )12397 )12398 uid 3664,012399 )12400 *420 (LeafLogPort12401 port (LogicalPort12402 decl (Decl12403 n "W_INT"12404 t "std_logic"12405 o 1312406 suid 111,012407 )12408 )12409 uid 3666,012410 )12411 *421 (LeafLogPort12412 port (LogicalPort12413 m 112414 decl (Decl12415 n "W_CS"12416 t "std_logic"12417 o 4412418 suid 112,012419 i "'1'"12420 )12421 )12422 uid 3668,012423 )12424 *422 (LeafLogPort12425 port (LogicalPort12426 m 112427 decl (Decl12428 n "MOSI"12429 t "std_logic"12430 o 2912431 suid 113,012432 i "'0'"12433 )12434 )12435 uid 3696,012436 )12437 *423 (LeafLogPort12438 port (LogicalPort12439 m 212440 decl (Decl12441 n "MISO"12442 t "std_logic"12443 preAdd 012444 posAdd 012445 o 4812446 suid 114,012447 )12448 )12449 uid 3698,012450 )12451 *424 (LeafLogPort12452 port (LogicalPort12453 m 112454 decl (Decl12455 n "TRG_V"12456 t "std_logic"12457 o 4212458 suid 126,012459 )12460 )12461 uid 3886,012462 )12463 *425 (LeafLogPort12464 port (LogicalPort12465 m 112466 decl (Decl12467 n "RS485_C_RE"12468 t "std_logic"12469 o 3212470 suid 127,012471 )12472 )12473 uid 3888,012474 )12475 *426 (LeafLogPort12476 port (LogicalPort12477 m 112478 decl (Decl12479 n "RS485_C_DE"12480 t "std_logic"12481 o 3112482 suid 128,012483 )12484 )12485 uid 3890,012486 )12487 *427 (LeafLogPort12488 port (LogicalPort12489 m 112490 decl (Decl12491 n "RS485_E_RE"12492 t "std_logic"12493 o 3412494 suid 129,012495 )12496 )12497 uid 3892,012498 )12499 *428 (LeafLogPort12500 port (LogicalPort12501 m 112502 decl (Decl12503 n "RS485_E_DE"12504 t "std_logic"12505 o 3312506 suid 130,012507 )12508 )12509 uid 3894,012510 )12511 *429 (LeafLogPort12512 port (LogicalPort12513 m 112514 decl (Decl12515 n "DENABLE"12516 t "std_logic"12517 o 2212518 suid 131,012519 i "'0'"12520 )12521 )12522 uid 3896,012523 12801 ) 12524 12802 *430 (LeafLogPort … … 12526 12804 m 1 12527 12805 decl (Decl 12528 n "SRIN" 12529 t "std_logic" 12530 o 36 12531 suid 132,0 12532 ) 12533 ) 12534 uid 3898,0 12806 n "W_RES" 12807 t "std_logic" 12808 o 48 12809 suid 108,0 12810 i "'1'" 12811 ) 12812 ) 12813 uid 3660,0 12535 12814 ) 12536 12815 *431 (LeafLogPort … … 12538 12817 m 1 12539 12818 decl (Decl 12540 n "EE_CS" 12541 t "std_logic" 12542 o 27 12543 suid 133,0 12544 ) 12545 ) 12546 uid 3900,0 12819 n "W_RD" 12820 t "std_logic" 12821 o 47 12822 suid 109,0 12823 i "'1'" 12824 ) 12825 ) 12826 uid 3662,0 12547 12827 ) 12548 12828 *432 (LeafLogPort … … 12550 12830 m 1 12551 12831 decl (Decl 12832 n "W_WR" 12833 t "std_logic" 12834 o 49 12835 suid 110,0 12836 i "'1'" 12837 ) 12838 ) 12839 uid 3664,0 12840 ) 12841 *433 (LeafLogPort 12842 port (LogicalPort 12843 decl (Decl 12844 n "W_INT" 12845 t "std_logic" 12846 o 13 12847 suid 111,0 12848 ) 12849 ) 12850 uid 3666,0 12851 ) 12852 *434 (LeafLogPort 12853 port (LogicalPort 12854 m 1 12855 decl (Decl 12856 n "W_CS" 12857 t "std_logic" 12858 o 46 12859 suid 112,0 12860 i "'1'" 12861 ) 12862 ) 12863 uid 3668,0 12864 ) 12865 *435 (LeafLogPort 12866 port (LogicalPort 12867 m 1 12868 decl (Decl 12869 n "MOSI" 12870 t "std_logic" 12871 o 30 12872 suid 113,0 12873 i "'0'" 12874 ) 12875 ) 12876 uid 3696,0 12877 ) 12878 *436 (LeafLogPort 12879 port (LogicalPort 12880 m 2 12881 decl (Decl 12882 n "MISO" 12883 t "std_logic" 12884 preAdd 0 12885 posAdd 0 12886 o 50 12887 suid 114,0 12888 ) 12889 ) 12890 uid 3698,0 12891 ) 12892 *437 (LeafLogPort 12893 port (LogicalPort 12894 m 1 12895 decl (Decl 12896 n "TRG_V" 12897 t "std_logic" 12898 o 44 12899 suid 126,0 12900 ) 12901 ) 12902 uid 3886,0 12903 ) 12904 *438 (LeafLogPort 12905 port (LogicalPort 12906 m 1 12907 decl (Decl 12908 n "RS485_C_RE" 12909 t "std_logic" 12910 o 34 12911 suid 127,0 12912 ) 12913 ) 12914 uid 3888,0 12915 ) 12916 *439 (LeafLogPort 12917 port (LogicalPort 12918 m 1 12919 decl (Decl 12920 n "RS485_C_DE" 12921 t "std_logic" 12922 o 32 12923 suid 128,0 12924 ) 12925 ) 12926 uid 3890,0 12927 ) 12928 *440 (LeafLogPort 12929 port (LogicalPort 12930 m 1 12931 decl (Decl 12932 n "RS485_E_RE" 12933 t "std_logic" 12934 o 36 12935 suid 129,0 12936 ) 12937 ) 12938 uid 3892,0 12939 ) 12940 *441 (LeafLogPort 12941 port (LogicalPort 12942 m 1 12943 decl (Decl 12944 n "RS485_E_DE" 12945 t "std_logic" 12946 o 35 12947 suid 130,0 12948 ) 12949 ) 12950 uid 3894,0 12951 ) 12952 *442 (LeafLogPort 12953 port (LogicalPort 12954 m 1 12955 decl (Decl 12956 n "DENABLE" 12957 t "std_logic" 12958 o 23 12959 suid 131,0 12960 i "'0'" 12961 ) 12962 ) 12963 uid 3896,0 12964 ) 12965 *443 (LeafLogPort 12966 port (LogicalPort 12967 m 1 12968 decl (Decl 12969 n "EE_CS" 12970 t "std_logic" 12971 o 28 12972 suid 133,0 12973 ) 12974 ) 12975 uid 3900,0 12976 ) 12977 *444 (LeafLogPort 12978 port (LogicalPort 12979 m 1 12980 decl (Decl 12552 12981 n "LED" 12553 12982 t "std_logic_vector" 12554 12983 b "( 2 DOWNTO 0 )" 12555 o 2 812984 o 29 12556 12985 suid 134,0 12557 12986 i "(others => '1')" … … 12560 12989 uid 3902,0 12561 12990 ) 12562 *4 33(LeafLogPort12991 *445 (LeafLogPort 12563 12992 port (LogicalPort 12564 12993 m 1 … … 12567 12996 t "std_logic_vector" 12568 12997 b "(7 DOWNTO 0)" 12569 o 2 512998 o 26 12570 12999 suid 141,0 12571 13000 i "(OTHERS => '0')" … … 12574 13003 uid 5322,0 12575 13004 ) 12576 *4 34(LeafLogPort13005 *446 (LeafLogPort 12577 13006 port (LogicalPort 12578 13007 decl (Decl … … 12587 13016 scheme 0 12588 13017 ) 12589 *4 35(LeafLogPort13018 *447 (LeafLogPort 12590 13019 port (LogicalPort 12591 13020 m 1 … … 12594 13023 t "std_logic_vector" 12595 13024 b "(3 DOWNTO 0)" 12596 o 2 613025 o 27 12597 13026 suid 154,0 12598 13027 i "(others => '0')" … … 12602 13031 scheme 0 12603 13032 ) 12604 *4 36(LeafLogPort13033 *448 (LeafLogPort 12605 13034 port (LogicalPort 12606 13035 m 1 … … 12609 13038 t "std_logic_vector" 12610 13039 b "(7 DOWNTO 0)" 12611 o 1 513040 o 16 12612 13041 suid 155,0 12613 13042 i "(OTHERS => '0')" … … 12617 13046 scheme 0 12618 13047 ) 12619 *4 37(LeafLogPort13048 *449 (LeafLogPort 12620 13049 port (LogicalPort 12621 13050 m 4 … … 12623 13052 n "dummy" 12624 13053 t "std_logic" 12625 o 5813054 o 72 12626 13055 suid 157,0 12627 13056 ) … … 12630 13059 scheme 0 12631 13060 ) 12632 *4 38(LeafLogPort13061 *450 (LeafLogPort 12633 13062 port (LogicalPort 12634 13063 m 4 … … 12637 13066 t "std_logic_vector" 12638 13067 b "(3 downto 0)" 12639 o 5713068 o 71 12640 13069 suid 159,0 12641 13070 i "(others => '0')" … … 12644 13073 uid 8875,0 12645 13074 ) 12646 *4 39(LeafLogPort13075 *451 (LeafLogPort 12647 13076 port (LogicalPort 12648 13077 m 4 … … 12650 13079 n "CLK_50" 12651 13080 t "std_logic" 12652 o 5 113081 o 57 12653 13082 suid 163,0 12654 13083 ) … … 12656 13085 uid 9516,0 12657 13086 ) 12658 *4 40(LeafLogPort13087 *452 (LeafLogPort 12659 13088 port (LogicalPort 12660 13089 m 4 … … 12662 13091 n "CLK_25_PS1" 12663 13092 t "std_logic" 12664 o 5 813093 o 56 12665 13094 suid 164,0 12666 13095 ) … … 12668 13097 uid 10056,0 12669 13098 ) 12670 *4 41(LeafLogPort13099 *453 (LeafLogPort 12671 13100 port (LogicalPort 12672 13101 m 4 … … 12674 13103 n "adc_clk_en" 12675 13104 t "std_logic" 12676 o 5913105 o 67 12677 13106 suid 165,0 12678 13107 i "'0'" … … 12681 13110 uid 10058,0 12682 13111 ) 12683 *4 42(LeafLogPort13112 *454 (LeafLogPort 12684 13113 port (LogicalPort 12685 13114 m 1 … … 12688 13117 t "std_logic_vector" 12689 13118 b "(7 DOWNTO 0)" 12690 o 6013119 o 15 12691 13120 suid 166,0 12692 13121 i "(others => '0')" … … 12696 13125 scheme 0 12697 13126 ) 12698 *4 43(LeafLogPort13127 *455 (LeafLogPort 12699 13128 port (LogicalPort 12700 13129 m 4 … … 12702 13131 n "CLK50_OUT" 12703 13132 t "std_logic" 12704 o 6113133 o 54 12705 13134 suid 184,0 12706 13135 ) … … 12708 13137 uid 10704,0 12709 13138 ) 12710 *4 44(LeafLogPort13139 *456 (LeafLogPort 12711 13140 port (LogicalPort 12712 13141 m 4 … … 12714 13143 n "CLK25_OUT" 12715 13144 t "std_logic" 12716 o 6213145 o 52 12717 13146 suid 185,0 12718 13147 ) … … 12720 13149 uid 10706,0 12721 13150 ) 12722 *4 45(LeafLogPort13151 *457 (LeafLogPort 12723 13152 port (LogicalPort 12724 13153 m 4 … … 12726 13155 n "CLK25_PSOUT" 12727 13156 t "std_logic" 12728 o 6313157 o 53 12729 13158 suid 186,0 12730 13159 ) … … 12732 13161 uid 10708,0 12733 13162 ) 12734 *4 46(LeafLogPort13163 *458 (LeafLogPort 12735 13164 port (LogicalPort 12736 13165 m 4 … … 12744 13173 uid 10710,0 12745 13174 ) 12746 *4 47(LeafLogPort13175 *459 (LeafLogPort 12747 13176 port (LogicalPort 12748 13177 m 4 … … 12756 13185 uid 10712,0 12757 13186 ) 12758 *4 48(LeafLogPort13187 *460 (LeafLogPort 12759 13188 port (LogicalPort 12760 13189 m 4 … … 12762 13191 n "PSEN_OUT" 12763 13192 t "std_logic" 12764 o 6 613193 o 62 12765 13194 suid 189,0 12766 13195 ) … … 12768 13197 uid 10714,0 12769 13198 ) 12770 *4 49(LeafLogPort13199 *461 (LeafLogPort 12771 13200 port (LogicalPort 12772 13201 m 4 … … 12774 13203 n "PSINCDEC_OUT" 12775 13204 t "std_logic" 12776 o 6 713205 o 63 12777 13206 suid 190,0 12778 13207 ) … … 12780 13209 uid 10716,0 12781 13210 ) 12782 *4 50(LeafLogPort13211 *462 (LeafLogPort 12783 13212 port (LogicalPort 12784 13213 m 4 … … 12788 13217 preAdd 0 12789 13218 posAdd 0 12790 o 6813219 o 58 12791 13220 suid 191,0 12792 13221 ) … … 12794 13223 uid 10718,0 12795 13224 ) 12796 *4 51(LeafLogPort13225 *463 (LeafLogPort 12797 13226 port (LogicalPort 12798 13227 m 4 … … 12802 13231 preAdd 0 12803 13232 posAdd 0 12804 o 6913233 o 73 12805 13234 suid 192,0 12806 13235 i "'0'" … … 12809 13238 uid 10720,0 12810 13239 ) 12811 *4 52(LeafLogPort13240 *464 (LeafLogPort 12812 13241 port (LogicalPort 12813 13242 m 4 … … 12818 13247 preAdd 0 12819 13248 posAdd 0 12820 o 7 013249 o 75 12821 13250 suid 193,0 12822 13251 i "'0'" … … 12825 13254 uid 10722,0 12826 13255 ) 12827 *4 53(LeafLogPort13256 *465 (LeafLogPort 12828 13257 port (LogicalPort 12829 13258 m 4 … … 12831 13260 n "PSDONE_extraOUT" 12832 13261 t "std_logic" 12833 o 7113262 o 61 12834 13263 suid 194,0 12835 13264 ) … … 12837 13266 uid 10724,0 12838 13267 ) 12839 *4 54(LeafLogPort13268 *466 (LeafLogPort 12840 13269 port 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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak
r9912 r10073 109 109 (vvPair 110 110 variable "HDLDir" 111 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"111 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" 112 112 ) 113 113 (vvPair 114 114 variable "HDSDir" 115 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"115 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 116 116 ) 117 117 (vvPair 118 118 variable "SideDataDesignDir" 119 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"119 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info" 120 120 ) 121 121 (vvPair 122 122 variable "SideDataUserDir" 123 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"123 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user" 124 124 ) 125 125 (vvPair 126 126 variable "SourceDir" 127 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"127 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 128 128 ) 129 129 (vvPair … … 141 141 (vvPair 142 142 variable "d" 143 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board"143 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board" 144 144 ) 145 145 (vvPair 146 146 variable "d_logical" 147 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board"147 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board" 148 148 ) 149 149 (vvPair 150 150 variable "date" 151 value " 27.08.2010"151 value "03.01.2011" 152 152 ) 153 153 (vvPair 154 154 variable "day" 155 value " Fr"155 value "Mo" 156 156 ) 157 157 (vvPair 158 158 variable "day_long" 159 value " Freitag"159 value "Montag" 160 160 ) 161 161 (vvPair 162 162 variable "dd" 163 value " 27"163 value "03" 164 164 ) 165 165 (vvPair … … 221 221 (vvPair 222 222 variable "mm" 223 value "0 8"223 value "01" 224 224 ) 225 225 (vvPair … … 229 229 (vvPair 230 230 variable "month" 231 value " Aug"231 value "Jan" 232 232 ) 233 233 (vvPair 234 234 variable "month_long" 235 value " August"235 value "Januar" 236 236 ) 237 237 (vvPair 238 238 variable "p" 239 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"239 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd" 240 240 ) 241 241 (vvPair 242 242 variable "p_logical" 243 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"243 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd" 244 244 ) 245 245 (vvPair … … 297 297 (vvPair 298 298 variable "time" 299 value "16: 35:54"299 value "16:57:01" 300 300 ) 301 301 (vvPair … … 317 317 (vvPair 318 318 variable "year" 319 value "201 0"319 value "2011" 320 320 ) 321 321 (vvPair 322 322 variable "yy" 323 value "1 0"323 value "11" 324 324 ) 325 325 ] … … 349 349 bg "0,0,32768" 350 350 ) 351 xt "99200,4000,108 900,5000"351 xt "99200,4000,108700,5000" 352 352 st " 353 353 by %user on %dd %month %year … … 1509 1509 n "RSRLOAD" 1510 1510 t "std_logic" 1511 o 2 61511 o 25 1512 1512 suid 56,0 1513 1513 i "'0'" … … 1545 1545 n "SRCLK" 1546 1546 t "std_logic" 1547 o 2 71547 o 26 1548 1548 suid 57,0 1549 1549 i "'0'" … … 1849 1849 ) 1850 1850 *46 (CptPort 1851 uid 10250,01852 ps "OnEdgeStrategy"1853 shape (Triangle1854 uid 10251,01855 ro 901856 va (VaSet1857 vasetType 11858 fg "0,65535,0"1859 )1860 xt "80000,137625,80750,138375"1861 )1862 tg (CPTG1863 uid 10252,01864 ps "CptPortTextPlaceStrategy"1865 stg "RightVerticalLayoutStrategy"1866 f (Text1867 uid 10253,01868 va (VaSet1869 )1870 xt "71700,137500,79000,138500"1871 st "DCM_status : (7:0)"1872 ju 21873 blo "79000,138300"1874 )1875 )1876 thePort (LogicalPort1877 m 11878 decl (Decl1879 n "DCM_status"1880 t "std_logic_vector"1881 b "(7 downto 0)"1882 preAdd 01883 posAdd 01884 o 181885 suid 75,01886 )1887 )1888 )1889 *47 (CptPort1890 1851 uid 10254,0 1891 1852 ps "OnEdgeStrategy" … … 1918 1879 n "LOCKED_extraOUT" 1919 1880 t "std_logic" 1920 o 1 91881 o 18 1921 1882 suid 70,0 1922 1883 ) 1923 1884 ) 1924 1885 ) 1925 *4 8(CptPort1886 *47 (CptPort 1926 1887 uid 10258,0 1927 1888 ps "OnEdgeStrategy" … … 1963 1924 ) 1964 1925 ) 1965 *4 9(CptPort1926 *48 (CptPort 1966 1927 uid 10262,0 1967 1928 ps "OnEdgeStrategy" … … 1994 1955 n "PS_DIR_IN" 1995 1956 t "std_logic" 1996 o 2 41957 o 23 1997 1958 suid 80,0 1998 1959 ) 1999 1960 ) 2000 1961 ) 2001 * 50(CptPort1962 *49 (CptPort 2002 1963 uid 10266,0 2003 1964 ps "OnEdgeStrategy" … … 2030 1991 n "PS_DO_IN" 2031 1992 t "std_logic" 2032 o 2 51993 o 24 2033 1994 suid 81,0 2034 1995 ) 2035 1996 ) 2036 1997 ) 2037 *5 1(CptPort1998 *50 (CptPort 2038 1999 uid 10270,0 2039 2000 ps "OnEdgeStrategy" … … 2066 2027 n "PSCLK_OUT" 2067 2028 t "std_logic" 2068 o 202029 o 19 2069 2030 suid 74,0 2070 2031 ) 2071 2032 ) 2072 2033 ) 2073 *5 2(CptPort2034 *51 (CptPort 2074 2035 uid 10274,0 2075 2036 ps "OnEdgeStrategy" … … 2102 2063 n "PSDONE_extraOUT" 2103 2064 t "std_logic" 2104 o 2 12065 o 20 2105 2066 suid 71,0 2106 2067 ) 2107 2068 ) 2108 2069 ) 2109 *5 3(CptPort2070 *52 (CptPort 2110 2071 uid 10278,0 2111 2072 ps "OnEdgeStrategy" … … 2138 2099 n "PSEN_OUT" 2139 2100 t "std_logic" 2140 o 2 22101 o 21 2141 2102 suid 73,0 2142 2103 ) 2143 2104 ) 2144 2105 ) 2145 *5 4(CptPort2106 *53 (CptPort 2146 2107 uid 10282,0 2147 2108 ps "OnEdgeStrategy" … … 2174 2135 n "PSINCDEC_OUT" 2175 2136 t "std_logic" 2176 o 2 32137 o 22 2177 2138 suid 72,0 2178 2139 ) 2179 2140 ) 2180 2141 ) 2181 *5 5(CptPort2142 *54 (CptPort 2182 2143 uid 10286,0 2183 2144 ps "OnEdgeStrategy" … … 2218 2179 ) 2219 2180 ) 2220 *5 6(CptPort2181 *55 (CptPort 2221 2182 uid 10290,0 2222 2183 ps "OnEdgeStrategy" … … 2258 2219 ) 2259 2220 ) 2260 *5 7(CptPort2221 *56 (CptPort 2261 2222 uid 10320,0 2262 2223 ps "OnEdgeStrategy" … … 2294 2255 ) 2295 2256 ) 2296 *5 8(CptPort2257 *57 (CptPort 2297 2258 uid 10324,0 2298 2259 ps "OnEdgeStrategy" … … 2330 2291 ) 2331 2292 ) 2332 *5 9(CptPort2293 *58 (CptPort 2333 2294 uid 10328,0 2334 2295 ps "OnEdgeStrategy" … … 2366 2327 ) 2367 2328 ) 2329 *59 (CptPort 2330 uid 12314,0 2331 ps "OnEdgeStrategy" 2332 shape (Triangle 2333 uid 12315,0 2334 ro 90 2335 va (VaSet 2336 vasetType 1 2337 fg "0,65535,0" 2338 ) 2339 xt "80000,139625,80750,140375" 2340 ) 2341 tg (CPTG 2342 uid 12316,0 2343 ps "CptPortTextPlaceStrategy" 2344 stg "RightVerticalLayoutStrategy" 2345 f (Text 2346 uid 12317,0 2347 va (VaSet 2348 ) 2349 xt "75300,139500,79000,140500" 2350 st "SRIN_out" 2351 ju 2 2352 blo "79000,140300" 2353 ) 2354 ) 2355 thePort (LogicalPort 2356 m 1 2357 decl (Decl 2358 n "SRIN_out" 2359 t "std_logic" 2360 o 27 2361 suid 85,0 2362 i "'0'" 2363 ) 2364 ) 2365 ) 2368 2366 ] 2369 2367 shape (Rectangle … … 2375 2373 lineWidth 2 2376 2374 ) 2377 xt "52000,66000,80000,14 0000"2375 xt "52000,66000,80000,141000" 2378 2376 ) 2379 2377 oxt "15000,-1000,43000,27000" … … 2445 2443 fg "49152,49152,49152" 2446 2444 ) 2447 xt "52250,13 8250,53750,139750"2445 xt "52250,139250,53750,140750" 2448 2446 iconName "BlockDiagram.png" 2449 2447 iconMaskName "BlockDiagram.msk" … … 2642 2640 preAdd 0 2643 2641 posAdd 0 2644 o 552642 o 69 2645 2643 suid 5,0 2646 2644 ) … … 2650 2648 font "Courier New,8,0" 2651 2649 ) 2652 xt "39000,57600,67500,58400" 2653 st "SIGNAL board_id : std_logic_vector(3 downto 0) 2654 " 2650 xt "39000,61600,67500,62400" 2651 st "SIGNAL board_id : std_logic_vector(3 downto 0)" 2655 2652 ) 2656 2653 ) … … 2661 2658 t "std_logic_vector" 2662 2659 b "(1 downto 0)" 2663 o 562660 o 70 2664 2661 suid 6,0 2665 2662 ) … … 2669 2666 font "Courier New,8,0" 2670 2667 ) 2671 xt "39000,58400,67500,59200" 2672 st "SIGNAL crate_id : std_logic_vector(1 downto 0) 2673 " 2668 xt "39000,62400,67500,63200" 2669 st "SIGNAL crate_id : std_logic_vector(1 downto 0)" 2674 2670 ) 2675 2671 ) … … 2985 2981 n "adc_data_array" 2986 2982 t "adc_data_array_type" 2987 o 542983 o 68 2988 2984 suid 29,0 2989 2985 ) … … 2993 2989 font "Courier New,8,0" 2994 2990 ) 2995 xt "39000,56800,63000,57600" 2996 st "SIGNAL adc_data_array : adc_data_array_type 2997 " 2991 xt "39000,60800,63000,61600" 2992 st "SIGNAL adc_data_array : adc_data_array_type" 2998 2993 ) 2999 2994 ) … … 3003 2998 n "RSRLOAD" 3004 2999 t "std_logic" 3005 o 3 53000 o 37 3006 3001 suid 57,0 3007 3002 i "'0'" … … 3012 3007 font "Courier New,8,0" 3013 3008 ) 3014 xt "39000,31000,68500,31800" 3015 st "RSRLOAD : std_logic := '0' 3016 " 3009 xt "39000,34200,68500,35000" 3010 st "RSRLOAD : std_logic := '0'" 3017 3011 ) 3018 3012 ) … … 3067 3061 n "SRCLK" 3068 3062 t "std_logic" 3069 o 523063 o 66 3070 3064 suid 58,0 3071 3065 i "'0'" … … 3076 3070 font "Courier New,8,0" 3077 3071 ) 3078 xt "39000,55200,72000,56000" 3079 st "SIGNAL SRCLK : std_logic := '0' 3080 " 3072 xt "39000,59200,72000,60000" 3073 st "SIGNAL SRCLK : std_logic := '0'" 3081 3074 ) 3082 3075 ) … … 3087 3080 t "std_logic_vector" 3088 3081 b "(3 DOWNTO 0)" 3089 o 593082 o 74 3090 3083 suid 65,0 3091 3084 ) … … 3095 3088 font "Courier New,8,0" 3096 3089 ) 3097 xt "39000,61600,67500,62400" 3098 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0) 3099 " 3090 xt "39000,65600,67500,66400" 3091 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" 3100 3092 ) 3101 3093 ) … … 3105 3097 n "DAC_CS" 3106 3098 t "std_logic" 3107 o 2 13099 o 22 3108 3100 suid 66,0 3109 3101 ) … … 3113 3105 font "Courier New,8,0" 3114 3106 ) 3115 xt "39000,19800,54000,20600" 3116 st "DAC_CS : std_logic 3117 " 3107 xt "39000,22200,54000,23000" 3108 st "DAC_CS : std_logic" 3118 3109 ) 3119 3110 ) … … 3178 3169 font "Courier New,8,0" 3179 3170 ) 3180 xt "39000,13400,54000,14200" 3181 st "X_50M : STD_LOGIC 3182 " 3171 xt "39000,15800,54000,16600" 3172 st "X_50M : STD_LOGIC" 3183 3173 ) 3184 3174 ) … … 3196 3186 font "Courier New,8,0" 3197 3187 ) 3198 xt "39000,11800,54000,12600" 3199 st "TRG : STD_LOGIC 3200 " 3188 xt "39000,14200,54000,15000" 3189 st "TRG : STD_LOGIC" 3201 3190 ) 3202 3191 ) … … 3298 3287 t "std_logic_vector" 3299 3288 b "(3 downto 0)" 3300 o 1 63289 o 17 3301 3290 suid 71,0 3302 3291 ) … … 3306 3295 font "Courier New,8,0" 3307 3296 ) 3308 xt "39000,15800,64000,16600" 3309 st "A_CLK : std_logic_vector(3 downto 0) 3310 " 3297 xt "39000,18200,64000,19000" 3298 st "A_CLK : std_logic_vector(3 downto 0)" 3311 3299 ) 3312 3300 ) … … 3316 3304 n "CLK_25_PS" 3317 3305 t "std_logic" 3318 o 5 03306 o 55 3319 3307 suid 72,0 3320 3308 ) … … 3324 3312 font "Courier New,8,0" 3325 3313 ) 3326 xt "39000,46400,57500,47200" 3327 st "SIGNAL CLK_25_PS : std_logic 3328 " 3314 xt "39000,50400,57500,51200" 3315 st "SIGNAL CLK_25_PS : std_logic" 3329 3316 ) 3330 3317 ) … … 3381 3368 preAdd 0 3382 3369 posAdd 0 3383 o 3 03370 o 31 3384 3371 suid 73,0 3385 3372 ) … … 3389 3376 font "Courier New,8,0" 3390 3377 ) 3391 xt "39000,27000,54000,27800" 3392 st "OE_ADC : STD_LOGIC 3393 " 3378 xt "39000,29400,54000,30200" 3379 st "OE_ADC : STD_LOGIC" 3394 3380 ) 3395 3381 ) … … 3454 3440 ) 3455 3441 xt "39000,7000,64000,7800" 3456 st "A_OTR : std_logic_vector(3 DOWNTO 0) 3457 " 3442 st "A_OTR : std_logic_vector(3 DOWNTO 0)" 3458 3443 ) 3459 3444 ) … … 3744 3729 ) 3745 3730 xt "39000,3800,64500,4600" 3746 st "A0_D : std_logic_vector(11 DOWNTO 0) 3747 " 3731 st "A0_D : std_logic_vector(11 DOWNTO 0)" 3748 3732 ) 3749 3733 ) … … 3763 3747 ) 3764 3748 xt "39000,4600,64500,5400" 3765 st "A1_D : std_logic_vector(11 DOWNTO 0) 3766 " 3749 st "A1_D : std_logic_vector(11 DOWNTO 0)" 3767 3750 ) 3768 3751 ) … … 3782 3765 ) 3783 3766 xt "39000,5400,64500,6200" 3784 st "A2_D : std_logic_vector(11 DOWNTO 0) 3785 " 3767 st "A2_D : std_logic_vector(11 DOWNTO 0)" 3786 3768 ) 3787 3769 ) … … 3801 3783 ) 3802 3784 xt "39000,6200,64500,7000" 3803 st "A3_D : std_logic_vector(11 DOWNTO 0) 3804 " 3785 st "A3_D : std_logic_vector(11 DOWNTO 0)" 3805 3786 ) 3806 3787 ) … … 3901 3882 n "D0_SRCLK" 3902 3883 t "STD_LOGIC" 3903 o 1 73884 o 18 3904 3885 suid 87,0 3905 3886 ) … … 3909 3890 font "Courier New,8,0" 3910 3891 ) 3911 xt "39000,16600,54000,17400" 3912 st "D0_SRCLK : STD_LOGIC 3913 " 3892 xt "39000,19000,54000,19800" 3893 st "D0_SRCLK : STD_LOGIC" 3914 3894 ) 3915 3895 ) … … 3919 3899 n "D1_SRCLK" 3920 3900 t "STD_LOGIC" 3921 o 1 83901 o 19 3922 3902 suid 88,0 3923 3903 ) … … 3927 3907 font "Courier New,8,0" 3928 3908 ) 3929 xt "39000,17400,54000,18200" 3930 st "D1_SRCLK : STD_LOGIC 3931 " 3909 xt "39000,19800,54000,20600" 3910 st "D1_SRCLK : STD_LOGIC" 3932 3911 ) 3933 3912 ) … … 3937 3916 n "D2_SRCLK" 3938 3917 t "STD_LOGIC" 3939 o 193918 o 20 3940 3919 suid 89,0 3941 3920 ) … … 3945 3924 font "Courier New,8,0" 3946 3925 ) 3947 xt "39000,18200,54000,19000" 3948 st "D2_SRCLK : STD_LOGIC 3949 " 3926 xt "39000,20600,54000,21400" 3927 st "D2_SRCLK : STD_LOGIC" 3950 3928 ) 3951 3929 ) … … 3955 3933 n "D3_SRCLK" 3956 3934 t "STD_LOGIC" 3957 o 2 03935 o 21 3958 3936 suid 90,0 3959 3937 ) … … 3963 3941 font "Courier New,8,0" 3964 3942 ) 3965 xt "39000,19000,54000,19800" 3966 st "D3_SRCLK : STD_LOGIC 3967 " 3943 xt "39000,21400,54000,22200" 3944 st "D3_SRCLK : STD_LOGIC" 3968 3945 ) 3969 3946 ) … … 4162 4139 ) 4163 4140 xt "39000,7800,54000,8600" 4164 st "D0_SROUT : std_logic 4165 " 4141 st "D0_SROUT : std_logic" 4166 4142 ) 4167 4143 ) … … 4180 4156 ) 4181 4157 xt "39000,8600,54000,9400" 4182 st "D1_SROUT : std_logic 4183 " 4158 st "D1_SROUT : std_logic" 4184 4159 ) 4185 4160 ) … … 4198 4173 ) 4199 4174 xt "39000,9400,54000,10200" 4200 st "D2_SROUT : std_logic 4201 " 4175 st "D2_SROUT : std_logic" 4202 4176 ) 4203 4177 ) … … 4216 4190 ) 4217 4191 xt "39000,10200,54000,11000" 4218 st "D3_SROUT : std_logic 4219 " 4192 st "D3_SROUT : std_logic" 4220 4193 ) 4221 4194 ) … … 4271 4244 t "std_logic_vector" 4272 4245 b "(3 DOWNTO 0)" 4273 o 2 44246 o 25 4274 4247 suid 95,0 4275 4248 i "(others => '0')" … … 4280 4253 font "Courier New,8,0" 4281 4254 ) 4282 xt "39000,22200,74500,23000" 4283 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0') 4284 " 4255 xt "39000,24600,74500,25400" 4256 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0')" 4285 4257 ) 4286 4258 ) … … 4335 4307 n "DWRITE" 4336 4308 t "std_logic" 4337 o 2 34309 o 24 4338 4310 suid 96,0 4339 4311 i "'0'" … … 4344 4316 font "Courier New,8,0" 4345 4317 ) 4346 xt "39000,21400,68500,22200" 4347 st "DWRITE : std_logic := '0' 4348 " 4318 xt "39000,23800,68500,24600" 4319 st "DWRITE : std_logic := '0'" 4349 4320 ) 4350 4321 ) … … 4665 4636 n "T0_CS" 4666 4637 t "std_logic" 4667 o 384638 o 40 4668 4639 suid 101,0 4669 4640 ) … … 4673 4644 font "Courier New,8,0" 4674 4645 ) 4675 xt "39000,33400,54000,34200" 4676 st "T0_CS : std_logic 4677 " 4646 xt "39000,37400,54000,38200" 4647 st "T0_CS : std_logic" 4678 4648 ) 4679 4649 ) … … 4683 4653 n "T1_CS" 4684 4654 t "std_logic" 4685 o 394655 o 41 4686 4656 suid 102,0 4687 4657 ) … … 4691 4661 font "Courier New,8,0" 4692 4662 ) 4693 xt "39000,34200,54000,35000" 4694 st "T1_CS : std_logic 4695 " 4663 xt "39000,38200,54000,39000" 4664 st "T1_CS : std_logic" 4696 4665 ) 4697 4666 ) … … 4701 4670 n "T2_CS" 4702 4671 t "std_logic" 4703 o 4 04672 o 42 4704 4673 suid 103,0 4705 4674 ) … … 4709 4678 font "Courier New,8,0" 4710 4679 ) 4711 xt "39000,35000,54000,35800" 4712 st "T2_CS : std_logic 4713 " 4680 xt "39000,39000,54000,39800" 4681 st "T2_CS : std_logic" 4714 4682 ) 4715 4683 ) … … 4719 4687 n "T3_CS" 4720 4688 t "std_logic" 4721 o 4 14689 o 43 4722 4690 suid 104,0 4723 4691 ) … … 4727 4695 font "Courier New,8,0" 4728 4696 ) 4729 xt "39000,35800,54000,36600" 4730 st "T3_CS : std_logic 4731 " 4697 xt "39000,39800,54000,40600" 4698 st "T3_CS : std_logic" 4732 4699 ) 4733 4700 ) … … 4781 4748 n "S_CLK" 4782 4749 t "std_logic" 4783 o 3 74750 o 39 4784 4751 suid 105,0 4785 4752 ) … … 4789 4756 font "Courier New,8,0" 4790 4757 ) 4791 xt "39000,32600,54000,33400" 4792 st "S_CLK : std_logic 4793 " 4758 xt "39000,36600,54000,37400" 4759 st "S_CLK : std_logic" 4794 4760 ) 4795 4761 ) … … 4800 4766 t "std_logic_vector" 4801 4767 b "(9 DOWNTO 0)" 4802 o 4 34768 o 45 4803 4769 suid 106,0 4804 4770 ) … … 4808 4774 font "Courier New,8,0" 4809 4775 ) 4810 xt "39000,37400,64000,38200" 4811 st "W_A : std_logic_vector(9 DOWNTO 0) 4812 " 4776 xt "39000,41400,64000,42200" 4777 st "W_A : std_logic_vector(9 DOWNTO 0)" 4813 4778 ) 4814 4779 ) … … 4819 4784 t "std_logic_vector" 4820 4785 b "(15 DOWNTO 0)" 4821 o 494786 o 51 4822 4787 suid 107,0 4823 4788 ) … … 4827 4792 font "Courier New,8,0" 4828 4793 ) 4829 xt "39000,42200,64500,43000" 4830 st "W_D : std_logic_vector(15 DOWNTO 0) 4831 " 4794 xt "39000,46200,64500,47000" 4795 st "W_D : std_logic_vector(15 DOWNTO 0)" 4832 4796 ) 4833 4797 ) … … 4837 4801 n "W_RES" 4838 4802 t "std_logic" 4839 o 4 64803 o 48 4840 4804 suid 108,0 4841 4805 i "'1'" … … 4846 4810 font "Courier New,8,0" 4847 4811 ) 4848 xt "39000,39800,68500,40600" 4849 st "W_RES : std_logic := '1' 4850 " 4812 xt "39000,43800,68500,44600" 4813 st "W_RES : std_logic := '1'" 4851 4814 ) 4852 4815 ) … … 4856 4819 n "W_RD" 4857 4820 t "std_logic" 4858 o 4 54821 o 47 4859 4822 suid 109,0 4860 4823 i "'1'" … … 4865 4828 font "Courier New,8,0" 4866 4829 ) 4867 xt "39000,39000,68500,39800" 4868 st "W_RD : std_logic := '1' 4869 " 4830 xt "39000,43000,68500,43800" 4831 st "W_RD : std_logic := '1'" 4870 4832 ) 4871 4833 ) … … 4875 4837 n "W_WR" 4876 4838 t "std_logic" 4877 o 4 74839 o 49 4878 4840 suid 110,0 4879 4841 i "'1'" … … 4884 4846 font "Courier New,8,0" 4885 4847 ) 4886 xt "39000,40600,68500,41400" 4887 st "W_WR : std_logic := '1' 4888 " 4848 xt "39000,44600,68500,45400" 4849 st "W_WR : std_logic := '1'" 4889 4850 ) 4890 4851 ) … … 4902 4863 font "Courier New,8,0" 4903 4864 ) 4904 xt "39000,12600,54000,13400" 4905 st "W_INT : std_logic 4906 " 4865 xt "39000,15000,54000,15800" 4866 st "W_INT : std_logic" 4907 4867 ) 4908 4868 ) … … 4912 4872 n "W_CS" 4913 4873 t "std_logic" 4914 o 4 44874 o 46 4915 4875 suid 112,0 4916 4876 i "'1'" … … 4921 4881 font "Courier New,8,0" 4922 4882 ) 4923 xt "39000,38200,68500,39000" 4924 st "W_CS : std_logic := '1' 4925 " 4883 xt "39000,42200,68500,43000" 4884 st "W_CS : std_logic := '1'" 4926 4885 ) 4927 4886 ) … … 4973 4932 n "MOSI" 4974 4933 t "std_logic" 4975 o 294934 o 30 4976 4935 suid 113,0 4977 4936 i "'0'" … … 4982 4941 font "Courier New,8,0" 4983 4942 ) 4984 xt "39000,26200,68500,27000" 4985 st "MOSI : std_logic := '0' 4986 " 4943 xt "39000,28600,68500,29400" 4944 st "MOSI : std_logic := '0'" 4987 4945 ) 4988 4946 ) … … 5038 4996 preAdd 0 5039 4997 posAdd 0 5040 o 484998 o 50 5041 4999 suid 114,0 5042 5000 ) … … 5046 5004 font "Courier New,8,0" 5047 5005 ) 5048 xt "39000,41400,54000,42200" 5049 st "MISO : std_logic 5050 " 5006 xt "39000,45400,54000,46200" 5007 st "MISO : std_logic" 5051 5008 ) 5052 5009 ) … … 5067 5024 lineWidth 2 5068 5025 ) 5069 xt "82000,10 2000,100000,118000"5026 xt "82000,106000,99000,118000" 5070 5027 ) 5071 5028 oxt "0,0,18000,5000" … … 5074 5031 va (VaSet 5075 5032 ) 5076 xt "82200,10 2200,98600,118200"5033 xt "82200,106200,98600,118200" 5077 5034 st " 5078 5035 -- MISC 6 5079 5036 TRG_V <= '0'; 5080 RS485_C_RE <= ' 1';5037 RS485_C_RE <= '0'; 5081 5038 RS485_C_DE <= '0'; 5082 RS485_E_RE <= '1'; 5039 RS485_C_DO <= RS485_C_DI; 5040 5041 RS485_E_RE <= '0'; 5083 5042 RS485_E_DE <= '0'; 5043 --RS485_E_DO <= RS485_E_DI; 5084 5044 5085 5045 -- DENABLE <= '0'; -- domino wave stopped … … 5099 5059 tm "HdlTextMgr" 5100 5060 wrapOption 3 5101 visibleHeight 1 60005102 visibleWidth 1 80005061 visibleHeight 12000 5062 visibleWidth 17000 5103 5063 ) 5104 5064 ) … … 5558 5518 n "TRG_V" 5559 5519 t "std_logic" 5560 o 4 25520 o 44 5561 5521 suid 126,0 5562 5522 ) … … 5566 5526 font "Courier New,8,0" 5567 5527 ) 5568 xt "39000,36600,54000,37400" 5569 st "TRG_V : std_logic 5570 " 5528 xt "39000,40600,54000,41400" 5529 st "TRG_V : std_logic" 5571 5530 ) 5572 5531 ) … … 5576 5535 n "RS485_C_RE" 5577 5536 t "std_logic" 5578 o 3 25537 o 34 5579 5538 suid 127,0 5580 5539 ) … … 5584 5543 font "Courier New,8,0" 5585 5544 ) 5586 xt "39000,28600,54000,29400" 5587 st "RS485_C_RE : std_logic 5588 " 5545 xt "39000,31800,54000,32600" 5546 st "RS485_C_RE : std_logic" 5589 5547 ) 5590 5548 ) … … 5594 5552 n "RS485_C_DE" 5595 5553 t "std_logic" 5596 o 3 15554 o 32 5597 5555 suid 128,0 5598 5556 ) … … 5602 5560 font "Courier New,8,0" 5603 5561 ) 5604 xt "39000,27800,54000,28600" 5605 st "RS485_C_DE : std_logic 5606 " 5562 xt "39000,30200,54000,31000" 5563 st "RS485_C_DE : std_logic" 5607 5564 ) 5608 5565 ) … … 5612 5569 n "RS485_E_RE" 5613 5570 t "std_logic" 5614 o 3 45571 o 36 5615 5572 suid 129,0 5616 5573 ) … … 5620 5577 font "Courier New,8,0" 5621 5578 ) 5622 xt "39000,30200,54000,31000" 5623 st "RS485_E_RE : std_logic 5624 " 5579 xt "39000,33400,54000,34200" 5580 st "RS485_E_RE : std_logic" 5625 5581 ) 5626 5582 ) … … 5630 5586 n "RS485_E_DE" 5631 5587 t "std_logic" 5632 o 3 35588 o 35 5633 5589 suid 130,0 5634 5590 ) … … 5638 5594 font "Courier New,8,0" 5639 5595 ) 5640 xt "39000,29400,54000,30200" 5641 st "RS485_E_DE : std_logic 5642 " 5596 xt "39000,32600,54000,33400" 5597 st "RS485_E_DE : std_logic" 5643 5598 ) 5644 5599 ) … … 5648 5603 n "DENABLE" 5649 5604 t "std_logic" 5650 o 2 25605 o 23 5651 5606 suid 131,0 5652 5607 i "'0'" … … 5657 5612 font "Courier New,8,0" 5658 5613 ) 5659 xt "39000,20600,68500,21400" 5660 st "DENABLE : std_logic := '0' 5661 " 5614 xt "39000,23000,68500,23800" 5615 st "DENABLE : std_logic := '0'" 5662 5616 ) 5663 5617 ) … … 5667 5621 n "SRIN" 5668 5622 t "std_logic" 5669 o 3 65623 o 38 5670 5624 suid 132,0 5671 5625 ) … … 5675 5629 font "Courier New,8,0" 5676 5630 ) 5677 xt "39000,31800,54000,32600" 5678 st "SRIN : std_logic 5679 " 5631 xt "39000,35000,54000,35800" 5632 st "SRIN : std_logic" 5680 5633 ) 5681 5634 ) … … 5685 5638 n "EE_CS" 5686 5639 t "std_logic" 5687 o 2 75640 o 28 5688 5641 suid 133,0 5689 5642 ) … … 5693 5646 font "Courier New,8,0" 5694 5647 ) 5695 xt "39000,24600,54000,25400" 5696 st "EE_CS : std_logic 5697 " 5648 xt "39000,27000,54000,27800" 5649 st "EE_CS : std_logic" 5698 5650 ) 5699 5651 ) … … 5704 5656 t "std_logic_vector" 5705 5657 b "( 2 DOWNTO 0 )" 5706 o 2 85658 o 29 5707 5659 suid 134,0 5708 5660 i "(others => '1')" … … 5713 5665 font "Courier New,8,0" 5714 5666 ) 5715 xt "39000,25400,74500,26200" 5716 st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1') 5717 " 5667 xt "39000,27800,74500,28600" 5668 st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')" 5718 5669 ) 5719 5670 ) … … 5948 5899 t "std_logic_vector" 5949 5900 b "(7 DOWNTO 0)" 5950 o 2 55901 o 26 5951 5902 suid 141,0 5952 5903 i "(OTHERS => '0')" … … 5957 5908 font "Courier New,8,0" 5958 5909 ) 5959 xt "39000,23000,74500,23800" 5960 st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 5961 " 5910 xt "39000,25400,74500,26200" 5911 st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 5962 5912 ) 5963 5913 ) … … 6022 5972 ) 6023 5973 xt "39000,11000,64000,11800" 6024 st "D_PLLLCK : std_logic_vector(3 DOWNTO 0) 6025 " 5974 st "D_PLLLCK : std_logic_vector(3 DOWNTO 0)" 6026 5975 ) 6027 5976 ) … … 6076 6025 t "std_logic_vector" 6077 6026 b "(3 DOWNTO 0)" 6078 o 2 66027 o 27 6079 6028 suid 154,0 6080 6029 i "(others => '0')" … … 6085 6034 font "Courier New,8,0" 6086 6035 ) 6087 xt "39000,23800,74500,24600" 6088 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0') 6089 " 6036 xt "39000,26200,74500,27000" 6037 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0')" 6090 6038 ) 6091 6039 ) … … 6316 6264 t "std_logic_vector" 6317 6265 b "(7 DOWNTO 0)" 6318 o 1 56266 o 16 6319 6267 suid 155,0 6320 6268 i "(OTHERS => '0')" … … 6325 6273 font "Courier New,8,0" 6326 6274 ) 6327 xt "39000,15000,74500,15800" 6328 st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 6329 " 6275 xt "39000,17400,74500,18200" 6276 st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 6330 6277 ) 6331 6278 ) … … 6335 6282 n "dummy" 6336 6283 t "std_logic" 6337 o 586284 o 72 6338 6285 suid 157,0 6339 6286 ) … … 6343 6290 font "Courier New,8,0" 6344 6291 ) 6345 xt "39000,60000,57500,60800" 6346 st "SIGNAL dummy : std_logic 6347 " 6292 xt "39000,64000,57500,64800" 6293 st "SIGNAL dummy : std_logic" 6348 6294 ) 6349 6295 ) … … 6408 6354 n "s" 6409 6355 t "std_logic" 6410 o 586356 o 72 6411 6357 suid 1,0 6412 6358 ) … … 6473 6419 n "t" 6474 6420 t "std_logic" 6475 o 2 16421 o 22 6476 6422 suid 2,0 6477 6423 ) … … 6671 6617 t "std_logic_vector" 6672 6618 b "(3 downto 0)" 6673 o 576619 o 71 6674 6620 suid 159,0 6675 6621 i "(others => '0')" … … 6680 6626 font "Courier New,8,0" 6681 6627 ) 6682 xt "39000,59200,78000,60000" 6683 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6684 " 6628 xt "39000,63200,78000,64000" 6629 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 6685 6630 ) 6686 6631 ) … … 6690 6635 n "CLK_50" 6691 6636 t "std_logic" 6692 o 5 16637 o 57 6693 6638 suid 163,0 6694 6639 ) … … 6698 6643 font "Courier New,8,0" 6699 6644 ) 6700 xt "39000,48000,57500,48800" 6701 st "SIGNAL CLK_50 : std_logic 6702 " 6645 xt "39000,52000,57500,52800" 6646 st "SIGNAL CLK_50 : std_logic" 6703 6647 ) 6704 6648 ) … … 6761 6705 n "dout" 6762 6706 t "std_logic" 6763 o 5 06707 o 55 6764 6708 suid 1,0 6765 6709 ) … … 6815 6759 n "din0" 6816 6760 t "std_logic" 6817 o 596761 o 67 6818 6762 suid 2,0 6819 6763 i "'0'" … … 6870 6814 n "din1" 6871 6815 t "std_logic" 6872 o 5 86816 o 56 6873 6817 suid 3,0 6874 6818 ) … … 7075 7019 n "CLK_25_PS1" 7076 7020 t "std_logic" 7077 o 5 87021 o 56 7078 7022 suid 164,0 7079 7023 ) … … 7083 7027 font "Courier New,8,0" 7084 7028 ) 7085 xt "39000,47200,57500,48000" 7086 st "SIGNAL CLK_25_PS1 : std_logic 7087 " 7029 xt "39000,51200,57500,52000" 7030 st "SIGNAL CLK_25_PS1 : std_logic" 7088 7031 ) 7089 7032 ) … … 7093 7036 n "adc_clk_en" 7094 7037 t "std_logic" 7095 o 597038 o 67 7096 7039 suid 165,0 7097 7040 i "'0'" … … 7102 7045 font "Courier New,8,0" 7103 7046 ) 7104 xt "39000,56000,72000,56800" 7105 st "SIGNAL adc_clk_en : std_logic := '0' 7106 " 7047 xt "39000,60000,72000,60800" 7048 st "SIGNAL adc_clk_en : std_logic := '0'" 7107 7049 ) 7108 7050 ) … … 7157 7099 t "std_logic_vector" 7158 7100 b "(7 DOWNTO 0)" 7159 o 607101 o 15 7160 7102 suid 166,0 7161 7103 i "(others => '0')" … … 7166 7108 font "Courier New,8,0" 7167 7109 ) 7168 xt "39000,14200,74500,15000" 7169 st "A0_T : std_logic_vector(7 DOWNTO 0) := (others => '0') 7170 " 7110 xt "39000,16600,74500,17400" 7111 st "A0_T : std_logic_vector(7 DOWNTO 0) := (others => '0')" 7171 7112 ) 7172 7113 ) … … 7281 7222 n "CLK50_OUT" 7282 7223 t "std_logic" 7283 o 617224 o 54 7284 7225 suid 184,0 7285 7226 ) … … 7289 7230 font "Courier New,8,0" 7290 7231 ) 7291 xt "39000,45600,57500,46400" 7292 st "SIGNAL CLK50_OUT : std_logic 7293 " 7232 xt "39000,49600,57500,50400" 7233 st "SIGNAL CLK50_OUT : std_logic" 7294 7234 ) 7295 7235 ) … … 7299 7239 n "CLK25_OUT" 7300 7240 t "std_logic" 7301 o 627241 o 52 7302 7242 suid 185,0 7303 7243 ) … … 7307 7247 font "Courier New,8,0" 7308 7248 ) 7309 xt "39000,44000,57500,44800" 7310 st "SIGNAL CLK25_OUT : std_logic 7311 " 7249 xt "39000,48000,57500,48800" 7250 st "SIGNAL CLK25_OUT : std_logic" 7312 7251 ) 7313 7252 ) … … 7317 7256 n "CLK25_PSOUT" 7318 7257 t "std_logic" 7319 o 637258 o 53 7320 7259 suid 186,0 7321 7260 ) … … 7325 7264 font "Courier New,8,0" 7326 7265 ) 7327 xt "39000,44800,57500,45600" 7328 st "SIGNAL CLK25_PSOUT : std_logic 7329 " 7266 xt "39000,48800,57500,49600" 7267 st "SIGNAL CLK25_PSOUT : std_logic" 7330 7268 ) 7331 7269 ) … … 7343 7281 font "Courier New,8,0" 7344 7282 ) 7345 xt "39000,53600,57500,54400" 7346 st "SIGNAL PS_DIR_IN : std_logic 7347 " 7283 xt "39000,57600,57500,58400" 7284 st "SIGNAL PS_DIR_IN : std_logic" 7348 7285 ) 7349 7286 ) … … 7361 7298 font "Courier New,8,0" 7362 7299 ) 7363 xt "39000,54400,57500,55200" 7364 st "SIGNAL PS_DO_IN : std_logic 7365 " 7300 xt "39000,58400,57500,59200" 7301 st "SIGNAL PS_DO_IN : std_logic" 7366 7302 ) 7367 7303 ) … … 7371 7307 n "PSEN_OUT" 7372 7308 t "std_logic" 7373 o 6 67309 o 62 7374 7310 suid 189,0 7375 7311 ) … … 7379 7315 font "Courier New,8,0" 7380 7316 ) 7381 xt "39000,52000,57500,52800" 7382 st "SIGNAL PSEN_OUT : std_logic 7383 " 7317 xt "39000,56000,57500,56800" 7318 st "SIGNAL PSEN_OUT : std_logic" 7384 7319 ) 7385 7320 ) … … 7389 7324 n "PSINCDEC_OUT" 7390 7325 t "std_logic" 7391 o 6 77326 o 63 7392 7327 suid 190,0 7393 7328 ) … … 7397 7332 font "Courier New,8,0" 7398 7333 ) 7399 xt "39000,52800,57500,53600" 7400 st "SIGNAL PSINCDEC_OUT : std_logic 7401 " 7334 xt "39000,56800,57500,57600" 7335 st "SIGNAL PSINCDEC_OUT : std_logic" 7402 7336 ) 7403 7337 ) … … 7409 7343 preAdd 0 7410 7344 posAdd 0 7411 o 687345 o 58 7412 7346 suid 191,0 7413 7347 ) … … 7417 7351 font "Courier New,8,0" 7418 7352 ) 7419 xt "39000,48800,57500,49600" 7420 st "SIGNAL DCM_locked : std_logic 7421 " 7353 xt "39000,52800,57500,53600" 7354 st "SIGNAL DCM_locked : std_logic" 7422 7355 ) 7423 7356 ) … … 7429 7362 preAdd 0 7430 7363 posAdd 0 7431 o 697364 o 73 7432 7365 suid 192,0 7433 7366 i "'0'" … … 7438 7371 font "Courier New,8,0" 7439 7372 ) 7440 xt "39000,60800,72000,61600" 7441 st "SIGNAL ready : std_logic := '0' 7442 " 7373 xt "39000,64800,72000,65600" 7374 st "SIGNAL ready : std_logic := '0'" 7443 7375 ) 7444 7376 ) … … 7451 7383 preAdd 0 7452 7384 posAdd 0 7453 o 7 07385 o 75 7454 7386 suid 193,0 7455 7387 i "'0'" … … 7460 7392 font "Courier New,8,0" 7461 7393 ) 7462 xt "39000,6 2400,72000,64000"7394 xt "39000,66400,72000,68000" 7463 7395 st "-- status: 7464 SIGNAL shifting : std_logic := '0' 7465 " 7396 SIGNAL shifting : std_logic := '0'" 7466 7397 ) 7467 7398 ) … … 7471 7402 n "PSDONE_extraOUT" 7472 7403 t "std_logic" 7473 o 717404 o 61 7474 7405 suid 194,0 7475 7406 ) … … 7479 7410 font "Courier New,8,0" 7480 7411 ) 7481 xt "39000,51200,57500,52000" 7482 st "SIGNAL PSDONE_extraOUT : std_logic 7483 " 7412 xt "39000,55200,57500,56000" 7413 st "SIGNAL PSDONE_extraOUT : std_logic" 7484 7414 ) 7485 7415 ) … … 7489 7419 n "PSCLK_OUT" 7490 7420 t "std_logic" 7491 o 727421 o 60 7492 7422 suid 195,0 7493 7423 ) … … 7497 7427 font "Courier New,8,0" 7498 7428 ) 7499 xt "39000,50400,57500,51200" 7500 st "SIGNAL PSCLK_OUT : std_logic 7501 " 7429 xt "39000,54400,57500,55200" 7430 st "SIGNAL PSCLK_OUT : std_logic" 7502 7431 ) 7503 7432 ) … … 7507 7436 n "LOCKED_extraOUT" 7508 7437 t "std_logic" 7509 o 737438 o 59 7510 7439 suid 196,0 7511 7440 ) … … 7515 7444 font "Courier New,8,0" 7516 7445 ) 7517 xt "39000,49600,57500,50400" 7518 st "SIGNAL LOCKED_extraOUT : std_logic 7519 " 7520 ) 7521 ) 7522 *252 (Wire 7446 xt "39000,53600,57500,54400" 7447 st "SIGNAL LOCKED_extraOUT : std_logic" 7448 ) 7449 ) 7450 *252 (PortIoIn 7451 uid 11090,0 7452 shape (CompositeShape 7453 uid 11091,0 7454 va (VaSet 7455 vasetType 1 7456 fg "0,0,32768" 7457 ) 7458 optionalChildren [ 7459 (Pentagon 7460 uid 11092,0 7461 sl 0 7462 ro 270 7463 xt "94000,102625,95500,103375" 7464 ) 7465 (Line 7466 uid 11093,0 7467 sl 0 7468 ro 270 7469 xt "95500,103000,96000,103000" 7470 pts [ 7471 "95500,103000" 7472 "96000,103000" 7473 ] 7474 ) 7475 ] 7476 ) 7477 stc 0 7478 sf 1 7479 tg (WTG 7480 uid 11094,0 7481 ps "PortIoTextPlaceStrategy" 7482 stg "STSignalDisplayStrategy" 7483 f (Text 7484 uid 11095,0 7485 va (VaSet 7486 ) 7487 xt "87700,102500,93000,103500" 7488 st "RS485_C_DI" 7489 ju 2 7490 blo "93000,103300" 7491 tm "WireNameMgr" 7492 ) 7493 ) 7494 ) 7495 *253 (Net 7496 uid 11102,0 7497 decl (Decl 7498 n "RS485_C_DI" 7499 t "std_logic" 7500 o 74 7501 suid 197,0 7502 ) 7503 declText (MLText 7504 uid 11103,0 7505 va (VaSet 7506 font "Courier New,8,0" 7507 ) 7508 xt "39000,11800,54000,12600" 7509 st "RS485_C_DI : std_logic" 7510 ) 7511 ) 7512 *254 (PortIoOut 7513 uid 11104,0 7514 shape (CompositeShape 7515 uid 11105,0 7516 va (VaSet 7517 vasetType 1 7518 fg "0,0,32768" 7519 ) 7520 optionalChildren [ 7521 (Pentagon 7522 uid 11106,0 7523 sl 0 7524 ro 270 7525 xt "111500,111625,113000,112375" 7526 ) 7527 (Line 7528 uid 11107,0 7529 sl 0 7530 ro 270 7531 xt "111000,112000,111500,112000" 7532 pts [ 7533 "111000,112000" 7534 "111500,112000" 7535 ] 7536 ) 7537 ] 7538 ) 7539 stc 0 7540 sf 1 7541 tg (WTG 7542 uid 11108,0 7543 ps "PortIoTextPlaceStrategy" 7544 stg "STSignalDisplayStrategy" 7545 f (Text 7546 uid 11109,0 7547 va (VaSet 7548 ) 7549 xt "114000,111500,119700,112500" 7550 st "RS485_C_DO" 7551 blo "114000,112300" 7552 tm "WireNameMgr" 7553 ) 7554 ) 7555 ) 7556 *255 (Net 7557 uid 11116,0 7558 decl (Decl 7559 n "RS485_C_DO" 7560 t "std_logic" 7561 o 75 7562 suid 198,0 7563 ) 7564 declText (MLText 7565 uid 11117,0 7566 va (VaSet 7567 font "Courier New,8,0" 7568 ) 7569 xt "39000,31000,54000,31800" 7570 st "RS485_C_DO : std_logic" 7571 ) 7572 ) 7573 *256 (PortIoIn 7574 uid 11508,0 7575 shape (CompositeShape 7576 uid 11509,0 7577 va (VaSet 7578 vasetType 1 7579 fg "0,0,32768" 7580 ) 7581 optionalChildren [ 7582 (Pentagon 7583 uid 11510,0 7584 sl 0 7585 ro 270 7586 xt "121000,115625,122500,116375" 7587 ) 7588 (Line 7589 uid 11511,0 7590 sl 0 7591 ro 270 7592 xt "122500,116000,123000,116000" 7593 pts [ 7594 "122500,116000" 7595 "123000,116000" 7596 ] 7597 ) 7598 ] 7599 ) 7600 stc 0 7601 sf 1 7602 tg (WTG 7603 uid 11512,0 7604 ps "PortIoTextPlaceStrategy" 7605 stg "STSignalDisplayStrategy" 7606 f (Text 7607 uid 11513,0 7608 va (VaSet 7609 ) 7610 xt "114800,115500,120000,116500" 7611 st "RS485_E_DI" 7612 ju 2 7613 blo "120000,116300" 7614 tm "WireNameMgr" 7615 ) 7616 ) 7617 ) 7618 *257 (Net 7619 uid 11520,0 7620 decl (Decl 7621 n "RS485_E_DI" 7622 t "std_logic" 7623 o 76 7624 suid 200,0 7625 ) 7626 declText (MLText 7627 uid 11521,0 7628 va (VaSet 7629 font "Courier New,8,0" 7630 ) 7631 xt "39000,12600,54000,13400" 7632 st "RS485_E_DI : std_logic" 7633 ) 7634 ) 7635 *258 (Net 7636 uid 11534,0 7637 decl (Decl 7638 n "RS485_E_DO" 7639 t "std_logic" 7640 o 77 7641 suid 201,0 7642 ) 7643 declText (MLText 7644 uid 11535,0 7645 va (VaSet 7646 font "Courier New,8,0" 7647 ) 7648 xt "39000,13400,54000,14200" 7649 st "RS485_E_DO : std_logic" 7650 ) 7651 ) 7652 *259 (PortIoIn 7653 uid 11922,0 7654 shape (CompositeShape 7655 uid 11923,0 7656 va (VaSet 7657 vasetType 1 7658 fg "0,0,32768" 7659 ) 7660 optionalChildren [ 7661 (Pentagon 7662 uid 11924,0 7663 sl 0 7664 ro 90 7665 xt "126500,113625,128000,114375" 7666 ) 7667 (Line 7668 uid 11925,0 7669 sl 0 7670 ro 90 7671 xt "126000,114000,126500,114000" 7672 pts [ 7673 "126500,114000" 7674 "126000,114000" 7675 ] 7676 ) 7677 ] 7678 ) 7679 stc 0 7680 sf 1 7681 tg (WTG 7682 uid 11926,0 7683 ps "PortIoTextPlaceStrategy" 7684 stg "STSignalDisplayStrategy" 7685 f (Text 7686 uid 11927,0 7687 va (VaSet 7688 ) 7689 xt "129000,113500,134600,114500" 7690 st "RS485_E_DO" 7691 blo "129000,114300" 7692 tm "WireNameMgr" 7693 ) 7694 ) 7695 ) 7696 *260 (Net 7697 uid 12318,0 7698 decl (Decl 7699 n "SRIN_out" 7700 t "std_logic" 7701 o 78 7702 suid 202,0 7703 i "'0'" 7704 ) 7705 declText (MLText 7706 uid 12319,0 7707 va (VaSet 7708 font "Courier New,8,0" 7709 ) 7710 xt "39000,35800,68500,36600" 7711 st "SRIN_out : std_logic := '0'" 7712 ) 7713 ) 7714 *261 (PortIoOut 7715 uid 12326,0 7716 shape (CompositeShape 7717 uid 12327,0 7718 va (VaSet 7719 vasetType 1 7720 fg "0,0,32768" 7721 ) 7722 optionalChildren [ 7723 (Pentagon 7724 uid 12328,0 7725 sl 0 7726 ro 270 7727 xt "87500,139625,89000,140375" 7728 ) 7729 (Line 7730 uid 12329,0 7731 sl 0 7732 ro 270 7733 xt "87000,140000,87500,140000" 7734 pts [ 7735 "87000,140000" 7736 "87500,140000" 7737 ] 7738 ) 7739 ] 7740 ) 7741 stc 0 7742 sf 1 7743 tg (WTG 7744 uid 12330,0 7745 ps "PortIoTextPlaceStrategy" 7746 stg "STSignalDisplayStrategy" 7747 f (Text 7748 uid 12331,0 7749 va (VaSet 7750 ) 7751 xt "90000,139500,93700,140500" 7752 st "SRIN_out" 7753 blo "90000,140300" 7754 tm "WireNameMgr" 7755 ) 7756 ) 7757 ) 7758 *262 (Wire 7523 7759 uid 245,0 7524 7760 shape (OrthoPolyLine … … 7559 7795 on &85 7560 7796 ) 7561 *2 53 (Wire7797 *263 (Wire 7562 7798 uid 277,0 7563 7799 shape (OrthoPolyLine … … 7597 7833 on &69 7598 7834 ) 7599 *2 54 (Wire7835 *264 (Wire 7600 7836 uid 285,0 7601 7837 shape (OrthoPolyLine … … 7635 7871 on &70 7636 7872 ) 7637 *2 55 (Wire7873 *265 (Wire 7638 7874 uid 362,0 7639 7875 shape (OrthoPolyLine … … 7673 7909 on &94 7674 7910 ) 7675 *2 56 (Wire7911 *266 (Wire 7676 7912 uid 418,0 7677 7913 shape (OrthoPolyLine … … 7711 7947 on &146 7712 7948 ) 7713 *2 57 (Wire7949 *267 (Wire 7714 7950 uid 426,0 7715 7951 shape (OrthoPolyLine … … 7751 7987 on &144 7752 7988 ) 7753 *2 58 (Wire7989 *268 (Wire 7754 7990 uid 434,0 7755 7991 shape (OrthoPolyLine … … 7789 8025 on &150 7790 8026 ) 7791 *2 59 (Wire8027 *269 (Wire 7792 8028 uid 442,0 7793 8029 shape (OrthoPolyLine … … 7829 8065 on &145 7830 8066 ) 7831 *2 60 (Wire8067 *270 (Wire 7832 8068 uid 450,0 7833 8069 shape (OrthoPolyLine … … 7867 8103 on &149 7868 8104 ) 7869 *2 61 (Wire8105 *271 (Wire 7870 8106 uid 458,0 7871 8107 shape (OrthoPolyLine … … 7905 8141 on &147 7906 8142 ) 7907 *2 62 (Wire8143 *272 (Wire 7908 8144 uid 466,0 7909 8145 shape (OrthoPolyLine … … 7943 8179 on &148 7944 8180 ) 7945 *2 63 (Wire8181 *273 (Wire 7946 8182 uid 1467,0 7947 8183 shape (OrthoPolyLine … … 7979 8215 on &78 7980 8216 ) 7981 *2 64 (Wire8217 *274 (Wire 7982 8218 uid 1730,0 7983 8219 shape (OrthoPolyLine … … 8019 8255 on &96 8020 8256 ) 8021 *2 65 (Wire8257 *275 (Wire 8022 8258 uid 1833,0 8023 8259 shape (OrthoPolyLine … … 8059 8295 on &126 8060 8296 ) 8061 *2 66 (Wire8297 *276 (Wire 8062 8298 uid 1841,0 8063 8299 shape (OrthoPolyLine … … 8097 8333 on &128 8098 8334 ) 8099 *2 67 (Wire8335 *277 (Wire 8100 8336 uid 1865,0 8101 8337 shape (OrthoPolyLine … … 8135 8371 on &121 8136 8372 ) 8137 *2 68 (Wire8373 *278 (Wire 8138 8374 uid 1873,0 8139 8375 shape (OrthoPolyLine … … 8173 8409 on &122 8174 8410 ) 8175 *2 69 (Wire8411 *279 (Wire 8176 8412 uid 1881,0 8177 8413 shape (OrthoPolyLine … … 8211 8447 on &123 8212 8448 ) 8213 *2 70 (Wire8449 *280 (Wire 8214 8450 uid 1889,0 8215 8451 shape (OrthoPolyLine … … 8249 8485 on &124 8250 8486 ) 8251 *2 71 (Wire8487 *281 (Wire 8252 8488 uid 2409,0 8253 8489 shape (OrthoPolyLine … … 8287 8523 on &79 8288 8524 ) 8289 *2 72 (Wire8525 *282 (Wire 8290 8526 uid 2423,0 8291 8527 shape (OrthoPolyLine … … 8325 8561 on &81 8326 8562 ) 8327 *2 73 (Wire8563 *283 (Wire 8328 8564 uid 3009,0 8329 8565 shape (OrthoPolyLine … … 8363 8599 on &143 8364 8600 ) 8365 *2 74 (Wire8601 *284 (Wire 8366 8602 uid 3015,0 8367 8603 shape (OrthoPolyLine … … 8401 8637 on &154 8402 8638 ) 8403 *2 75 (Wire8639 *285 (Wire 8404 8640 uid 3021,0 8405 8641 shape (OrthoPolyLine … … 8439 8675 on &82 8440 8676 ) 8441 *2 76 (Wire8677 *286 (Wire 8442 8678 uid 3027,0 8443 8679 shape (OrthoPolyLine … … 8478 8714 on &83 8479 8715 ) 8480 *2 77 (Wire8716 *287 (Wire 8481 8717 uid 3218,0 8482 8718 shape (OrthoPolyLine … … 8516 8752 on &86 8517 8753 ) 8518 *2 78 (Wire8754 *288 (Wire 8519 8755 uid 3260,0 8520 8756 shape (OrthoPolyLine … … 8556 8792 on &91 8557 8793 ) 8558 *2 79 (Wire8794 *289 (Wire 8559 8795 uid 3270,0 8560 8796 shape (OrthoPolyLine … … 8594 8830 on &92 8595 8831 ) 8596 *2 80 (Wire8832 *290 (Wire 8597 8833 uid 3318,0 8598 8834 shape (OrthoPolyLine … … 8634 8870 on &105 8635 8871 ) 8636 *2 81 (Wire8872 *291 (Wire 8637 8873 uid 3352,0 8638 8874 shape (OrthoPolyLine … … 8674 8910 on &106 8675 8911 ) 8676 *2 82 (Wire8912 *292 (Wire 8677 8913 uid 3360,0 8678 8914 shape (OrthoPolyLine … … 8714 8950 on &107 8715 8951 ) 8716 *2 83 (Wire8952 *293 (Wire 8717 8953 uid 3368,0 8718 8954 shape (OrthoPolyLine … … 8754 8990 on &108 8755 8991 ) 8756 *2 84 (Wire8992 *294 (Wire 8757 8993 uid 3430,0 8758 8994 shape (OrthoPolyLine … … 8792 9028 on &113 8793 9029 ) 8794 *2 85 (Wire9030 *295 (Wire 8795 9031 uid 3438,0 8796 9032 shape (OrthoPolyLine … … 8830 9066 on &114 8831 9067 ) 8832 *2 86 (Wire9068 *296 (Wire 8833 9069 uid 3446,0 8834 9070 shape (OrthoPolyLine … … 8868 9104 on &115 8869 9105 ) 8870 *2 87 (Wire9106 *297 (Wire 8871 9107 uid 3454,0 8872 9108 shape (OrthoPolyLine … … 8906 9142 on &116 8907 9143 ) 8908 *2 88 (Wire9144 *298 (Wire 8909 9145 uid 3574,0 8910 9146 shape (OrthoPolyLine … … 8944 9180 on &138 8945 9181 ) 8946 *2 89 (Wire9182 *299 (Wire 8947 9183 uid 3582,0 8948 9184 shape (OrthoPolyLine … … 8982 9218 on &139 8983 9219 ) 8984 * 290 (Wire9220 *300 (Wire 8985 9221 uid 3590,0 8986 9222 shape (OrthoPolyLine … … 9020 9256 on &140 9021 9257 ) 9022 * 291 (Wire9258 *301 (Wire 9023 9259 uid 3598,0 9024 9260 shape (OrthoPolyLine … … 9058 9294 on &141 9059 9295 ) 9060 * 292 (Wire9296 *302 (Wire 9061 9297 uid 3682,0 9062 9298 shape (OrthoPolyLine … … 9096 9332 on &152 9097 9333 ) 9098 * 293 (Wire9334 *303 (Wire 9099 9335 uid 3778,0 9100 9336 shape (OrthoPolyLine … … 9134 9370 on &168 9135 9371 ) 9136 * 294 (Wire9372 *304 (Wire 9137 9373 uid 3786,0 9138 9374 shape (OrthoPolyLine … … 9172 9408 on &169 9173 9409 ) 9174 * 295 (Wire9410 *305 (Wire 9175 9411 uid 3794,0 9176 9412 shape (OrthoPolyLine … … 9210 9446 on &170 9211 9447 ) 9212 * 296 (Wire9448 *306 (Wire 9213 9449 uid 3802,0 9214 9450 shape (OrthoPolyLine … … 9248 9484 on &171 9249 9485 ) 9250 * 297 (Wire9486 *307 (Wire 9251 9487 uid 3810,0 9252 9488 shape (OrthoPolyLine … … 9286 9522 on &172 9287 9523 ) 9288 * 298 (Wire9524 *308 (Wire 9289 9525 uid 3826,0 9290 9526 shape (OrthoPolyLine … … 9324 9560 on &174 9325 9561 ) 9326 * 299 (Wire9562 *309 (Wire 9327 9563 uid 3834,0 9328 9564 shape (OrthoPolyLine … … 9362 9598 on &175 9363 9599 ) 9364 *3 00 (Wire9600 *310 (Wire 9365 9601 uid 3842,0 9366 9602 shape (OrthoPolyLine … … 9402 9638 on &176 9403 9639 ) 9404 *3 01 (Wire9640 *311 (Wire 9405 9641 uid 4942,0 9406 9642 shape (OrthoPolyLine … … 9442 9678 on &182 9443 9679 ) 9444 *3 02 (Wire9680 *312 (Wire 9445 9681 uid 6431,0 9446 9682 shape (OrthoPolyLine … … 9480 9716 on &173 9481 9717 ) 9482 *3 03 (Wire9718 *313 (Wire 9483 9719 uid 6787,0 9484 9720 shape (OrthoPolyLine … … 9519 9755 on &184 9520 9756 ) 9521 *3 04 (Wire9757 *314 (Wire 9522 9758 uid 6880,0 9523 9759 shape (OrthoPolyLine … … 9558 9794 on &186 9559 9795 ) 9560 *3 05 (Wire9796 *315 (Wire 9561 9797 uid 7144,0 9562 9798 shape (OrthoPolyLine … … 9596 9832 on &196 9597 9833 ) 9598 *3 06 (Wire9834 *316 (Wire 9599 9835 uid 7477,0 9600 9836 shape (OrthoPolyLine … … 9633 9869 on &197 9634 9870 ) 9635 *3 07 (Wire9871 *317 (Wire 9636 9872 uid 8853,0 9637 9873 shape (OrthoPolyLine … … 9673 9909 on &211 9674 9910 ) 9675 *3 08 (Wire9911 *318 (Wire 9676 9912 uid 9502,0 9677 9913 shape (OrthoPolyLine … … 9708 9944 on &212 9709 9945 ) 9710 *3 09 (Wire9946 *319 (Wire 9711 9947 uid 10034,0 9712 9948 shape (OrthoPolyLine … … 9746 9982 on &231 9747 9983 ) 9748 *3 10 (Wire9984 *320 (Wire 9749 9985 uid 10052,0 9750 9986 shape (OrthoPolyLine … … 9783 10019 on &232 9784 10020 ) 9785 *3 11 (Wire10021 *321 (Wire 9786 10022 uid 10302,0 9787 10023 shape (OrthoPolyLine … … 9821 10057 on &234 9822 10058 ) 9823 *3 12 (Wire10059 *322 (Wire 9824 10060 uid 10452,0 9825 10061 shape (OrthoPolyLine … … 9827 10063 va (VaSet 9828 10064 vasetType 3 10065 lineWidth 2 9829 10066 ) 9830 10067 xt "112000,126000,122000,126000" … … 9837 10074 sat 2 9838 10075 eat 16 10076 sty 1 9839 10077 st 0 9840 10078 sf 1 … … 9856 10094 on &234 9857 10095 ) 9858 *3 13 (Wire10096 *323 (Wire 9859 10097 uid 10460,0 9860 10098 shape (OrthoPolyLine … … 9862 10100 va (VaSet 9863 10101 vasetType 3 10102 lineWidth 2 9864 10103 ) 9865 10104 xt "112000,127000,122000,127000" … … 9872 10111 sat 2 9873 10112 eat 16 10113 sty 1 9874 10114 st 0 9875 10115 sf 1 … … 9891 10131 on &196 9892 10132 ) 9893 *3 14 (Wire10133 *324 (Wire 9894 10134 uid 10498,0 9895 10135 shape (OrthoPolyLine … … 9904 10144 ] 9905 10145 ) 9906 start &5 910146 start &58 9907 10147 sat 32 9908 10148 eat 16 … … 9926 10166 on &239 9927 10167 ) 9928 *3 15 (Wire10168 *325 (Wire 9929 10169 uid 10506,0 9930 10170 shape (OrthoPolyLine … … 9937 10177 "80750,124000" 9938 10178 "88000,124000" 10179 ] 10180 ) 10181 start &56 10182 sat 32 10183 eat 16 10184 st 0 10185 sf 1 10186 si 0 10187 tg (WTG 10188 uid 10510,0 10189 ps "ConnStartEndStrategy" 10190 stg "STSignalDisplayStrategy" 10191 f (Text 10192 uid 10511,0 10193 va (VaSet 10194 ) 10195 xt "82000,123000,86800,124000" 10196 st "CLK25_OUT" 10197 blo "82000,123800" 10198 tm "WireNameMgr" 10199 ) 10200 ) 10201 on &240 10202 ) 10203 *326 (Wire 10204 uid 10514,0 10205 shape (OrthoPolyLine 10206 uid 10515,0 10207 va (VaSet 10208 vasetType 3 10209 ) 10210 xt "80750,125000,89000,125000" 10211 pts [ 10212 "80750,125000" 10213 "89000,125000" 9939 10214 ] 9940 10215 ) … … 9946 10221 si 0 9947 10222 tg (WTG 9948 uid 1051 0,010223 uid 10518,0 9949 10224 ps "ConnStartEndStrategy" 9950 10225 stg "STSignalDisplayStrategy" 9951 10226 f (Text 9952 uid 1051 1,09953 va (VaSet 9954 ) 9955 xt "82000,12 3000,86800,124000"9956 st "CLK25_ OUT"9957 blo "82000,12 3800"9958 tm "WireNameMgr" 9959 ) 9960 ) 9961 on &24 09962 ) 9963 *3 16(Wire9964 uid 105 14,010227 uid 10519,0 10228 va (VaSet 10229 ) 10230 xt "82000,124000,88200,125000" 10231 st "CLK25_PSOUT" 10232 blo "82000,124800" 10233 tm "WireNameMgr" 10234 ) 10235 ) 10236 on &241 10237 ) 10238 *327 (Wire 10239 uid 10522,0 9965 10240 shape (OrthoPolyLine 9966 uid 105 15,010241 uid 10523,0 9967 10242 va (VaSet 9968 10243 vasetType 3 9969 10244 ) 9970 xt "80750,12 5000,89000,125000"9971 pts [ 9972 "80750,12 5000"9973 "8 9000,125000"9974 ] 9975 ) 9976 start & 5810245 xt "80750,126000,87000,126000" 10246 pts [ 10247 "80750,126000" 10248 "87000,126000" 10249 ] 10250 ) 10251 start &48 9977 10252 sat 32 9978 10253 eat 16 … … 9981 10256 si 0 9982 10257 tg (WTG 9983 uid 105 18,010258 uid 10526,0 9984 10259 ps "ConnStartEndStrategy" 9985 10260 stg "STSignalDisplayStrategy" 9986 10261 f (Text 9987 uid 105 19,09988 va (VaSet 9989 ) 9990 xt "82000,12 4000,88200,125000"9991 st " CLK25_PSOUT"9992 blo "82000,12 4800"9993 tm "WireNameMgr" 9994 ) 9995 ) 9996 on &24 19997 ) 9998 *3 17(Wire9999 uid 105 22,010262 uid 10527,0 10263 va (VaSet 10264 ) 10265 xt "82000,125000,86400,126000" 10266 st "PS_DIR_IN" 10267 blo "82000,125800" 10268 tm "WireNameMgr" 10269 ) 10270 ) 10271 on &242 10272 ) 10273 *328 (Wire 10274 uid 10530,0 10000 10275 shape (OrthoPolyLine 10001 uid 105 23,010276 uid 10531,0 10002 10277 va (VaSet 10003 10278 vasetType 3 10004 10279 ) 10005 xt "80750,12 6000,87000,126000"10006 pts [ 10007 "80750,12 6000"10008 "87000,12 6000"10280 xt "80750,127000,87000,127000" 10281 pts [ 10282 "80750,127000" 10283 "87000,127000" 10009 10284 ] 10010 10285 ) … … 10016 10291 si 0 10017 10292 tg (WTG 10018 uid 105 26,010293 uid 10534,0 10019 10294 ps "ConnStartEndStrategy" 10020 10295 stg "STSignalDisplayStrategy" 10021 10296 f (Text 10022 uid 105 27,010023 va (VaSet 10024 ) 10025 xt "82000,12 5000,86400,126000"10026 st "PS_D IR_IN"10027 blo "82000,12 5800"10028 tm "WireNameMgr" 10029 ) 10030 ) 10031 on &24 210032 ) 10033 *3 18(Wire10034 uid 1053 0,010297 uid 10535,0 10298 va (VaSet 10299 ) 10300 xt "82000,126000,86200,127000" 10301 st "PS_DO_IN" 10302 blo "82000,126800" 10303 tm "WireNameMgr" 10304 ) 10305 ) 10306 on &243 10307 ) 10308 *329 (Wire 10309 uid 10538,0 10035 10310 shape (OrthoPolyLine 10036 uid 1053 1,010311 uid 10539,0 10037 10312 va (VaSet 10038 10313 vasetType 3 10039 10314 ) 10040 xt "80750,127000,87000,127000" 10041 pts [ 10042 "80750,127000" 10043 "87000,127000" 10315 xt "80750,129000,88000,129000" 10316 pts [ 10317 "80750,129000" 10318 "88000,129000" 10319 ] 10320 ) 10321 start &52 10322 sat 32 10323 eat 16 10324 st 0 10325 sf 1 10326 si 0 10327 tg (WTG 10328 uid 10542,0 10329 ps "ConnStartEndStrategy" 10330 stg "STSignalDisplayStrategy" 10331 f (Text 10332 uid 10543,0 10333 va (VaSet 10334 ) 10335 xt "82000,128000,86600,129000" 10336 st "PSEN_OUT" 10337 blo "82000,128800" 10338 tm "WireNameMgr" 10339 ) 10340 ) 10341 on &244 10342 ) 10343 *330 (Wire 10344 uid 10546,0 10345 shape (OrthoPolyLine 10346 uid 10547,0 10347 va (VaSet 10348 vasetType 3 10349 ) 10350 xt "80750,128000,90000,128000" 10351 pts [ 10352 "80750,128000" 10353 "90000,128000" 10354 ] 10355 ) 10356 start &53 10357 sat 32 10358 eat 16 10359 st 0 10360 sf 1 10361 si 0 10362 tg (WTG 10363 uid 10550,0 10364 ps "ConnStartEndStrategy" 10365 stg "STSignalDisplayStrategy" 10366 f (Text 10367 uid 10551,0 10368 va (VaSet 10369 ) 10370 xt "82000,127000,89000,128000" 10371 st "PSINCDEC_OUT" 10372 blo "82000,127800" 10373 tm "WireNameMgr" 10374 ) 10375 ) 10376 on &245 10377 ) 10378 *331 (Wire 10379 uid 10554,0 10380 shape (OrthoPolyLine 10381 uid 10555,0 10382 va (VaSet 10383 vasetType 3 10384 ) 10385 xt "80750,130000,88000,130000" 10386 pts [ 10387 "80750,130000" 10388 "88000,130000" 10389 ] 10390 ) 10391 start &45 10392 sat 32 10393 eat 16 10394 st 0 10395 sf 1 10396 si 0 10397 tg (WTG 10398 uid 10558,0 10399 ps "ConnStartEndStrategy" 10400 stg "STSignalDisplayStrategy" 10401 f (Text 10402 uid 10559,0 10403 va (VaSet 10404 ) 10405 xt "82000,129000,87200,130000" 10406 st "DCM_locked" 10407 blo "82000,129800" 10408 tm "WireNameMgr" 10409 ) 10410 ) 10411 on &246 10412 ) 10413 *332 (Wire 10414 uid 10562,0 10415 shape (OrthoPolyLine 10416 uid 10563,0 10417 va (VaSet 10418 vasetType 3 10419 ) 10420 xt "80750,132000,85000,132000" 10421 pts [ 10422 "80750,132000" 10423 "85000,132000" 10424 ] 10425 ) 10426 start &54 10427 sat 32 10428 eat 16 10429 st 0 10430 sf 1 10431 si 0 10432 tg (WTG 10433 uid 10566,0 10434 ps "ConnStartEndStrategy" 10435 stg "STSignalDisplayStrategy" 10436 f (Text 10437 uid 10567,0 10438 va (VaSet 10439 ) 10440 xt "82000,131000,84200,132000" 10441 st "ready" 10442 blo "82000,131800" 10443 tm "WireNameMgr" 10444 ) 10445 ) 10446 on &247 10447 ) 10448 *333 (Wire 10449 uid 10570,0 10450 shape (OrthoPolyLine 10451 uid 10571,0 10452 va (VaSet 10453 vasetType 3 10454 ) 10455 xt "80750,133000,86000,133000" 10456 pts [ 10457 "80750,133000" 10458 "86000,133000" 10459 ] 10460 ) 10461 start &55 10462 sat 32 10463 eat 16 10464 st 0 10465 sf 1 10466 si 0 10467 tg (WTG 10468 uid 10574,0 10469 ps "ConnStartEndStrategy" 10470 stg "STSignalDisplayStrategy" 10471 f (Text 10472 uid 10575,0 10473 va (VaSet 10474 ) 10475 xt "82000,132000,84900,133000" 10476 st "shifting" 10477 blo "82000,132800" 10478 tm "WireNameMgr" 10479 ) 10480 ) 10481 on &248 10482 ) 10483 *334 (Wire 10484 uid 10578,0 10485 shape (OrthoPolyLine 10486 uid 10579,0 10487 va (VaSet 10488 vasetType 3 10489 ) 10490 xt "80750,134000,91000,134000" 10491 pts [ 10492 "80750,134000" 10493 "91000,134000" 10494 ] 10495 ) 10496 start &51 10497 sat 32 10498 eat 16 10499 st 0 10500 sf 1 10501 si 0 10502 tg (WTG 10503 uid 10582,0 10504 ps "ConnStartEndStrategy" 10505 stg "STSignalDisplayStrategy" 10506 f (Text 10507 uid 10583,0 10508 va (VaSet 10509 ) 10510 xt "82000,133000,89800,134000" 10511 st "PSDONE_extraOUT" 10512 blo "82000,133800" 10513 tm "WireNameMgr" 10514 ) 10515 ) 10516 on &249 10517 ) 10518 *335 (Wire 10519 uid 10586,0 10520 shape (OrthoPolyLine 10521 uid 10587,0 10522 va (VaSet 10523 vasetType 3 10524 ) 10525 xt "80750,135000,88000,135000" 10526 pts [ 10527 "80750,135000" 10528 "88000,135000" 10044 10529 ] 10045 10530 ) … … 10051 10536 si 0 10052 10537 tg (WTG 10053 uid 105 34,010538 uid 10590,0 10054 10539 ps "ConnStartEndStrategy" 10055 10540 stg "STSignalDisplayStrategy" 10056 10541 f (Text 10057 uid 105 35,010058 va (VaSet 10059 ) 10060 xt "82000,1 26000,86200,127000"10061 st "PS _DO_IN"10062 blo "82000,1 26800"10063 tm "WireNameMgr" 10064 ) 10065 ) 10066 on &2 4310067 ) 10068 *3 19(Wire10069 uid 105 38,010542 uid 10591,0 10543 va (VaSet 10544 ) 10545 xt "82000,134000,87000,135000" 10546 st "PSCLK_OUT" 10547 blo "82000,134800" 10548 tm "WireNameMgr" 10549 ) 10550 ) 10551 on &250 10552 ) 10553 *336 (Wire 10554 uid 10594,0 10070 10555 shape (OrthoPolyLine 10071 uid 105 39,010556 uid 10595,0 10072 10557 va (VaSet 10073 10558 vasetType 3 10074 10559 ) 10075 xt "80750,1 29000,88000,129000"10076 pts [ 10077 "80750,1 29000"10078 " 88000,129000"10079 ] 10080 ) 10081 start & 5310560 xt "80750,136000,91000,136000" 10561 pts [ 10562 "80750,136000" 10563 "91000,136000" 10564 ] 10565 ) 10566 start &46 10082 10567 sat 32 10083 10568 eat 16 … … 10086 10571 si 0 10087 10572 tg (WTG 10088 uid 10542,010089 ps "ConnStartEndStrategy"10090 stg "STSignalDisplayStrategy"10091 f (Text10092 uid 10543,010093 va (VaSet10094 )10095 xt "82000,128000,86600,129000"10096 st "PSEN_OUT"10097 blo "82000,128800"10098 tm "WireNameMgr"10099 )10100 )10101 on &24410102 )10103 *320 (Wire10104 uid 10546,010105 shape (OrthoPolyLine10106 uid 10547,010107 va (VaSet10108 vasetType 310109 )10110 xt "80750,128000,90000,128000"10111 pts [10112 "80750,128000"10113 "90000,128000"10114 ]10115 )10116 start &5410117 sat 3210118 eat 1610119 st 010120 sf 110121 si 010122 tg (WTG10123 uid 10550,010124 ps "ConnStartEndStrategy"10125 stg "STSignalDisplayStrategy"10126 f (Text10127 uid 10551,010128 va (VaSet10129 )10130 xt "82000,127000,89000,128000"10131 st "PSINCDEC_OUT"10132 blo "82000,127800"10133 tm "WireNameMgr"10134 )10135 )10136 on &24510137 )10138 *321 (Wire10139 uid 10554,010140 shape (OrthoPolyLine10141 uid 10555,010142 va (VaSet10143 vasetType 310144 )10145 xt "80750,130000,88000,130000"10146 pts [10147 "80750,130000"10148 "88000,130000"10149 ]10150 )10151 start &4510152 sat 3210153 eat 1610154 st 010155 sf 110156 si 010157 tg (WTG10158 uid 10558,010159 ps "ConnStartEndStrategy"10160 stg "STSignalDisplayStrategy"10161 f (Text10162 uid 10559,010163 va (VaSet10164 )10165 xt "82000,129000,87200,130000"10166 st "DCM_locked"10167 blo "82000,129800"10168 tm "WireNameMgr"10169 )10170 )10171 on &24610172 )10173 *322 (Wire10174 uid 10562,010175 shape (OrthoPolyLine10176 uid 10563,010177 va (VaSet10178 vasetType 310179 )10180 xt "80750,132000,85000,132000"10181 pts [10182 "80750,132000"10183 "85000,132000"10184 ]10185 )10186 start &5510187 sat 3210188 eat 1610189 st 010190 sf 110191 si 010192 tg (WTG10193 uid 10566,010194 ps "ConnStartEndStrategy"10195 stg "STSignalDisplayStrategy"10196 f (Text10197 uid 10567,010198 va (VaSet10199 )10200 xt "82000,131000,84200,132000"10201 st "ready"10202 blo "82000,131800"10203 tm "WireNameMgr"10204 )10205 )10206 on &24710207 )10208 *323 (Wire10209 uid 10570,010210 shape (OrthoPolyLine10211 uid 10571,010212 va (VaSet10213 vasetType 310214 )10215 xt "80750,133000,86000,133000"10216 pts [10217 "80750,133000"10218 "86000,133000"10219 ]10220 )10221 start &5610222 sat 3210223 eat 1610224 st 010225 sf 110226 si 010227 tg (WTG10228 uid 10574,010229 ps "ConnStartEndStrategy"10230 stg "STSignalDisplayStrategy"10231 f (Text10232 uid 10575,010233 va (VaSet10234 )10235 xt "82000,132000,84900,133000"10236 st "shifting"10237 blo "82000,132800"10238 tm "WireNameMgr"10239 )10240 )10241 on &24810242 )10243 *324 (Wire10244 uid 10578,010245 shape (OrthoPolyLine10246 uid 10579,010247 va (VaSet10248 vasetType 310249 )10250 xt "80750,134000,91000,134000"10251 pts [10252 "80750,134000"10253 "91000,134000"10254 ]10255 )10256 start &5210257 sat 3210258 eat 1610259 st 010260 sf 110261 si 010262 tg (WTG10263 uid 10582,010264 ps "ConnStartEndStrategy"10265 stg "STSignalDisplayStrategy"10266 f (Text10267 uid 10583,010268 va (VaSet10269 )10270 xt "82000,133000,89800,134000"10271 st "PSDONE_extraOUT"10272 blo "82000,133800"10273 tm "WireNameMgr"10274 )10275 )10276 on &24910277 )10278 *325 (Wire10279 uid 10586,010280 shape (OrthoPolyLine10281 uid 10587,010282 va (VaSet10283 vasetType 310284 )10285 xt "80750,135000,88000,135000"10286 pts [10287 "80750,135000"10288 "88000,135000"10289 ]10290 )10291 start &5110292 sat 3210293 eat 1610294 st 010295 sf 110296 si 010297 tg (WTG10298 uid 10590,010299 ps "ConnStartEndStrategy"10300 stg "STSignalDisplayStrategy"10301 f (Text10302 uid 10591,010303 va (VaSet10304 )10305 xt "82000,134000,87000,135000"10306 st "PSCLK_OUT"10307 blo "82000,134800"10308 tm "WireNameMgr"10309 )10310 )10311 on &25010312 )10313 *326 (Wire10314 uid 10594,010315 shape (OrthoPolyLine10316 uid 10595,010317 va (VaSet10318 vasetType 310319 )10320 xt "80750,136000,91000,136000"10321 pts [10322 "80750,136000"10323 "91000,136000"10324 ]10325 )10326 start &4710327 sat 3210328 eat 1610329 st 010330 sf 110331 si 010332 tg (WTG10333 10573 uid 10598,0 10334 10574 ps "ConnStartEndStrategy" … … 10346 10586 on &251 10347 10587 ) 10348 *3 27 (Wire10588 *337 (Wire 10349 10589 uid 10600,0 10350 10590 shape (OrthoPolyLine … … 10381 10621 on &240 10382 10622 ) 10383 *3 28 (Wire10623 *338 (Wire 10384 10624 uid 10608,0 10385 10625 shape (OrthoPolyLine … … 10416 10656 on &241 10417 10657 ) 10418 *3 29 (Wire10658 *339 (Wire 10419 10659 uid 10616,0 10420 10660 shape (OrthoPolyLine … … 10451 10691 on &239 10452 10692 ) 10453 *3 30 (Wire10693 *340 (Wire 10454 10694 uid 10624,0 10455 10695 shape (OrthoPolyLine … … 10486 10726 on &246 10487 10727 ) 10488 *3 31 (Wire10728 *341 (Wire 10489 10729 uid 10632,0 10490 10730 shape (OrthoPolyLine … … 10521 10761 on &251 10522 10762 ) 10523 *3 32 (Wire10763 *342 (Wire 10524 10764 uid 10640,0 10525 10765 shape (OrthoPolyLine … … 10556 10796 on &250 10557 10797 ) 10558 *3 33 (Wire10798 *343 (Wire 10559 10799 uid 10648,0 10560 10800 shape (OrthoPolyLine … … 10591 10831 on &249 10592 10832 ) 10593 *3 34 (Wire10833 *344 (Wire 10594 10834 uid 10656,0 10595 10835 shape (OrthoPolyLine … … 10626 10866 on &244 10627 10867 ) 10628 *3 35 (Wire10868 *345 (Wire 10629 10869 uid 10664,0 10630 10870 shape (OrthoPolyLine … … 10661 10901 on &245 10662 10902 ) 10663 *3 36 (Wire10903 *346 (Wire 10664 10904 uid 10672,0 10665 10905 shape (OrthoPolyLine … … 10696 10936 on &242 10697 10937 ) 10698 *3 37 (Wire10938 *347 (Wire 10699 10939 uid 10680,0 10700 10940 shape (OrthoPolyLine … … 10731 10971 on &243 10732 10972 ) 10733 *3 38 (Wire10973 *348 (Wire 10734 10974 uid 10688,0 10735 10975 shape (OrthoPolyLine … … 10766 11006 on &247 10767 11007 ) 10768 *3 39 (Wire11008 *349 (Wire 10769 11009 uid 10696,0 10770 11010 shape (OrthoPolyLine … … 10800 11040 ) 10801 11041 on &248 11042 ) 11043 *350 (Wire 11044 uid 11096,0 11045 shape (OrthoPolyLine 11046 uid 11097,0 11047 va (VaSet 11048 vasetType 3 11049 ) 11050 xt "96000,103000,100000,103000" 11051 pts [ 11052 "96000,103000" 11053 "100000,103000" 11054 ] 11055 ) 11056 start &252 11057 end &155 11058 sat 32 11059 eat 1 11060 st 0 11061 sf 1 11062 si 0 11063 tg (WTG 11064 uid 11100,0 11065 ps "ConnStartEndStrategy" 11066 stg "STSignalDisplayStrategy" 11067 f (Text 11068 uid 11101,0 11069 va (VaSet 11070 isHidden 1 11071 ) 11072 xt "126000,96000,131300,97000" 11073 st "RS485_C_DI" 11074 blo "126000,96800" 11075 tm "WireNameMgr" 11076 ) 11077 ) 11078 on &253 11079 ) 11080 *351 (Wire 11081 uid 11110,0 11082 shape (OrthoPolyLine 11083 uid 11111,0 11084 va (VaSet 11085 vasetType 3 11086 ) 11087 xt "108000,112000,111000,112000" 11088 pts [ 11089 "108000,112000" 11090 "111000,112000" 11091 ] 11092 ) 11093 start &155 11094 end &254 11095 sat 2 11096 eat 32 11097 st 0 11098 sf 1 11099 si 0 11100 tg (WTG 11101 uid 11114,0 11102 ps "ConnStartEndStrategy" 11103 stg "STSignalDisplayStrategy" 11104 f (Text 11105 uid 11115,0 11106 va (VaSet 11107 isHidden 1 11108 ) 11109 xt "110000,111000,115700,112000" 11110 st "RS485_C_DO" 11111 blo "110000,111800" 11112 tm "WireNameMgr" 11113 ) 11114 ) 11115 on &255 11116 ) 11117 *352 (Wire 11118 uid 11514,0 11119 shape (OrthoPolyLine 11120 uid 11515,0 11121 va (VaSet 11122 vasetType 3 11123 ) 11124 xt "123000,116000,127000,116000" 11125 pts [ 11126 "123000,116000" 11127 "127000,116000" 11128 ] 11129 ) 11130 start &256 11131 sat 32 11132 eat 16 11133 st 0 11134 sf 1 11135 si 0 11136 tg (WTG 11137 uid 11518,0 11138 ps "ConnStartEndStrategy" 11139 stg "STSignalDisplayStrategy" 11140 f (Text 11141 uid 11519,0 11142 va (VaSet 11143 isHidden 1 11144 ) 11145 xt "125000,115000,130200,116000" 11146 st "RS485_E_DI" 11147 blo "125000,115800" 11148 tm "WireNameMgr" 11149 ) 11150 ) 11151 on &257 11152 ) 11153 *353 (Wire 11154 uid 11528,0 11155 shape (OrthoPolyLine 11156 uid 11529,0 11157 va (VaSet 11158 vasetType 3 11159 ) 11160 xt "123000,114000,126000,114000" 11161 pts [ 11162 "123000,114000" 11163 "126000,114000" 11164 ] 11165 ) 11166 end &259 11167 sat 16 11168 eat 32 11169 st 0 11170 sf 1 11171 si 0 11172 tg (WTG 11173 uid 11532,0 11174 ps "ConnStartEndStrategy" 11175 stg "STSignalDisplayStrategy" 11176 f (Text 11177 uid 11533,0 11178 va (VaSet 11179 isHidden 1 11180 ) 11181 xt "125000,113000,130600,114000" 11182 st "RS485_E_DO" 11183 blo "125000,113800" 11184 tm "WireNameMgr" 11185 ) 11186 ) 11187 on &258 11188 ) 11189 *354 (Wire 11190 uid 12320,0 11191 shape (OrthoPolyLine 11192 uid 12321,0 11193 va (VaSet 11194 vasetType 3 11195 ) 11196 xt "80750,140000,87000,140000" 11197 pts [ 11198 "80750,140000" 11199 "87000,140000" 11200 ] 11201 ) 11202 start &59 11203 end &261 11204 sat 32 11205 eat 32 11206 stc 0 11207 st 0 11208 sf 1 11209 si 0 11210 tg (WTG 11211 uid 12324,0 11212 ps "ConnStartEndStrategy" 11213 stg "STSignalDisplayStrategy" 11214 f (Text 11215 uid 12325,0 11216 va (VaSet 11217 isHidden 1 11218 ) 11219 xt "82000,139000,85700,140000" 11220 st "SRIN_out" 11221 blo "82000,139800" 11222 tm "WireNameMgr" 11223 ) 11224 ) 11225 on &260 10802 11226 ) 10803 11227 ] … … 10813 11237 color "26368,26368,26368" 10814 11238 ) 10815 packageList *3 40(PackageList11239 packageList *355 (PackageList 10816 11240 uid 41,0 10817 11241 stg "VerticalLayoutStrategy" 10818 11242 textVec [ 10819 *3 41(Text11243 *356 (Text 10820 11244 uid 42,0 10821 11245 va (VaSet … … 10826 11250 blo "0,800" 10827 11251 ) 10828 *3 42(MLText11252 *357 (MLText 10829 11253 uid 43,0 10830 11254 va (VaSet … … 10847 11271 stg "VerticalLayoutStrategy" 10848 11272 textVec [ 10849 *3 43(Text11273 *358 (Text 10850 11274 uid 45,0 10851 11275 va (VaSet … … 10857 11281 blo "20000,800" 10858 11282 ) 10859 *3 44(Text11283 *359 (Text 10860 11284 uid 46,0 10861 11285 va (VaSet … … 10867 11291 blo "20000,1800" 10868 11292 ) 10869 *3 45(MLText11293 *360 (MLText 10870 11294 uid 47,0 10871 11295 va (VaSet … … 10877 11301 tm "BdCompilerDirectivesTextMgr" 10878 11302 ) 10879 *3 46(Text11303 *361 (Text 10880 11304 uid 48,0 10881 11305 va (VaSet … … 10887 11311 blo "20000,4800" 10888 11312 ) 10889 *3 47(MLText11313 *362 (MLText 10890 11314 uid 49,0 10891 11315 va (VaSet … … 10895 11319 tm "BdCompilerDirectivesTextMgr" 10896 11320 ) 10897 *3 48(Text11321 *363 (Text 10898 11322 uid 50,0 10899 11323 va (VaSet … … 10905 11329 blo "20000,5800" 10906 11330 ) 10907 *3 49(MLText11331 *364 (MLText 10908 11332 uid 51,0 10909 11333 va (VaSet … … 10916 11340 associable 1 10917 11341 ) 10918 windowSize " 1276,-4,2564,1028"10919 viewArea " 50354,105045,134172,174344"11342 windowSize "0,0,1281,1002" 11343 viewArea "16140,87720,101020,155960" 10920 11344 cachedDiagramExtent "0,0,699000,450107" 10921 11345 pageSetupInfo (PageSetupInfo … … 10930 11354 hasePageBreakOrigin 1 10931 11355 pageBreakOrigin "0,0" 10932 lastUid 1 0729,011356 lastUid 12333,0 10933 11357 defaultCommentText (CommentText 10934 11358 shape (Rectangle … … 10992 11416 stg "VerticalLayoutStrategy" 10993 11417 textVec [ 10994 *3 50(Text11418 *365 (Text 10995 11419 va (VaSet 10996 11420 font "Arial,8,1" … … 11001 11425 tm "BdLibraryNameMgr" 11002 11426 ) 11003 *3 51(Text11427 *366 (Text 11004 11428 va (VaSet 11005 11429 font "Arial,8,1" … … 11010 11434 tm "BlkNameMgr" 11011 11435 ) 11012 *3 52(Text11436 *367 (Text 11013 11437 va (VaSet 11014 11438 font "Arial,8,1" … … 11061 11485 stg "VerticalLayoutStrategy" 11062 11486 textVec [ 11063 *3 53(Text11487 *368 (Text 11064 11488 va (VaSet 11065 11489 font "Arial,8,1" … … 11069 11493 blo "550,4300" 11070 11494 ) 11071 *3 54(Text11495 *369 (Text 11072 11496 va (VaSet 11073 11497 font "Arial,8,1" … … 11077 11501 blo "550,5300" 11078 11502 ) 11079 *3 55(Text11503 *370 (Text 11080 11504 va (VaSet 11081 11505 font "Arial,8,1" … … 11126 11550 stg "VerticalLayoutStrategy" 11127 11551 textVec [ 11128 *3 56(Text11552 *371 (Text 11129 11553 va (VaSet 11130 11554 font "Arial,8,1" … … 11135 11559 tm "BdLibraryNameMgr" 11136 11560 ) 11137 *3 57(Text11561 *372 (Text 11138 11562 va (VaSet 11139 11563 font "Arial,8,1" … … 11144 11568 tm "CptNameMgr" 11145 11569 ) 11146 *3 58(Text11570 *373 (Text 11147 11571 va (VaSet 11148 11572 font "Arial,8,1" … … 11198 11622 stg "VerticalLayoutStrategy" 11199 11623 textVec [ 11200 *3 59(Text11624 *374 (Text 11201 11625 va (VaSet 11202 11626 font "Arial,8,1" … … 11206 11630 blo "500,4300" 11207 11631 ) 11208 *3 60(Text11632 *375 (Text 11209 11633 va (VaSet 11210 11634 font "Arial,8,1" … … 11214 11638 blo "500,5300" 11215 11639 ) 11216 *3 61(Text11640 *376 (Text 11217 11641 va (VaSet 11218 11642 font "Arial,8,1" … … 11259 11683 stg "VerticalLayoutStrategy" 11260 11684 textVec [ 11261 *3 62(Text11685 *377 (Text 11262 11686 va (VaSet 11263 11687 font "Arial,8,1" … … 11267 11691 blo "50,4300" 11268 11692 ) 11269 *3 63(Text11693 *378 (Text 11270 11694 va (VaSet 11271 11695 font "Arial,8,1" … … 11275 11699 blo "50,5300" 11276 11700 ) 11277 *3 64(Text11701 *379 (Text 11278 11702 va (VaSet 11279 11703 font "Arial,8,1" … … 11316 11740 stg "VerticalLayoutStrategy" 11317 11741 textVec [ 11318 *3 65(Text11742 *380 (Text 11319 11743 va (VaSet 11320 11744 font "Arial,8,1" … … 11325 11749 tm "HdlTextNameMgr" 11326 11750 ) 11327 *3 66(Text11751 *381 (Text 11328 11752 va (VaSet 11329 11753 font "Arial,8,1" … … 11728 12152 stg "VerticalLayoutStrategy" 11729 12153 textVec [ 11730 *3 67(Text12154 *382 (Text 11731 12155 va (VaSet 11732 12156 font "Arial,8,1" … … 11736 12160 blo "14100,20800" 11737 12161 ) 11738 *3 68(MLText12162 *383 (MLText 11739 12163 va (VaSet 11740 12164 ) … … 11788 12212 stg "VerticalLayoutStrategy" 11789 12213 textVec [ 11790 *3 69(Text12214 *384 (Text 11791 12215 va (VaSet 11792 12216 font "Arial,8,1" … … 11796 12220 blo "14100,20800" 11797 12221 ) 11798 *3 70(MLText12222 *385 (MLText 11799 12223 va (VaSet 11800 12224 ) … … 11914 12338 font "Arial,8,1" 11915 12339 ) 11916 xt "37000,4 3000,44100,44000"12340 xt "37000,47000,44100,48000" 11917 12341 st "Diagram Signals:" 11918 blo "37000,4 3800"12342 blo "37000,47800" 11919 12343 ) 11920 12344 postUserLabel (Text … … 11940 12364 commonDM (CommonDM 11941 12365 ldm (LogicalDM 11942 suid 196,012366 suid 202,0 11943 12367 usingSuid 1 11944 emptyRow *3 71(LEmptyRow12368 emptyRow *386 (LEmptyRow 11945 12369 ) 11946 12370 uid 54,0 11947 12371 optionalChildren [ 11948 *3 72(RefLabelRowHdr11949 ) 11950 *3 73(TitleRowHdr11951 ) 11952 *3 74(FilterRowHdr11953 ) 11954 *3 75(RefLabelColHdr12372 *387 (RefLabelRowHdr 12373 ) 12374 *388 (TitleRowHdr 12375 ) 12376 *389 (FilterRowHdr 12377 ) 12378 *390 (RefLabelColHdr 11955 12379 tm "RefLabelColHdrMgr" 11956 12380 ) 11957 *3 76(RowExpandColHdr12381 *391 (RowExpandColHdr 11958 12382 tm "RowExpandColHdrMgr" 11959 12383 ) 11960 *3 77(GroupColHdr12384 *392 (GroupColHdr 11961 12385 tm "GroupColHdrMgr" 11962 12386 ) 11963 *3 78(NameColHdr12387 *393 (NameColHdr 11964 12388 tm "BlockDiagramNameColHdrMgr" 11965 12389 ) 11966 *3 79(ModeColHdr12390 *394 (ModeColHdr 11967 12391 tm "BlockDiagramModeColHdrMgr" 11968 12392 ) 11969 *3 80(TypeColHdr12393 *395 (TypeColHdr 11970 12394 tm "BlockDiagramTypeColHdrMgr" 11971 12395 ) 11972 *3 81(BoundsColHdr12396 *396 (BoundsColHdr 11973 12397 tm "BlockDiagramBoundsColHdrMgr" 11974 12398 ) 11975 *3 82(InitColHdr12399 *397 (InitColHdr 11976 12400 tm "BlockDiagramInitColHdrMgr" 11977 12401 ) 11978 *3 83(EolColHdr12402 *398 (EolColHdr 11979 12403 tm "BlockDiagramEolColHdrMgr" 11980 12404 ) 11981 *3 84(LeafLogPort12405 *399 (LeafLogPort 11982 12406 port (LogicalPort 11983 12407 m 4 … … 11988 12412 preAdd 0 11989 12413 posAdd 0 11990 o 5512414 o 69 11991 12415 suid 5,0 11992 12416 ) … … 11994 12418 uid 327,0 11995 12419 ) 11996 * 385(LeafLogPort12420 *400 (LeafLogPort 11997 12421 port (LogicalPort 11998 12422 m 4 … … 12001 12425 t "std_logic_vector" 12002 12426 b "(1 downto 0)" 12003 o 5612427 o 70 12004 12428 suid 6,0 12005 12429 ) … … 12007 12431 uid 329,0 12008 12432 ) 12009 * 386(LeafLogPort12433 *401 (LeafLogPort 12010 12434 port (LogicalPort 12011 12435 m 4 … … 12013 12437 n "adc_data_array" 12014 12438 t "adc_data_array_type" 12015 o 5412439 o 68 12016 12440 suid 29,0 12017 12441 ) … … 12019 12443 uid 1491,0 12020 12444 ) 12021 * 387(LeafLogPort12445 *402 (LeafLogPort 12022 12446 port (LogicalPort 12023 12447 m 1 … … 12025 12449 n "RSRLOAD" 12026 12450 t "std_logic" 12027 o 3 512451 o 37 12028 12452 suid 57,0 12029 12453 i "'0'" … … 12032 12456 uid 2435,0 12033 12457 ) 12034 * 388(LeafLogPort12458 *403 (LeafLogPort 12035 12459 port (LogicalPort 12036 12460 m 4 … … 12038 12462 n "SRCLK" 12039 12463 t "std_logic" 12040 o 5212464 o 66 12041 12465 suid 58,0 12042 12466 i "'0'" … … 12045 12469 uid 2437,0 12046 12470 ) 12047 * 389(LeafLogPort12471 *404 (LeafLogPort 12048 12472 port (LogicalPort 12049 12473 m 4 … … 12052 12476 t "std_logic_vector" 12053 12477 b "(3 DOWNTO 0)" 12054 o 5912478 o 74 12055 12479 suid 65,0 12056 12480 ) … … 12058 12482 uid 3037,0 12059 12483 ) 12060 * 390(LeafLogPort12484 *405 (LeafLogPort 12061 12485 port (LogicalPort 12062 12486 m 1 … … 12064 12488 n "DAC_CS" 12065 12489 t "std_logic" 12066 o 2 112490 o 22 12067 12491 suid 66,0 12068 12492 ) … … 12070 12494 uid 3039,0 12071 12495 ) 12072 * 391(LeafLogPort12496 *406 (LeafLogPort 12073 12497 port (LogicalPort 12074 12498 decl (Decl … … 12083 12507 uid 3276,0 12084 12508 ) 12085 * 392(LeafLogPort12509 *407 (LeafLogPort 12086 12510 port (LogicalPort 12087 12511 decl (Decl … … 12094 12518 uid 3278,0 12095 12519 ) 12096 * 393(LeafLogPort12520 *408 (LeafLogPort 12097 12521 port (LogicalPort 12098 12522 m 1 … … 12101 12525 t "std_logic_vector" 12102 12526 b "(3 downto 0)" 12103 o 1 612527 o 17 12104 12528 suid 71,0 12105 12529 ) … … 12107 12531 uid 3280,0 12108 12532 ) 12109 * 394(LeafLogPort12533 *409 (LeafLogPort 12110 12534 port (LogicalPort 12111 12535 m 4 … … 12113 12537 n "CLK_25_PS" 12114 12538 t "std_logic" 12115 o 5 012539 o 55 12116 12540 suid 72,0 12117 12541 ) … … 12119 12543 uid 3282,0 12120 12544 ) 12121 * 395(LeafLogPort12545 *410 (LeafLogPort 12122 12546 port (LogicalPort 12123 12547 m 1 … … 12127 12551 preAdd 0 12128 12552 posAdd 0 12129 o 3 012553 o 31 12130 12554 suid 73,0 12131 12555 ) … … 12133 12557 uid 3382,0 12134 12558 ) 12135 * 396(LeafLogPort12559 *411 (LeafLogPort 12136 12560 port (LogicalPort 12137 12561 decl (Decl … … 12145 12569 uid 3384,0 12146 12570 ) 12147 * 397(LeafLogPort12571 *412 (LeafLogPort 12148 12572 port (LogicalPort 12149 12573 decl (Decl … … 12157 12581 uid 3386,0 12158 12582 ) 12159 * 398(LeafLogPort12583 *413 (LeafLogPort 12160 12584 port (LogicalPort 12161 12585 decl (Decl … … 12169 12593 uid 3388,0 12170 12594 ) 12171 * 399(LeafLogPort12595 *414 (LeafLogPort 12172 12596 port (LogicalPort 12173 12597 decl (Decl … … 12181 12605 uid 3390,0 12182 12606 ) 12183 *4 00(LeafLogPort12607 *415 (LeafLogPort 12184 12608 port (LogicalPort 12185 12609 decl (Decl … … 12193 12617 uid 3392,0 12194 12618 ) 12195 *4 01(LeafLogPort12619 *416 (LeafLogPort 12196 12620 port (LogicalPort 12197 12621 m 1 … … 12199 12623 n "D0_SRCLK" 12200 12624 t "STD_LOGIC" 12201 o 1 712625 o 18 12202 12626 suid 87,0 12203 12627 ) … … 12205 12629 uid 3468,0 12206 12630 ) 12207 *4 02(LeafLogPort12631 *417 (LeafLogPort 12208 12632 port (LogicalPort 12209 12633 m 1 … … 12211 12635 n "D1_SRCLK" 12212 12636 t "STD_LOGIC" 12213 o 1 812637 o 19 12214 12638 suid 88,0 12215 12639 ) … … 12217 12641 uid 3470,0 12218 12642 ) 12219 *4 03(LeafLogPort12643 *418 (LeafLogPort 12220 12644 port (LogicalPort 12221 12645 m 1 … … 12223 12647 n "D2_SRCLK" 12224 12648 t "STD_LOGIC" 12225 o 1912649 o 20 12226 12650 suid 89,0 12227 12651 ) … … 12229 12653 uid 3472,0 12230 12654 ) 12231 *4 04(LeafLogPort12655 *419 (LeafLogPort 12232 12656 port (LogicalPort 12233 12657 m 1 … … 12235 12659 n "D3_SRCLK" 12236 12660 t "STD_LOGIC" 12237 o 2 012661 o 21 12238 12662 suid 90,0 12239 12663 ) … … 12241 12665 uid 3474,0 12242 12666 ) 12243 *4 05(LeafLogPort12667 *420 (LeafLogPort 12244 12668 port (LogicalPort 12245 12669 decl (Decl … … 12252 12676 uid 3524,0 12253 12677 ) 12254 *4 06(LeafLogPort12678 *421 (LeafLogPort 12255 12679 port (LogicalPort 12256 12680 decl (Decl … … 12263 12687 uid 3526,0 12264 12688 ) 12265 *4 07(LeafLogPort12689 *422 (LeafLogPort 12266 12690 port (LogicalPort 12267 12691 decl (Decl … … 12274 12698 uid 3528,0 12275 12699 ) 12276 *4 08(LeafLogPort12700 *423 (LeafLogPort 12277 12701 port (LogicalPort 12278 12702 decl (Decl … … 12285 12709 uid 3530,0 12286 12710 ) 12287 *4 09(LeafLogPort12711 *424 (LeafLogPort 12288 12712 port (LogicalPort 12289 12713 m 1 … … 12292 12716 t "std_logic_vector" 12293 12717 b "(3 DOWNTO 0)" 12294 o 2 412718 o 25 12295 12719 suid 95,0 12296 12720 i "(others => '0')" … … 12299 12723 uid 3532,0 12300 12724 ) 12301 *4 10(LeafLogPort12725 *425 (LeafLogPort 12302 12726 port (LogicalPort 12303 12727 m 1 … … 12305 12729 n "DWRITE" 12306 12730 t "std_logic" 12307 o 2 312731 o 24 12308 12732 suid 96,0 12309 12733 i "'0'" … … 12312 12736 uid 3534,0 12313 12737 ) 12314 *4 11(LeafLogPort12738 *426 (LeafLogPort 12315 12739 port (LogicalPort 12316 12740 m 1 … … 12318 12742 n "T0_CS" 12319 12743 t "std_logic" 12320 o 3812744 o 40 12321 12745 suid 101,0 12322 12746 ) … … 12324 12748 uid 3646,0 12325 12749 ) 12326 *4 12(LeafLogPort12750 *427 (LeafLogPort 12327 12751 port (LogicalPort 12328 12752 m 1 … … 12330 12754 n "T1_CS" 12331 12755 t "std_logic" 12332 o 3912756 o 41 12333 12757 suid 102,0 12334 12758 ) … … 12336 12760 uid 3648,0 12337 12761 ) 12338 *4 13(LeafLogPort12762 *428 (LeafLogPort 12339 12763 port (LogicalPort 12340 12764 m 1 … … 12342 12766 n "T2_CS" 12343 12767 t "std_logic" 12344 o 4 012768 o 42 12345 12769 suid 103,0 12346 12770 ) … … 12348 12772 uid 3650,0 12349 12773 ) 12350 *4 14(LeafLogPort12774 *429 (LeafLogPort 12351 12775 port (LogicalPort 12352 12776 m 1 … … 12354 12778 n "T3_CS" 12355 12779 t "std_logic" 12356 o 4 112780 o 43 12357 12781 suid 104,0 12358 12782 ) … … 12360 12784 uid 3652,0 12361 12785 ) 12362 *4 15(LeafLogPort12786 *430 (LeafLogPort 12363 12787 port (LogicalPort 12364 12788 m 1 … … 12366 12790 n "S_CLK" 12367 12791 t "std_logic" 12368 o 3 712792 o 39 12369 12793 suid 105,0 12370 12794 ) … … 12372 12796 uid 3654,0 12373 12797 ) 12374 *4 16(LeafLogPort12798 *431 (LeafLogPort 12375 12799 port (LogicalPort 12376 12800 m 1 … … 12379 12803 t "std_logic_vector" 12380 12804 b "(9 DOWNTO 0)" 12381 o 4 312805 o 45 12382 12806 suid 106,0 12383 12807 ) … … 12385 12809 uid 3656,0 12386 12810 ) 12387 *4 17(LeafLogPort12811 *432 (LeafLogPort 12388 12812 port (LogicalPort 12389 12813 m 2 … … 12392 12816 t "std_logic_vector" 12393 12817 b "(15 DOWNTO 0)" 12394 o 4912818 o 51 12395 12819 suid 107,0 12396 12820 ) 12397 12821 ) 12398 12822 uid 3658,0 12399 )12400 *418 (LeafLogPort12401 port (LogicalPort12402 m 112403 decl (Decl12404 n "W_RES"12405 t "std_logic"12406 o 4612407 suid 108,012408 i "'1'"12409 )12410 )12411 uid 3660,012412 )12413 *419 (LeafLogPort12414 port (LogicalPort12415 m 112416 decl (Decl12417 n "W_RD"12418 t "std_logic"12419 o 4512420 suid 109,012421 i "'1'"12422 )12423 )12424 uid 3662,012425 )12426 *420 (LeafLogPort12427 port (LogicalPort12428 m 112429 decl (Decl12430 n "W_WR"12431 t "std_logic"12432 o 4712433 suid 110,012434 i "'1'"12435 )12436 )12437 uid 3664,012438 )12439 *421 (LeafLogPort12440 port (LogicalPort12441 decl (Decl12442 n "W_INT"12443 t "std_logic"12444 o 1312445 suid 111,012446 )12447 )12448 uid 3666,012449 )12450 *422 (LeafLogPort12451 port (LogicalPort12452 m 112453 decl (Decl12454 n "W_CS"12455 t "std_logic"12456 o 4412457 suid 112,012458 i "'1'"12459 )12460 )12461 uid 3668,012462 )12463 *423 (LeafLogPort12464 port (LogicalPort12465 m 112466 decl (Decl12467 n "MOSI"12468 t "std_logic"12469 o 2912470 suid 113,012471 i "'0'"12472 )12473 )12474 uid 3696,012475 )12476 *424 (LeafLogPort12477 port (LogicalPort12478 m 212479 decl (Decl12480 n "MISO"12481 t "std_logic"12482 preAdd 012483 posAdd 012484 o 4812485 suid 114,012486 )12487 )12488 uid 3698,012489 )12490 *425 (LeafLogPort12491 port (LogicalPort12492 m 112493 decl (Decl12494 n "TRG_V"12495 t "std_logic"12496 o 4212497 suid 126,012498 )12499 )12500 uid 3886,012501 )12502 *426 (LeafLogPort12503 port (LogicalPort12504 m 112505 decl (Decl12506 n "RS485_C_RE"12507 t "std_logic"12508 o 3212509 suid 127,012510 )12511 )12512 uid 3888,012513 )12514 *427 (LeafLogPort12515 port (LogicalPort12516 m 112517 decl (Decl12518 n "RS485_C_DE"12519 t "std_logic"12520 o 3112521 suid 128,012522 )12523 )12524 uid 3890,012525 )12526 *428 (LeafLogPort12527 port (LogicalPort12528 m 112529 decl (Decl12530 n "RS485_E_RE"12531 t "std_logic"12532 o 3412533 suid 129,012534 )12535 )12536 uid 3892,012537 )12538 *429 (LeafLogPort12539 port (LogicalPort12540 m 112541 decl (Decl12542 n "RS485_E_DE"12543 t "std_logic"12544 o 3312545 suid 130,012546 )12547 )12548 uid 3894,012549 )12550 *430 (LeafLogPort12551 port (LogicalPort12552 m 112553 decl (Decl12554 n "DENABLE"12555 t "std_logic"12556 o 2212557 suid 131,012558 i "'0'"12559 )12560 )12561 uid 3896,012562 )12563 *431 (LeafLogPort12564 port (LogicalPort12565 m 112566 decl (Decl12567 n "SRIN"12568 t "std_logic"12569 o 3612570 suid 132,012571 )12572 )12573 uid 3898,012574 )12575 *432 (LeafLogPort12576 port (LogicalPort12577 m 112578 decl (Decl12579 n "EE_CS"12580 t "std_logic"12581 o 2712582 suid 133,012583 )12584 )12585 uid 3900,012586 12823 ) 12587 12824 *433 (LeafLogPort … … 12589 12826 m 1 12590 12827 decl (Decl 12828 n "W_RES" 12829 t "std_logic" 12830 o 48 12831 suid 108,0 12832 i "'1'" 12833 ) 12834 ) 12835 uid 3660,0 12836 ) 12837 *434 (LeafLogPort 12838 port (LogicalPort 12839 m 1 12840 decl (Decl 12841 n "W_RD" 12842 t "std_logic" 12843 o 47 12844 suid 109,0 12845 i "'1'" 12846 ) 12847 ) 12848 uid 3662,0 12849 ) 12850 *435 (LeafLogPort 12851 port (LogicalPort 12852 m 1 12853 decl (Decl 12854 n "W_WR" 12855 t "std_logic" 12856 o 49 12857 suid 110,0 12858 i "'1'" 12859 ) 12860 ) 12861 uid 3664,0 12862 ) 12863 *436 (LeafLogPort 12864 port (LogicalPort 12865 decl (Decl 12866 n "W_INT" 12867 t "std_logic" 12868 o 13 12869 suid 111,0 12870 ) 12871 ) 12872 uid 3666,0 12873 ) 12874 *437 (LeafLogPort 12875 port (LogicalPort 12876 m 1 12877 decl (Decl 12878 n "W_CS" 12879 t "std_logic" 12880 o 46 12881 suid 112,0 12882 i "'1'" 12883 ) 12884 ) 12885 uid 3668,0 12886 ) 12887 *438 (LeafLogPort 12888 port (LogicalPort 12889 m 1 12890 decl (Decl 12891 n "MOSI" 12892 t "std_logic" 12893 o 30 12894 suid 113,0 12895 i "'0'" 12896 ) 12897 ) 12898 uid 3696,0 12899 ) 12900 *439 (LeafLogPort 12901 port (LogicalPort 12902 m 2 12903 decl (Decl 12904 n "MISO" 12905 t "std_logic" 12906 preAdd 0 12907 posAdd 0 12908 o 50 12909 suid 114,0 12910 ) 12911 ) 12912 uid 3698,0 12913 ) 12914 *440 (LeafLogPort 12915 port (LogicalPort 12916 m 1 12917 decl (Decl 12918 n "TRG_V" 12919 t "std_logic" 12920 o 44 12921 suid 126,0 12922 ) 12923 ) 12924 uid 3886,0 12925 ) 12926 *441 (LeafLogPort 12927 port (LogicalPort 12928 m 1 12929 decl (Decl 12930 n "RS485_C_RE" 12931 t "std_logic" 12932 o 34 12933 suid 127,0 12934 ) 12935 ) 12936 uid 3888,0 12937 ) 12938 *442 (LeafLogPort 12939 port (LogicalPort 12940 m 1 12941 decl (Decl 12942 n "RS485_C_DE" 12943 t "std_logic" 12944 o 32 12945 suid 128,0 12946 ) 12947 ) 12948 uid 3890,0 12949 ) 12950 *443 (LeafLogPort 12951 port (LogicalPort 12952 m 1 12953 decl (Decl 12954 n "RS485_E_RE" 12955 t "std_logic" 12956 o 36 12957 suid 129,0 12958 ) 12959 ) 12960 uid 3892,0 12961 ) 12962 *444 (LeafLogPort 12963 port (LogicalPort 12964 m 1 12965 decl (Decl 12966 n "RS485_E_DE" 12967 t "std_logic" 12968 o 35 12969 suid 130,0 12970 ) 12971 ) 12972 uid 3894,0 12973 ) 12974 *445 (LeafLogPort 12975 port (LogicalPort 12976 m 1 12977 decl (Decl 12978 n "DENABLE" 12979 t "std_logic" 12980 o 23 12981 suid 131,0 12982 i "'0'" 12983 ) 12984 ) 12985 uid 3896,0 12986 ) 12987 *446 (LeafLogPort 12988 port (LogicalPort 12989 m 1 12990 decl (Decl 12991 n "SRIN" 12992 t "std_logic" 12993 o 38 12994 suid 132,0 12995 ) 12996 ) 12997 uid 3898,0 12998 ) 12999 *447 (LeafLogPort 13000 port (LogicalPort 13001 m 1 13002 decl (Decl 13003 n "EE_CS" 13004 t "std_logic" 13005 o 28 13006 suid 133,0 13007 ) 13008 ) 13009 uid 3900,0 13010 ) 13011 *448 (LeafLogPort 13012 port (LogicalPort 13013 m 1 13014 decl (Decl 12591 13015 n "LED" 12592 13016 t "std_logic_vector" 12593 13017 b "( 2 DOWNTO 0 )" 12594 o 2 813018 o 29 12595 13019 suid 134,0 12596 13020 i "(others => '1')" … … 12599 13023 uid 3902,0 12600 13024 ) 12601 *4 34(LeafLogPort13025 *449 (LeafLogPort 12602 13026 port (LogicalPort 12603 13027 m 1 … … 12606 13030 t "std_logic_vector" 12607 13031 b "(7 DOWNTO 0)" 12608 o 2 513032 o 26 12609 13033 suid 141,0 12610 13034 i "(OTHERS => '0')" … … 12613 13037 uid 5322,0 12614 13038 ) 12615 *4 35(LeafLogPort13039 *450 (LeafLogPort 12616 13040 port (LogicalPort 12617 13041 decl (Decl … … 12626 13050 scheme 0 12627 13051 ) 12628 *4 36(LeafLogPort13052 *451 (LeafLogPort 12629 13053 port (LogicalPort 12630 13054 m 1 … … 12633 13057 t "std_logic_vector" 12634 13058 b "(3 DOWNTO 0)" 12635 o 2 613059 o 27 12636 13060 suid 154,0 12637 13061 i "(others => '0')" … … 12641 13065 scheme 0 12642 13066 ) 12643 *4 37(LeafLogPort13067 *452 (LeafLogPort 12644 13068 port (LogicalPort 12645 13069 m 1 … … 12648 13072 t "std_logic_vector" 12649 13073 b "(7 DOWNTO 0)" 12650 o 1 513074 o 16 12651 13075 suid 155,0 12652 13076 i "(OTHERS => '0')" … … 12656 13080 scheme 0 12657 13081 ) 12658 *4 38(LeafLogPort13082 *453 (LeafLogPort 12659 13083 port (LogicalPort 12660 13084 m 4 … … 12662 13086 n "dummy" 12663 13087 t "std_logic" 12664 o 5813088 o 72 12665 13089 suid 157,0 12666 13090 ) … … 12669 13093 scheme 0 12670 13094 ) 12671 *4 39(LeafLogPort13095 *454 (LeafLogPort 12672 13096 port (LogicalPort 12673 13097 m 4 … … 12676 13100 t "std_logic_vector" 12677 13101 b "(3 downto 0)" 12678 o 5713102 o 71 12679 13103 suid 159,0 12680 13104 i "(others => '0')" … … 12683 13107 uid 8875,0 12684 13108 ) 12685 *4 40(LeafLogPort13109 *455 (LeafLogPort 12686 13110 port (LogicalPort 12687 13111 m 4 … … 12689 13113 n "CLK_50" 12690 13114 t "std_logic" 12691 o 5 113115 o 57 12692 13116 suid 163,0 12693 13117 ) … … 12695 13119 uid 9516,0 12696 13120 ) 12697 *4 41(LeafLogPort13121 *456 (LeafLogPort 12698 13122 port (LogicalPort 12699 13123 m 4 … … 12701 13125 n "CLK_25_PS1" 12702 13126 t "std_logic" 12703 o 5 813127 o 56 12704 13128 suid 164,0 12705 13129 ) … … 12707 13131 uid 10056,0 12708 13132 ) 12709 *4 42(LeafLogPort13133 *457 (LeafLogPort 12710 13134 port (LogicalPort 12711 13135 m 4 … … 12713 13137 n "adc_clk_en" 12714 13138 t "std_logic" 12715 o 5913139 o 67 12716 13140 suid 165,0 12717 13141 i "'0'" … … 12720 13144 uid 10058,0 12721 13145 ) 12722 *4 43(LeafLogPort13146 *458 (LeafLogPort 12723 13147 port (LogicalPort 12724 13148 m 1 … … 12727 13151 t "std_logic_vector" 12728 13152 b "(7 DOWNTO 0)" 12729 o 6013153 o 15 12730 13154 suid 166,0 12731 13155 i "(others => '0')" … … 12735 13159 scheme 0 12736 13160 ) 12737 *4 44(LeafLogPort13161 *459 (LeafLogPort 12738 13162 port (LogicalPort 12739 13163 m 4 … … 12741 13165 n "CLK50_OUT" 12742 13166 t "std_logic" 12743 o 6113167 o 54 12744 13168 suid 184,0 12745 13169 ) … … 12747 13171 uid 10704,0 12748 13172 ) 12749 *4 45(LeafLogPort13173 *460 (LeafLogPort 12750 13174 port (LogicalPort 12751 13175 m 4 … … 12753 13177 n "CLK25_OUT" 12754 13178 t "std_logic" 12755 o 6213179 o 52 12756 13180 suid 185,0 12757 13181 ) … … 12759 13183 uid 10706,0 12760 13184 ) 12761 *4 46(LeafLogPort13185 *461 (LeafLogPort 12762 13186 port (LogicalPort 12763 13187 m 4 … … 12765 13189 n "CLK25_PSOUT" 12766 13190 t "std_logic" 12767 o 6313191 o 53 12768 13192 suid 186,0 12769 13193 ) … … 12771 13195 uid 10708,0 12772 13196 ) 12773 *4 47(LeafLogPort13197 *462 (LeafLogPort 12774 13198 port (LogicalPort 12775 13199 m 4 … … 12783 13207 uid 10710,0 12784 13208 ) 12785 *4 48(LeafLogPort13209 *463 (LeafLogPort 12786 13210 port (LogicalPort 12787 13211 m 4 … … 12795 13219 uid 10712,0 12796 13220 ) 12797 *4 49(LeafLogPort13221 *464 (LeafLogPort 12798 13222 port (LogicalPort 12799 13223 m 4 … … 12801 13225 n "PSEN_OUT" 12802 13226 t "std_logic" 12803 o 6 613227 o 62 12804 13228 suid 189,0 12805 13229 ) … … 12807 13231 uid 10714,0 12808 13232 ) 12809 *4 50(LeafLogPort13233 *465 (LeafLogPort 12810 13234 port (LogicalPort 12811 13235 m 4 … … 12813 13237 n "PSINCDEC_OUT" 12814 13238 t "std_logic" 12815 o 6 713239 o 63 12816 13240 suid 190,0 12817 13241 ) … … 12819 13243 uid 10716,0 12820 13244 ) 12821 *4 51(LeafLogPort13245 *466 (LeafLogPort 12822 13246 port (LogicalPort 12823 13247 m 4 … … 12827 13251 preAdd 0 12828 13252 posAdd 0 12829 o 6813253 o 58 12830 13254 suid 191,0 12831 13255 ) … … 12833 13257 uid 10718,0 12834 13258 ) 12835 *4 52(LeafLogPort13259 *467 (LeafLogPort 12836 13260 port (LogicalPort 12837 13261 m 4 … … 12841 13265 preAdd 0 12842 13266 posAdd 0 12843 o 6913267 o 73 12844 13268 suid 192,0 12845 13269 i "'0'" … … 12848 13272 uid 10720,0 12849 13273 ) 12850 *4 53(LeafLogPort13274 *468 (LeafLogPort 12851 13275 port (LogicalPort 12852 13276 m 4 … … 12857 13281 preAdd 0 12858 13282 posAdd 0 12859 o 7 013283 o 75 12860 13284 suid 193,0 12861 13285 i "'0'" … … 12864 13288 uid 10722,0 12865 13289 ) 12866 *4 54(LeafLogPort13290 *469 (LeafLogPort 12867 13291 port (LogicalPort 12868 13292 m 4 … … 12870 13294 n "PSDONE_extraOUT" 12871 13295 t "std_logic" 12872 o 7113296 o 61 12873 13297 suid 194,0 12874 13298 ) … … 12876 13300 uid 10724,0 12877 13301 ) 12878 *4 55(LeafLogPort13302 *470 (LeafLogPort 12879 13303 port (LogicalPort 12880 13304 m 4 … … 12882 13306 n "PSCLK_OUT" 12883 13307 t "std_logic" 12884 o 7213308 o 60 12885 13309 suid 195,0 12886 13310 ) … … 12888 13312 uid 10726,0 12889 13313 ) 12890 *4 56(LeafLogPort13314 *471 (LeafLogPort 12891 13315 port (LogicalPort 12892 13316 m 4 … … 12894 13318 n "LOCKED_extraOUT" 12895 13319 t "std_logic" 12896 o 7313320 o 59 12897 13321 suid 196,0 12898 13322 ) 12899 13323 ) 12900 13324 uid 10728,0 13325 ) 13326 *472 (LeafLogPort 13327 port (LogicalPort 13328 decl (Decl 13329 n "RS485_C_DI" 13330 t "std_logic" 13331 o 74 13332 suid 197,0 13333 ) 13334 ) 13335 uid 11084,0 13336 scheme 0 13337 ) 13338 *473 (LeafLogPort 13339 port (LogicalPort 13340 m 1 13341 decl (Decl 13342 n "RS485_C_DO" 13343 t "std_logic" 13344 o 75 13345 suid 198,0 13346 ) 13347 ) 13348 uid 11086,0 13349 scheme 0 13350 ) 13351 *474 (LeafLogPort 13352 port (LogicalPort 13353 decl (Decl 13354 n "RS485_E_DI" 13355 t "std_logic" 13356 o 76 13357 suid 200,0 13358 ) 13359 ) 13360 uid 11504,0 13361 scheme 0 13362 ) 13363 *475 (LeafLogPort 13364 port (LogicalPort 13365 decl (Decl 13366 n "RS485_E_DO" 13367 t "std_logic" 13368 o 77 13369 suid 201,0 13370 ) 13371 ) 13372 uid 11506,0 13373 scheme 0 13374 ) 13375 *476 (LeafLogPort 13376 port (LogicalPort 13377 m 1 13378 decl (Decl 13379 n "SRIN_out" 13380 t "std_logic" 13381 o 78 13382 suid 202,0 13383 i "'0'" 13384 ) 13385 ) 13386 uid 12332,0 12901 13387 ) 12902 13388 ] … … 12907 13393 uid 67,0 12908 13394 optionalChildren [ 12909 *4 57 (Sheet13395 *477 (Sheet 12910 13396 sheetRow (SheetRow 12911 13397 headerVa (MVa … … 12924 13410 font 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100 13417 13933 uid 76,0 13418 13934 ) 13419 *5 38(MRCItem13420 litem &3 7913935 *563 (MRCItem 13936 litem &394 13421 13937 pos 3 13422 13938 dimension 50 13423 13939 uid 77,0 13424 13940 ) 13425 *5 39(MRCItem13426 litem &3 8013941 *564 (MRCItem 13942 litem &395 13427 13943 pos 4 13428 13944 dimension 100 13429 13945 uid 78,0 13430 13946 ) 13431 *5 40(MRCItem13432 litem &3 8113947 *565 (MRCItem 13948 litem &396 13433 13949 pos 5 13434 13950 dimension 100 13435 13951 uid 79,0 13436 13952 ) 13437 *5 41(MRCItem13438 litem &3 8213953 *566 (MRCItem 13954 litem &397 13439 13955 pos 6 13440 13956 dimension 92 13441 13957 uid 80,0 13442 13958 ) 13443 *5 42(MRCItem13444 litem &3 8313959 *567 (MRCItem 13960 litem &398 13445 13961 pos 7 13446 13962 dimension 80 … … 13462 13978 genericsCommonDM (CommonDM 13463 13979 ldm (LogicalDM 13464 emptyRow *5 43(LEmptyRow13980 emptyRow *568 (LEmptyRow 13465 13981 ) 13466 13982 uid 83,0 13467 13983 optionalChildren [ 13468 *5 44(RefLabelRowHdr13469 ) 13470 *5 45(TitleRowHdr13471 ) 13472 *5 46(FilterRowHdr13473 ) 13474 *5 47(RefLabelColHdr13984 *569 (RefLabelRowHdr 13985 ) 13986 *570 (TitleRowHdr 13987 ) 13988 *571 (FilterRowHdr 13989 ) 13990 *572 (RefLabelColHdr 13475 13991 tm "RefLabelColHdrMgr" 13476 13992 ) 13477 *5 48(RowExpandColHdr13993 *573 (RowExpandColHdr 13478 13994 tm "RowExpandColHdrMgr" 13479 13995 ) 13480 *5 49(GroupColHdr13996 *574 (GroupColHdr 13481 13997 tm "GroupColHdrMgr" 13482 13998 ) 13483 *5 50(NameColHdr13999 *575 (NameColHdr 13484 14000 tm "GenericNameColHdrMgr" 13485 14001 ) 13486 *5 51(TypeColHdr14002 *576 (TypeColHdr 13487 14003 tm "GenericTypeColHdrMgr" 13488 14004 ) 13489 *5 52(InitColHdr14005 *577 (InitColHdr 13490 14006 tm "GenericValueColHdrMgr" 13491 14007 ) 13492 *5 53(PragmaColHdr14008 *578 (PragmaColHdr 13493 14009 tm "GenericPragmaColHdrMgr" 13494 14010 ) 13495 *5 54(EolColHdr14011 *579 (EolColHdr 13496 14012 tm "GenericEolColHdrMgr" 13497 14013 ) … … 13503 14019 uid 95,0 13504 14020 optionalChildren [ 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4914081 *586 (MRCItem 14082 litem &574 13567 14083 pos 1 13568 14084 dimension 50 13569 14085 uid 103,0 13570 14086 ) 13571 *5 62(MRCItem13572 litem &5 5014087 *587 (MRCItem 14088 litem &575 13573 14089 pos 2 13574 14090 dimension 100 13575 14091 uid 104,0 13576 14092 ) 13577 *5 63(MRCItem13578 litem &5 5114093 *588 (MRCItem 14094 litem &576 13579 14095 pos 3 13580 14096 dimension 100 13581 14097 uid 105,0 13582 14098 ) 13583 *5 64(MRCItem13584 litem &5 5214099 *589 (MRCItem 14100 litem &577 13585 14101 pos 4 13586 14102 dimension 50 13587 14103 uid 106,0 13588 14104 ) 13589 *5 65(MRCItem13590 litem &5 5314105 *590 (MRCItem 14106 litem &578 13591 14107 pos 5 13592 14108 dimension 50 13593 14109 uid 107,0 13594 14110 ) 13595 *5 66(MRCItem13596 litem &5 5414111 *591 (MRCItem 14112 litem &579 13597 14113 pos 6 13598 14114 dimension 80 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb
r9912 r10073 21 21 commonDM (CommonDM 22 22 ldm (LogicalDM 23 suid 68,023 suid 73,0 24 24 usingSuid 1 25 25 emptyRow *1 (LEmptyRow … … 66 66 n "RSRLOAD" 67 67 t "std_logic" 68 o 3 568 o 39 69 69 suid 11,0 70 70 i "'0'" … … 80 80 preAdd 0 81 81 posAdd 0 82 o 1 382 o 16 83 83 suid 15,0 84 84 ) … … 91 91 n "TRG" 92 92 t "STD_LOGIC" 93 o 1 193 o 14 94 94 suid 16,0 95 95 ) … … 104 104 t "std_logic_vector" 105 105 b "(3 downto 0)" 106 o 1 6106 o 19 107 107 suid 17,0 108 108 ) … … 118 118 preAdd 0 119 119 posAdd 0 120 o 3 0120 o 33 121 121 suid 18,0 122 122 ) … … 190 190 n "D0_SRCLK" 191 191 t "STD_LOGIC" 192 o 17192 o 20 193 193 suid 24,0 194 194 ) … … 202 202 n "D1_SRCLK" 203 203 t "STD_LOGIC" 204 o 18204 o 21 205 205 suid 25,0 206 206 ) … … 214 214 n "D2_SRCLK" 215 215 t "STD_LOGIC" 216 o 19216 o 22 217 217 suid 26,0 218 218 ) … … 226 226 n "D3_SRCLK" 227 227 t "STD_LOGIC" 228 o 2 0228 o 23 229 229 suid 27,0 230 230 ) … … 283 283 t "std_logic_vector" 284 284 b "(3 DOWNTO 0)" 285 o 2 4285 o 27 286 286 suid 32,0 287 287 i "(others => '0')" … … 296 296 n "DWRITE" 297 297 t "std_logic" 298 o 2 3298 o 26 299 299 suid 33,0 300 300 i "'0'" … … 309 309 n "DAC_CS" 310 310 t "std_logic" 311 o 2 1311 o 24 312 312 suid 34,0 313 313 ) … … 321 321 n "T0_CS" 322 322 t "std_logic" 323 o 38323 o 42 324 324 suid 35,0 325 325 ) … … 333 333 n "T1_CS" 334 334 t "std_logic" 335 o 39335 o 43 336 336 suid 36,0 337 337 ) … … 345 345 n "T2_CS" 346 346 t "std_logic" 347 o 4 0347 o 44 348 348 suid 37,0 349 349 ) … … 357 357 n "T3_CS" 358 358 t "std_logic" 359 o 45 360 suid 38,0 361 ) 362 ) 363 uid 1346,0 364 ) 365 *39 (LogPort 366 port (LogicalPort 367 m 1 368 decl (Decl 369 n "S_CLK" 370 t "std_logic" 359 371 o 41 360 suid 38,0361 )362 )363 uid 1346,0364 )365 *39 (LogPort366 port (LogicalPort367 m 1368 decl (Decl369 n "S_CLK"370 t "std_logic"371 o 37372 372 suid 39,0 373 373 ) … … 382 382 t "std_logic_vector" 383 383 b "(9 DOWNTO 0)" 384 o 4 3384 o 47 385 385 suid 40,0 386 386 ) … … 395 395 t "std_logic_vector" 396 396 b "(15 DOWNTO 0)" 397 o 49397 o 53 398 398 suid 41,0 399 399 ) … … 407 407 n "W_RES" 408 408 t "std_logic" 409 o 46409 o 50 410 410 suid 42,0 411 411 i "'1'" … … 420 420 n "W_RD" 421 421 t "std_logic" 422 o 4 5422 o 49 423 423 suid 43,0 424 424 i "'1'" … … 433 433 n "W_WR" 434 434 t "std_logic" 435 o 47435 o 51 436 436 suid 44,0 437 437 i "'1'" … … 445 445 n "W_INT" 446 446 t "std_logic" 447 o 1 2447 o 15 448 448 suid 45,0 449 449 ) … … 457 457 n "W_CS" 458 458 t "std_logic" 459 o 4 4459 o 48 460 460 suid 46,0 461 461 i "'1'" … … 470 470 n "MOSI" 471 471 t "std_logic" 472 o 29472 o 32 473 473 suid 47,0 474 474 i "'0'" … … 485 485 preAdd 0 486 486 posAdd 0 487 o 48487 o 52 488 488 suid 48,0 489 489 ) … … 497 497 n "TRG_V" 498 498 t "std_logic" 499 o 4 2499 o 46 500 500 suid 49,0 501 501 ) … … 509 509 n "RS485_C_RE" 510 510 t "std_logic" 511 o 3 2511 o 36 512 512 suid 50,0 513 513 ) … … 521 521 n "RS485_C_DE" 522 522 t "std_logic" 523 o 3 1523 o 34 524 524 suid 51,0 525 525 ) … … 533 533 n "RS485_E_RE" 534 534 t "std_logic" 535 o 3 4535 o 38 536 536 suid 52,0 537 537 ) … … 545 545 n "RS485_E_DE" 546 546 t "std_logic" 547 o 3 3547 o 37 548 548 suid 53,0 549 549 ) … … 557 557 n "DENABLE" 558 558 t "std_logic" 559 o 2 2559 o 25 560 560 suid 54,0 561 561 i "'0'" … … 570 570 n "SRIN" 571 571 t "std_logic" 572 o 36572 o 40 573 573 suid 55,0 574 i "'0'" 574 575 ) 575 576 ) … … 582 583 n "EE_CS" 583 584 t "std_logic" 584 o 27585 o 30 585 586 suid 56,0 586 587 ) … … 595 596 t "std_logic_vector" 596 597 b "(7 DOWNTO 0)" 597 o 2 5598 o 28 598 599 suid 61,0 599 600 i "(OTHERS => '0')" … … 609 610 t "std_logic_vector" 610 611 b "( 2 DOWNTO 0 )" 611 o 28612 o 31 612 613 suid 62,0 613 614 i "(others => '1')" … … 635 636 t "std_logic_vector" 636 637 b "(3 DOWNTO 0)" 637 o 2 6638 o 29 638 639 suid 65,0 639 640 i "(others => '0')" … … 649 650 t "std_logic_vector" 650 651 b "(7 DOWNTO 0)" 651 o 1 5652 o 18 652 653 suid 66,0 653 654 i "(OTHERS => '0')" … … 663 664 t "std_logic_vector" 664 665 b "(7 DOWNTO 0)" 665 o 1 4666 o 17 666 667 suid 68,0 667 668 i "(others => '0')" … … 669 670 ) 670 671 uid 3455,0 672 ) 673 *63 (LogPort 674 port (LogicalPort 675 decl (Decl 676 n "RS485_C_DI" 677 t "std_logic" 678 o 11 679 suid 69,0 680 ) 681 ) 682 uid 3578,0 683 ) 684 *64 (LogPort 685 port (LogicalPort 686 m 1 687 decl (Decl 688 n "RS485_C_DO" 689 t "std_logic" 690 o 35 691 suid 70,0 692 ) 693 ) 694 uid 3580,0 695 ) 696 *65 (LogPort 697 port (LogicalPort 698 decl (Decl 699 n "RS485_E_DI" 700 t "std_logic" 701 o 12 702 suid 71,0 703 ) 704 ) 705 uid 3684,0 706 ) 707 *66 (LogPort 708 port (LogicalPort 709 decl (Decl 710 n "RS485_E_DO" 711 t "std_logic" 712 o 13 713 suid 72,0 714 ) 715 ) 716 uid 3686,0 671 717 ) 672 718 ] … … 677 723 uid 66,0 678 724 optionalChildren [ 679 *6 3(Sheet725 *67 (Sheet 680 726 sheetRow (SheetRow 681 727 headerVa (MVa … … 694 740 font "Tahoma,10,0" 695 741 ) 696 emptyMRCItem *6 4(MRCItem742 emptyMRCItem *68 (MRCItem 697 743 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(LEmptyRow 1091 1161 ) 1092 1162 uid 82,0 1093 1163 optionalChildren [ 1094 *1 26(RefLabelRowHdr1095 ) 1096 *1 27(TitleRowHdr1097 ) 1098 *1 28(FilterRowHdr1099 ) 1100 *1 29(RefLabelColHdr1164 *134 (RefLabelRowHdr 1165 ) 1166 *135 (TitleRowHdr 1167 ) 1168 *136 (FilterRowHdr 1169 ) 1170 *137 (RefLabelColHdr 1101 1171 tm "RefLabelColHdrMgr" 1102 1172 ) 1103 *13 0(RowExpandColHdr1173 *138 (RowExpandColHdr 1104 1174 tm "RowExpandColHdrMgr" 1105 1175 ) 1106 *13 1(GroupColHdr1176 *139 (GroupColHdr 1107 1177 tm "GroupColHdrMgr" 1108 1178 ) 1109 *1 32(NameColHdr1179 *140 (NameColHdr 1110 1180 tm "GenericNameColHdrMgr" 1111 1181 ) 1112 *1 33(TypeColHdr1182 *141 (TypeColHdr 1113 1183 tm "GenericTypeColHdrMgr" 1114 1184 ) 1115 *1 34(InitColHdr1185 *142 (InitColHdr 1116 1186 tm "GenericValueColHdrMgr" 1117 1187 ) 1118 *1 35(PragmaColHdr1188 *143 (PragmaColHdr 1119 1189 tm "GenericPragmaColHdrMgr" 1120 1190 ) 1121 *1 36(EolColHdr1191 *144 (EolColHdr 1122 1192 tm "GenericEolColHdrMgr" 1123 1193 ) … … 1129 1199 uid 94,0 1130 1200 optionalChildren [ 1131 *1 37(Sheet1201 *145 (Sheet 1132 1202 sheetRow (SheetRow 1133 1203 headerVa (MVa … … 1146 1216 font "Tahoma,10,0" 1147 1217 ) 1148 emptyMRCItem *1 38(MRCItem1149 litem &1 251218 emptyMRCItem *146 (MRCItem 1219 litem &133 1150 1220 pos 3 1151 1221 dimension 20 … … 1153 1223 uid 96,0 1154 1224 optionalChildren [ 1155 *1 39(MRCItem1156 litem &1 261225 *147 (MRCItem 1226 litem &134 1157 1227 pos 0 1158 1228 dimension 20 1159 1229 uid 97,0 1160 1230 ) 1161 *14 0(MRCItem1162 litem &1 271231 *148 (MRCItem 1232 litem &135 1163 1233 pos 1 1164 1234 dimension 23 1165 1235 uid 98,0 1166 1236 ) 1167 *14 1(MRCItem1168 litem &1 281237 *149 (MRCItem 1238 litem &136 1169 1239 pos 2 1170 1240 hidden 1 … … 1183 1253 uid 100,0 1184 1254 optionalChildren [ 1185 *1 42(MRCItem1186 litem &1 291255 *150 (MRCItem 1256 litem &137 1187 1257 pos 0 1188 1258 dimension 20 1189 1259 uid 101,0 1190 1260 ) 1191 *1 43(MRCItem1192 litem &13 11261 *151 (MRCItem 1262 litem &139 1193 1263 pos 1 1194 1264 dimension 50 1195 1265 uid 102,0 1196 1266 ) 1197 *1 44(MRCItem1198 litem &1 321267 *152 (MRCItem 1268 litem &140 1199 1269 pos 2 1200 1270 dimension 100 1201 1271 uid 103,0 1202 1272 ) 1203 *1 45(MRCItem1204 litem &1 331273 *153 (MRCItem 1274 litem &141 1205 1275 pos 3 1206 1276 dimension 100 1207 1277 uid 104,0 1208 1278 ) 1209 *1 46(MRCItem1210 litem &1 341279 *154 (MRCItem 1280 litem &142 1211 1281 pos 4 1212 1282 dimension 50 1213 1283 uid 105,0 1214 1284 ) 1215 *1 47(MRCItem1216 litem &1 351285 *155 (MRCItem 1286 litem &143 1217 1287 pos 5 1218 1288 dimension 50 1219 1289 uid 106,0 1220 1290 ) 1221 *1 48(MRCItem1222 litem &1 361291 *156 (MRCItem 1292 litem &144 1223 1293 pos 6 1224 1294 dimension 80 … … 1243 1313 (vvPair 1244 1314 variable "HDLDir" 1245 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"1315 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" 1246 1316 ) 1247 1317 (vvPair 1248 1318 variable "HDSDir" 1249 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"1319 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 1250 1320 ) 1251 1321 (vvPair 1252 1322 variable "SideDataDesignDir" 1253 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info"1323 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info" 1254 1324 ) 1255 1325 (vvPair 1256 1326 variable "SideDataUserDir" 1257 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user"1327 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user" 1258 1328 ) 1259 1329 (vvPair 1260 1330 variable "SourceDir" 1261 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"1331 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 1262 1332 ) 1263 1333 (vvPair … … 1275 1345 (vvPair 1276 1346 variable "d" 1277 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board"1347 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board" 1278 1348 ) 1279 1349 (vvPair 1280 1350 variable "d_logical" 1281 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board"1351 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board" 1282 1352 ) 1283 1353 (vvPair 1284 1354 variable "date" 1285 value " 27.08.2010"1355 value "03.01.2011" 1286 1356 ) 1287 1357 (vvPair 1288 1358 variable "day" 1289 value " Fr"1359 value "Mo" 1290 1360 ) 1291 1361 (vvPair 1292 1362 variable "day_long" 1293 value " Freitag"1363 value "Montag" 1294 1364 ) 1295 1365 (vvPair 1296 1366 variable "dd" 1297 value " 27"1367 value "03" 1298 1368 ) 1299 1369 (vvPair … … 1355 1425 (vvPair 1356 1426 variable "mm" 1357 value "0 8"1427 value "01" 1358 1428 ) 1359 1429 (vvPair … … 1363 1433 (vvPair 1364 1434 variable "month" 1365 value " Aug"1435 value "Jan" 1366 1436 ) 1367 1437 (vvPair 1368 1438 variable "month_long" 1369 value " August"1439 value "Januar" 1370 1440 ) 1371 1441 (vvPair 1372 1442 variable "p" 1373 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb"1443 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb" 1374 1444 ) 1375 1445 (vvPair 1376 1446 variable "p_logical" 1377 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb"1447 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb" 1378 1448 ) 1379 1449 (vvPair … … 1431 1501 (vvPair 1432 1502 variable "time" 1433 value "1 7:10:56"1503 value "16:58:24" 1434 1504 ) 1435 1505 (vvPair … … 1451 1521 (vvPair 1452 1522 variable "year" 1453 value "201 0"1523 value "2011" 1454 1524 ) 1455 1525 (vvPair 1456 1526 variable "yy" 1457 value "1 0"1527 value "11" 1458 1528 ) 1459 1529 ] … … 1462 1532 uid 51,0 1463 1533 optionalChildren [ 1464 *1 49(SymbolBody1534 *157 (SymbolBody 1465 1535 uid 8,0 1466 1536 optionalChildren [ 1467 *15 0(CptPort1537 *158 (CptPort 1468 1538 uid 693,0 1469 1539 ps "OnEdgeStrategy" … … 1507 1577 font "Courier New,8,0" 1508 1578 ) 1509 xt "44000,29200,76000,30000" 1510 st "RSRLOAD : OUT std_logic := '0' ;" 1579 xt "44000,32400,76000,33200" 1580 st "RSRLOAD : OUT std_logic := '0' ; 1581 " 1511 1582 ) 1512 1583 thePort (LogicalPort … … 1515 1586 n "RSRLOAD" 1516 1587 t "std_logic" 1517 o 3 51588 o 39 1518 1589 suid 11,0 1519 1590 i "'0'" … … 1521 1592 ) 1522 1593 ) 1523 *15 1(CptPort1594 *159 (CptPort 1524 1595 uid 1116,0 1525 1596 ps "OnEdgeStrategy" … … 1552 1623 font "Courier New,8,0" 1553 1624 ) 1554 xt "44000,11600,61500,12400" 1555 st "X_50M : IN STD_LOGIC ;" 1625 xt "44000,14000,61500,14800" 1626 st "X_50M : IN STD_LOGIC ; 1627 " 1556 1628 ) 1557 1629 thePort (LogicalPort … … 1561 1633 preAdd 0 1562 1634 posAdd 0 1563 o 1 31635 o 16 1564 1636 suid 15,0 1565 1637 ) 1566 1638 ) 1567 1639 ) 1568 *1 52(CptPort1640 *160 (CptPort 1569 1641 uid 1121,0 1570 1642 ps "OnEdgeStrategy" … … 1597 1669 font "Courier New,8,0" 1598 1670 ) 1599 xt "44000,10000,61500,10800" 1600 st "TRG : IN STD_LOGIC ;" 1671 xt "44000,12400,61500,13200" 1672 st "TRG : IN STD_LOGIC ; 1673 " 1601 1674 ) 1602 1675 thePort (LogicalPort … … 1604 1677 n "TRG" 1605 1678 t "STD_LOGIC" 1606 o 1 11679 o 14 1607 1680 suid 16,0 1608 1681 ) 1609 1682 ) 1610 1683 ) 1611 *1 53(CptPort1684 *161 (CptPort 1612 1685 uid 1126,0 1613 1686 ps "OnEdgeStrategy" … … 1641 1714 font "Courier New,8,0" 1642 1715 ) 1643 xt "44000,14000,71500,14800" 1644 st "A_CLK : OUT std_logic_vector (3 downto 0) ;" 1716 xt "44000,16400,71500,17200" 1717 st "A_CLK : OUT std_logic_vector (3 downto 0) ; 1718 " 1645 1719 ) 1646 1720 thePort (LogicalPort … … 1650 1724 t "std_logic_vector" 1651 1725 b "(3 downto 0)" 1652 o 1 61726 o 19 1653 1727 suid 17,0 1654 1728 ) 1655 1729 ) 1656 1730 ) 1657 *1 54(CptPort1731 *162 (CptPort 1658 1732 uid 1166,0 1659 1733 ps "OnEdgeStrategy" … … 1687 1761 font "Courier New,8,0" 1688 1762 ) 1689 xt "44000,25200,61500,26000" 1690 st "OE_ADC : OUT STD_LOGIC ;" 1763 xt "44000,27600,61500,28400" 1764 st "OE_ADC : OUT STD_LOGIC ; 1765 " 1691 1766 ) 1692 1767 thePort (LogicalPort … … 1697 1772 preAdd 0 1698 1773 posAdd 0 1699 o 3 01774 o 33 1700 1775 suid 18,0 1701 1776 ) 1702 1777 ) 1703 1778 ) 1704 *1 55(CptPort1779 *163 (CptPort 1705 1780 uid 1171,0 1706 1781 ps "OnEdgeStrategy" … … 1734 1809 ) 1735 1810 xt "44000,5200,71500,6000" 1736 st "A_OTR : IN std_logic_vector (3 DOWNTO 0) ;" 1811 st "A_OTR : IN std_logic_vector (3 DOWNTO 0) ; 1812 " 1737 1813 ) 1738 1814 thePort (LogicalPort … … 1746 1822 ) 1747 1823 ) 1748 *1 56(CptPort1824 *164 (CptPort 1749 1825 uid 1176,0 1750 1826 ps "OnEdgeStrategy" … … 1778 1854 ) 1779 1855 xt "44000,2000,72000,2800" 1780 st "A0_D : IN std_logic_vector (11 DOWNTO 0) ;" 1856 st "A0_D : IN std_logic_vector (11 DOWNTO 0) ; 1857 " 1781 1858 ) 1782 1859 thePort (LogicalPort … … 1790 1867 ) 1791 1868 ) 1792 *1 57(CptPort1869 *165 (CptPort 1793 1870 uid 1181,0 1794 1871 ps "OnEdgeStrategy" … … 1822 1899 ) 1823 1900 xt "44000,2800,72000,3600" 1824 st "A1_D : IN std_logic_vector (11 DOWNTO 0) ;" 1901 st "A1_D : IN std_logic_vector (11 DOWNTO 0) ; 1902 " 1825 1903 ) 1826 1904 thePort (LogicalPort … … 1834 1912 ) 1835 1913 ) 1836 *1 58(CptPort1914 *166 (CptPort 1837 1915 uid 1186,0 1838 1916 ps "OnEdgeStrategy" … … 1866 1944 ) 1867 1945 xt "44000,3600,72000,4400" 1868 st "A2_D : IN std_logic_vector (11 DOWNTO 0) ;" 1946 st "A2_D : IN std_logic_vector (11 DOWNTO 0) ; 1947 " 1869 1948 ) 1870 1949 thePort (LogicalPort … … 1878 1957 ) 1879 1958 ) 1880 *1 59(CptPort1959 *167 (CptPort 1881 1960 uid 1191,0 1882 1961 ps "OnEdgeStrategy" … … 1910 1989 ) 1911 1990 xt "44000,4400,72000,5200" 1912 st "A3_D : IN std_logic_vector (11 DOWNTO 0) ;" 1991 st "A3_D : IN std_logic_vector (11 DOWNTO 0) ; 1992 " 1913 1993 ) 1914 1994 thePort (LogicalPort … … 1922 2002 ) 1923 2003 ) 1924 *16 0(CptPort2004 *168 (CptPort 1925 2005 uid 1227,0 1926 2006 ps "OnEdgeStrategy" … … 1954 2034 font "Courier New,8,0" 1955 2035 ) 1956 xt "44000,14800,61500,15600" 1957 st "D0_SRCLK : OUT STD_LOGIC ;" 2036 xt "44000,17200,61500,18000" 2037 st "D0_SRCLK : OUT STD_LOGIC ; 2038 " 1958 2039 ) 1959 2040 thePort (LogicalPort … … 1962 2043 n "D0_SRCLK" 1963 2044 t "STD_LOGIC" 1964 o 172045 o 20 1965 2046 suid 24,0 1966 2047 ) 1967 2048 ) 1968 2049 ) 1969 *16 1(CptPort2050 *169 (CptPort 1970 2051 uid 1232,0 1971 2052 ps "OnEdgeStrategy" … … 1999 2080 font "Courier New,8,0" 2000 2081 ) 2001 xt "44000,15600,61500,16400" 2002 st "D1_SRCLK : OUT STD_LOGIC ;" 2082 xt "44000,18000,61500,18800" 2083 st "D1_SRCLK : OUT STD_LOGIC ; 2084 " 2003 2085 ) 2004 2086 thePort (LogicalPort … … 2007 2089 n "D1_SRCLK" 2008 2090 t "STD_LOGIC" 2009 o 182091 o 21 2010 2092 suid 25,0 2011 2093 ) 2012 2094 ) 2013 2095 ) 2014 *1 62(CptPort2096 *170 (CptPort 2015 2097 uid 1237,0 2016 2098 ps "OnEdgeStrategy" … … 2044 2126 font "Courier New,8,0" 2045 2127 ) 2046 xt "44000,16400,61500,17200" 2047 st "D2_SRCLK : OUT STD_LOGIC ;" 2128 xt "44000,18800,61500,19600" 2129 st "D2_SRCLK : OUT STD_LOGIC ; 2130 " 2048 2131 ) 2049 2132 thePort (LogicalPort … … 2052 2135 n "D2_SRCLK" 2053 2136 t "STD_LOGIC" 2054 o 192137 o 22 2055 2138 suid 26,0 2056 2139 ) 2057 2140 ) 2058 2141 ) 2059 *1 63(CptPort2142 *171 (CptPort 2060 2143 uid 1242,0 2061 2144 ps "OnEdgeStrategy" … … 2089 2172 font "Courier New,8,0" 2090 2173 ) 2091 xt "44000,17200,61500,18000" 2092 st "D3_SRCLK : OUT STD_LOGIC ;" 2174 xt "44000,19600,61500,20400" 2175 st "D3_SRCLK : OUT STD_LOGIC ; 2176 " 2093 2177 ) 2094 2178 thePort (LogicalPort … … 2097 2181 n "D3_SRCLK" 2098 2182 t "STD_LOGIC" 2099 o 2 02183 o 23 2100 2184 suid 27,0 2101 2185 ) 2102 2186 ) 2103 2187 ) 2104 *1 64(CptPort2188 *172 (CptPort 2105 2189 uid 1282,0 2106 2190 ps "OnEdgeStrategy" … … 2134 2218 ) 2135 2219 xt "44000,6000,61500,6800" 2136 st "D0_SROUT : IN std_logic ;" 2220 st "D0_SROUT : IN std_logic ; 2221 " 2137 2222 ) 2138 2223 thePort (LogicalPort … … 2145 2230 ) 2146 2231 ) 2147 *1 65(CptPort2232 *173 (CptPort 2148 2233 uid 1287,0 2149 2234 ps "OnEdgeStrategy" … … 2177 2262 ) 2178 2263 xt "44000,6800,61500,7600" 2179 st "D1_SROUT : IN std_logic ;" 2264 st "D1_SROUT : IN std_logic ; 2265 " 2180 2266 ) 2181 2267 thePort (LogicalPort … … 2188 2274 ) 2189 2275 ) 2190 *1 66(CptPort2276 *174 (CptPort 2191 2277 uid 1292,0 2192 2278 ps "OnEdgeStrategy" … … 2220 2306 ) 2221 2307 xt "44000,7600,61500,8400" 2222 st "D2_SROUT : IN std_logic ;" 2308 st "D2_SROUT : IN std_logic ; 2309 " 2223 2310 ) 2224 2311 thePort (LogicalPort … … 2231 2318 ) 2232 2319 ) 2233 *1 67(CptPort2320 *175 (CptPort 2234 2321 uid 1297,0 2235 2322 ps "OnEdgeStrategy" … … 2263 2350 ) 2264 2351 xt "44000,8400,61500,9200" 2265 st "D3_SROUT : IN std_logic ;" 2352 st "D3_SROUT : IN std_logic ; 2353 " 2266 2354 ) 2267 2355 thePort (LogicalPort … … 2274 2362 ) 2275 2363 ) 2276 *1 68(CptPort2364 *176 (CptPort 2277 2365 uid 1302,0 2278 2366 ps "OnEdgeStrategy" … … 2316 2404 font "Courier New,8,0" 2317 2405 ) 2318 xt "44000,20400,82000,21200" 2319 st "D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ;" 2406 xt "44000,22800,82000,23600" 2407 st "D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ; 2408 " 2320 2409 ) 2321 2410 thePort (LogicalPort … … 2325 2414 t "std_logic_vector" 2326 2415 b "(3 DOWNTO 0)" 2327 o 2 42416 o 27 2328 2417 suid 32,0 2329 2418 i "(others => '0')" … … 2331 2420 ) 2332 2421 ) 2333 *1 69(CptPort2422 *177 (CptPort 2334 2423 uid 1308,0 2335 2424 ps "OnEdgeStrategy" … … 2373 2462 font "Courier New,8,0" 2374 2463 ) 2375 xt "44000,19600,76000,20400" 2376 st "DWRITE : OUT std_logic := '0' ;" 2464 xt "44000,22000,76000,22800" 2465 st "DWRITE : OUT std_logic := '0' ; 2466 " 2377 2467 ) 2378 2468 thePort (LogicalPort … … 2381 2471 n "DWRITE" 2382 2472 t "std_logic" 2383 o 2 32473 o 26 2384 2474 suid 33,0 2385 2475 i "'0'" … … 2387 2477 ) 2388 2478 ) 2389 *17 0(CptPort2479 *178 (CptPort 2390 2480 uid 1363,0 2391 2481 ps "OnEdgeStrategy" … … 2419 2509 font "Courier New,8,0" 2420 2510 ) 2421 xt "44000,18000,61500,18800" 2422 st "DAC_CS : OUT std_logic ;" 2511 xt "44000,20400,61500,21200" 2512 st "DAC_CS : OUT std_logic ; 2513 " 2423 2514 ) 2424 2515 thePort (LogicalPort … … 2427 2518 n "DAC_CS" 2428 2519 t "std_logic" 2429 o 2 12520 o 24 2430 2521 suid 34,0 2431 2522 ) 2432 2523 ) 2433 2524 ) 2434 *17 1(CptPort2525 *179 (CptPort 2435 2526 uid 1368,0 2436 2527 ps "OnEdgeStrategy" … … 2464 2555 font "Courier New,8,0" 2465 2556 ) 2466 xt "44000,31600,61500,32400" 2467 st "T0_CS : OUT std_logic ;" 2557 xt "44000,34800,61500,35600" 2558 st "T0_CS : OUT std_logic ; 2559 " 2468 2560 ) 2469 2561 thePort (LogicalPort … … 2472 2564 n "T0_CS" 2473 2565 t "std_logic" 2474 o 382566 o 42 2475 2567 suid 35,0 2476 2568 ) 2477 2569 ) 2478 2570 ) 2479 *1 72(CptPort2571 *180 (CptPort 2480 2572 uid 1373,0 2481 2573 ps "OnEdgeStrategy" … … 2509 2601 font "Courier New,8,0" 2510 2602 ) 2511 xt "44000,32400,61500,33200" 2512 st "T1_CS : OUT std_logic ;" 2603 xt "44000,35600,61500,36400" 2604 st "T1_CS : OUT std_logic ; 2605 " 2513 2606 ) 2514 2607 thePort (LogicalPort … … 2517 2610 n "T1_CS" 2518 2611 t "std_logic" 2519 o 392612 o 43 2520 2613 suid 36,0 2521 2614 ) 2522 2615 ) 2523 2616 ) 2524 *1 73(CptPort2617 *181 (CptPort 2525 2618 uid 1378,0 2526 2619 ps "OnEdgeStrategy" … … 2554 2647 font "Courier New,8,0" 2555 2648 ) 2556 xt "44000,33200,61500,34000" 2557 st "T2_CS : OUT std_logic ;" 2649 xt "44000,36400,61500,37200" 2650 st "T2_CS : OUT std_logic ; 2651 " 2558 2652 ) 2559 2653 thePort (LogicalPort … … 2562 2656 n "T2_CS" 2563 2657 t "std_logic" 2564 o 4 02658 o 44 2565 2659 suid 37,0 2566 2660 ) 2567 2661 ) 2568 2662 ) 2569 *1 74(CptPort2663 *182 (CptPort 2570 2664 uid 1383,0 2571 2665 ps "OnEdgeStrategy" … … 2599 2693 font "Courier New,8,0" 2600 2694 ) 2601 xt "44000,34000,61500,34800" 2602 st "T3_CS : OUT std_logic ;" 2695 xt "44000,37200,61500,38000" 2696 st "T3_CS : OUT std_logic ; 2697 " 2603 2698 ) 2604 2699 thePort (LogicalPort … … 2607 2702 n "T3_CS" 2608 2703 t "std_logic" 2609 o 4 12704 o 45 2610 2705 suid 38,0 2611 2706 ) 2612 2707 ) 2613 2708 ) 2614 *1 75(CptPort2709 *183 (CptPort 2615 2710 uid 1388,0 2616 2711 ps "OnEdgeStrategy" … … 2644 2739 font "Courier New,8,0" 2645 2740 ) 2646 xt "44000,30800,61500,31600" 2647 st "S_CLK : OUT std_logic ;" 2741 xt "44000,34000,61500,34800" 2742 st "S_CLK : OUT std_logic ; 2743 " 2648 2744 ) 2649 2745 thePort (LogicalPort … … 2652 2748 n "S_CLK" 2653 2749 t "std_logic" 2654 o 372750 o 41 2655 2751 suid 39,0 2656 2752 ) 2657 2753 ) 2658 2754 ) 2659 *1 76(CptPort2755 *184 (CptPort 2660 2756 uid 1393,0 2661 2757 ps "OnEdgeStrategy" … … 2689 2785 font "Courier New,8,0" 2690 2786 ) 2691 xt "44000,35600,71500,36400" 2692 st "W_A : OUT std_logic_vector (9 DOWNTO 0) ;" 2787 xt "44000,38800,71500,39600" 2788 st "W_A : OUT std_logic_vector (9 DOWNTO 0) ; 2789 " 2693 2790 ) 2694 2791 thePort (LogicalPort … … 2698 2795 t "std_logic_vector" 2699 2796 b "(9 DOWNTO 0)" 2700 o 4 32797 o 47 2701 2798 suid 40,0 2702 2799 ) 2703 2800 ) 2704 2801 ) 2705 *1 77(CptPort2802 *185 (CptPort 2706 2803 uid 1398,0 2707 2804 ps "OnEdgeStrategy" … … 2735 2832 font "Courier New,8,0" 2736 2833 ) 2737 xt "44000,40400,71000,41200" 2738 st "W_D : INOUT std_logic_vector (15 DOWNTO 0)" 2834 xt "44000,43600,71000,44400" 2835 st "W_D : INOUT std_logic_vector (15 DOWNTO 0) 2836 " 2739 2837 ) 2740 2838 thePort (LogicalPort … … 2744 2842 t "std_logic_vector" 2745 2843 b "(15 DOWNTO 0)" 2746 o 492844 o 53 2747 2845 suid 41,0 2748 2846 ) 2749 2847 ) 2750 2848 ) 2751 *1 78(CptPort2849 *186 (CptPort 2752 2850 uid 1403,0 2753 2851 ps "OnEdgeStrategy" … … 2791 2889 font "Courier New,8,0" 2792 2890 ) 2793 xt "44000,38000,76000,38800" 2794 st "W_RES : OUT std_logic := '1' ;" 2891 xt "44000,41200,76000,42000" 2892 st "W_RES : OUT std_logic := '1' ; 2893 " 2795 2894 ) 2796 2895 thePort (LogicalPort … … 2799 2898 n "W_RES" 2800 2899 t "std_logic" 2801 o 462900 o 50 2802 2901 suid 42,0 2803 2902 i "'1'" … … 2805 2904 ) 2806 2905 ) 2807 *1 79(CptPort2906 *187 (CptPort 2808 2907 uid 1409,0 2809 2908 ps "OnEdgeStrategy" … … 2847 2946 font "Courier New,8,0" 2848 2947 ) 2849 xt "44000,37200,76000,38000" 2850 st "W_RD : OUT std_logic := '1' ;" 2948 xt "44000,40400,76000,41200" 2949 st "W_RD : OUT std_logic := '1' ; 2950 " 2851 2951 ) 2852 2952 thePort (LogicalPort … … 2855 2955 n "W_RD" 2856 2956 t "std_logic" 2857 o 4 52957 o 49 2858 2958 suid 43,0 2859 2959 i "'1'" … … 2861 2961 ) 2862 2962 ) 2863 *18 0(CptPort2963 *188 (CptPort 2864 2964 uid 1415,0 2865 2965 ps "OnEdgeStrategy" … … 2903 3003 font "Courier New,8,0" 2904 3004 ) 2905 xt "44000,38800,76000,39600" 2906 st "W_WR : OUT std_logic := '1' ;" 3005 xt "44000,42000,76000,42800" 3006 st "W_WR : OUT std_logic := '1' ; 3007 " 2907 3008 ) 2908 3009 thePort (LogicalPort … … 2911 3012 n "W_WR" 2912 3013 t "std_logic" 2913 o 473014 o 51 2914 3015 suid 44,0 2915 3016 i "'1'" … … 2917 3018 ) 2918 3019 ) 2919 *18 1(CptPort3020 *189 (CptPort 2920 3021 uid 1421,0 2921 3022 ps "OnEdgeStrategy" … … 2948 3049 font "Courier New,8,0" 2949 3050 ) 2950 xt "44000,10800,61500,11600" 2951 st "W_INT : IN std_logic ;" 3051 xt "44000,13200,61500,14000" 3052 st "W_INT : IN std_logic ; 3053 " 2952 3054 ) 2953 3055 thePort (LogicalPort … … 2955 3057 n "W_INT" 2956 3058 t "std_logic" 2957 o 1 23059 o 15 2958 3060 suid 45,0 2959 3061 ) 2960 3062 ) 2961 3063 ) 2962 *1 82(CptPort3064 *190 (CptPort 2963 3065 uid 1426,0 2964 3066 ps "OnEdgeStrategy" … … 3002 3104 font "Courier New,8,0" 3003 3105 ) 3004 xt "44000,36400,76000,37200" 3005 st "W_CS : OUT std_logic := '1' ;" 3106 xt "44000,39600,76000,40400" 3107 st "W_CS : OUT std_logic := '1' ; 3108 " 3006 3109 ) 3007 3110 thePort (LogicalPort … … 3010 3113 n "W_CS" 3011 3114 t "std_logic" 3012 o 4 43115 o 48 3013 3116 suid 46,0 3014 3117 i "'1'" … … 3016 3119 ) 3017 3120 ) 3018 *1 83(CptPort3121 *191 (CptPort 3019 3122 uid 1620,0 3020 3123 ps "OnEdgeStrategy" … … 3058 3161 font "Courier New,8,0" 3059 3162 ) 3060 xt "44000,24400,76000,25200" 3061 st "MOSI : OUT std_logic := '0' ;" 3163 xt "44000,26800,76000,27600" 3164 st "MOSI : OUT std_logic := '0' ; 3165 " 3062 3166 ) 3063 3167 thePort (LogicalPort … … 3066 3170 n "MOSI" 3067 3171 t "std_logic" 3068 o 293172 o 32 3069 3173 suid 47,0 3070 3174 i "'0'" … … 3072 3176 ) 3073 3177 ) 3074 *1 84(CptPort3178 *192 (CptPort 3075 3179 uid 1626,0 3076 3180 ps "OnEdgeStrategy" … … 3104 3208 font "Courier New,8,0" 3105 3209 ) 3106 xt "44000,39600,61500,40400" 3107 st "MISO : INOUT std_logic ;" 3210 xt "44000,42800,61500,43600" 3211 st "MISO : INOUT std_logic ; 3212 " 3108 3213 ) 3109 3214 thePort (LogicalPort … … 3114 3219 preAdd 0 3115 3220 posAdd 0 3116 o 483221 o 52 3117 3222 suid 48,0 3118 3223 ) 3119 3224 ) 3120 3225 ) 3121 *1 85(CptPort3226 *193 (CptPort 3122 3227 uid 1676,0 3123 3228 ps "OnEdgeStrategy" … … 3151 3256 font "Courier New,8,0" 3152 3257 ) 3153 xt "44000,34800,61500,35600" 3154 st "TRG_V : OUT std_logic ;" 3258 xt "44000,38000,61500,38800" 3259 st "TRG_V : OUT std_logic ; 3260 " 3155 3261 ) 3156 3262 thePort (LogicalPort … … 3159 3265 n "TRG_V" 3160 3266 t "std_logic" 3161 o 4 23267 o 46 3162 3268 suid 49,0 3163 3269 ) 3164 3270 ) 3165 3271 ) 3166 *1 86(CptPort3272 *194 (CptPort 3167 3273 uid 1681,0 3168 3274 ps "OnEdgeStrategy" … … 3196 3302 font "Courier New,8,0" 3197 3303 ) 3198 xt "44000,26800,61500,27600" 3199 st "RS485_C_RE : OUT std_logic ;" 3304 xt "44000,30000,61500,30800" 3305 st "RS485_C_RE : OUT std_logic ; 3306 " 3200 3307 ) 3201 3308 thePort (LogicalPort … … 3204 3311 n "RS485_C_RE" 3205 3312 t "std_logic" 3206 o 3 23313 o 36 3207 3314 suid 50,0 3208 3315 ) 3209 3316 ) 3210 3317 ) 3211 *1 87(CptPort3318 *195 (CptPort 3212 3319 uid 1686,0 3213 3320 ps "OnEdgeStrategy" … … 3241 3348 font "Courier New,8,0" 3242 3349 ) 3243 xt "44000,26000,61500,26800" 3244 st "RS485_C_DE : OUT std_logic ;" 3350 xt "44000,28400,61500,29200" 3351 st "RS485_C_DE : OUT std_logic ; 3352 " 3245 3353 ) 3246 3354 thePort (LogicalPort … … 3249 3357 n "RS485_C_DE" 3250 3358 t "std_logic" 3251 o 3 13359 o 34 3252 3360 suid 51,0 3253 3361 ) 3254 3362 ) 3255 3363 ) 3256 *1 88(CptPort3364 *196 (CptPort 3257 3365 uid 1691,0 3258 3366 ps "OnEdgeStrategy" … … 3286 3394 font "Courier New,8,0" 3287 3395 ) 3288 xt "44000,28400,61500,29200" 3289 st "RS485_E_RE : OUT std_logic ;" 3396 xt "44000,31600,61500,32400" 3397 st "RS485_E_RE : OUT std_logic ; 3398 " 3290 3399 ) 3291 3400 thePort (LogicalPort … … 3294 3403 n "RS485_E_RE" 3295 3404 t "std_logic" 3296 o 3 43405 o 38 3297 3406 suid 52,0 3298 3407 ) 3299 3408 ) 3300 3409 ) 3301 *1 89(CptPort3410 *197 (CptPort 3302 3411 uid 1696,0 3303 3412 ps "OnEdgeStrategy" … … 3331 3440 font "Courier New,8,0" 3332 3441 ) 3333 xt "44000,27600,61500,28400" 3334 st "RS485_E_DE : OUT std_logic ;" 3442 xt "44000,30800,61500,31600" 3443 st "RS485_E_DE : OUT std_logic ; 3444 " 3335 3445 ) 3336 3446 thePort (LogicalPort … … 3339 3449 n "RS485_E_DE" 3340 3450 t "std_logic" 3341 o 3 33451 o 37 3342 3452 suid 53,0 3343 3453 ) 3344 3454 ) 3345 3455 ) 3346 *19 0(CptPort3456 *198 (CptPort 3347 3457 uid 1701,0 3348 3458 ps "OnEdgeStrategy" … … 3386 3496 font "Courier New,8,0" 3387 3497 ) 3388 xt "44000,18800,76000,19600" 3389 st "DENABLE : OUT std_logic := '0' ;" 3498 xt "44000,21200,76000,22000" 3499 st "DENABLE : OUT std_logic := '0' ; 3500 " 3390 3501 ) 3391 3502 thePort (LogicalPort … … 3394 3505 n "DENABLE" 3395 3506 t "std_logic" 3396 o 2 23507 o 25 3397 3508 suid 54,0 3398 3509 i "'0'" … … 3400 3511 ) 3401 3512 ) 3402 *19 1(CptPort3513 *199 (CptPort 3403 3514 uid 1706,0 3404 3515 ps "OnEdgeStrategy" … … 3426 3537 tm "CptPortNameMgr" 3427 3538 ) 3539 t (Text 3540 va (VaSet 3541 ) 3542 xt "30800,74500,32000,75500" 3543 st "'0'" 3544 ju 2 3545 blo "32000,75300" 3546 tm "InitValueDelayMgr" 3547 ) 3428 3548 ) 3429 3549 dt (MLText … … 3432 3552 font "Courier New,8,0" 3433 3553 ) 3434 xt "44000,30000,61500,30800" 3435 st "SRIN : OUT std_logic ;" 3554 xt "44000,33200,76000,34000" 3555 st "SRIN : OUT std_logic := '0' ; 3556 " 3436 3557 ) 3437 3558 thePort (LogicalPort … … 3440 3561 n "SRIN" 3441 3562 t "std_logic" 3442 o 363563 o 40 3443 3564 suid 55,0 3444 ) 3445 ) 3446 ) 3447 *192 (CptPort 3565 i "'0'" 3566 ) 3567 ) 3568 ) 3569 *200 (CptPort 3448 3570 uid 1711,0 3449 3571 ps "OnEdgeStrategy" … … 3477 3599 font "Courier New,8,0" 3478 3600 ) 3479 xt "44000,22800,61500,23600" 3480 st "EE_CS : OUT std_logic ;" 3601 xt "44000,25200,61500,26000" 3602 st "EE_CS : OUT std_logic ; 3603 " 3481 3604 ) 3482 3605 thePort (LogicalPort … … 3485 3608 n "EE_CS" 3486 3609 t "std_logic" 3487 o 273610 o 30 3488 3611 suid 56,0 3489 3612 ) 3490 3613 ) 3491 3614 ) 3492 * 193(CptPort3615 *201 (CptPort 3493 3616 uid 2068,0 3494 3617 ps "OnEdgeStrategy" … … 3532 3655 font "Courier New,8,0" 3533 3656 ) 3534 xt "44000,21200,82000,22000" 3535 st "D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;" 3657 xt "44000,23600,82000,24400" 3658 st "D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; 3659 " 3536 3660 ) 3537 3661 thePort (LogicalPort … … 3541 3665 t "std_logic_vector" 3542 3666 b "(7 DOWNTO 0)" 3543 o 2 53667 o 28 3544 3668 suid 61,0 3545 3669 i "(OTHERS => '0')" … … 3547 3671 ) 3548 3672 ) 3549 * 194(CptPort3673 *202 (CptPort 3550 3674 uid 2375,0 3551 3675 ps "OnEdgeStrategy" … … 3589 3713 font "Courier New,8,0" 3590 3714 ) 3591 xt "44000,23600,82000,24400" 3592 st "LED : OUT std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ;" 3715 xt "44000,26000,82000,26800" 3716 st "LED : OUT std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ; 3717 " 3593 3718 ) 3594 3719 thePort (LogicalPort … … 3598 3723 t "std_logic_vector" 3599 3724 b "( 2 DOWNTO 0 )" 3600 o 283725 o 31 3601 3726 suid 62,0 3602 3727 i "(others => '1')" … … 3604 3729 ) 3605 3730 ) 3606 * 195(CptPort3731 *203 (CptPort 3607 3732 uid 2919,0 3608 3733 ps "OnEdgeStrategy" … … 3636 3761 ) 3637 3762 xt "44000,9200,71500,10000" 3638 st "D_PLLLCK : IN std_logic_vector (3 DOWNTO 0) ;" 3763 st "D_PLLLCK : IN std_logic_vector (3 DOWNTO 0) ; 3764 " 3639 3765 ) 3640 3766 thePort (LogicalPort … … 3648 3774 ) 3649 3775 ) 3650 * 196(CptPort3776 *204 (CptPort 3651 3777 uid 2949,0 3652 3778 ps "OnEdgeStrategy" … … 3690 3816 font "Courier New,8,0" 3691 3817 ) 3692 xt "44000,22000,82000,22800" 3693 st "D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ;" 3818 xt "44000,24400,82000,25200" 3819 st "D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ; 3820 " 3694 3821 ) 3695 3822 thePort (LogicalPort … … 3699 3826 t "std_logic_vector" 3700 3827 b "(3 DOWNTO 0)" 3701 o 2 63828 o 29 3702 3829 suid 65,0 3703 3830 i "(others => '0')" … … 3705 3832 ) 3706 3833 ) 3707 * 197(CptPort3834 *205 (CptPort 3708 3835 uid 3026,0 3709 3836 ps "OnEdgeStrategy" … … 3747 3874 font "Courier New,8,0" 3748 3875 ) 3749 xt "44000,13200,82000,14000" 3750 st "A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;" 3876 xt "44000,15600,82000,16400" 3877 st "A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; 3878 " 3751 3879 ) 3752 3880 thePort (LogicalPort … … 3756 3884 t "std_logic_vector" 3757 3885 b "(7 DOWNTO 0)" 3758 o 1 53886 o 18 3759 3887 suid 66,0 3760 3888 i "(OTHERS => '0')" … … 3762 3890 ) 3763 3891 ) 3764 * 198(CptPort3892 *206 (CptPort 3765 3893 uid 3456,0 3766 3894 ps "OnEdgeStrategy" … … 3804 3932 font "Courier New,8,0" 3805 3933 ) 3806 xt "44000,12400,82000,13200" 3807 st "A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0') ;" 3934 xt "44000,14800,82000,15600" 3935 st "A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0') ; 3936 " 3808 3937 ) 3809 3938 thePort (LogicalPort … … 3813 3942 t "std_logic_vector" 3814 3943 b "(7 DOWNTO 0)" 3815 o 1 43944 o 17 3816 3945 suid 68,0 3817 3946 i "(others => '0')" 3947 ) 3948 ) 3949 ) 3950 *207 (CptPort 3951 uid 3581,0 3952 ps "OnEdgeStrategy" 3953 shape (Triangle 3954 uid 3582,0 3955 ro 90 3956 va (VaSet 3957 vasetType 1 3958 fg "0,65535,0" 3959 ) 3960 xt "14250,47625,15000,48375" 3961 ) 3962 tg (CPTG 3963 uid 3583,0 3964 ps "CptPortTextPlaceStrategy" 3965 stg "VerticalLayoutStrategy" 3966 f (Text 3967 uid 3584,0 3968 va (VaSet 3969 ) 3970 xt "16000,47500,21300,48500" 3971 st "RS485_C_DI" 3972 blo "16000,48300" 3973 tm "CptPortNameMgr" 3974 ) 3975 ) 3976 dt (MLText 3977 uid 3585,0 3978 va (VaSet 3979 font "Courier New,8,0" 3980 ) 3981 xt "44000,10000,61500,10800" 3982 st "RS485_C_DI : IN std_logic ; 3983 " 3984 ) 3985 thePort (LogicalPort 3986 decl (Decl 3987 n "RS485_C_DI" 3988 t "std_logic" 3989 o 11 3990 suid 69,0 3991 ) 3992 ) 3993 ) 3994 *208 (CptPort 3995 uid 3586,0 3996 ps "OnEdgeStrategy" 3997 shape (Triangle 3998 uid 3587,0 3999 ro 90 4000 va (VaSet 4001 vasetType 1 4002 fg "0,65535,0" 4003 ) 4004 xt "33000,101625,33750,102375" 4005 ) 4006 tg (CPTG 4007 uid 3588,0 4008 ps "CptPortTextPlaceStrategy" 4009 stg "RightVerticalLayoutStrategy" 4010 f (Text 4011 uid 3589,0 4012 va (VaSet 4013 ) 4014 xt "26300,101500,32000,102500" 4015 st "RS485_C_DO" 4016 ju 2 4017 blo "32000,102300" 4018 tm "CptPortNameMgr" 4019 ) 4020 ) 4021 dt (MLText 4022 uid 3590,0 4023 va (VaSet 4024 font "Courier New,8,0" 4025 ) 4026 xt "44000,29200,61500,30000" 4027 st "RS485_C_DO : OUT std_logic ; 4028 " 4029 ) 4030 thePort (LogicalPort 4031 m 1 4032 decl (Decl 4033 n "RS485_C_DO" 4034 t "std_logic" 4035 o 35 4036 suid 70,0 4037 ) 4038 ) 4039 ) 4040 *209 (CptPort 4041 uid 3687,0 4042 ps "OnEdgeStrategy" 4043 shape (Triangle 4044 uid 3688,0 4045 ro 90 4046 va (VaSet 4047 vasetType 1 4048 fg "0,65535,0" 4049 ) 4050 xt "14250,49625,15000,50375" 4051 ) 4052 tg (CPTG 4053 uid 3689,0 4054 ps "CptPortTextPlaceStrategy" 4055 stg "VerticalLayoutStrategy" 4056 f (Text 4057 uid 3690,0 4058 va (VaSet 4059 ) 4060 xt "16000,49500,21200,50500" 4061 st "RS485_E_DI" 4062 blo "16000,50300" 4063 tm "CptPortNameMgr" 4064 ) 4065 ) 4066 dt (MLText 4067 uid 3691,0 4068 va (VaSet 4069 font "Courier New,8,0" 4070 ) 4071 xt "44000,10800,61500,11600" 4072 st "RS485_E_DI : IN std_logic ; 4073 " 4074 ) 4075 thePort (LogicalPort 4076 decl (Decl 4077 n "RS485_E_DI" 4078 t "std_logic" 4079 o 12 4080 suid 71,0 4081 ) 4082 ) 4083 ) 4084 *210 (CptPort 4085 uid 3692,0 4086 ps "OnEdgeStrategy" 4087 shape (Triangle 4088 uid 3789,0 4089 ro 90 4090 va (VaSet 4091 vasetType 1 4092 fg "0,65535,0" 4093 ) 4094 xt "14250,51625,15000,52375" 4095 ) 4096 tg (CPTG 4097 uid 3694,0 4098 ps "CptPortTextPlaceStrategy" 4099 stg "VerticalLayoutStrategy" 4100 f (Text 4101 uid 3695,0 4102 va (VaSet 4103 ) 4104 xt "16000,51500,21600,52500" 4105 st "RS485_E_DO" 4106 blo "16000,52300" 4107 tm "CptPortNameMgr" 4108 ) 4109 ) 4110 dt (MLText 4111 uid 3696,0 4112 va (VaSet 4113 font "Courier New,8,0" 4114 ) 4115 xt "44000,11600,61500,12400" 4116 st "RS485_E_DO : IN std_logic ; 4117 " 4118 ) 4119 thePort (LogicalPort 4120 decl (Decl 4121 n "RS485_E_DO" 4122 t "std_logic" 4123 o 13 4124 suid 72,0 3818 4125 ) 3819 4126 ) … … 3828 4135 lineWidth 2 3829 4136 ) 3830 xt "15000,6000,33000,10 1000"4137 xt "15000,6000,33000,105000" 3831 4138 ) 3832 4139 oxt "15000,6000,33000,26000" … … 3854 4161 ) 3855 4162 ) 3856 gi * 199(GenericInterface4163 gi *211 (GenericInterface 3857 4164 uid 13,0 3858 4165 ps "CenterOffsetStrategy" … … 3881 4188 ) 3882 4189 ) 3883 *2 00(Grouping4190 *212 (Grouping 3884 4191 uid 16,0 3885 4192 optionalChildren [ 3886 *2 01(CommentText4193 *213 (CommentText 3887 4194 uid 18,0 3888 4195 shape (Rectangle … … 3902 4209 bg "0,0,32768" 3903 4210 ) 3904 xt "36200,48000,45 900,49000"4211 xt "36200,48000,45700,49000" 3905 4212 st " 3906 4213 by %user on %dd %month %year … … 3915 4222 titleBlock 1 3916 4223 ) 3917 *2 02(CommentText4224 *214 (CommentText 3918 4225 uid 21,0 3919 4226 shape (Rectangle … … 3946 4253 titleBlock 1 3947 4254 ) 3948 *2 03(CommentText4255 *215 (CommentText 3949 4256 uid 24,0 3950 4257 shape (Rectangle … … 3977 4284 titleBlock 1 3978 4285 ) 3979 *2 04(CommentText4286 *216 (CommentText 3980 4287 uid 27,0 3981 4288 shape (Rectangle … … 4008 4315 titleBlock 1 4009 4316 ) 4010 *2 05(CommentText4317 *217 (CommentText 4011 4318 uid 30,0 4012 4319 shape (Rectangle … … 4038 4345 titleBlock 1 4039 4346 ) 4040 *2 06(CommentText4347 *218 (CommentText 4041 4348 uid 33,0 4042 4349 shape (Rectangle … … 4069 4376 titleBlock 1 4070 4377 ) 4071 *2 07(CommentText4378 *219 (CommentText 4072 4379 uid 36,0 4073 4380 shape (Rectangle … … 4101 4408 titleBlock 1 4102 4409 ) 4103 *2 08(CommentText4410 *220 (CommentText 4104 4411 uid 39,0 4105 4412 shape (Rectangle … … 4132 4439 titleBlock 1 4133 4440 ) 4134 *2 09(CommentText4441 *221 (CommentText 4135 4442 uid 42,0 4136 4443 shape (Rectangle … … 4163 4470 titleBlock 1 4164 4471 ) 4165 *2 10(CommentText4472 *222 (CommentText 4166 4473 uid 45,0 4167 4474 shape (Rectangle … … 4219 4526 color "26368,26368,26368" 4220 4527 ) 4221 packageList *2 11(PackageList4528 packageList *223 (PackageList 4222 4529 uid 48,0 4223 4530 stg "VerticalLayoutStrategy" 4224 4531 textVec [ 4225 *2 12(Text4532 *224 (Text 4226 4533 uid 49,0 4227 4534 va (VaSet … … 4232 4539 blo "0,800" 4233 4540 ) 4234 *2 13(MLText4541 *225 (MLText 4235 4542 uid 50,0 4236 4543 va (VaSet … … 4330 4637 ) 4331 4638 ) 4332 gi *2 14(GenericInterface4639 gi *226 (GenericInterface 4333 4640 ps "CenterOffsetStrategy" 4334 4641 matrix (Matrix … … 4427 4734 ) 4428 4735 ) 4429 DeclarativeBlock *2 15(SymDeclBlock4736 DeclarativeBlock *227 (SymDeclBlock 4430 4737 uid 1,0 4431 4738 stg "SymDeclLayoutStrategy" … … 4453 4760 font "Arial,8,1" 4454 4761 ) 4455 xt "42000,4 1200,44400,42200"4762 xt "42000,44400,44400,45400" 4456 4763 st "User:" 4457 blo "42000,4 2000"4764 blo "42000,45200" 4458 4765 ) 4459 4766 internalLabel (Text … … 4472 4779 font "Courier New,8,0" 4473 4780 ) 4474 xt "44000,4 2200,44000,42200"4781 xt "44000,45400,44000,45400" 4475 4782 tm "SyDeclarativeTextMgr" 4476 4783 ) … … 4485 4792 ) 4486 4793 ) 4487 lastUid 3 530,04794 lastUid 3958,0 4488 4795 activeModelName "Symbol:CDM" 4489 4796 ) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd
r9912 r10073 224 224 uid 9957,0 225 225 ) 226 (Instance 227 name "U_9" 228 duLibraryName "moduleware" 229 duName "or" 230 elements [ 231 ] 232 mwi 1 233 uid 10380,0 234 ) 226 235 ] 227 236 libraryRefs [ … … 239 248 (vvPair 240 249 variable "HDLDir" 241 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"250 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" 242 251 ) 243 252 (vvPair 244 253 variable "HDSDir" 245 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"254 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 246 255 ) 247 256 (vvPair 248 257 variable "SideDataDesignDir" 249 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info"258 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info" 250 259 ) 251 260 (vvPair 252 261 variable "SideDataUserDir" 253 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user"262 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user" 254 263 ) 255 264 (vvPair 256 265 variable "SourceDir" 257 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"266 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 258 267 ) 259 268 (vvPair … … 271 280 (vvPair 272 281 variable "d" 273 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main"282 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main" 274 283 ) 275 284 (vvPair 276 285 variable "d_logical" 277 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_main"286 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main" 278 287 ) 279 288 (vvPair 280 289 variable "date" 281 value " 30.08.2010"290 value "04.01.2011" 282 291 ) 283 292 (vvPair 284 293 variable "day" 285 value " Mo"294 value "Di" 286 295 ) 287 296 (vvPair 288 297 variable "day_long" 289 value " Montag"298 value "Dienstag" 290 299 ) 291 300 (vvPair 292 301 variable "dd" 293 value " 30"302 value "04" 294 303 ) 295 304 (vvPair … … 355 364 (vvPair 356 365 variable "mm" 357 value "0 8"366 value "01" 358 367 ) 359 368 (vvPair … … 363 372 (vvPair 364 373 variable "month" 365 value " Aug"374 value "Jan" 366 375 ) 367 376 (vvPair 368 377 variable "month_long" 369 value " August"378 value "Januar" 370 379 ) 371 380 (vvPair 372 381 variable "p" 373 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd"382 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd" 374 383 ) 375 384 (vvPair 376 385 variable "p_logical" 377 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd"386 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd" 378 387 ) 379 388 (vvPair … … 431 440 (vvPair 432 441 variable "time" 433 value "1 0:49:09"442 value "11:02:29" 434 443 ) 435 444 (vvPair … … 451 460 (vvPair 452 461 variable "year" 453 value "201 0"462 value "2011" 454 463 ) 455 464 (vvPair 456 465 variable "yy" 457 value "1 0"466 value "11" 458 467 ) 459 468 ] … … 522 531 font "Courier New,8,0" 523 532 ) 524 xt "-103000,105000,-59500,105800" 525 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\" 526 " 533 xt "-103000,114600,-59500,115400" 534 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\"" 527 535 ) 528 536 ) … … 541 549 font "Courier New,8,0" 542 550 ) 543 xt "-103000,61000,-63000,61800" 544 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 545 " 551 xt "-103000,61800,-63000,62600" 552 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 546 553 ) 547 554 ) … … 560 567 font "Courier New,8,0" 561 568 ) 562 xt "-103000,75400,-70500,76200" 563 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0) 564 " 569 xt "-103000,79400,-70500,80200" 570 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0)" 565 571 ) 566 572 ) … … 579 585 font "Courier New,8,0" 580 586 ) 581 xt "-103000,87400,-63000,88200" 582 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) 583 " 587 xt "-103000,92200,-63000,93000" 588 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)" 584 589 ) 585 590 ) … … 598 603 font "Courier New,8,0" 599 604 ) 600 xt "-103000,88200,-70500,89000" 601 st "SIGNAL ram_data : std_logic_vector(15 downto 0) 602 " 605 xt "-103000,93000,-70500,93800" 606 st "SIGNAL ram_data : std_logic_vector(15 downto 0)" 603 607 ) 604 608 ) … … 617 621 font "Courier New,8,0" 618 622 ) 619 xt "-103000,52600,-63000,53400" 620 st "wiz_reset : std_logic := '1' 621 " 623 xt "-103000,53400,-63000,54200" 624 st "wiz_reset : std_logic := '1'" 622 625 ) 623 626 ) … … 636 639 font "Courier New,8,0" 637 640 ) 638 xt "-103000,50200,-74500,51000" 639 st "wiz_addr : std_logic_vector(9 DOWNTO 0) 640 " 641 xt "-103000,51000,-74500,51800" 642 st "wiz_addr : std_logic_vector(9 DOWNTO 0)" 641 643 ) 642 644 ) … … 655 657 font "Courier New,8,0" 656 658 ) 657 xt "-103000,55000,-74000,55800" 658 st "wiz_data : std_logic_vector(15 DOWNTO 0) 659 " 659 xt "-103000,55800,-74000,56600" 660 st "wiz_data : std_logic_vector(15 DOWNTO 0)" 660 661 ) 661 662 ) … … 674 675 font "Courier New,8,0" 675 676 ) 676 xt "-103000,51000,-63000,51800" 677 st "wiz_cs : std_logic := '1' 678 " 677 xt "-103000,51800,-63000,52600" 678 st "wiz_cs : std_logic := '1'" 679 679 ) 680 680 ) … … 693 693 font "Courier New,8,0" 694 694 ) 695 xt "-103000,53400,-63000,54200" 696 st "wiz_wr : std_logic := '1' 697 " 695 xt "-103000,54200,-63000,55000" 696 st "wiz_wr : std_logic := '1'" 698 697 ) 699 698 ) … … 712 711 font "Courier New,8,0" 713 712 ) 714 xt "-103000,51800,-63000,52600" 715 st "wiz_rd : std_logic := '1' 716 " 713 xt "-103000,52600,-63000,53400" 714 st "wiz_rd : std_logic := '1'" 717 715 ) 718 716 ) … … 731 729 ) 732 730 xt "-103000,26200,-84500,27000" 733 st "wiz_int : std_logic 734 " 731 st "wiz_int : std_logic" 735 732 ) 736 733 ) … … 748 745 sl 0 749 746 ro 270 750 xt "15 3500,51625,155000,52375"747 xt "154500,51625,156000,52375" 751 748 ) 752 749 (Line … … 754 751 sl 0 755 752 ro 270 756 xt "15 3000,52000,153500,52000"757 pts [ 758 "15 3000,52000"759 "15 3500,52000"753 xt "154000,52000,154500,52000" 754 pts [ 755 "154000,52000" 756 "154500,52000" 760 757 ] 761 758 ) … … 771 768 va (VaSet 772 769 ) 773 xt "15 6000,51500,159600,52500"770 xt "157000,51500,160600,52500" 774 771 st "wiz_reset" 775 blo "15 6000,52300"772 blo "157000,52300" 776 773 tm "WireNameMgr" 777 774 ) … … 791 788 sl 0 792 789 ro 270 793 xt "15 3500,59625,155000,60375"790 xt "154500,59625,156000,60375" 794 791 ) 795 792 (Line … … 797 794 sl 0 798 795 ro 270 799 xt "15 3000,60000,153500,60000"800 pts [ 801 "15 3000,60000"802 "15 3500,60000"796 xt "154000,60000,154500,60000" 797 pts [ 798 "154000,60000" 799 "154500,60000" 803 800 ] 804 801 ) … … 814 811 va (VaSet 815 812 ) 816 xt "15 6000,59500,162000,60500"813 xt "157000,59500,163000,60500" 817 814 st "wiz_addr : (9:0)" 818 blo "15 6000,60300"815 blo "157000,60300" 819 816 tm "WireNameMgr" 820 817 ) … … 833 830 uid 468,0 834 831 sl 0 835 xt "15 3500,60625,155000,61375"832 xt "154500,60625,156000,61375" 836 833 ) 837 834 (Line 838 835 uid 469,0 839 836 sl 0 840 xt "15 3000,61000,153500,61000"841 pts [ 842 "15 3000,61000"843 "15 3500,61000"837 xt "154000,61000,154500,61000" 838 pts [ 839 "154000,61000" 840 "154500,61000" 844 841 ] 845 842 ) … … 855 852 va (VaSet 856 853 ) 857 xt "15 6000,60500,162300,61500"854 xt "157000,60500,163300,61500" 858 855 st "wiz_data : (15:0)" 859 blo "15 6000,61300"856 blo "157000,61300" 860 857 tm "WireNameMgr" 861 858 ) … … 875 872 sl 0 876 873 ro 270 877 xt "15 3500,52625,155000,53375"874 xt "154500,52625,156000,53375" 878 875 ) 879 876 (Line … … 881 878 sl 0 882 879 ro 270 883 xt "15 3000,53000,153500,53000"884 pts [ 885 "15 3000,53000"886 "15 3500,53000"880 xt "154000,53000,154500,53000" 881 pts [ 882 "154000,53000" 883 "154500,53000" 887 884 ] 888 885 ) … … 899 896 va (VaSet 900 897 ) 901 xt "15 6000,52500,158700,53500"898 xt "157000,52500,159700,53500" 902 899 st "wiz_cs" 903 blo "15 6000,53300"900 blo "157000,53300" 904 901 tm "WireNameMgr" 905 902 ) … … 919 916 sl 0 920 917 ro 270 921 xt "15 3500,53625,155000,54375"918 xt "154500,53625,156000,54375" 922 919 ) 923 920 (Line … … 925 922 sl 0 926 923 ro 270 927 xt "15 3000,54000,153500,54000"928 pts [ 929 "15 3000,54000"930 "15 3500,54000"924 xt "154000,54000,154500,54000" 925 pts [ 926 "154000,54000" 927 "154500,54000" 931 928 ] 932 929 ) … … 943 940 va (VaSet 944 941 ) 945 xt "15 6000,53500,158700,54500"942 xt "157000,53500,159700,54500" 946 943 st "wiz_wr" 947 blo "15 6000,54300"944 blo "157000,54300" 948 945 tm "WireNameMgr" 949 946 ) … … 963 960 sl 0 964 961 ro 270 965 xt "15 3500,70625,155000,71375"962 xt "154500,70625,156000,71375" 966 963 ) 967 964 (Line … … 969 966 sl 0 970 967 ro 270 971 xt "15 3000,71000,153500,71000"972 pts [ 973 "15 3000,71000"974 "15 3500,71000"968 xt "154000,71000,154500,71000" 969 pts [ 970 "154000,71000" 971 "154500,71000" 975 972 ] 976 973 ) … … 986 983 va (VaSet 987 984 ) 988 xt "15 6000,70500,160000,71500"985 xt "157000,70500,161000,71500" 989 986 st "led : (7:0)" 990 blo "15 6000,71300"987 blo "157000,71300" 991 988 tm "WireNameMgr" 992 989 ) … … 1006 1003 sl 0 1007 1004 ro 270 1008 xt "15 3500,54625,155000,55375"1005 xt "154500,54625,156000,55375" 1009 1006 ) 1010 1007 (Line … … 1012 1009 sl 0 1013 1010 ro 270 1014 xt "15 3000,55000,153500,55000"1015 pts [ 1016 "15 3000,55000"1017 "15 3500,55000"1011 xt "154000,55000,154500,55000" 1012 pts [ 1013 "154000,55000" 1014 "154500,55000" 1018 1015 ] 1019 1016 ) … … 1030 1027 va (VaSet 1031 1028 ) 1032 xt "15 6000,54500,158600,55500"1029 xt "157000,54500,159600,55500" 1033 1030 st "wiz_rd" 1034 blo "15 6000,55300"1031 blo "157000,55300" 1035 1032 tm "WireNameMgr" 1036 1033 ) … … 1050 1047 sl 0 1051 1048 ro 90 1052 xt "15 3500,55625,155000,56375"1049 xt "154500,55625,156000,56375" 1053 1050 ) 1054 1051 (Line … … 1056 1053 sl 0 1057 1054 ro 90 1058 xt "15 3000,56000,153500,56000"1059 pts [ 1060 "15 3500,56000"1061 "15 3000,56000"1055 xt "154000,56000,154500,56000" 1056 pts [ 1057 "154500,56000" 1058 "154000,56000" 1062 1059 ] 1063 1060 ) … … 1074 1071 va (VaSet 1075 1072 ) 1076 xt "15 6000,55500,158700,56500"1073 xt "157000,55500,159700,56500" 1077 1074 st "wiz_int" 1078 blo "15 6000,56300"1075 blo "157000,56300" 1079 1076 tm "WireNameMgr" 1080 1077 ) … … 1113 1110 n "clk" 1114 1111 t "std_logic" 1112 prec "-- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');" 1115 1113 preAdd 0 1116 1114 posAdd 0 … … 1308 1306 preAdd 0 1309 1307 posAdd 0 1310 o 2 31308 o 24 1311 1309 suid 9,0 1312 1310 ) … … 1345 1343 preAdd 0 1346 1344 posAdd 0 1347 o 2 51345 o 26 1348 1346 suid 10,0 1349 1347 ) … … 1381 1379 preAdd 0 1382 1380 posAdd 0 1383 o 2 61381 o 27 1384 1382 suid 11,0 1385 1383 ) … … 1416 1414 t "std_logic_vector" 1417 1415 b "(1 downto 0)" 1418 o 2 41416 o 25 1419 1417 suid 12,0 1420 1418 ) … … 1487 1485 n "ram_write_ready" 1488 1486 t "std_logic" 1487 posAdd 0 1489 1488 o 7 1490 1489 suid 17,0 … … 1523 1522 n "roi_max" 1524 1523 t "roi_max_type" 1525 o 1 81524 o 19 1526 1525 suid 18,0 1527 1526 ) … … 1558 1557 n "roi_array" 1559 1558 t "roi_array_type" 1560 o 1 71559 o 18 1561 1560 suid 19,0 1562 1561 ) … … 1594 1593 t "std_logic_vector" 1595 1594 b "(15 downto 0)" 1596 o 2 21595 o 23 1597 1596 suid 20,0 1598 1597 ) … … 1680 1679 fg "0,65535,0" 1681 1680 ) 1682 xt "18250, 56625,19000,57375"1681 xt "18250,63625,19000,64375" 1683 1682 ) 1684 1683 tg (CPTG … … 1690 1689 va (VaSet 1691 1690 ) 1692 xt "20000, 56500,28500,57500"1691 xt "20000,63500,28500,64500" 1693 1692 st "drs_channel_id : (3:0)" 1694 blo "20000, 57300"1693 blo "20000,64300" 1695 1694 ) 1696 1695 ) … … 1844 1843 n "drs_read_s_cell_ready" 1845 1844 t "std_logic" 1846 o 381845 o 42 1847 1846 suid 34,0 1848 1847 ) … … 1878 1877 n "drs_s_cell_array" 1879 1878 t "drs_s_cell_array_type" 1880 o 391879 o 43 1881 1880 suid 35,0 1882 1881 ) … … 1947 1946 n "config_ready_cm" 1948 1947 t "std_logic" 1949 o 1 21948 o 13 1950 1949 suid 39,0 1951 1950 ) … … 1983 1982 n "config_start_cm" 1984 1983 t "std_logic" 1985 o 9 1984 prec "-- --" 1985 preAdd 0 1986 posAdd 0 1987 o 10 1986 1988 suid 40,0 1987 1989 i "'0'" … … 1990 1992 ) 1991 1993 *48 (CptPort 1992 uid 5271,01993 ps "OnEdgeStrategy"1994 shape (Triangle1995 uid 5272,01996 ro 2701997 va (VaSet1998 vasetType 11999 fg "0,65535,0"2000 )2001 xt "40000,52625,40750,53375"2002 )2003 tg (CPTG2004 uid 5273,02005 ps "CptPortTextPlaceStrategy"2006 stg "RightVerticalLayoutStrategy"2007 f (Text2008 uid 5274,02009 va (VaSet2010 )2011 xt "35400,52500,39000,53500"2012 st "s_trigger"2013 ju 22014 blo "39000,53300"2015 )2016 )2017 thePort (LogicalPort2018 decl (Decl2019 n "s_trigger"2020 t "std_logic"2021 o 272022 suid 41,02023 )2024 )2025 )2026 *49 (CptPort2027 1994 uid 5392,0 2028 1995 ps "OnEdgeStrategy" … … 2054 2021 n "config_ready_mm" 2055 2022 t "std_logic" 2056 o 1 12023 o 12 2057 2024 suid 42,0 2058 2025 ) 2059 2026 ) 2060 2027 ) 2061 * 50(CptPort2028 *49 (CptPort 2062 2029 uid 5396,0 2063 2030 ps "OnEdgeStrategy" … … 2089 2056 n "config_ready_spi" 2090 2057 t "std_logic" 2091 o 1 32058 o 14 2092 2059 suid 43,0 2093 2060 ) 2094 2061 ) 2095 2062 ) 2096 *5 1(CptPort2063 *50 (CptPort 2097 2064 uid 5464,0 2098 2065 ps "OnEdgeStrategy" … … 2124 2091 n "sensor_array" 2125 2092 t "sensor_array_type" 2126 o 192093 o 20 2127 2094 suid 44,0 2128 2095 ) 2129 2096 ) 2130 2097 ) 2131 *5 2(CptPort2098 *51 (CptPort 2132 2099 uid 5468,0 2133 2100 ps "OnEdgeStrategy" … … 2159 2126 n "sensor_ready" 2160 2127 t "std_logic" 2161 o 2 02128 o 21 2162 2129 suid 45,0 2163 2130 ) 2164 2131 ) 2165 2132 ) 2166 *5 3(CptPort2133 *52 (CptPort 2167 2134 uid 5735,0 2168 2135 ps "OnEdgeStrategy" … … 2195 2162 n "config_start_mm" 2196 2163 t "std_logic" 2197 o 8 2164 prec "-- --" 2165 preAdd 0 2166 posAdd 0 2167 o 9 2198 2168 suid 46,0 2199 2169 i "'0'" … … 2201 2171 ) 2202 2172 ) 2203 *5 4(CptPort2173 *53 (CptPort 2204 2174 uid 5739,0 2205 2175 ps "OnEdgeStrategy" … … 2232 2202 n "config_start_spi" 2233 2203 t "std_logic" 2234 o 10 2204 prec "-- --" 2205 preAdd 0 2206 o 11 2235 2207 suid 47,0 2236 2208 i "'0'" … … 2238 2210 ) 2239 2211 ) 2240 *5 5(CptPort2212 *54 (CptPort 2241 2213 uid 5916,0 2242 2214 ps "OnEdgeStrategy" … … 2275 2247 ) 2276 2248 ) 2277 *5 6(CptPort2249 *55 (CptPort 2278 2250 uid 5920,0 2279 2251 ps "OnEdgeStrategy" … … 2305 2277 n "new_config" 2306 2278 t "std_logic" 2279 prec "-- s_trigger : in std_logic;" 2280 preAdd 0 2307 2281 o 28 2308 2282 suid 49,0 … … 2310 2284 ) 2311 2285 ) 2312 *5 7(CptPort2286 *56 (CptPort 2313 2287 uid 5974,0 2314 2288 ps "OnEdgeStrategy" … … 2340 2314 n "config_started_cm" 2341 2315 t "std_logic" 2342 o 1 52316 o 16 2343 2317 suid 50,0 2344 2318 ) 2345 2319 ) 2346 2320 ) 2347 *5 8(CptPort2321 *57 (CptPort 2348 2322 uid 5978,0 2349 2323 ps "OnEdgeStrategy" … … 2375 2349 n "config_started_mm" 2376 2350 t "std_logic" 2377 o 1 42351 o 15 2378 2352 suid 51,0 2379 2353 ) 2380 2354 ) 2381 2355 ) 2382 *5 9(CptPort2356 *58 (CptPort 2383 2357 uid 5982,0 2384 2358 ps "OnEdgeStrategy" … … 2410 2384 n "config_started_spi" 2411 2385 t "std_logic" 2412 o 1 62386 o 17 2413 2387 suid 52,0 2414 2388 ) 2415 2389 ) 2416 2390 ) 2417 * 60(CptPort2391 *59 (CptPort 2418 2392 uid 6060,0 2419 2393 ps "OnEdgeStrategy" … … 2445 2419 n "dac_array" 2446 2420 t "dac_array_type" 2447 o 2 12421 o 22 2448 2422 suid 53,0 2449 2423 ) 2450 2424 ) 2451 2425 ) 2452 *6 1(CptPort2426 *60 (CptPort 2453 2427 uid 9000,0 2454 2428 ps "OnEdgeStrategy" … … 2483 2457 suid 54,0 2484 2458 i "'0'" 2459 ) 2460 ) 2461 ) 2462 *61 (CptPort 2463 uid 10244,0 2464 ps "OnEdgeStrategy" 2465 shape (Triangle 2466 uid 10245,0 2467 ro 270 2468 va (VaSet 2469 vasetType 1 2470 fg "0,65535,0" 2471 ) 2472 xt "18250,56625,19000,57375" 2473 ) 2474 tg (CPTG 2475 uid 10246,0 2476 ps "CptPortTextPlaceStrategy" 2477 stg "VerticalLayoutStrategy" 2478 f (Text 2479 uid 10247,0 2480 va (VaSet 2481 ) 2482 xt "20000,56500,28000,57500" 2483 st "drs_srin_data : (7:0)" 2484 blo "20000,57300" 2485 ) 2486 ) 2487 thePort (LogicalPort 2488 m 1 2489 decl (Decl 2490 n "drs_srin_data" 2491 t "std_logic_vector" 2492 b "(7 downto 0)" 2493 o 40 2494 suid 56,0 2495 i "(others => '0')" 2496 ) 2497 ) 2498 ) 2499 *62 (CptPort 2500 uid 10248,0 2501 ps "OnEdgeStrategy" 2502 shape (Triangle 2503 uid 10249,0 2504 ro 270 2505 va (VaSet 2506 vasetType 1 2507 fg "0,65535,0" 2508 ) 2509 xt "18250,53625,19000,54375" 2510 ) 2511 tg (CPTG 2512 uid 10250,0 2513 ps "CptPortTextPlaceStrategy" 2514 stg "VerticalLayoutStrategy" 2515 f (Text 2516 uid 10251,0 2517 va (VaSet 2518 ) 2519 xt "20000,53500,26800,54500" 2520 st "drs_srin_write_8b" 2521 blo "20000,54300" 2522 ) 2523 ) 2524 thePort (LogicalPort 2525 m 1 2526 decl (Decl 2527 n "drs_srin_write_8b" 2528 t "std_logic" 2529 o 38 2530 suid 57,0 2531 i "'0'" 2532 ) 2533 ) 2534 ) 2535 *63 (CptPort 2536 uid 10252,0 2537 ps "OnEdgeStrategy" 2538 shape (Triangle 2539 uid 10253,0 2540 ro 90 2541 va (VaSet 2542 vasetType 1 2543 fg "0,65535,0" 2544 ) 2545 xt "18250,54625,19000,55375" 2546 ) 2547 tg (CPTG 2548 uid 10254,0 2549 ps "CptPortTextPlaceStrategy" 2550 stg "VerticalLayoutStrategy" 2551 f (Text 2552 uid 10255,0 2553 va (VaSet 2554 ) 2555 xt "20000,54500,27100,55500" 2556 st "drs_srin_write_ack" 2557 blo "20000,55300" 2558 ) 2559 ) 2560 thePort (LogicalPort 2561 decl (Decl 2562 n "drs_srin_write_ack" 2563 t "std_logic" 2564 o 39 2565 suid 58,0 2566 ) 2567 ) 2568 ) 2569 *64 (CptPort 2570 uid 10256,0 2571 ps "OnEdgeStrategy" 2572 shape (Triangle 2573 uid 10257,0 2574 ro 90 2575 va (VaSet 2576 vasetType 1 2577 fg "0,65535,0" 2578 ) 2579 xt "18250,55625,19000,56375" 2580 ) 2581 tg (CPTG 2582 uid 10258,0 2583 ps "CptPortTextPlaceStrategy" 2584 stg "VerticalLayoutStrategy" 2585 f (Text 2586 uid 10259,0 2587 va (VaSet 2588 ) 2589 xt "20000,55500,28200,56500" 2590 st "drs_srin_write_ready" 2591 blo "20000,56300" 2592 ) 2593 ) 2594 thePort (LogicalPort 2595 decl (Decl 2596 n "drs_srin_write_ready" 2597 t "std_logic" 2598 o 41 2599 suid 59,0 2600 ) 2601 ) 2602 ) 2603 *65 (CptPort 2604 uid 10260,0 2605 ps "OnEdgeStrategy" 2606 shape (Triangle 2607 uid 10261,0 2608 ro 270 2609 va (VaSet 2610 vasetType 1 2611 fg "0,65535,0" 2612 ) 2613 xt "40000,65625,40750,66375" 2614 ) 2615 tg (CPTG 2616 uid 10262,0 2617 ps "CptPortTextPlaceStrategy" 2618 stg "RightVerticalLayoutStrategy" 2619 f (Text 2620 uid 10263,0 2621 va (VaSet 2622 ) 2623 xt "31200,65500,39000,66500" 2624 st "ram_write_ready_ack" 2625 ju 2 2626 blo "39000,66300" 2627 ) 2628 ) 2629 thePort (LogicalPort 2630 decl (Decl 2631 n "ram_write_ready_ack" 2632 t "std_logic" 2633 prec "-- --" 2634 preAdd 0 2635 posAdd 0 2636 o 8 2637 suid 60,0 2485 2638 ) 2486 2639 ) … … 2503 2656 stg "VerticalLayoutStrategy" 2504 2657 textVec [ 2505 *6 2(Text2658 *66 (Text 2506 2659 uid 1402,0 2507 2660 va (VaSet … … 2513 2666 tm "BdLibraryNameMgr" 2514 2667 ) 2515 *6 3(Text2668 *67 (Text 2516 2669 uid 1403,0 2517 2670 va (VaSet … … 2523 2676 tm "CptNameMgr" 2524 2677 ) 2525 *6 4(Text2678 *68 (Text 2526 2679 uid 1404,0 2527 2680 va (VaSet … … 2576 2729 archFileType "UNKNOWN" 2577 2730 ) 2578 *6 5(Net2731 *69 (Net 2579 2732 uid 1409,0 2580 2733 decl (Decl … … 2593 2746 ) 2594 2747 xt "-103000,23800,-74500,24600" 2595 st "board_id : std_logic_vector(3 downto 0) 2596 " 2597 ) 2598 ) 2599 *66 (Net 2748 st "board_id : std_logic_vector(3 downto 0)" 2749 ) 2750 ) 2751 *70 (Net 2600 2752 uid 1423,0 2601 2753 decl (Decl … … 2613 2765 ) 2614 2766 xt "-103000,25400,-84500,26200" 2615 st "trigger : std_logic 2616 " 2617 ) 2618 ) 2619 *67 (PortIoIn 2767 st "trigger : std_logic" 2768 ) 2769 ) 2770 *71 (PortIoIn 2620 2771 uid 1443,0 2621 2772 shape (CompositeShape … … 2630 2781 sl 0 2631 2782 ro 270 2632 xt "- 28000,68625,-26500,69375"2783 xt "-34000,69625,-32500,70375" 2633 2784 ) 2634 2785 (Line … … 2636 2787 sl 0 2637 2788 ro 270 2638 xt "- 26500,69000,-26000,69000"2639 pts [ 2640 "- 26500,69000"2641 "- 26000,69000"2789 xt "-32500,70000,-32000,70000" 2790 pts [ 2791 "-32500,70000" 2792 "-32000,70000" 2642 2793 ] 2643 2794 ) … … 2654 2805 va (VaSet 2655 2806 ) 2656 xt "-3 1800,68500,-29000,69500"2807 xt "-36800,69500,-34000,70500" 2657 2808 st "trigger" 2658 2809 ju 2 2659 blo "- 29000,69300"2810 blo "-34000,70300" 2660 2811 tm "WireNameMgr" 2661 2812 ) 2662 2813 ) 2663 2814 ) 2664 * 68(SaComponent2815 *72 (SaComponent 2665 2816 uid 1606,0 2666 2817 optionalChildren [ 2667 * 69(CptPort2818 *73 (CptPort 2668 2819 uid 1542,0 2669 2820 ps "OnEdgeStrategy" … … 2675 2826 fg "0,65535,0" 2676 2827 ) 2677 xt "12 6250,51625,127000,52375"2828 xt "127250,51625,128000,52375" 2678 2829 ) 2679 2830 tg (CPTG … … 2685 2836 va (VaSet 2686 2837 ) 2687 xt "12 8000,51500,129300,52500"2838 xt "129000,51500,130300,52500" 2688 2839 st "clk" 2689 blo "12 8000,52300"2840 blo "129000,52300" 2690 2841 ) 2691 2842 ) … … 2701 2852 ) 2702 2853 ) 2703 *7 0(CptPort2854 *74 (CptPort 2704 2855 uid 1546,0 2705 2856 ps "OnEdgeStrategy" … … 2711 2862 fg "0,65535,0" 2712 2863 ) 2713 xt "14 8000,51625,148750,52375"2864 xt "149000,51625,149750,52375" 2714 2865 ) 2715 2866 tg (CPTG … … 2721 2872 va (VaSet 2722 2873 ) 2723 xt "14 3400,51500,147000,52500"2874 xt "144400,51500,148000,52500" 2724 2875 st "wiz_reset" 2725 2876 ju 2 2726 blo "14 7000,52300"2877 blo "148000,52300" 2727 2878 ) 2728 2879 ) … … 2740 2891 ) 2741 2892 ) 2742 *7 1(CptPort2893 *75 (CptPort 2743 2894 uid 1550,0 2744 2895 ps "OnEdgeStrategy" … … 2750 2901 fg "0,65535,0" 2751 2902 ) 2752 xt "14 8000,59625,148750,60375"2903 xt "149000,59625,149750,60375" 2753 2904 ) 2754 2905 tg (CPTG … … 2760 2911 va (VaSet 2761 2912 ) 2762 xt "14 2500,59500,147000,60500"2913 xt "143500,59500,148000,60500" 2763 2914 st "addr : (9:0)" 2764 2915 ju 2 2765 blo "14 7000,60300"2916 blo "148000,60300" 2766 2917 ) 2767 2918 ) … … 2779 2930 ) 2780 2931 ) 2781 *7 2(CptPort2932 *76 (CptPort 2782 2933 uid 1554,0 2783 2934 ps "OnEdgeStrategy" … … 2789 2940 fg "0,65535,0" 2790 2941 ) 2791 xt "14 8000,60625,148750,61375"2942 xt "149000,60625,149750,61375" 2792 2943 ) 2793 2944 tg (CPTG … … 2799 2950 va (VaSet 2800 2951 ) 2801 xt "14 2200,60500,147000,61500"2952 xt "143200,60500,148000,61500" 2802 2953 st "data : (15:0)" 2803 2954 ju 2 2804 blo "14 7000,61300"2955 blo "148000,61300" 2805 2956 ) 2806 2957 ) … … 2818 2969 ) 2819 2970 ) 2820 *7 3(CptPort2971 *77 (CptPort 2821 2972 uid 1558,0 2822 2973 ps "OnEdgeStrategy" … … 2828 2979 fg "0,65535,0" 2829 2980 ) 2830 xt "14 8000,52625,148750,53375"2981 xt "149000,52625,149750,53375" 2831 2982 ) 2832 2983 tg (CPTG … … 2838 2989 va (VaSet 2839 2990 ) 2840 xt "14 5800,52500,147000,53500"2991 xt "146800,52500,148000,53500" 2841 2992 st "cs" 2842 2993 ju 2 2843 blo "14 7000,53300"2994 blo "148000,53300" 2844 2995 ) 2845 2996 ) … … 2857 3008 ) 2858 3009 ) 2859 *7 4(CptPort3010 *78 (CptPort 2860 3011 uid 1562,0 2861 3012 ps "OnEdgeStrategy" … … 2867 3018 fg "0,65535,0" 2868 3019 ) 2869 xt "14 8000,53625,148750,54375"3020 xt "149000,53625,149750,54375" 2870 3021 ) 2871 3022 tg (CPTG … … 2877 3028 va (VaSet 2878 3029 ) 2879 xt "14 5800,53500,147000,54500"3030 xt "146800,53500,148000,54500" 2880 3031 st "wr" 2881 3032 ju 2 2882 blo "14 7000,54300"3033 blo "148000,54300" 2883 3034 ) 2884 3035 ) … … 2896 3047 ) 2897 3048 ) 2898 *7 5(CptPort3049 *79 (CptPort 2899 3050 uid 1570,0 2900 3051 ps "OnEdgeStrategy" … … 2906 3057 fg "0,65535,0" 2907 3058 ) 2908 xt "14 8000,54625,148750,55375"3059 xt "149000,54625,149750,55375" 2909 3060 ) 2910 3061 tg (CPTG … … 2916 3067 va (VaSet 2917 3068 ) 2918 xt "14 5900,54500,147000,55500"3069 xt "146900,54500,148000,55500" 2919 3070 st "rd" 2920 3071 ju 2 2921 blo "14 7000,55300"3072 blo "148000,55300" 2922 3073 ) 2923 3074 ) … … 2935 3086 ) 2936 3087 ) 2937 * 76(CptPort3088 *80 (CptPort 2938 3089 uid 1574,0 2939 3090 ps "OnEdgeStrategy" … … 2945 3096 fg "0,65535,0" 2946 3097 ) 2947 xt "14 8000,55625,148750,56375"3098 xt "149000,55625,149750,56375" 2948 3099 ) 2949 3100 tg (CPTG … … 2955 3106 va (VaSet 2956 3107 ) 2957 xt "14 5800,55500,147000,56500"3108 xt "146800,55500,148000,56500" 2958 3109 st "int" 2959 3110 ju 2 2960 blo "14 7000,56300"3111 blo "148000,56300" 2961 3112 ) 2962 3113 ) … … 2972 3123 ) 2973 3124 ) 2974 * 77(CptPort3125 *81 (CptPort 2975 3126 uid 1578,0 2976 3127 ps "OnEdgeStrategy" … … 2982 3133 fg "0,65535,0" 2983 3134 ) 2984 xt "12 6250,69625,127000,70375"3135 xt "127250,69625,128000,70375" 2985 3136 ) 2986 3137 tg (CPTG … … 2992 3143 va (VaSet 2993 3144 ) 2994 xt "12 8000,69500,135900,70500"3145 xt "129000,69500,136900,70500" 2995 3146 st "write_length : (16:0)" 2996 blo "12 8000,70300"3147 blo "129000,70300" 2997 3148 ) 2998 3149 ) … … 3009 3160 ) 3010 3161 ) 3011 * 78(CptPort3162 *82 (CptPort 3012 3163 uid 1582,0 3013 3164 ps "OnEdgeStrategy" … … 3019 3170 fg "0,65535,0" 3020 3171 ) 3021 xt "12 6250,70625,127000,71375"3172 xt "127250,70625,128000,71375" 3022 3173 ) 3023 3174 tg (CPTG … … 3029 3180 va (VaSet 3030 3181 ) 3031 xt "12 8000,70500,144300,71500"3182 xt "129000,70500,145300,71500" 3032 3183 st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)" 3033 blo "12 8000,71300"3184 blo "129000,71300" 3034 3185 ) 3035 3186 ) … … 3046 3197 ) 3047 3198 ) 3048 * 79(CptPort3199 *83 (CptPort 3049 3200 uid 1586,0 3050 3201 ps "OnEdgeStrategy" … … 3056 3207 fg "0,65535,0" 3057 3208 ) 3058 xt "12 6250,54625,127000,55375"3209 xt "127250,54625,128000,55375" 3059 3210 ) 3060 3211 tg (CPTG … … 3066 3217 va (VaSet 3067 3218 ) 3068 xt "12 8000,54500,134500,55500"3219 xt "129000,54500,135500,55500" 3069 3220 st "ram_data : (15:0)" 3070 blo "12 8000,55300"3221 blo "129000,55300" 3071 3222 ) 3072 3223 ) … … 3083 3234 ) 3084 3235 ) 3085 *8 0(CptPort3236 *84 (CptPort 3086 3237 uid 1590,0 3087 3238 ps "OnEdgeStrategy" … … 3093 3244 fg "0,65535,0" 3094 3245 ) 3095 xt "12 6250,53625,127000,54375"3246 xt "127250,53625,128000,54375" 3096 3247 ) 3097 3248 tg (CPTG … … 3103 3254 va (VaSet 3104 3255 ) 3105 xt "12 8000,53500,142400,54500"3256 xt "129000,53500,143400,54500" 3106 3257 st "ram_addr : (RAM_ADDR_WIDTH-1:0)" 3107 blo "12 8000,54300"3258 blo "129000,54300" 3108 3259 ) 3109 3260 ) … … 3121 3272 ) 3122 3273 ) 3123 *8 1(CptPort3274 *85 (CptPort 3124 3275 uid 1594,0 3125 3276 ps "OnEdgeStrategy" … … 3131 3282 fg "0,65535,0" 3132 3283 ) 3133 xt "12 6250,68625,127000,69375"3284 xt "127250,68625,128000,69375" 3134 3285 ) 3135 3286 tg (CPTG … … 3141 3292 va (VaSet 3142 3293 ) 3143 xt "12 8000,68500,132100,69500"3294 xt "129000,68500,133100,69500" 3144 3295 st "data_valid" 3145 blo "12 8000,69300"3296 blo "129000,69300" 3146 3297 ) 3147 3298 ) … … 3157 3308 ) 3158 3309 ) 3159 *8 2(CptPort3310 *86 (CptPort 3160 3311 uid 1598,0 3161 3312 ps "OnEdgeStrategy" … … 3167 3318 fg "0,65535,0" 3168 3319 ) 3169 xt "12 6250,67625,127000,68375"3320 xt "127250,67625,128000,68375" 3170 3321 ) 3171 3322 tg (CPTG … … 3177 3328 va (VaSet 3178 3329 ) 3179 xt "12 8000,67500,129900,68500"3330 xt "129000,67500,130900,68500" 3180 3331 st "busy" 3181 blo "12 8000,68300"3332 blo "129000,68300" 3182 3333 ) 3183 3334 ) … … 3195 3346 ) 3196 3347 ) 3197 *8 3(CptPort3348 *87 (CptPort 3198 3349 uid 2218,0 3199 3350 ps "OnEdgeStrategy" … … 3205 3356 fg "0,65535,0" 3206 3357 ) 3207 xt "12 6250,71625,127000,72375"3358 xt "127250,71625,128000,72375" 3208 3359 ) 3209 3360 tg (CPTG … … 3215 3366 va (VaSet 3216 3367 ) 3217 xt "12 8000,71500,135800,72500"3368 xt "129000,71500,136800,72500" 3218 3369 st "fifo_channels : (3:0)" 3219 blo "12 8000,72300"3370 blo "129000,72300" 3220 3371 ) 3221 3372 ) … … 3230 3381 ) 3231 3382 ) 3232 *8 4(CptPort3383 *88 (CptPort 3233 3384 uid 2222,0 3234 3385 ps "OnEdgeStrategy" … … 3240 3391 fg "0,65535,0" 3241 3392 ) 3242 xt "12 6250,72625,127000,73375"3393 xt "127250,72625,128000,73375" 3243 3394 ) 3244 3395 tg (CPTG … … 3250 3401 va (VaSet 3251 3402 ) 3252 xt "12 8000,72500,133700,73500"3403 xt "129000,72500,134700,73500" 3253 3404 st "write_end_flag" 3254 blo "12 8000,73300"3405 blo "129000,73300" 3255 3406 ) 3256 3407 ) … … 3264 3415 ) 3265 3416 ) 3266 *8 5(CptPort3417 *89 (CptPort 3267 3418 uid 2226,0 3268 3419 ps "OnEdgeStrategy" … … 3274 3425 fg "0,65535,0" 3275 3426 ) 3276 xt "12 6250,73625,127000,74375"3427 xt "127250,73625,128000,74375" 3277 3428 ) 3278 3429 tg (CPTG … … 3284 3435 va (VaSet 3285 3436 ) 3286 xt "12 8000,73500,134800,74500"3437 xt "129000,73500,135800,74500" 3287 3438 st "write_header_flag" 3288 blo "12 8000,74300"3439 blo "129000,74300" 3289 3440 ) 3290 3441 ) … … 3298 3449 ) 3299 3450 ) 3300 * 86(CptPort3451 *90 (CptPort 3301 3452 uid 5216,0 3302 3453 ps "OnEdgeStrategy" … … 3308 3459 fg "0,65535,0" 3309 3460 ) 3310 xt "14 8000,70625,148750,71375"3461 xt "149000,70625,149750,71375" 3311 3462 ) 3312 3463 tg (CPTG … … 3318 3469 va (VaSet 3319 3470 ) 3320 xt "14 3000,70500,147000,71500"3471 xt "144000,70500,148000,71500" 3321 3472 st "led : (7:0)" 3322 3473 ju 2 3323 blo "14 7000,71300"3474 blo "148000,71300" 3324 3475 ) 3325 3476 ) … … 3337 3488 ) 3338 3489 ) 3339 * 87(CptPort3490 *91 (CptPort 3340 3491 uid 5275,0 3341 3492 ps "OnEdgeStrategy" … … 3347 3498 fg "0,65535,0" 3348 3499 ) 3349 xt "12 6250,58625,127000,59375"3500 xt "127250,63625,128000,64375" 3350 3501 ) 3351 3502 tg (CPTG … … 3357 3508 va (VaSet 3358 3509 ) 3359 xt "12 8000,58500,131600,59500"3510 xt "129000,63500,132600,64500" 3360 3511 st "s_trigger" 3361 blo "12 8000,59300"3512 blo "129000,64300" 3362 3513 ) 3363 3514 ) … … 3373 3524 ) 3374 3525 ) 3375 * 88(CptPort3526 *92 (CptPort 3376 3527 uid 5924,0 3377 3528 ps "OnEdgeStrategy" … … 3383 3534 fg "0,65535,0" 3384 3535 ) 3385 xt "12 6250,78625,127000,79375"3536 xt "127250,78625,128000,79375" 3386 3537 ) 3387 3538 tg (CPTG … … 3393 3544 va (VaSet 3394 3545 ) 3395 xt "12 8000,78500,135000,79500"3546 xt "129000,78500,136000,79500" 3396 3547 st "config_addr : (7:0)" 3397 blo "12 8000,79300"3548 blo "129000,79300" 3398 3549 ) 3399 3550 ) … … 3409 3560 ) 3410 3561 ) 3411 * 89(CptPort3562 *93 (CptPort 3412 3563 uid 5928,0 3413 3564 ps "OnEdgeStrategy" … … 3419 3570 fg "0,65535,0" 3420 3571 ) 3421 xt "12 6250,83625,127000,84375"3572 xt "127250,83625,128000,84375" 3422 3573 ) 3423 3574 tg (CPTG … … 3429 3580 va (VaSet 3430 3581 ) 3431 xt "12 8000,83500,132800,84500"3582 xt "129000,83500,133800,84500" 3432 3583 st "config_busy" 3433 blo "12 8000,84300"3584 blo "129000,84300" 3434 3585 ) 3435 3586 ) … … 3438 3589 n "config_busy" 3439 3590 t "std_logic" 3440 o 27 3591 prec "-- --" 3592 preAdd 0 3593 o 29 3441 3594 suid 25,0 3442 3595 ) 3443 3596 ) 3444 3597 ) 3445 *9 0(CptPort3598 *94 (CptPort 3446 3599 uid 5932,0 3447 3600 ps "OnEdgeStrategy" … … 3453 3606 fg "0,65535,0" 3454 3607 ) 3455 xt "12 6250,79625,127000,80375"3608 xt "127250,79625,128000,80375" 3456 3609 ) 3457 3610 tg (CPTG … … 3463 3616 va (VaSet 3464 3617 ) 3465 xt "12 8000,79500,135700,80500"3618 xt "129000,79500,136700,80500" 3466 3619 st "config_data : (15:0)" 3467 blo "12 8000,80300"3620 blo "129000,80300" 3468 3621 ) 3469 3622 ) … … 3480 3633 ) 3481 3634 ) 3482 *9 1(CptPort3635 *95 (CptPort 3483 3636 uid 5936,0 3484 3637 ps "OnEdgeStrategy" … … 3490 3643 fg "0,65535,0" 3491 3644 ) 3492 xt "12 6250,60625,127000,61375"3645 xt "127250,60625,128000,61375" 3493 3646 ) 3494 3647 tg (CPTG … … 3500 3653 va (VaSet 3501 3654 ) 3502 xt "12 8000,60500,133600,61500"3655 xt "129000,60500,134600,61500" 3503 3656 st "config_started" 3504 blo "12 8000,61300"3657 blo "129000,61300" 3505 3658 ) 3506 3659 ) … … 3514 3667 ) 3515 3668 ) 3516 *9 2(CptPort3669 *96 (CptPort 3517 3670 uid 5940,0 3518 3671 ps "OnEdgeStrategy" … … 3524 3677 fg "0,65535,0" 3525 3678 ) 3526 xt "12 6250,81625,127000,82375"3679 xt "127250,81625,128000,82375" 3527 3680 ) 3528 3681 tg (CPTG … … 3534 3687 va (VaSet 3535 3688 ) 3536 xt "12 8000,81500,133300,82500"3689 xt "129000,81500,134300,82500" 3537 3690 st "config_wr_en" 3538 blo "12 8000,82300"3691 blo "129000,82300" 3539 3692 ) 3540 3693 ) … … 3550 3703 ) 3551 3704 ) 3552 *9 3(CptPort3705 *97 (CptPort 3553 3706 uid 5944,0 3554 3707 ps "OnEdgeStrategy" … … 3560 3713 fg "0,65535,0" 3561 3714 ) 3562 xt "12 6250,59625,127000,60375"3715 xt "127250,59625,128000,60375" 3563 3716 ) 3564 3717 tg (CPTG … … 3570 3723 va (VaSet 3571 3724 ) 3572 xt "12 8000,59500,132600,60500"3725 xt "129000,59500,133600,60500" 3573 3726 st "new_config" 3574 blo "12 8000,60300"3727 blo "129000,60300" 3575 3728 ) 3576 3729 ) … … 3586 3739 ) 3587 3740 ) 3588 *9 4(CptPort3741 *98 (CptPort 3589 3742 uid 5970,0 3590 3743 ps "OnEdgeStrategy" … … 3596 3749 fg "0,65535,0" 3597 3750 ) 3598 xt "12 6250,82625,127000,83375"3751 xt "127250,82625,128000,83375" 3599 3752 ) 3600 3753 tg (CPTG … … 3606 3759 va (VaSet 3607 3760 ) 3608 xt "12 8000,82500,133200,83500"3761 xt "129000,82500,134200,83500" 3609 3762 st "config_rd_en" 3610 blo "12 8000,83300"3763 blo "129000,83300" 3611 3764 ) 3612 3765 ) … … 3616 3769 n "config_rd_en" 3617 3770 t "std_logic" 3771 posAdd 0 3618 3772 o 26 3619 3773 suid 30,0 … … 3622 3776 ) 3623 3777 ) 3624 *9 5(CptPort3778 *99 (CptPort 3625 3779 uid 6356,0 3626 3780 ps "OnEdgeStrategy" … … 3632 3786 fg "0,65535,0" 3633 3787 ) 3634 xt "14 8000,74625,148750,75375"3788 xt "149000,74625,149750,75375" 3635 3789 ) 3636 3790 tg (CPTG … … 3642 3796 va (VaSet 3643 3797 ) 3644 xt "14 4000,74500,147000,75500"3798 xt "145000,74500,148000,75500" 3645 3799 st "denable" 3646 3800 ju 2 3647 blo "14 7000,75300"3801 blo "148000,75300" 3648 3802 ) 3649 3803 ) … … 3655 3809 eolc "-- default domino wave off" 3656 3810 posAdd 0 3657 o 283811 o 30 3658 3812 suid 31,0 3659 3813 i "'0'" … … 3661 3815 ) 3662 3816 ) 3663 * 96(CptPort3817 *100 (CptPort 3664 3818 uid 6446,0 3665 3819 ps "OnEdgeStrategy" … … 3671 3825 fg "0,65535,0" 3672 3826 ) 3673 xt "14 8000,75625,148750,76375"3827 xt "149000,75625,149750,76375" 3674 3828 ) 3675 3829 tg (CPTG … … 3681 3835 va (VaSet 3682 3836 ) 3683 xt "14 1600,75500,147000,76500"3837 xt "142600,75500,148000,76500" 3684 3838 st "dwrite_enable" 3685 3839 ju 2 3686 blo "14 7000,76300"3840 blo "148000,76300" 3687 3841 ) 3688 3842 ) … … 3695 3849 preAdd 0 3696 3850 posAdd 0 3697 o 293851 o 31 3698 3852 suid 32,0 3699 3853 i "'0'" … … 3701 3855 ) 3702 3856 ) 3703 * 97(CptPort3857 *101 (CptPort 3704 3858 uid 8406,0 3705 3859 ps "OnEdgeStrategy" … … 3711 3865 fg "0,65535,0" 3712 3866 ) 3713 xt "12 6250,74625,127000,75375"3867 xt "127250,74625,128000,75375" 3714 3868 ) 3715 3869 tg (CPTG … … 3721 3875 va (VaSet 3722 3876 ) 3723 xt "12 8000,74500,133600,75500"3877 xt "129000,74500,134600,75500" 3724 3878 st "data_valid_ack" 3725 blo "12 8000,75300"3879 blo "129000,75300" 3726 3880 ) 3727 3881 ) … … 3737 3891 ) 3738 3892 ) 3739 * 98(CptPort3893 *102 (CptPort 3740 3894 uid 8748,0 3741 3895 ps "OnEdgeStrategy" … … 3747 3901 fg "0,65535,0" 3748 3902 ) 3749 xt "14 8000,76625,148750,77375"3903 xt "149000,76625,149750,77375" 3750 3904 ) 3751 3905 tg (CPTG … … 3757 3911 va (VaSet 3758 3912 ) 3759 xt "14 2300,76500,147000,77500"3913 xt "143300,76500,148000,77500" 3760 3914 st "sclk_enable" 3761 3915 ju 2 3762 blo "14 7000,77300"3916 blo "148000,77300" 3763 3917 ) 3764 3918 ) … … 3770 3924 eolc "-- default DWRITE HIGH." 3771 3925 posAdd 0 3772 o 3 03926 o 32 3773 3927 suid 35,0 3774 3928 i "'1'" … … 3776 3930 ) 3777 3931 ) 3778 * 99(CptPort3932 *103 (CptPort 3779 3933 uid 9223,0 3780 3934 ps "OnEdgeStrategy" … … 3786 3940 fg "0,65535,0" 3787 3941 ) 3788 xt "14 8000,80625,148750,81375"3942 xt "149000,80625,149750,81375" 3789 3943 ) 3790 3944 tg (CPTG … … 3796 3950 va (VaSet 3797 3951 ) 3798 xt "14 2100,80500,147000,81500"3952 xt "143100,80500,148000,81500" 3799 3953 st "ps_direction" 3800 3954 ju 2 3801 blo "14 7000,81300"3955 blo "148000,81300" 3802 3956 ) 3803 3957 ) … … 3809 3963 eolc "-- default phase shift upwards" 3810 3964 posAdd 0 3811 o 3 13965 o 33 3812 3966 suid 36,0 3813 3967 i "'1'" … … 3815 3969 ) 3816 3970 ) 3817 *10 0(CptPort3971 *104 (CptPort 3818 3972 uid 9227,0 3819 3973 ps "OnEdgeStrategy" … … 3825 3979 fg "0,65535,0" 3826 3980 ) 3827 xt "14 8000,81625,148750,82375"3981 xt "149000,81625,149750,82375" 3828 3982 ) 3829 3983 tg (CPTG … … 3835 3989 va (VaSet 3836 3990 ) 3837 xt "14 0000,81500,147000,82500"3991 xt "141000,81500,148000,82500" 3838 3992 st "ps_do_phase_shift" 3839 3993 ju 2 3840 blo "14 7000,82300"3994 blo "148000,82300" 3841 3995 ) 3842 3996 ) … … 3849 4003 preAdd 0 3850 4004 posAdd 0 3851 o 3 24005 o 34 3852 4006 suid 37,0 3853 4007 i "'0'" … … 3855 4009 ) 3856 4010 ) 3857 *10 1(CptPort4011 *105 (CptPort 3858 4012 uid 9933,0 3859 4013 ps "OnEdgeStrategy" … … 3865 4019 fg "0,65535,0" 3866 4020 ) 3867 xt "14 8000,82625,148750,83375"4021 xt "149000,82625,149750,83375" 3868 4022 ) 3869 4023 tg (CPTG … … 3875 4029 va (VaSet 3876 4030 ) 3877 xt "14 3700,82500,147000,83500"4031 xt "144700,82500,148000,83500" 3878 4032 st "ps_reset" 3879 4033 ju 2 3880 blo "14 7000,83300"4034 blo "148000,83300" 3881 4035 ) 3882 4036 ) … … 3888 4042 eolc "-- pulse this to reset the variable phase shift" 3889 4043 posAdd 0 3890 o 3 34044 o 35 3891 4045 suid 38,0 3892 4046 i "'0'" … … 3894 4048 ) 3895 4049 ) 3896 *10 2(CptPort4050 *106 (CptPort 3897 4051 uid 9937,0 3898 4052 ps "OnEdgeStrategy" … … 3904 4058 fg "0,65535,0" 3905 4059 ) 3906 xt "14 8000,84625,148750,85375"4060 xt "149000,84625,149750,85375" 3907 4061 ) 3908 4062 tg (CPTG … … 3914 4068 va (VaSet 3915 4069 ) 3916 xt "14 2000,84500,147000,85500"4070 xt "143000,84500,148000,85500" 3917 4071 st "srclk_enable" 3918 4072 ju 2 3919 blo "14 7000,85300"4073 blo "148000,85300" 3920 4074 ) 3921 4075 ) … … 3927 4081 eolc "-- default SRCLK on." 3928 4082 posAdd 0 3929 o 3 44083 o 36 3930 4084 suid 39,0 3931 4085 i "'1'" 4086 ) 4087 ) 4088 ) 4089 *107 (CptPort 4090 uid 10212,0 4091 ps "OnEdgeStrategy" 4092 shape (Triangle 4093 uid 10213,0 4094 ro 90 4095 va (VaSet 4096 vasetType 1 4097 fg "0,65535,0" 4098 ) 4099 xt "127250,84625,128000,85375" 4100 ) 4101 tg (CPTG 4102 uid 10214,0 4103 ps "CptPortTextPlaceStrategy" 4104 stg "VerticalLayoutStrategy" 4105 f (Text 4106 uid 10215,0 4107 va (VaSet 4108 ) 4109 xt "129000,84500,134600,85500" 4110 st "config_rw_ack" 4111 blo "129000,85300" 4112 ) 4113 ) 4114 thePort (LogicalPort 4115 decl (Decl 4116 n "config_rw_ack" 4117 t "std_logic" 4118 prec "-- --" 4119 preAdd 0 4120 posAdd 0 4121 o 27 4122 suid 40,0 4123 ) 4124 ) 4125 ) 4126 *108 (CptPort 4127 uid 10216,0 4128 ps "OnEdgeStrategy" 4129 shape (Triangle 4130 uid 10217,0 4131 ro 90 4132 va (VaSet 4133 vasetType 1 4134 fg "0,65535,0" 4135 ) 4136 xt "127250,85625,128000,86375" 4137 ) 4138 tg (CPTG 4139 uid 10218,0 4140 ps "CptPortTextPlaceStrategy" 4141 stg "VerticalLayoutStrategy" 4142 f (Text 4143 uid 10219,0 4144 va (VaSet 4145 ) 4146 xt "129000,85500,135300,86500" 4147 st "config_rw_ready" 4148 blo "129000,86300" 4149 ) 4150 ) 4151 thePort (LogicalPort 4152 decl (Decl 4153 n "config_rw_ready" 4154 t "std_logic" 4155 prec "-- --" 4156 preAdd 0 4157 posAdd 0 4158 o 28 4159 suid 41,0 3932 4160 ) 3933 4161 ) … … 3942 4170 lineWidth 2 3943 4171 ) 3944 xt "12 7000,51000,148000,89000"4172 xt "128000,51000,149000,89000" 3945 4173 ) 3946 4174 oxt "43000,2000,56000,22000" … … 3950 4178 stg "VerticalLayoutStrategy" 3951 4179 textVec [ 3952 *10 3(Text4180 *109 (Text 3953 4181 uid 1609,0 3954 4182 va (VaSet 3955 4183 font "Arial,8,1" 3956 4184 ) 3957 xt "12 6700,87000,132900,88000"4185 xt "127700,87000,133900,88000" 3958 4186 st "FACT_FAD_lib" 3959 blo "12 6700,87800"4187 blo "127700,87800" 3960 4188 tm "BdLibraryNameMgr" 3961 4189 ) 3962 *1 04(Text4190 *110 (Text 3963 4191 uid 1610,0 3964 4192 va (VaSet 3965 4193 font "Arial,8,1" 3966 4194 ) 3967 xt "12 6700,88000,132400,89000"4195 xt "127700,88000,133400,89000" 3968 4196 st "w5300_modul" 3969 blo "12 6700,88800"4197 blo "127700,88800" 3970 4198 tm "CptNameMgr" 3971 4199 ) 3972 *1 05(Text4200 *111 (Text 3973 4201 uid 1611,0 3974 4202 va (VaSet 3975 4203 font "Arial,8,1" 3976 4204 ) 3977 xt "12 6700,89000,133400,90000"4205 xt "127700,89000,134400,90000" 3978 4206 st "I_main_ethernet" 3979 blo "12 6700,89800"4207 blo "127700,89800" 3980 4208 tm "InstanceNameMgr" 3981 4209 ) … … 3992 4220 font "Courier New,8,0" 3993 4221 ) 3994 xt "12 7000,50200,154500,51000"4222 xt "128000,50200,155500,51000" 3995 4223 st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b+2 ( integer ) " 3996 4224 ) … … 4012 4240 fg "49152,49152,49152" 4013 4241 ) 4014 xt "12 7250,87250,128750,88750"4242 xt "128250,87250,129750,88750" 4015 4243 iconName "VhdlFileViewIcon.png" 4016 4244 iconMaskName "VhdlFileViewIcon.msk" … … 4023 4251 archFileType "UNKNOWN" 4024 4252 ) 4025 *1 06(Net4253 *112 (Net 4026 4254 uid 1680,0 4027 4255 decl (Decl … … 4038 4266 ) 4039 4267 xt "-103000,24600,-74500,25400" 4040 st "crate_id : std_logic_vector(1 downto 0) 4041 " 4042 ) 4043 ) 4044 *107 (SaComponent 4268 st "crate_id : std_logic_vector(1 downto 0)" 4269 ) 4270 ) 4271 *113 (SaComponent 4045 4272 uid 1768,0 4046 4273 optionalChildren [ 4047 *1 08(CptPort4274 *114 (CptPort 4048 4275 uid 1760,0 4049 4276 ps "OnEdgeStrategy" … … 4085 4312 ) 4086 4313 ) 4087 *1 09(CptPort4314 *115 (CptPort 4088 4315 uid 1764,0 4089 4316 ps "OnEdgeStrategy" … … 4122 4349 ) 4123 4350 ) 4124 *11 0(CptPort4351 *116 (CptPort 4125 4352 uid 6207,0 4126 4353 ps "OnEdgeStrategy" … … 4174 4401 stg "VerticalLayoutStrategy" 4175 4402 textVec [ 4176 *11 1(Text4403 *117 (Text 4177 4404 uid 1771,0 4178 4405 va (VaSet … … 4184 4411 tm "BdLibraryNameMgr" 4185 4412 ) 4186 *11 2(Text4413 *118 (Text 4187 4414 uid 1772,0 4188 4415 va (VaSet … … 4194 4421 tm "CptNameMgr" 4195 4422 ) 4196 *11 3(Text4423 *119 (Text 4197 4424 uid 1773,0 4198 4425 va (VaSet … … 4242 4469 archFileType "UNKNOWN" 4243 4470 ) 4244 *1 14(Net4471 *120 (Net 4245 4472 uid 1981,0 4246 4473 lang 2 … … 4259 4486 font "Courier New,8,0" 4260 4487 ) 4261 xt "-103000,97800,-70500,98600" 4262 st "SIGNAL trigger_id : std_logic_vector(47 downto 0) 4263 " 4264 ) 4265 ) 4266 *115 (Net 4488 xt "-103000,106600,-70500,107400" 4489 st "SIGNAL trigger_id : std_logic_vector(47 downto 0)" 4490 ) 4491 ) 4492 *121 (Net 4267 4493 uid 2297,0 4268 4494 decl (Decl … … 4280 4506 font "Courier New,8,0" 4281 4507 ) 4282 xt "-103000,89000,-63000,89800" 4283 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 4284 " 4285 ) 4286 ) 4287 *116 (SaComponent 4508 xt "-103000,93800,-63000,94600" 4509 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 4510 ) 4511 ) 4512 *122 (SaComponent 4288 4513 uid 2311,0 4289 4514 optionalChildren [ 4290 *1 17(CptPort4515 *123 (CptPort 4291 4516 uid 2307,0 4292 4517 ps "OnEdgeStrategy" … … 4323 4548 preAdd 0 4324 4549 posAdd 0 4325 o 1 84550 o 19 4326 4551 suid 1,0 4327 4552 i "(others => '0')" … … 4329 4554 ) 4330 4555 ) 4331 *1 18(CptPort4556 *124 (CptPort 4332 4557 uid 2351,0 4333 4558 ps "OnEdgeStrategy" … … 4365 4590 ) 4366 4591 ) 4367 *1 19(CptPort4592 *125 (CptPort 4368 4593 uid 2361,0 4369 4594 ps "OnEdgeStrategy" … … 4397 4622 n "config_ready" 4398 4623 t "std_logic" 4399 o 64624 o 7 4400 4625 suid 5,0 4401 4626 i "'0'" … … 4403 4628 ) 4404 4629 ) 4405 *12 0(CptPort4630 *126 (CptPort 4406 4631 uid 2365,0 4407 4632 ps "OnEdgeStrategy" … … 4439 4664 ) 4440 4665 ) 4441 *12 1(CptPort4666 *127 (CptPort 4442 4667 uid 2369,0 4443 4668 ps "OnEdgeStrategy" … … 4471 4696 n "ram_write_ea" 4472 4697 t "std_logic" 4473 o 54698 o 6 4474 4699 suid 4,0 4475 4700 i "'0'" … … 4477 4702 ) 4478 4703 ) 4479 *12 2(CptPort4704 *128 (CptPort 4480 4705 uid 2373,0 4481 4706 ps "OnEdgeStrategy" … … 4508 4733 n "ram_write_ready" 4509 4734 t "std_logic" 4735 posAdd 0 4510 4736 o 3 4511 4737 suid 12,0 … … 4513 4739 ) 4514 4740 ) 4515 *12 3(CptPort4741 *129 (CptPort 4516 4742 uid 2377,0 4517 4743 ps "OnEdgeStrategy" … … 4546 4772 t "roi_max_type" 4547 4773 posAdd 0 4548 o 84774 o 9 4549 4775 suid 14,0 4550 4776 i "(others => conv_std_logic_vector (0, 11))" … … 4552 4778 ) 4553 4779 ) 4554 *1 24(CptPort4780 *130 (CptPort 4555 4781 uid 2381,0 4556 4782 ps "OnEdgeStrategy" … … 4584 4810 n "wiz_busy" 4585 4811 t "std_logic" 4586 o 1 64812 o 17 4587 4813 suid 13,0 4588 4814 ) 4589 4815 ) 4590 4816 ) 4591 *1 25(CptPort4817 *131 (CptPort 4592 4818 uid 2385,0 4593 4819 ps "OnEdgeStrategy" … … 4623 4849 t "std_logic_vector" 4624 4850 b "(3 downto 0)" 4625 o 1 24851 o 13 4626 4852 suid 6,0 4627 4853 i "(others => '0')" … … 4629 4855 ) 4630 4856 ) 4631 *1 26(CptPort4857 *132 (CptPort 4632 4858 uid 2389,0 4633 4859 ps "OnEdgeStrategy" … … 4664 4890 b "(RAM_ADDR_WIDTH_16B-1 downto 0)" 4665 4891 preAdd 0 4666 o 1 04892 o 11 4667 4893 suid 7,0 4668 4894 i "(others => '0')" … … 4670 4896 ) 4671 4897 ) 4672 *1 27(CptPort4898 *133 (CptPort 4673 4899 uid 2393,0 4674 4900 ps "OnEdgeStrategy" … … 4703 4929 n "wiz_write_ea" 4704 4930 t "std_logic" 4705 o 1 34931 o 14 4706 4932 suid 8,0 4707 4933 i "'0'" … … 4709 4935 ) 4710 4936 ) 4711 *1 28(CptPort4937 *134 (CptPort 4712 4938 uid 2397,0 4713 4939 ps "OnEdgeStrategy" … … 4742 4968 n "wiz_write_end" 4743 4969 t "std_logic" 4744 o 1 54970 o 16 4745 4971 suid 9,0 4746 4972 i "'0'" … … 4748 4974 ) 4749 4975 ) 4750 *1 29(CptPort4976 *135 (CptPort 4751 4977 uid 2401,0 4752 4978 ps "OnEdgeStrategy" … … 4781 5007 n "wiz_write_header" 4782 5008 t "std_logic" 4783 o 1 45009 o 15 4784 5010 suid 10,0 4785 5011 i "'0'" … … 4787 5013 ) 4788 5014 ) 4789 *13 0(CptPort5015 *136 (CptPort 4790 5016 uid 2405,0 4791 5017 ps "OnEdgeStrategy" … … 4821 5047 t "std_logic_vector" 4822 5048 b "(16 downto 0)" 4823 o 1 15049 o 12 4824 5050 suid 11,0 4825 5051 i "(others => '0')" … … 4827 5053 ) 4828 5054 ) 4829 *13 1(CptPort5055 *137 (CptPort 4830 5056 uid 2454,0 4831 5057 ps "OnEdgeStrategy" … … 4858 5084 n "roi_array" 4859 5085 t "roi_array_type" 4860 o 4 5086 prec "-- --" 5087 preAdd 0 5088 o 5 4861 5089 suid 15,0 4862 5090 ) 4863 5091 ) 4864 5092 ) 4865 *13 2(CptPort5093 *138 (CptPort 4866 5094 uid 2628,0 4867 5095 ps "OnEdgeStrategy" … … 4896 5124 t "std_logic_vector" 4897 5125 b "(15 downto 0)" 4898 o 95126 o 10 4899 5127 suid 18,0 4900 5128 i "(others => '0')" … … 4902 5130 ) 4903 5131 ) 4904 *13 3(CptPort5132 *139 (CptPort 4905 5133 uid 5991,0 4906 5134 ps "OnEdgeStrategy" … … 4934 5162 n "config_started" 4935 5163 t "std_logic" 4936 o 75164 o 8 4937 5165 suid 21,0 4938 5166 i "'0'" … … 4940 5168 ) 4941 5169 ) 4942 *1 34(CptPort5170 *140 (CptPort 4943 5171 uid 8410,0 4944 5172 ps "OnEdgeStrategy" … … 4972 5200 n "wiz_ack" 4973 5201 t "std_logic" 4974 o 1 75202 o 18 4975 5203 suid 22,0 5204 ) 5205 ) 5206 ) 5207 *141 (CptPort 5208 uid 10232,0 5209 ps "OnEdgeStrategy" 5210 shape (Triangle 5211 uid 10233,0 5212 ro 270 5213 va (VaSet 5214 vasetType 1 5215 fg "0,65535,0" 5216 ) 5217 xt "71250,72625,72000,73375" 5218 ) 5219 tg (CPTG 5220 uid 10234,0 5221 ps "CptPortTextPlaceStrategy" 5222 stg "VerticalLayoutStrategy" 5223 f (Text 5224 uid 10235,0 5225 va (VaSet 5226 font "arial,8,0" 5227 ) 5228 xt "73000,72500,80800,73500" 5229 st "ram_write_ready_ack" 5230 blo "73000,73300" 5231 ) 5232 ) 5233 thePort (LogicalPort 5234 lang 2 5235 m 1 5236 decl (Decl 5237 n "ram_write_ready_ack" 5238 t "std_logic" 5239 prec "-- --" 5240 preAdd 0 5241 posAdd 0 5242 o 4 5243 suid 23,0 5244 i "'0'" 4976 5245 ) 4977 5246 ) … … 4994 5263 stg "VerticalLayoutStrategy" 4995 5264 textVec [ 4996 *1 35(Text5265 *142 (Text 4997 5266 uid 2314,0 4998 5267 va (VaSet … … 5004 5273 tm "BdLibraryNameMgr" 5005 5274 ) 5006 *1 36(Text5275 *143 (Text 5007 5276 uid 2315,0 5008 5277 va (VaSet … … 5014 5283 tm "CptNameMgr" 5015 5284 ) 5016 *1 37(Text5285 *144 (Text 5017 5286 uid 2316,0 5018 5287 va (VaSet … … 5073 5342 archFileType "UNKNOWN" 5074 5343 ) 5075 *1 38(Net5344 *145 (Net 5076 5345 uid 2468,0 5077 5346 lang 2 … … 5087 5356 font "Courier New,8,0" 5088 5357 ) 5089 xt "-103000,99400,-80500,100200" 5090 st "SIGNAL wiz_busy : std_logic 5091 " 5092 ) 5093 ) 5094 *139 (Net 5358 xt "-103000,109000,-80500,109800" 5359 st "SIGNAL wiz_busy : std_logic" 5360 ) 5361 ) 5362 *146 (Net 5095 5363 uid 2474,0 5096 5364 lang 2 … … 5107 5375 font "Courier New,8,0" 5108 5376 ) 5109 xt "-103000,101800,-59500,102600" 5110 st "SIGNAL wiz_write_ea : std_logic := '0' 5111 " 5112 ) 5113 ) 5114 *140 (Net 5377 xt "-103000,111400,-59500,112200" 5378 st "SIGNAL wiz_write_ea : std_logic := '0'" 5379 ) 5380 ) 5381 *147 (Net 5115 5382 uid 2480,0 5116 5383 lang 2 … … 5128 5395 font "Courier New,8,0" 5129 5396 ) 5130 xt "-103000,104200,-53500,105000" 5131 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') 5132 " 5133 ) 5134 ) 5135 *141 (Net 5397 xt "-103000,113800,-53500,114600" 5398 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0')" 5399 ) 5400 ) 5401 *148 (Net 5136 5402 uid 2486,0 5137 5403 lang 2 … … 5150 5416 font "Courier New,8,0" 5151 5417 ) 5152 xt "-103000,101000,-53500,101800" 5153 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') 5154 " 5155 ) 5156 ) 5157 *142 (Net 5418 xt "-103000,110600,-53500,111400" 5419 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')" 5420 ) 5421 ) 5422 *149 (Net 5158 5423 uid 2492,0 5159 5424 lang 2 … … 5171 5436 font "Courier New,8,0" 5172 5437 ) 5173 xt "-103000,100200,-53500,101000" 5174 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') 5175 " 5176 ) 5177 ) 5178 *143 (Net 5438 xt "-103000,109800,-53500,110600" 5439 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0')" 5440 ) 5441 ) 5442 *150 (Net 5179 5443 uid 2498,0 5180 5444 lang 2 … … 5191 5455 font "Courier New,8,0" 5192 5456 ) 5193 xt "-103000,102600,-59500,103400" 5194 st "SIGNAL wiz_write_end : std_logic := '0' 5195 " 5196 ) 5197 ) 5198 *144 (Net 5457 xt "-103000,112200,-59500,113000" 5458 st "SIGNAL wiz_write_end : std_logic := '0'" 5459 ) 5460 ) 5461 *151 (Net 5199 5462 uid 2504,0 5200 5463 lang 2 … … 5211 5474 font "Courier New,8,0" 5212 5475 ) 5213 xt "-103000,103400,-59500,104200" 5214 st "SIGNAL wiz_write_header : std_logic := '0' 5215 " 5216 ) 5217 ) 5218 *145 (Net 5476 xt "-103000,113000,-59500,113800" 5477 st "SIGNAL wiz_write_header : std_logic := '0'" 5478 ) 5479 ) 5480 *152 (Net 5219 5481 uid 2574,0 5220 5482 decl (Decl … … 5229 5491 font "Courier New,8,0" 5230 5492 ) 5231 xt "-103000,89800,-80500,90600" 5232 st "SIGNAL ram_write_ea : std_logic 5233 " 5234 ) 5235 ) 5236 *146 (Net 5493 xt "-103000,94600,-80500,95400" 5494 st "SIGNAL ram_write_ea : std_logic" 5495 ) 5496 ) 5497 *153 (Net 5237 5498 uid 2580,0 5238 5499 decl (Decl … … 5248 5509 font "Courier New,8,0" 5249 5510 ) 5250 xt "-103000,90600,-59500,91400" 5251 st "SIGNAL ram_write_ready : std_logic := '0' 5252 " 5253 ) 5254 ) 5255 *147 (Net 5511 xt "-103000,95400,-59500,96200" 5512 st "SIGNAL ram_write_ready : std_logic := '0'" 5513 ) 5514 ) 5515 *154 (Net 5256 5516 uid 2586,0 5257 5517 decl (Decl … … 5267 5527 font "Courier New,8,0" 5268 5528 ) 5269 xt "-103000,68200,-59500,69000" 5270 st "SIGNAL config_start : std_logic := '0' 5271 " 5272 ) 5273 ) 5274 *148 (Net 5529 xt "-103000,72200,-59500,73000" 5530 st "SIGNAL config_start : std_logic := '0'" 5531 ) 5532 ) 5533 *155 (Net 5275 5534 uid 2592,0 5276 5535 decl (Decl … … 5285 5544 font "Courier New,8,0" 5286 5545 ) 5287 xt "-103000,65800,-80500,66600" 5288 st "SIGNAL config_ready : std_logic 5289 " 5290 ) 5291 ) 5292 *149 (Net 5546 xt "-103000,66600,-80500,67400" 5547 st "SIGNAL config_ready : std_logic" 5548 ) 5549 ) 5550 *156 (Net 5293 5551 uid 2598,0 5294 5552 decl (Decl … … 5303 5561 font "Courier New,8,0" 5304 5562 ) 5305 xt "-103000,92200,-79000,93000" 5306 st "SIGNAL roi_max : roi_max_type 5307 " 5308 ) 5309 ) 5310 *150 (Net 5563 xt "-103000,98600,-79000,99400" 5564 st "SIGNAL roi_max : roi_max_type" 5565 ) 5566 ) 5567 *157 (Net 5311 5568 uid 2640,0 5312 5569 decl (Decl … … 5322 5579 font "Courier New,8,0" 5323 5580 ) 5324 xt "-103000,84200,-70500,85000" 5325 st "SIGNAL package_length : std_logic_vector(15 downto 0) 5326 " 5327 ) 5328 ) 5329 *151 (Net 5581 xt "-103000,89000,-70500,89800" 5582 st "SIGNAL package_length : std_logic_vector(15 downto 0)" 5583 ) 5584 ) 5585 *158 (Net 5330 5586 uid 2776,0 5331 5587 decl (Decl … … 5341 5597 font "Courier New,8,0" 5342 5598 ) 5343 xt "-103000,39800,-63000,40600" 5344 st "adc_oeb : std_logic := '1' 5345 " 5346 ) 5347 ) 5348 *152 (PortIoOut 5599 xt "-103000,40600,-63000,41400" 5600 st "adc_oeb : std_logic := '1'" 5601 ) 5602 ) 5603 *159 (PortIoOut 5349 5604 uid 2798,0 5350 5605 shape (CompositeShape … … 5391 5646 ) 5392 5647 ) 5393 *1 53(PortIoIn5648 *160 (PortIoIn 5394 5649 uid 2804,0 5395 5650 shape (CompositeShape … … 5436 5691 ) 5437 5692 ) 5438 *1 54(Net5693 *161 (Net 5439 5694 uid 2924,0 5440 5695 decl (Decl … … 5449 5704 font "Courier New,8,0" 5450 5705 ) 5451 xt "-103000,91400,-78000,92200" 5452 st "SIGNAL roi_array : roi_array_type 5453 " 5454 ) 5455 ) 5456 *155 (PortIoIn 5706 xt "-103000,97800,-78000,98600" 5707 st "SIGNAL roi_array : roi_array_type" 5708 ) 5709 ) 5710 *162 (PortIoIn 5457 5711 uid 2950,0 5458 5712 shape (CompositeShape … … 5499 5753 ) 5500 5754 ) 5501 *1 56(PortIoIn5755 *163 (PortIoIn 5502 5756 uid 2956,0 5503 5757 shape (CompositeShape … … 5544 5798 ) 5545 5799 ) 5546 *1 57(Grouping5800 *164 (Grouping 5547 5801 uid 3137,0 5548 5802 optionalChildren [ 5549 *1 58(CommentText5803 *165 (CommentText 5550 5804 uid 3139,0 5551 5805 shape (Rectangle … … 5565 5819 bg "0,0,32768" 5566 5820 ) 5567 xt "125200,175000,134 900,176000"5821 xt "125200,175000,134700,176000" 5568 5822 st " 5569 5823 by %user on %dd %month %year … … 5578 5832 titleBlock 1 5579 5833 ) 5580 *1 59(CommentText5834 *166 (CommentText 5581 5835 uid 3142,0 5582 5836 shape (Rectangle … … 5609 5863 titleBlock 1 5610 5864 ) 5611 *16 0(CommentText5865 *167 (CommentText 5612 5866 uid 3145,0 5613 5867 shape (Rectangle … … 5640 5894 titleBlock 1 5641 5895 ) 5642 *16 1(CommentText5896 *168 (CommentText 5643 5897 uid 3148,0 5644 5898 shape (Rectangle … … 5671 5925 titleBlock 1 5672 5926 ) 5673 *16 2(CommentText5927 *169 (CommentText 5674 5928 uid 3151,0 5675 5929 shape (Rectangle … … 5701 5955 titleBlock 1 5702 5956 ) 5703 *1 63(CommentText5957 *170 (CommentText 5704 5958 uid 3154,0 5705 5959 shape (Rectangle … … 5732 5986 titleBlock 1 5733 5987 ) 5734 *1 64(CommentText5988 *171 (CommentText 5735 5989 uid 3157,0 5736 5990 shape (Rectangle … … 5764 6018 titleBlock 1 5765 6019 ) 5766 *1 65(CommentText6020 *172 (CommentText 5767 6021 uid 3160,0 5768 6022 shape (Rectangle … … 5795 6049 titleBlock 1 5796 6050 ) 5797 *1 66(CommentText6051 *173 (CommentText 5798 6052 uid 3163,0 5799 6053 shape (Rectangle … … 5826 6080 titleBlock 1 5827 6081 ) 5828 *1 67(CommentText6082 *174 (CommentText 5829 6083 uid 3166,0 5830 6084 shape (Rectangle … … 5870 6124 oxt "14000,66000,55000,71000" 5871 6125 ) 5872 *1 68(Net6126 *175 (Net 5873 6127 uid 3894,0 5874 6128 decl (Decl … … 5884 6138 ) 5885 6139 xt "-103000,29400,-84500,30200" 5886 st "CLK_25_PS : std_logic 5887 " 5888 ) 5889 ) 5890 *169 (PortIoOut 6140 st "CLK_25_PS : std_logic" 6141 ) 6142 ) 6143 *176 (PortIoOut 5891 6144 uid 3978,0 5892 6145 shape (CompositeShape … … 5933 6186 ) 5934 6187 ) 5935 *17 0(Net6188 *177 (Net 5936 6189 uid 4068,0 5937 6190 decl (Decl … … 5947 6200 ) 5948 6201 xt "-103000,30200,-84500,31000" 5949 st "CLK_50 : std_logic 5950 " 5951 ) 5952 ) 5953 *171 (Net 6202 st "CLK_50 : std_logic" 6203 ) 6204 ) 6205 *178 (Net 5954 6206 uid 4204,0 5955 6207 decl (Decl … … 5964 6216 font "Courier New,8,0" 5965 6217 ) 5966 xt "-103000,57800,-80500,58600" 5967 st "SIGNAL CLK_25 : std_logic 5968 " 5969 ) 5970 ) 5971 *172 (PortIoOut 6218 xt "-103000,58600,-80500,59400" 6219 st "SIGNAL CLK_25 : std_logic" 6220 ) 6221 ) 6222 *179 (PortIoOut 5972 6223 uid 4220,0 5973 6224 shape (CompositeShape … … 6014 6265 ) 6015 6266 ) 6016 *1 73(Net6267 *180 (Net 6017 6268 uid 4232,0 6018 6269 decl (Decl … … 6028 6279 ) 6029 6280 xt "-103000,18200,-84500,19000" 6030 st "CLK : std_logic 6031 " 6032 ) 6033 ) 6034 *174 (Net 6281 st "CLK : std_logic" 6282 ) 6283 ) 6284 *181 (Net 6035 6285 uid 4260,0 6036 6286 decl (Decl … … 6047 6297 ) 6048 6298 xt "-103000,23000,-74500,23800" 6049 st "adc_otr_array : std_logic_vector(3 DOWNTO 0) 6050 " 6051 ) 6052 ) 6053 *175 (Net 6299 st "adc_otr_array : std_logic_vector(3 DOWNTO 0)" 6300 ) 6301 ) 6302 *182 (Net 6054 6303 uid 4270,0 6055 6304 decl (Decl … … 6065 6314 ) 6066 6315 xt "-103000,22200,-79000,23000" 6067 st "adc_data_array : adc_data_array_type 6068 " 6069 ) 6070 ) 6071 *176 (PortIoIn 6316 st "adc_data_array : adc_data_array_type" 6317 ) 6318 ) 6319 *183 (PortIoIn 6072 6320 uid 4307,0 6073 6321 shape (CompositeShape … … 6114 6362 ) 6115 6363 ) 6116 *1 77(Net6364 *184 (Net 6117 6365 uid 4399,0 6118 6366 decl (Decl … … 6128 6376 font "Courier New,8,0" 6129 6377 ) 6130 xt "-103000,78600,-59500,79400" 6131 st "SIGNAL drs_clk_en : std_logic := '0' 6132 " 6133 ) 6134 ) 6135 *178 (Net 6378 xt "-103000,82600,-59500,83400" 6379 st "SIGNAL drs_clk_en : std_logic := '0'" 6380 ) 6381 ) 6382 *185 (Net 6136 6383 uid 4405,0 6137 6384 decl (Decl … … 6146 6393 font "Courier New,8,0" 6147 6394 ) 6148 xt "-103000,81000,-74500,81800" 6149 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type 6150 " 6151 ) 6152 ) 6153 *179 (Net 6395 xt "-103000,85000,-74500,85800" 6396 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type" 6397 ) 6398 ) 6399 *186 (Net 6154 6400 uid 4417,0 6155 6401 decl (Decl … … 6165 6411 font "Courier New,8,0" 6166 6412 ) 6167 xt "-103000,79400,-59500,80200" 6168 st "SIGNAL drs_read_s_cell : std_logic := '0' 6169 " 6170 ) 6171 ) 6172 *180 (Net 6413 xt "-103000,83400,-59500,84200" 6414 st "SIGNAL drs_read_s_cell : std_logic := '0'" 6415 ) 6416 ) 6417 *187 (Net 6173 6418 uid 4535,0 6174 6419 decl (Decl … … 6185 6430 font "Courier New,8,0" 6186 6431 ) 6187 xt "-103000,42200,-57000,43000" 6188 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6189 " 6190 ) 6191 ) 6192 *181 (Net 6432 xt "-103000,43000,-57000,43800" 6433 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 6434 ) 6435 ) 6436 *188 (Net 6193 6437 uid 4543,0 6194 6438 decl (Decl … … 6204 6448 font "Courier New,8,0" 6205 6449 ) 6206 xt "-103000,43000,-63000,43800" 6207 st "drs_dwrite : std_logic := '1' 6208 " 6209 ) 6210 ) 6211 *182 (PortIoOut 6450 xt "-103000,43800,-63000,44600" 6451 st "drs_dwrite : std_logic := '1'" 6452 ) 6453 ) 6454 *189 (PortIoOut 6212 6455 uid 4551,0 6213 6456 shape (CompositeShape … … 6254 6497 ) 6255 6498 ) 6256 *1 83(PortIoOut6499 *190 (PortIoOut 6257 6500 uid 4557,0 6258 6501 shape (CompositeShape … … 6299 6542 ) 6300 6543 ) 6301 *1 84(Net6544 *191 (Net 6302 6545 uid 4669,0 6303 6546 decl (Decl … … 6313 6556 ) 6314 6557 xt "-103000,19000,-84500,19800" 6315 st "SROUT_in_0 : std_logic 6316 " 6317 ) 6318 ) 6319 *185 (Net 6558 st "SROUT_in_0 : std_logic" 6559 ) 6560 ) 6561 *192 (Net 6320 6562 uid 4677,0 6321 6563 decl (Decl … … 6331 6573 ) 6332 6574 xt "-103000,19800,-84500,20600" 6333 st "SROUT_in_1 : std_logic 6334 " 6335 ) 6336 ) 6337 *186 (Net 6575 st "SROUT_in_1 : std_logic" 6576 ) 6577 ) 6578 *193 (Net 6338 6579 uid 4685,0 6339 6580 decl (Decl … … 6349 6590 ) 6350 6591 xt "-103000,20600,-84500,21400" 6351 st "SROUT_in_2 : std_logic 6352 " 6353 ) 6354 ) 6355 *187 (Net 6592 st "SROUT_in_2 : std_logic" 6593 ) 6594 ) 6595 *194 (Net 6356 6596 uid 4693,0 6357 6597 decl (Decl … … 6367 6607 ) 6368 6608 xt "-103000,21400,-84500,22200" 6369 st "SROUT_in_3 : std_logic 6370 " 6371 ) 6372 ) 6373 *188 (PortIoIn 6609 st "SROUT_in_3 : std_logic" 6610 ) 6611 ) 6612 *195 (PortIoIn 6374 6613 uid 4701,0 6375 6614 shape (CompositeShape … … 6416 6655 ) 6417 6656 ) 6418 *1 89(PortIoIn6657 *196 (PortIoIn 6419 6658 uid 4707,0 6420 6659 shape (CompositeShape … … 6461 6700 ) 6462 6701 ) 6463 *19 0(PortIoIn6702 *197 (PortIoIn 6464 6703 uid 4713,0 6465 6704 shape (CompositeShape … … 6506 6745 ) 6507 6746 ) 6508 *19 1(PortIoIn6747 *198 (PortIoIn 6509 6748 uid 4719,0 6510 6749 shape (CompositeShape … … 6551 6790 ) 6552 6791 ) 6553 *19 2(Net6792 *199 (Net 6554 6793 uid 4741,0 6555 6794 decl (Decl … … 6564 6803 font "Courier New,8,0" 6565 6804 ) 6566 xt "-103000,80200,-80500,81000" 6567 st "SIGNAL drs_read_s_cell_ready : std_logic 6568 " 6569 ) 6570 ) 6571 *193 (SaComponent 6805 xt "-103000,84200,-80500,85000" 6806 st "SIGNAL drs_read_s_cell_ready : std_logic" 6807 ) 6808 ) 6809 *200 (SaComponent 6572 6810 uid 4903,0 6573 6811 optionalChildren [ 6574 * 194(CptPort6812 *201 (CptPort 6575 6813 uid 4867,0 6576 6814 ps "OnEdgeStrategy" … … 6605 6843 ) 6606 6844 ) 6607 * 195(CptPort6845 *202 (CptPort 6608 6846 uid 4871,0 6609 6847 ps "OnEdgeStrategy" … … 6615 6853 fg "0,65535,0" 6616 6854 ) 6617 xt "1000, 52625,1750,53375"6855 xt "1000,48625,1750,49375" 6618 6856 ) 6619 6857 tg (CPTG … … 6625 6863 va (VaSet 6626 6864 ) 6627 xt "-7500, 52500,0,53500"6865 xt "-7500,48500,0,49500" 6628 6866 st "start_endless_mode" 6629 6867 ju 2 6630 blo "0, 53300"6868 blo "0,49300" 6631 6869 ) 6632 6870 ) … … 6639 6877 ) 6640 6878 ) 6641 * 196(CptPort6879 *203 (CptPort 6642 6880 uid 4875,0 6643 6881 ps "OnEdgeStrategy" … … 6649 6887 fg "0,65535,0" 6650 6888 ) 6651 xt "1000,4 9625,1750,50375"6889 xt "1000,45625,1750,46375" 6652 6890 ) 6653 6891 tg (CPTG … … 6659 6897 va (VaSet 6660 6898 ) 6661 xt "-10200,4 9500,0,50500"6899 xt "-10200,45500,0,46500" 6662 6900 st "start_read_stop_pos_mode" 6663 6901 ju 2 6664 blo "0, 50300"6902 blo "0,46300" 6665 6903 ) 6666 6904 ) … … 6673 6911 ) 6674 6912 ) 6675 * 197(CptPort6913 *204 (CptPort 6676 6914 uid 4879,0 6677 6915 ps "OnEdgeStrategy" … … 6706 6944 ) 6707 6945 ) 6708 * 198(CptPort6946 *205 (CptPort 6709 6947 uid 4883,0 6710 6948 ps "OnEdgeStrategy" … … 6739 6977 ) 6740 6978 ) 6741 * 199(CptPort6979 *206 (CptPort 6742 6980 uid 4887,0 6743 6981 ps "OnEdgeStrategy" … … 6772 7010 ) 6773 7011 ) 6774 *20 0(CptPort7012 *207 (CptPort 6775 7013 uid 4891,0 6776 7014 ps "OnEdgeStrategy" … … 6805 7043 ) 6806 7044 ) 6807 *20 1(CptPort7045 *208 (CptPort 6808 7046 uid 4895,0 6809 7047 ps "OnEdgeStrategy" … … 6815 7053 fg "0,65535,0" 6816 7054 ) 6817 xt "1000, 51625,1750,52375"7055 xt "1000,47625,1750,48375" 6818 7056 ) 6819 7057 tg (CPTG … … 6825 7063 va (VaSet 6826 7064 ) 6827 xt "-3400, 51500,0,52500"7065 xt "-3400,47500,0,48500" 6828 7066 st "stop_pos" 6829 7067 ju 2 6830 blo "0, 52300"7068 blo "0,48300" 6831 7069 ) 6832 7070 ) … … 6840 7078 ) 6841 7079 ) 6842 *20 2(CptPort7080 *209 (CptPort 6843 7081 uid 4899,0 6844 7082 ps "OnEdgeStrategy" … … 6850 7088 fg "0,65535,0" 6851 7089 ) 6852 xt "1000, 50625,1750,51375"7090 xt "1000,46625,1750,47375" 6853 7091 ) 6854 7092 tg (CPTG … … 6860 7098 va (VaSet 6861 7099 ) 6862 xt "-5700, 50500,0,51500"7100 xt "-5700,46500,0,47500" 6863 7101 st "stop_pos_valid" 6864 7102 ju 2 6865 blo "0, 51300"7103 blo "0,47300" 6866 7104 ) 6867 7105 ) … … 6876 7114 ) 6877 7115 ) 6878 *2 03(CptPort7116 *210 (CptPort 6879 7117 uid 4938,0 6880 7118 ps "OnEdgeStrategy" … … 6906 7144 n "RSRLOAD" 6907 7145 t "std_logic" 6908 o 1 07146 o 15 6909 7147 i "'0'" 6910 7148 ) 6911 7149 ) 6912 7150 ) 6913 *2 04(CptPort7151 *211 (CptPort 6914 7152 uid 4942,0 6915 7153 ps "OnEdgeStrategy" … … 6941 7179 n "SRCLK" 6942 7180 t "std_logic" 7181 o 16 7182 i "'0'" 7183 ) 7184 ) 7185 ) 7186 *212 (CptPort 7187 uid 10272,0 7188 ps "OnEdgeStrategy" 7189 shape (Triangle 7190 uid 10273,0 7191 ro 270 7192 va (VaSet 7193 vasetType 1 7194 fg "0,65535,0" 7195 ) 7196 xt "1000,56625,1750,57375" 7197 ) 7198 tg (CPTG 7199 uid 10274,0 7200 ps "CptPortTextPlaceStrategy" 7201 stg "RightVerticalLayoutStrategy" 7202 f (Text 7203 uid 10275,0 7204 va (VaSet 7205 ) 7206 xt "-6100,56500,0,57500" 7207 st "srin_data : (7:0)" 7208 ju 2 7209 blo "0,57300" 7210 ) 7211 ) 7212 thePort (LogicalPort 7213 decl (Decl 7214 n "srin_data" 7215 t "std_logic_vector" 7216 b "(7 downto 0)" 7217 o 13 7218 ) 7219 ) 7220 ) 7221 *213 (CptPort 7222 uid 10276,0 7223 ps "OnEdgeStrategy" 7224 shape (Triangle 7225 uid 10277,0 7226 ro 270 7227 va (VaSet 7228 vasetType 1 7229 fg "0,65535,0" 7230 ) 7231 xt "-18750,56625,-18000,57375" 7232 ) 7233 tg (CPTG 7234 uid 10278,0 7235 ps "CptPortTextPlaceStrategy" 7236 stg "VerticalLayoutStrategy" 7237 f (Text 7238 uid 10279,0 7239 va (VaSet 7240 ) 7241 xt "-17000,56500,-13300,57500" 7242 st "SRIN_out" 7243 blo "-17000,57300" 7244 ) 7245 ) 7246 thePort (LogicalPort 7247 m 1 7248 decl (Decl 7249 n "SRIN_out" 7250 t "std_logic" 7251 o 14 7252 i "'0'" 7253 ) 7254 ) 7255 ) 7256 *214 (CptPort 7257 uid 10280,0 7258 ps "OnEdgeStrategy" 7259 shape (Triangle 7260 uid 10281,0 7261 ro 90 7262 va (VaSet 7263 vasetType 1 7264 fg "0,65535,0" 7265 ) 7266 xt "1000,54625,1750,55375" 7267 ) 7268 tg (CPTG 7269 uid 10282,0 7270 ps "CptPortTextPlaceStrategy" 7271 stg "RightVerticalLayoutStrategy" 7272 f (Text 7273 uid 10283,0 7274 va (VaSet 7275 ) 7276 xt "-5600,54500,0,55500" 7277 st "srin_write_ack" 7278 ju 2 7279 blo "0,55300" 7280 ) 7281 ) 7282 thePort (LogicalPort 7283 m 1 7284 decl (Decl 7285 n "srin_write_ack" 7286 t "std_logic" 7287 o 12 7288 i "'0'" 7289 ) 7290 ) 7291 ) 7292 *215 (CptPort 7293 uid 10284,0 7294 ps "OnEdgeStrategy" 7295 shape (Triangle 7296 uid 10285,0 7297 ro 90 7298 va (VaSet 7299 vasetType 1 7300 fg "0,65535,0" 7301 ) 7302 xt "1000,55625,1750,56375" 7303 ) 7304 tg (CPTG 7305 uid 10286,0 7306 ps "CptPortTextPlaceStrategy" 7307 stg "RightVerticalLayoutStrategy" 7308 f (Text 7309 uid 10287,0 7310 va (VaSet 7311 ) 7312 xt "-6300,55500,0,56500" 7313 st "srin_write_ready" 7314 ju 2 7315 blo "0,56300" 7316 ) 7317 ) 7318 thePort (LogicalPort 7319 m 1 7320 decl (Decl 7321 n "srin_write_ready" 7322 t "std_logic" 6943 7323 o 11 6944 7324 i "'0'" 7325 ) 7326 ) 7327 ) 7328 *216 (CptPort 7329 uid 10288,0 7330 ps "OnEdgeStrategy" 7331 shape (Triangle 7332 uid 10289,0 7333 ro 270 7334 va (VaSet 7335 vasetType 1 7336 fg "0,65535,0" 7337 ) 7338 xt "1000,53625,1750,54375" 7339 ) 7340 tg (CPTG 7341 uid 10290,0 7342 ps "CptPortTextPlaceStrategy" 7343 stg "RightVerticalLayoutStrategy" 7344 f (Text 7345 uid 10291,0 7346 va (VaSet 7347 ) 7348 xt "-7200,53500,0,54500" 7349 st "start_srin_write_8b" 7350 ju 2 7351 blo "0,54300" 7352 ) 7353 ) 7354 thePort (LogicalPort 7355 decl (Decl 7356 n "start_srin_write_8b" 7357 t "std_logic" 7358 o 10 6945 7359 ) 6946 7360 ) … … 6955 7369 lineWidth 2 6956 7370 ) 6957 xt "-18000,44000,1000,5 4000"7371 xt "-18000,44000,1000,59000" 6958 7372 ) 6959 7373 oxt "0,0,8000,10000" … … 6963 7377 stg "VerticalLayoutStrategy" 6964 7378 textVec [ 6965 *2 05(Text7379 *217 (Text 6966 7380 uid 4906,0 6967 7381 va (VaSet 6968 7382 font "Arial,8,1" 6969 7383 ) 6970 xt "-1 7400,54000,-10800,55000"7384 xt "-12400,41000,-5800,42000" 6971 7385 st "FACT_FAD_LIB" 6972 blo "-1 7400,54800"7386 blo "-12400,41800" 6973 7387 tm "BdLibraryNameMgr" 6974 7388 ) 6975 *2 06(Text7389 *218 (Text 6976 7390 uid 4907,0 6977 7391 va (VaSet 6978 7392 font "Arial,8,1" 6979 7393 ) 6980 xt "-1 7400,55000,-12700,56000"7394 xt "-12400,42000,-7700,43000" 6981 7395 st "drs_pulser" 6982 blo "-1 7400,55800"7396 blo "-12400,42800" 6983 7397 tm "CptNameMgr" 6984 7398 ) 6985 *2 07(Text7399 *219 (Text 6986 7400 uid 4908,0 6987 7401 va (VaSet 6988 7402 font "Arial,8,1" 6989 7403 ) 6990 xt "-1 7400,56000,-9900,57000"7404 xt "-12400,43000,-4900,44000" 6991 7405 st "I_main_drs_pulser" 6992 blo "-1 7400,56800"7406 blo "-12400,43800" 6993 7407 tm "InstanceNameMgr" 6994 7408 ) … … 7019 7433 fg "49152,49152,49152" 7020 7434 ) 7021 xt "-17750,5 2250,-16250,53750"7435 xt "-17750,57250,-16250,58750" 7022 7436 iconName "VhdlFileViewIcon.png" 7023 7437 iconMaskName "VhdlFileViewIcon.msk" … … 7030 7444 archFileType "UNKNOWN" 7031 7445 ) 7032 *2 08(Net7446 *220 (Net 7033 7447 uid 4946,0 7034 7448 decl (Decl … … 7045 7459 ) 7046 7460 xt "-103000,37400,-63000,38200" 7047 st "RSRLOAD : std_logic := '0' 7048 " 7049 ) 7050 ) 7051 *209 (PortIoOut 7461 st "RSRLOAD : std_logic := '0'" 7462 ) 7463 ) 7464 *221 (PortIoOut 7052 7465 uid 4954,0 7053 7466 shape (CompositeShape … … 7094 7507 ) 7095 7508 ) 7096 *2 10(Net7509 *222 (Net 7097 7510 uid 4960,0 7098 7511 decl (Decl … … 7109 7522 ) 7110 7523 xt "-103000,38200,-63000,39000" 7111 st "SRCLK : std_logic := '0' 7112 " 7113 ) 7114 ) 7115 *211 (PortIoOut 7524 st "SRCLK : std_logic := '0'" 7525 ) 7526 ) 7527 *223 (PortIoOut 7116 7528 uid 4968,0 7117 7529 shape (CompositeShape … … 7158 7570 ) 7159 7571 ) 7160 *2 12(SaComponent7572 *224 (SaComponent 7161 7573 uid 5072,0 7162 7574 optionalChildren [ 7163 *2 13(CptPort7575 *225 (CptPort 7164 7576 uid 5028,0 7165 7577 ps "OnEdgeStrategy" … … 7195 7607 ) 7196 7608 ) 7197 *2 14(CptPort7609 *226 (CptPort 7198 7610 uid 5032,0 7199 7611 ps "OnEdgeStrategy" … … 7231 7643 ) 7232 7644 ) 7233 *2 15(CptPort7645 *227 (CptPort 7234 7646 uid 5036,0 7235 7647 ps "OnEdgeStrategy" … … 7267 7679 ) 7268 7680 ) 7269 *2 16(CptPort7681 *228 (CptPort 7270 7682 uid 5040,0 7271 7683 ps "OnEdgeStrategy" … … 7303 7715 ) 7304 7716 ) 7305 *2 17(CptPort7717 *229 (CptPort 7306 7718 uid 5044,0 7307 7719 ps "OnEdgeStrategy" … … 7340 7752 ) 7341 7753 ) 7342 *2 18(CptPort7754 *230 (CptPort 7343 7755 uid 5048,0 7344 7756 ps "OnEdgeStrategy" … … 7375 7787 ) 7376 7788 ) 7377 *2 19(CptPort7789 *231 (CptPort 7378 7790 uid 5052,0 7379 7791 ps "OnEdgeStrategy" … … 7410 7822 ) 7411 7823 ) 7412 *2 20(CptPort7824 *232 (CptPort 7413 7825 uid 5056,0 7414 7826 ps "OnEdgeStrategy" … … 7440 7852 n "dac_array" 7441 7853 t "dac_array_type" 7442 o 1 07854 o 12 7443 7855 suid 8,0 7444 7856 ) 7445 7857 ) 7446 7858 ) 7447 *2 21(CptPort7859 *233 (CptPort 7448 7860 uid 5060,0 7449 7861 ps "OnEdgeStrategy" … … 7480 7892 ) 7481 7893 ) 7482 *2 22(CptPort7894 *234 (CptPort 7483 7895 uid 5064,0 7484 7896 ps "OnEdgeStrategy" … … 7514 7926 ) 7515 7927 ) 7516 *2 23(CptPort7928 *235 (CptPort 7517 7929 uid 5068,0 7518 7930 ps "OnEdgeStrategy" … … 7549 7961 ) 7550 7962 ) 7551 *2 24(CptPort7963 *236 (CptPort 7552 7964 uid 5995,0 7553 7965 ps "OnEdgeStrategy" … … 7579 7991 n "config_started" 7580 7992 t "std_logic" 7581 o 97993 o 11 7582 7994 suid 12,0 7583 7995 i "'0'" … … 7585 7997 ) 7586 7998 ) 7587 *2 25(CptPort7588 uid 8500,07999 *237 (CptPort 8000 uid 10184,0 7589 8001 ps "OnEdgeStrategy" 7590 8002 shape (Triangle 7591 uid 8501,08003 uid 10185,0 7592 8004 ro 90 7593 8005 va (VaSet … … 7598 8010 ) 7599 8011 tg (CPTG 7600 uid 8502,08012 uid 10186,0 7601 8013 ps "CptPortTextPlaceStrategy" 7602 8014 stg "RightVerticalLayoutStrategy" 7603 8015 f (Text 7604 uid 8503,07605 va (VaSet 7606 ) 7607 xt "8 3800,109500,91000,110500"7608 st " drs_address : (3:0)"8016 uid 10187,0 8017 va (VaSet 8018 ) 8019 xt "85400,109500,91000,110500" 8020 st "config_rw_ack" 7609 8021 ju 2 7610 8022 blo "91000,110300" … … 7614 8026 m 1 7615 8027 decl (Decl 7616 n "drs_address" 7617 t "std_logic_vector" 7618 b "(3 DOWNTO 0)" 7619 o 11 7620 suid 13,0 7621 ) 7622 ) 7623 ) 7624 *226 (CptPort 7625 uid 8504,0 8028 n "config_rw_ack" 8029 t "std_logic" 8030 prec "-- --" 8031 preAdd 0 8032 posAdd 0 8033 o 9 8034 suid 15,0 8035 i "'0'" 8036 ) 8037 ) 8038 ) 8039 *238 (CptPort 8040 uid 10188,0 7626 8041 ps "OnEdgeStrategy" 7627 8042 shape (Triangle 7628 uid 8505,08043 uid 10189,0 7629 8044 ro 90 7630 8045 va (VaSet … … 7635 8050 ) 7636 8051 tg (CPTG 7637 uid 8506,08052 uid 10190,0 7638 8053 ps "CptPortTextPlaceStrategy" 7639 8054 stg "RightVerticalLayoutStrategy" 7640 8055 f (Text 7641 uid 8507,07642 va (VaSet 7643 ) 7644 xt "8 3800,110500,91000,111500"7645 st " drs_address_mode"8056 uid 10191,0 8057 va (VaSet 8058 ) 8059 xt "84700,110500,91000,111500" 8060 st "config_rw_ready" 7646 8061 ju 2 7647 8062 blo "91000,111300" … … 7651 8066 m 1 7652 8067 decl (Decl 7653 n "drs_address_mode" 7654 t "std_logic" 7655 o 12 7656 suid 14,0 8068 n "config_rw_ready" 8069 t "std_logic" 8070 prec "-- --" 8071 preAdd 0 8072 posAdd 0 8073 o 10 8074 suid 16,0 8075 i "'0'" 7657 8076 ) 7658 8077 ) … … 7675 8094 stg "VerticalLayoutStrategy" 7676 8095 textVec [ 7677 *2 27(Text8096 *239 (Text 7678 8097 uid 5075,0 7679 8098 va (VaSet … … 7685 8104 tm "BdLibraryNameMgr" 7686 8105 ) 7687 *2 28(Text8106 *240 (Text 7688 8107 uid 5076,0 7689 8108 va (VaSet … … 7695 8114 tm "CptNameMgr" 7696 8115 ) 7697 *2 29(Text8116 *241 (Text 7698 8117 uid 5077,0 7699 8118 va (VaSet … … 7741 8160 archFileType "UNKNOWN" 7742 8161 ) 7743 *2 30(Net8162 *242 (Net 7744 8163 uid 5088,0 7745 8164 decl (Decl … … 7755 8174 font "Courier New,8,0" 7756 8175 ) 7757 xt "-103000,61800,-71000,62600" 7758 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0) 7759 " 7760 ) 7761 ) 7762 *231 (Net 8176 xt "-103000,62600,-71000,63400" 8177 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0)" 8178 ) 8179 ) 8180 *243 (Net 7763 8181 uid 5096,0 7764 8182 decl (Decl … … 7773 8191 font "Courier New,8,0" 7774 8192 ) 7775 xt "-103000,64200,-80500,65000" 7776 st "SIGNAL config_data_valid : std_logic 7777 " 7778 ) 7779 ) 7780 *232 (Net 8193 xt "-103000,65000,-80500,65800" 8194 st "SIGNAL config_data_valid : std_logic" 8195 ) 8196 ) 8197 *244 (Net 7781 8198 uid 5104,0 7782 8199 decl (Decl … … 7791 8208 font "Courier New,8,0" 7792 8209 ) 7793 xt "-103000,62600,-80500,63400" 7794 st "SIGNAL config_busy : std_logic 7795 " 7796 ) 7797 ) 7798 *233 (Net 8210 xt "-103000,63400,-80500,64200" 8211 st "SIGNAL config_busy : std_logic" 8212 ) 8213 ) 8214 *245 (Net 7799 8215 uid 5112,0 7800 8216 decl (Decl … … 7810 8226 font "Courier New,8,0" 7811 8227 ) 7812 xt "-103000,63400,-70500,64200" 7813 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0) 7814 " 7815 ) 7816 ) 7817 *234 (Net 8228 xt "-103000,64200,-70500,65000" 8229 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0)" 8230 ) 8231 ) 8232 *246 (Net 7818 8233 uid 5120,0 7819 8234 decl (Decl … … 7828 8243 font "Courier New,8,0" 7829 8244 ) 7830 xt "-103000,73800,-80500,74600" 7831 st "SIGNAL config_wr_en : std_logic 7832 " 7833 ) 7834 ) 7835 *235 (Net 8245 xt "-103000,77800,-80500,78600" 8246 st "SIGNAL config_wr_en : std_logic" 8247 ) 8248 ) 8249 *247 (Net 7836 8250 uid 5128,0 7837 8251 decl (Decl … … 7846 8260 font "Courier New,8,0" 7847 8261 ) 7848 xt "-103000,65000,-80500,65800" 7849 st "SIGNAL config_rd_en : std_logic 7850 " 7851 ) 7852 ) 7853 *236 (Net 8262 xt "-103000,65800,-80500,66600" 8263 st "SIGNAL config_rd_en : std_logic" 8264 ) 8265 ) 8266 *248 (Net 7854 8267 uid 5144,0 7855 8268 decl (Decl … … 7864 8277 font "Courier New,8,0" 7865 8278 ) 7866 xt "-103000,74600,-78000,75400" 7867 st "SIGNAL dac_array : dac_array_type 7868 " 7869 ) 7870 ) 7871 *237 (Net 8279 xt "-103000,78600,-78000,79400" 8280 st "SIGNAL dac_array : dac_array_type" 8281 ) 8282 ) 8283 *249 (Net 7872 8284 uid 5194,0 7873 8285 decl (Decl … … 7882 8294 font "Courier New,8,0" 7883 8295 ) 7884 xt "-103000,69000,-80500,69800" 7885 st "SIGNAL config_start_cm : std_logic 7886 " 7887 ) 7888 ) 7889 *238 (Net 8296 xt "-103000,73000,-80500,73800" 8297 st "SIGNAL config_start_cm : std_logic" 8298 ) 8299 ) 8300 *250 (Net 7890 8301 uid 5196,0 7891 8302 decl (Decl … … 7900 8311 font "Courier New,8,0" 7901 8312 ) 7902 xt "-103000,66600,-80500,67400" 7903 st "SIGNAL config_ready_cm : std_logic 7904 " 7905 ) 7906 ) 7907 *239 (Net 8313 xt "-103000,67400,-80500,68200" 8314 st "SIGNAL config_ready_cm : std_logic" 8315 ) 8316 ) 8317 *251 (Net 7908 8318 uid 5220,0 7909 8319 decl (Decl … … 7921 8331 font "Courier New,8,0" 7922 8332 ) 7923 xt "-103000,43800,-57000,44600" 7924 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 7925 " 7926 ) 7927 ) 7928 *240 (Net 7929 uid 5279,0 7930 decl (Decl 7931 n "s_trigger" 7932 t "std_logic" 7933 o 69 7934 suid 134,0 7935 i "'0'" 7936 ) 7937 declText (MLText 7938 uid 5280,0 7939 va (VaSet 7940 font "Courier New,8,0" 7941 ) 7942 xt "-103000,93000,-59500,93800" 7943 st "SIGNAL s_trigger : std_logic := '0' 7944 " 7945 ) 7946 ) 7947 *241 (Net 8333 xt "-103000,44600,-57000,45400" 8334 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 8335 ) 8336 ) 8337 *252 (Net 7948 8338 uid 5472,0 7949 8339 decl (Decl … … 7958 8348 font "Courier New,8,0" 7959 8349 ) 7960 xt "-103000,96200,-80500,97000" 7961 st "SIGNAL sensor_ready : std_logic 7962 " 7963 ) 7964 ) 7965 *242 (Net 8350 xt "-103000,102600,-80500,103400" 8351 st "SIGNAL sensor_ready : std_logic" 8352 ) 8353 ) 8354 *253 (Net 7966 8355 uid 5478,0 7967 8356 decl (Decl … … 7976 8365 font "Courier New,8,0" 7977 8366 ) 7978 xt "-103000,95400,-76500,96200" 7979 st "SIGNAL sensor_array : sensor_array_type 7980 " 7981 ) 7982 ) 7983 *243 (Net 8367 xt "-103000,101800,-76500,102600" 8368 st "SIGNAL sensor_array : sensor_array_type" 8369 ) 8370 ) 8371 *254 (Net 7984 8372 uid 5588,0 7985 8373 decl (Decl … … 7994 8382 font "Courier New,8,0" 7995 8383 ) 7996 xt "-103000,67400,-80500,68200" 7997 st "SIGNAL config_ready_spi : std_logic 7998 " 7999 ) 8000 ) 8001 *244 (Net 8384 xt "-103000,68200,-80500,69000" 8385 st "SIGNAL config_ready_spi : std_logic" 8386 ) 8387 ) 8388 *255 (Net 8002 8389 uid 5632,0 8003 8390 lang 10 … … 8014 8401 font "Courier New,8,0" 8015 8402 ) 8016 xt "-103000,60200,-71000,61000" 8017 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0) 8018 " 8019 ) 8020 ) 8021 *245 (Net 8403 xt "-103000,61000,-71000,61800" 8404 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0)" 8405 ) 8406 ) 8407 *256 (Net 8022 8408 uid 5640,0 8023 8409 decl (Decl … … 8032 8418 font "Courier New,8,0" 8033 8419 ) 8034 xt "-103000,59400,-75500,60200" 8035 st "SIGNAL adc_data_array_int : adc_data_array_type 8036 " 8037 ) 8038 ) 8039 *246 (SaComponent 8420 xt "-103000,60200,-75500,61000" 8421 st "SIGNAL adc_data_array_int : adc_data_array_type" 8422 ) 8423 ) 8424 *257 (SaComponent 8040 8425 uid 5678,0 8041 8426 optionalChildren [ 8042 *2 47(CptPort8427 *258 (CptPort 8043 8428 uid 5658,0 8044 8429 ps "OnEdgeStrategy" … … 8075 8460 ) 8076 8461 ) 8077 *2 48(CptPort8462 *259 (CptPort 8078 8463 uid 5662,0 8079 8464 ps "OnEdgeStrategy" … … 8112 8497 ) 8113 8498 ) 8114 *2 49(CptPort8499 *260 (CptPort 8115 8500 uid 5666,0 8116 8501 ps "OnEdgeStrategy" … … 8151 8536 ) 8152 8537 ) 8153 *2 50(CptPort8538 *261 (CptPort 8154 8539 uid 5670,0 8155 8540 ps "OnEdgeStrategy" … … 8187 8572 ) 8188 8573 ) 8189 *2 51(CptPort8574 *262 (CptPort 8190 8575 uid 5674,0 8191 8576 ps "OnEdgeStrategy" … … 8240 8625 stg "VerticalLayoutStrategy" 8241 8626 textVec [ 8242 *2 52(Text8627 *263 (Text 8243 8628 uid 5681,0 8244 8629 va (VaSet … … 8250 8635 tm "BdLibraryNameMgr" 8251 8636 ) 8252 *2 53(Text8637 *264 (Text 8253 8638 uid 5682,0 8254 8639 va (VaSet … … 8260 8645 tm "CptNameMgr" 8261 8646 ) 8262 *2 54(Text8647 *265 (Text 8263 8648 uid 5683,0 8264 8649 va (VaSet … … 8309 8694 archFileType "UNKNOWN" 8310 8695 ) 8311 *2 55(Net8696 *266 (Net 8312 8697 uid 5743,0 8313 8698 decl (Decl … … 8323 8708 font "Courier New,8,0" 8324 8709 ) 8325 xt "-103000,69800,-59500,70600" 8326 st "SIGNAL config_start_spi : std_logic := '0' 8327 " 8328 ) 8329 ) 8330 *256 (SaComponent 8710 xt "-103000,73800,-59500,74600" 8711 st "SIGNAL config_start_spi : std_logic := '0'" 8712 ) 8713 ) 8714 *267 (SaComponent 8331 8715 uid 5793,0 8332 8716 optionalChildren [ 8333 *2 57(CptPort8717 *268 (CptPort 8334 8718 uid 5753,0 8335 8719 ps "OnEdgeStrategy" … … 8366 8750 ) 8367 8751 ) 8368 *2 58(CptPort8752 *269 (CptPort 8369 8753 uid 5761,0 8370 8754 ps "OnEdgeStrategy" … … 8401 8785 ) 8402 8786 ) 8403 *2 59(CptPort8787 *270 (CptPort 8404 8788 uid 5765,0 8405 8789 ps "OnEdgeStrategy" … … 8437 8821 ) 8438 8822 ) 8439 *2 60(CptPort8823 *271 (CptPort 8440 8824 uid 5769,0 8441 8825 ps "OnEdgeStrategy" … … 8472 8856 ) 8473 8857 ) 8474 *2 61(CptPort8858 *272 (CptPort 8475 8859 uid 5773,0 8476 8860 ps "OnEdgeStrategy" … … 8508 8892 ) 8509 8893 ) 8510 *2 62(CptPort8894 *273 (CptPort 8511 8895 uid 5777,0 8512 8896 ps "OnEdgeStrategy" … … 8544 8928 ) 8545 8929 ) 8546 *2 63(CptPort8930 *274 (CptPort 8547 8931 uid 5781,0 8548 8932 ps "OnEdgeStrategy" … … 8579 8963 ) 8580 8964 ) 8581 *2 64(CptPort8965 *275 (CptPort 8582 8966 uid 5785,0 8583 8967 ps "OnEdgeStrategy" … … 8615 8999 ) 8616 9000 ) 8617 *2 65(CptPort9001 *276 (CptPort 8618 9002 uid 5789,0 8619 9003 ps "OnEdgeStrategy" … … 8651 9035 ) 8652 9036 ) 8653 *2 66(CptPort9037 *277 (CptPort 8654 9038 uid 5986,0 8655 9039 ps "OnEdgeStrategy" … … 8688 9072 ) 8689 9073 ) 8690 *2 67(CptPort9074 *278 (CptPort 8691 9075 uid 6154,0 8692 9076 ps "OnEdgeStrategy" … … 8724 9108 ) 8725 9109 ) 8726 *2 68(CptPort9110 *279 (CptPort 8727 9111 uid 6317,0 8728 9112 ps "OnEdgeStrategy" … … 8778 9162 stg "VerticalLayoutStrategy" 8779 9163 textVec [ 8780 *2 69(Text9164 *280 (Text 8781 9165 uid 5796,0 8782 9166 va (VaSet … … 8788 9172 tm "BdLibraryNameMgr" 8789 9173 ) 8790 *2 70(Text9174 *281 (Text 8791 9175 uid 5797,0 8792 9176 va (VaSet … … 8798 9182 tm "CptNameMgr" 8799 9183 ) 8800 *2 71(Text9184 *282 (Text 8801 9185 uid 5798,0 8802 9186 va (VaSet … … 8844 9228 archFileType "UNKNOWN" 8845 9229 ) 8846 *2 72(Net9230 *283 (Net 8847 9231 uid 5811,0 8848 9232 decl (Decl … … 8857 9241 font "Courier New,8,0" 8858 9242 ) 8859 xt "-103000,47000,-84500,47800" 8860 st "sclk : std_logic 8861 " 8862 ) 8863 ) 8864 *273 (Net 9243 xt "-103000,47800,-84500,48600" 9244 st "sclk : std_logic" 9245 ) 9246 ) 9247 *284 (Net 8865 9248 uid 5819,0 8866 9249 decl (Decl … … 8877 9260 font "Courier New,8,0" 8878 9261 ) 8879 xt "-103000,54200,-84500,55000" 8880 st "sio : std_logic 8881 " 8882 ) 8883 ) 8884 *274 (Net 9262 xt "-103000,55000,-84500,55800" 9263 st "sio : std_logic" 9264 ) 9265 ) 9266 *285 (Net 8885 9267 uid 5827,0 8886 9268 decl (Decl … … 8895 9277 font "Courier New,8,0" 8896 9278 ) 8897 xt "-103000,40600,-84500,41400" 8898 st "dac_cs : std_logic 8899 " 8900 ) 8901 ) 8902 *275 (Net 9279 xt "-103000,41400,-84500,42200" 9280 st "dac_cs : std_logic" 9281 ) 9282 ) 9283 *286 (Net 8903 9284 uid 5835,0 8904 9285 decl (Decl … … 8914 9295 font "Courier New,8,0" 8915 9296 ) 8916 xt "-103000,47800,-74500,48600" 8917 st "sensor_cs : std_logic_vector(3 DOWNTO 0) 8918 " 8919 ) 8920 ) 8921 *276 (PortIoOut 9297 xt "-103000,48600,-74500,49400" 9298 st "sensor_cs : std_logic_vector(3 DOWNTO 0)" 9299 ) 9300 ) 9301 *287 (PortIoOut 8922 9302 uid 5843,0 8923 9303 shape (CompositeShape … … 8964 9344 ) 8965 9345 ) 8966 *2 77(PortIoInOut9346 *288 (PortIoInOut 8967 9347 uid 5849,0 8968 9348 shape (CompositeShape … … 9009 9389 ) 9010 9390 ) 9011 *2 78(PortIoOut9391 *289 (PortIoOut 9012 9392 uid 5855,0 9013 9393 shape (CompositeShape … … 9054 9434 ) 9055 9435 ) 9056 *2 79(PortIoOut9436 *290 (PortIoOut 9057 9437 uid 5861,0 9058 9438 shape (CompositeShape … … 9099 9479 ) 9100 9480 ) 9101 *2 80(Net9481 *291 (Net 9102 9482 uid 5948,0 9103 9483 decl (Decl … … 9113 9493 font "Courier New,8,0" 9114 9494 ) 9115 xt "-103000,83400,-59500,84200" 9116 st "SIGNAL new_config : std_logic := '0' 9117 " 9118 ) 9119 ) 9120 *281 (Net 9495 xt "-103000,88200,-59500,89000" 9496 st "SIGNAL new_config : std_logic := '0'" 9497 ) 9498 ) 9499 *292 (Net 9121 9500 uid 5960,0 9122 9501 decl (Decl … … 9131 9510 font "Courier New,8,0" 9132 9511 ) 9133 xt "-103000,70600,-80500,71400" 9134 st "SIGNAL config_started : std_logic 9135 " 9136 ) 9137 ) 9138 *282 (Net 9512 xt "-103000,74600,-80500,75400" 9513 st "SIGNAL config_started : std_logic" 9514 ) 9515 ) 9516 *293 (Net 9139 9517 uid 6012,0 9140 9518 decl (Decl … … 9150 9528 font "Courier New,8,0" 9151 9529 ) 9152 xt "-103000,73000,-59500,73800" 9153 st "SIGNAL config_started_spi : std_logic := '0' 9154 " 9155 ) 9156 ) 9157 *283 (Net 9530 xt "-103000,77000,-59500,77800" 9531 st "SIGNAL config_started_spi : std_logic := '0'" 9532 ) 9533 ) 9534 *294 (Net 9158 9535 uid 6014,0 9159 9536 decl (Decl … … 9169 9546 font "Courier New,8,0" 9170 9547 ) 9171 xt "-103000,71400,-59500,72200" 9172 st "SIGNAL config_started_cu : std_logic := '0' 9173 " 9174 ) 9175 ) 9176 *284 (Net 9548 xt "-103000,75400,-59500,76200" 9549 st "SIGNAL config_started_cu : std_logic := '0'" 9550 ) 9551 ) 9552 *295 (Net 9177 9553 uid 6016,0 9178 9554 decl (Decl … … 9187 9563 font "Courier New,8,0" 9188 9564 ) 9189 xt "-103000,72200,-80500,73000" 9190 st "SIGNAL config_started_mm : std_logic 9191 " 9192 ) 9193 ) 9194 *285 (Net 9565 xt "-103000,76200,-80500,77000" 9566 st "SIGNAL config_started_mm : std_logic" 9567 ) 9568 ) 9569 *296 (Net 9195 9570 uid 6158,0 9196 9571 decl (Decl … … 9206 9581 font "Courier New,8,0" 9207 9582 ) 9208 xt "-103000,44600,-63000,45400" 9209 st "mosi : std_logic := '0' 9210 " 9211 ) 9212 ) 9213 *286 (PortIoOut 9583 xt "-103000,45400,-63000,46200" 9584 st "mosi : std_logic := '0'" 9585 ) 9586 ) 9587 *297 (PortIoOut 9214 9588 uid 6166,0 9215 9589 shape (CompositeShape … … 9256 9630 ) 9257 9631 ) 9258 *2 87(Net9632 *298 (Net 9259 9633 uid 6360,0 9260 9634 decl (Decl … … 9272 9646 font "Courier New,8,0" 9273 9647 ) 9274 xt "-103000,41400,-49500,42200" 9275 st "denable : std_logic := '0' -- default domino wave off 9276 " 9277 ) 9278 ) 9279 *288 (PortIoOut 9648 xt "-103000,42200,-49500,43000" 9649 st "denable : std_logic := '0' -- default domino wave off" 9650 ) 9651 ) 9652 *299 (PortIoOut 9280 9653 uid 6368,0 9281 9654 shape (CompositeShape … … 9290 9663 sl 0 9291 9664 ro 270 9292 xt "15 3500,74625,155000,75375"9665 xt "154500,74625,156000,75375" 9293 9666 ) 9294 9667 (Line … … 9296 9669 sl 0 9297 9670 ro 270 9298 xt "15 3000,75000,153500,75000"9299 pts [ 9300 "15 3000,75000"9301 "15 3500,75000"9671 xt "154000,75000,154500,75000" 9672 pts [ 9673 "154000,75000" 9674 "154500,75000" 9302 9675 ] 9303 9676 ) … … 9314 9687 va (VaSet 9315 9688 ) 9316 xt "15 6000,74500,159000,75500"9689 xt "157000,74500,160000,75500" 9317 9690 st "denable" 9318 blo "15 6000,75300"9691 blo "157000,75300" 9319 9692 tm "WireNameMgr" 9320 9693 ) 9321 9694 ) 9322 9695 ) 9323 * 289(Net9696 *300 (Net 9324 9697 uid 6450,0 9325 9698 decl (Decl … … 9335 9708 font "Courier New,8,0" 9336 9709 ) 9337 xt "-103000,82600,-59500,83400" 9338 st "SIGNAL dwrite_enable : std_logic := '1' 9339 " 9340 ) 9341 ) 9342 *290 (MWC 9710 xt "-103000,87400,-59500,88200" 9711 st "SIGNAL dwrite_enable : std_logic := '1'" 9712 ) 9713 ) 9714 *301 (MWC 9343 9715 uid 6529,0 9344 9716 optionalChildren [ 9345 * 291(CptPort9717 *302 (CptPort 9346 9718 uid 6501,0 9347 9719 optionalChildren [ 9348 * 292(Line9720 *303 (Line 9349 9721 uid 6505,0 9350 9722 layer 5 … … 9359 9731 ] 9360 9732 ) 9361 * 293(Property9733 *304 (Property 9362 9734 uid 6506,0 9363 9735 pclass "_MW_GEOM_" … … 9404 9776 ) 9405 9777 ) 9406 * 294(CptPort9778 *305 (CptPort 9407 9779 uid 6507,0 9408 9780 optionalChildren [ 9409 * 295(Line9781 *306 (Line 9410 9782 uid 6511,0 9411 9783 layer 5 … … 9459 9831 ) 9460 9832 ) 9461 * 296(CptPort9833 *307 (CptPort 9462 9834 uid 6512,0 9463 9835 optionalChildren [ 9464 * 297(Line9836 *308 (Line 9465 9837 uid 6516,0 9466 9838 layer 5 … … 9514 9886 ) 9515 9887 ) 9516 * 298(CommentGraphic9888 *309 (CommentGraphic 9517 9889 uid 6517,0 9518 9890 optionalChildren [ 9519 * 299(Property9891 *310 (Property 9520 9892 uid 6519,0 9521 9893 pclass "_MW_GEOM_" … … 9541 9913 oxt "11000,10000,11000,10000" 9542 9914 ) 9543 *3 00(CommentGraphic9915 *311 (CommentGraphic 9544 9916 uid 6520,0 9545 9917 optionalChildren [ 9546 *3 01(Property9918 *312 (Property 9547 9919 uid 6522,0 9548 9920 pclass "_MW_GEOM_" … … 9568 9940 oxt "11000,6000,11000,6000" 9569 9941 ) 9570 *3 02(Grouping9942 *313 (Grouping 9571 9943 uid 6523,0 9572 9944 optionalChildren [ 9573 *3 03(CommentGraphic9945 *314 (CommentGraphic 9574 9946 uid 6525,0 9575 9947 shape (PolyLine2D … … 9592 9964 oxt "9000,6000,11000,10000" 9593 9965 ) 9594 *3 04(CommentGraphic9966 *315 (CommentGraphic 9595 9967 uid 6527,0 9596 9968 shape (Arc2D … … 9645 10017 stg "VerticalLayoutStrategy" 9646 10018 textVec [ 9647 *3 05(Text10019 *316 (Text 9648 10020 uid 6532,0 9649 10021 va (VaSet … … 9655 10027 blo "3500,59300" 9656 10028 ) 9657 *3 06(Text10029 *317 (Text 9658 10030 uid 6533,0 9659 10031 va (VaSet … … 9664 10036 blo "3500,60300" 9665 10037 ) 9666 *3 07(Text10038 *318 (Text 9667 10039 uid 6534,0 9668 10040 va (VaSet … … 9709 10081 ) 9710 10082 ) 9711 *3 08(Net10083 *319 (Net 9712 10084 uid 6544,0 9713 10085 decl (Decl … … 9723 10095 font "Courier New,8,0" 9724 10096 ) 9725 xt "-103000,81800,-59500,82600" 9726 st "SIGNAL dwrite : std_logic := '1' 9727 " 9728 ) 9729 ) 9730 *309 (SaComponent 10097 xt "-103000,86600,-59500,87400" 10098 st "SIGNAL dwrite : std_logic := '1'" 10099 ) 10100 ) 10101 *320 (SaComponent 9731 10102 uid 8277,0 9732 10103 optionalChildren [ 9733 *3 10(CptPort10104 *321 (CptPort 9734 10105 uid 8246,0 9735 10106 ps "OnEdgeStrategy" … … 9768 10139 ) 9769 10140 ) 9770 *3 11(CptPort10141 *322 (CptPort 9771 10142 uid 8250,0 9772 10143 ps "OnEdgeStrategy" … … 9806 10177 ) 9807 10178 ) 9808 *3 12(CptPort10179 *323 (CptPort 9809 10180 uid 8254,0 9810 10181 ps "OnEdgeStrategy" … … 9844 10215 ) 9845 10216 ) 9846 *3 13(CptPort10217 *324 (CptPort 9847 10218 uid 8258,0 9848 10219 ps "OnEdgeStrategy" … … 9882 10253 ) 9883 10254 ) 9884 *3 14(CptPort10255 *325 (CptPort 9885 10256 uid 8262,0 9886 10257 ps "OnEdgeStrategy" … … 9920 10291 ) 9921 10292 ) 9922 *3 15(CptPort10293 *326 (CptPort 9923 10294 uid 8266,0 9924 10295 ps "OnEdgeStrategy" … … 9959 10330 ) 9960 10331 ) 9961 *3 16(CptPort10332 *327 (CptPort 9962 10333 uid 8270,0 9963 10334 ps "OnEdgeStrategy" … … 10016 10387 stg "VerticalLayoutStrategy" 10017 10388 textVec [ 10018 *3 17(Text10389 *328 (Text 10019 10390 uid 8280,0 10020 10391 va (VaSet … … 10026 10397 tm "BdLibraryNameMgr" 10027 10398 ) 10028 *3 18(Text10399 *329 (Text 10029 10400 uid 8281,0 10030 10401 va (VaSet … … 10036 10407 tm "CptNameMgr" 10037 10408 ) 10038 *3 19(Text10409 *330 (Text 10039 10410 uid 8282,0 10040 10411 va (VaSet … … 10084 10455 archFileType "UNKNOWN" 10085 10456 ) 10086 *3 20(Net10457 *331 (Net 10087 10458 uid 8414,0 10088 10459 lang 2 … … 10098 10469 font "Courier New,8,0" 10099 10470 ) 10100 xt "-103000,98600,-80500,99400" 10101 st "SIGNAL wiz_ack : std_logic 10102 " 10103 ) 10104 ) 10105 *321 (Net 10471 xt "-103000,108200,-80500,109000" 10472 st "SIGNAL wiz_ack : std_logic" 10473 ) 10474 ) 10475 *332 (Net 10106 10476 uid 8508,0 10107 10477 decl (Decl … … 10118 10488 font "Courier New,8,0" 10119 10489 ) 10120 xt "-103000,76200,-53500,77000" 10121 st "SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0') 10122 " 10123 ) 10124 ) 10125 *322 (Net 10490 xt "-103000,80200,-53500,81000" 10491 st "SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0')" 10492 ) 10493 ) 10494 *333 (Net 10126 10495 uid 8516,0 10127 10496 decl (Decl … … 10136 10505 font "Courier New,8,0" 10137 10506 ) 10138 xt "-103000,77000,-80500,77800" 10139 st "SIGNAL drs_address_mode : std_logic 10140 " 10141 ) 10142 ) 10143 *323 (MWC 10507 xt "-103000,81000,-80500,81800" 10508 st "SIGNAL drs_address_mode : std_logic" 10509 ) 10510 ) 10511 *334 (MWC 10144 10512 uid 8562,0 10145 10513 optionalChildren [ 10146 *3 24(CptPort10514 *335 (CptPort 10147 10515 uid 8524,0 10148 10516 optionalChildren [ 10149 *3 25(Line10517 *336 (Line 10150 10518 uid 8528,0 10151 10519 layer 5 … … 10211 10579 ) 10212 10580 ) 10213 *3 26(CptPort10581 *337 (CptPort 10214 10582 uid 8529,0 10215 10583 optionalChildren [ 10216 *3 27(Line10584 *338 (Line 10217 10585 uid 8533,0 10218 10586 layer 5 … … 10228 10596 ] 10229 10597 ) 10230 *3 28(Property10598 *339 (Property 10231 10599 uid 8534,0 10232 10600 pclass "_MW_GEOM_" … … 10283 10651 ) 10284 10652 ) 10285 *3 29(CptPort10653 *340 (CptPort 10286 10654 uid 8535,0 10287 10655 optionalChildren [ 10288 *3 30(Line10656 *341 (Line 10289 10657 uid 8539,0 10290 10658 layer 5 … … 10350 10718 ) 10351 10719 ) 10352 *3 31(CptPort10720 *342 (CptPort 10353 10721 uid 8540,0 10354 10722 optionalChildren [ 10355 *3 32(Line10723 *343 (Line 10356 10724 uid 8544,0 10357 10725 layer 5 … … 10413 10781 ) 10414 10782 ) 10415 *3 33(CommentGraphic10783 *344 (CommentGraphic 10416 10784 uid 8545,0 10417 10785 shape (CustomPolygon … … 10436 10804 oxt "7000,7000,9000,11000" 10437 10805 ) 10438 *3 34(CommentGraphic10806 *345 (CommentGraphic 10439 10807 uid 8547,0 10440 10808 optionalChildren [ 10441 *3 35(Property10809 *346 (Property 10442 10810 uid 8549,0 10443 10811 pclass "_MW_GEOM_" … … 10463 10831 oxt "9000,7000,9000,7000" 10464 10832 ) 10465 *3 36(CommentGraphic10833 *347 (CommentGraphic 10466 10834 uid 8550,0 10467 10835 optionalChildren [ 10468 *3 37(Property10836 *348 (Property 10469 10837 uid 8552,0 10470 10838 pclass "_MW_GEOM_" … … 10490 10858 oxt "9000,11000,9000,11000" 10491 10859 ) 10492 *3 38(CommentText10860 *349 (CommentText 10493 10861 uid 8553,0 10494 10862 shape (Rectangle … … 10521 10889 ) 10522 10890 ) 10523 *3 39(CommentText10891 *350 (CommentText 10524 10892 uid 8556,0 10525 10893 shape (Rectangle … … 10553 10921 ) 10554 10922 ) 10555 *3 40(CommentText10923 *351 (CommentText 10556 10924 uid 8559,0 10557 10925 shape (Rectangle … … 10604 10972 stg "VerticalLayoutStrategy" 10605 10973 textVec [ 10606 *3 41(Text10974 *352 (Text 10607 10975 uid 8565,0 10608 10976 va (VaSet … … 10614 10982 blo "-30650,102900" 10615 10983 ) 10616 *3 42(Text10984 *353 (Text 10617 10985 uid 8566,0 10618 10986 va (VaSet … … 10623 10991 blo "-30650,103900" 10624 10992 ) 10625 *3 43(Text10993 *354 (Text 10626 10994 uid 8567,0 10627 10995 va (VaSet … … 10669 11037 ) 10670 11038 ) 10671 *3 44(Net11039 *355 (Net 10672 11040 uid 8583,0 10673 11041 decl (Decl … … 10684 11052 font "Courier New,8,0" 10685 11053 ) 10686 xt "-103000,77800,-53500,78600" 10687 st "SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0') 10688 " 10689 ) 10690 ) 10691 *345 (MWC 11054 xt "-103000,81800,-53500,82600" 11055 st "SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0')" 11056 ) 11057 ) 11058 *356 (MWC 10692 11059 uid 8721,0 10693 11060 optionalChildren [ 10694 *3 46(CptPort11061 *357 (CptPort 10695 11062 uid 8693,0 10696 11063 optionalChildren [ 10697 *3 47(Line11064 *358 (Line 10698 11065 uid 8697,0 10699 11066 layer 5 … … 10708 11075 ] 10709 11076 ) 10710 *3 48(Property11077 *359 (Property 10711 11078 uid 8698,0 10712 11079 pclass "_MW_GEOM_" … … 10752 11119 ) 10753 11120 ) 10754 *3 49(CptPort11121 *360 (CptPort 10755 11122 uid 8699,0 10756 11123 optionalChildren [ 10757 *3 50(Line11124 *361 (Line 10758 11125 uid 8703,0 10759 11126 layer 5 … … 10806 11173 ) 10807 11174 ) 10808 *3 51(CptPort11175 *362 (CptPort 10809 11176 uid 8704,0 10810 11177 optionalChildren [ 10811 *3 52(Line11178 *363 (Line 10812 11179 uid 8708,0 10813 11180 layer 5 … … 10860 11227 ) 10861 11228 ) 10862 *3 53(CommentGraphic11229 *364 (CommentGraphic 10863 11230 uid 8709,0 10864 11231 optionalChildren [ 10865 *3 54(Property11232 *365 (Property 10866 11233 uid 8711,0 10867 11234 pclass "_MW_GEOM_" … … 10887 11254 oxt "11000,6000,11000,6000" 10888 11255 ) 10889 *3 55(CommentGraphic11256 *366 (CommentGraphic 10890 11257 uid 8712,0 10891 11258 optionalChildren [ 10892 *3 56(Property11259 *367 (Property 10893 11260 uid 8714,0 10894 11261 pclass "_MW_GEOM_" … … 10914 11281 oxt "11000,10000,11000,10000" 10915 11282 ) 10916 *3 57(Grouping11283 *368 (Grouping 10917 11284 uid 8715,0 10918 11285 optionalChildren [ 10919 *3 58(CommentGraphic11286 *369 (CommentGraphic 10920 11287 uid 8717,0 10921 11288 shape (PolyLine2D … … 10938 11305 oxt "9000,6000,11000,10000" 10939 11306 ) 10940 *3 59(CommentGraphic11307 *370 (CommentGraphic 10941 11308 uid 8719,0 10942 11309 shape (Arc2D … … 10991 11358 stg "VerticalLayoutStrategy" 10992 11359 textVec [ 10993 *3 60(Text11360 *371 (Text 10994 11361 uid 8724,0 10995 11362 va (VaSet … … 11001 11368 blo "-11500,113300" 11002 11369 ) 11003 *3 61(Text11370 *372 (Text 11004 11371 uid 8725,0 11005 11372 va (VaSet … … 11010 11377 blo "-11500,114300" 11011 11378 ) 11012 *3 62(Text11379 *373 (Text 11013 11380 uid 8726,0 11014 11381 va (VaSet … … 11055 11422 ) 11056 11423 ) 11057 *3 63(Net11424 *374 (Net 11058 11425 uid 8730,0 11059 11426 decl (Decl … … 11068 11435 font "Courier New,8,0" 11069 11436 ) 11070 xt "-103000,93800,-80500,94600" 11071 st "SIGNAL sclk1 : std_logic 11072 " 11073 ) 11074 ) 11075 *364 (Net 11437 xt "-103000,100200,-80500,101000" 11438 st "SIGNAL sclk1 : std_logic" 11439 ) 11440 ) 11441 *375 (Net 11076 11442 uid 8746,0 11077 11443 decl (Decl … … 11086 11452 font "Courier New,8,0" 11087 11453 ) 11088 xt "-103000,94600,-80500,95400" 11089 st "SIGNAL sclk_enable : std_logic 11090 " 11091 ) 11092 ) 11093 *365 (Net 11454 xt "-103000,101000,-80500,101800" 11455 st "SIGNAL sclk_enable : std_logic" 11456 ) 11457 ) 11458 *376 (Net 11094 11459 uid 9004,0 11095 11460 decl (Decl … … 11105 11470 font "Courier New,8,0" 11106 11471 ) 11107 xt "-103000,39000,-63000,39800" 11108 st "adc_clk_en : std_logic := '0' 11109 " 11110 ) 11111 ) 11112 *366 (PortIoOut 11472 xt "-103000,39800,-63000,40600" 11473 st "adc_clk_en : std_logic := '0'" 11474 ) 11475 ) 11476 *377 (PortIoOut 11113 11477 uid 9012,0 11114 11478 shape (CompositeShape … … 11155 11519 ) 11156 11520 ) 11157 *3 67(SaComponent11521 *378 (SaComponent 11158 11522 uid 9175,0 11159 11523 optionalChildren [ 11160 *3 68(CptPort11524 *379 (CptPort 11161 11525 uid 9120,0 11162 11526 ps "OnEdgeStrategy" … … 11195 11559 ) 11196 11560 ) 11197 *3 69(CptPort11561 *380 (CptPort 11198 11562 uid 9124,0 11199 11563 ps "OnEdgeStrategy" … … 11232 11596 ) 11233 11597 ) 11234 *3 70(CptPort11598 *381 (CptPort 11235 11599 uid 9128,0 11236 11600 ps "OnEdgeStrategy" … … 11267 11631 ) 11268 11632 ) 11269 *3 71(CptPort11633 *382 (CptPort 11270 11634 uid 9132,0 11271 11635 ps "OnEdgeStrategy" … … 11317 11681 ) 11318 11682 ) 11319 *3 72(CptPort11683 *383 (CptPort 11320 11684 uid 9137,0 11321 11685 ps "OnEdgeStrategy" … … 11368 11732 ) 11369 11733 ) 11370 *3 73(CptPort11734 *384 (CptPort 11371 11735 uid 9142,0 11372 11736 ps "OnEdgeStrategy" … … 11419 11783 ) 11420 11784 ) 11421 *3 74(CptPort11785 *385 (CptPort 11422 11786 uid 9147,0 11423 11787 ps "OnEdgeStrategy" … … 11458 11822 ) 11459 11823 ) 11460 *3 75(CptPort11824 *386 (CptPort 11461 11825 uid 9155,0 11462 11826 ps "OnEdgeStrategy" … … 11495 11859 ) 11496 11860 ) 11497 *3 76(CptPort11861 *387 (CptPort 11498 11862 uid 9159,0 11499 11863 ps "OnEdgeStrategy" … … 11532 11896 ) 11533 11897 ) 11534 *3 77(CptPort11898 *388 (CptPort 11535 11899 uid 9163,0 11536 11900 ps "OnEdgeStrategy" … … 11569 11933 ) 11570 11934 ) 11571 *3 78(CptPort11935 *389 (CptPort 11572 11936 uid 9167,0 11573 11937 ps "OnEdgeStrategy" … … 11606 11970 ) 11607 11971 ) 11608 *3 79(CptPort11972 *390 (CptPort 11609 11973 uid 9171,0 11610 11974 ps "OnEdgeStrategy" … … 11643 12007 ) 11644 12008 ) 11645 *3 80(CptPort12009 *391 (CptPort 11646 12010 uid 9211,0 11647 12011 ps "OnEdgeStrategy" … … 11680 12044 ) 11681 12045 ) 11682 *3 81(CptPort12046 *392 (CptPort 11683 12047 uid 9215,0 11684 12048 ps "OnEdgeStrategy" … … 11715 12079 ) 11716 12080 ) 11717 *3 82(CptPort12081 *393 (CptPort 11718 12082 uid 9219,0 11719 12083 ps "OnEdgeStrategy" … … 11750 12114 ) 11751 12115 ) 11752 *3 83(CptPort12116 *394 (CptPort 11753 12117 uid 10030,0 11754 12118 ps "OnEdgeStrategy" … … 11802 12166 stg "VerticalLayoutStrategy" 11803 12167 textVec [ 11804 *3 84(Text12168 *395 (Text 11805 12169 uid 9178,0 11806 12170 va (VaSet … … 11812 12176 tm "BdLibraryNameMgr" 11813 12177 ) 11814 *3 85(Text12178 *396 (Text 11815 12179 uid 9179,0 11816 12180 va (VaSet … … 11822 12186 tm "CptNameMgr" 11823 12187 ) 11824 *3 86(Text12188 *397 (Text 11825 12189 uid 9180,0 11826 12190 va (VaSet … … 11869 12233 archFileType "UNKNOWN" 11870 12234 ) 11871 *3 87(Net12235 *398 (Net 11872 12236 uid 9231,0 11873 12237 decl (Decl … … 11885 12249 font "Courier New,8,0" 11886 12250 ) 11887 xt "-103000,85000,-44000,85800" 11888 st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards 11889 " 11890 ) 11891 ) 11892 *388 (Net 12251 xt "-103000,89800,-44000,90600" 12252 st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards" 12253 ) 12254 ) 12255 *399 (Net 11893 12256 uid 9239,0 11894 12257 decl (Decl … … 11907 12270 font "Courier New,8,0" 11908 12271 ) 11909 xt "-103000,85800,-43000,86600" 11910 st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once 11911 " 11912 ) 11913 ) 11914 *389 (Net 12272 xt "-103000,90600,-43000,91400" 12273 st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once" 12274 ) 12275 ) 12276 *400 (Net 11915 12277 uid 9267,0 11916 12278 decl (Decl … … 11926 12288 ) 11927 12289 xt "-103000,31800,-84500,32600" 11928 st "LOCKED_extraOUT : std_logic 11929 " 11930 ) 11931 ) 11932 *390 (PortIoOut 12290 st "LOCKED_extraOUT : std_logic" 12291 ) 12292 ) 12293 *401 (PortIoOut 11933 12294 uid 9275,0 11934 12295 shape (CompositeShape … … 11974 12335 ) 11975 12336 ) 11976 * 391(Net12337 *402 (Net 11977 12338 uid 9281,0 11978 12339 decl (Decl … … 11988 12349 ) 11989 12350 xt "-103000,33400,-84500,34200" 11990 st "PSDONE_extraOUT : std_logic 11991 " 11992 ) 11993 ) 11994 *392 (PortIoOut 12351 st "PSDONE_extraOUT : std_logic" 12352 ) 12353 ) 12354 *403 (PortIoOut 11995 12355 uid 9289,0 11996 12356 shape (CompositeShape … … 12036 12396 ) 12037 12397 ) 12038 * 393(Net12398 *404 (Net 12039 12399 uid 9295,0 12040 12400 decl (Decl … … 12050 12410 ) 12051 12411 xt "-103000,35000,-84500,35800" 12052 st "PSINCDEC_OUT : std_logic 12053 " 12054 ) 12055 ) 12056 *394 (PortIoOut 12412 st "PSINCDEC_OUT : std_logic" 12413 ) 12414 ) 12415 *405 (PortIoOut 12057 12416 uid 9303,0 12058 12417 shape (CompositeShape … … 12098 12457 ) 12099 12458 ) 12100 * 395(Net12459 *406 (Net 12101 12460 uid 9309,0 12102 12461 decl (Decl … … 12112 12471 ) 12113 12472 xt "-103000,34200,-84500,35000" 12114 st "PSEN_OUT : std_logic 12115 " 12116 ) 12117 ) 12118 *396 (PortIoOut 12473 st "PSEN_OUT : std_logic" 12474 ) 12475 ) 12476 *407 (PortIoOut 12119 12477 uid 9317,0 12120 12478 shape (CompositeShape … … 12160 12518 ) 12161 12519 ) 12162 * 397(Net12520 *408 (Net 12163 12521 uid 9323,0 12164 12522 decl (Decl … … 12174 12532 ) 12175 12533 xt "-103000,32600,-84500,33400" 12176 st "PSCLK_OUT : std_logic 12177 " 12178 ) 12179 ) 12180 *398 (PortIoOut 12534 st "PSCLK_OUT : std_logic" 12535 ) 12536 ) 12537 *409 (PortIoOut 12181 12538 uid 9331,0 12182 12539 shape (CompositeShape … … 12222 12579 ) 12223 12580 ) 12224 * 399(Net12581 *410 (Net 12225 12582 uid 9351,0 12226 12583 decl (Decl … … 12238 12595 ) 12239 12596 xt "-103000,31000,-84500,31800" 12240 st "DCM_locked : std_logic 12241 " 12242 ) 12243 ) 12244 *400 (PortIoOut 12597 st "DCM_locked : std_logic" 12598 ) 12599 ) 12600 *411 (PortIoOut 12245 12601 uid 9359,0 12246 12602 shape (CompositeShape … … 12286 12642 ) 12287 12643 ) 12288 *4 01(Net12644 *412 (Net 12289 12645 uid 9365,0 12290 12646 decl (Decl … … 12303 12659 font "Courier New,8,0" 12304 12660 ) 12305 xt "-103000,45400,-57000,46200" 12306 st "offset : std_logic_vector(7 downto 0) := (OTHERS => '0') 12307 " 12308 ) 12309 ) 12310 *402 (PortIoOut 12661 xt "-103000,46200,-57000,47000" 12662 st "offset : std_logic_vector(7 downto 0) := (OTHERS => '0')" 12663 ) 12664 ) 12665 *413 (PortIoOut 12311 12666 uid 9374,0 12312 12667 shape (CompositeShape … … 12352 12707 ) 12353 12708 ) 12354 *4 03(Net12709 *414 (Net 12355 12710 uid 9380,0 12356 12711 decl (Decl … … 12369 12724 font "Courier New,8,0" 12370 12725 ) 12371 xt "-103000,4 8600,-63000,50200"12726 xt "-103000,49400,-63000,51000" 12372 12727 st "-- status: 12373 shifting : std_logic := '0' 12374 " 12375 ) 12376 ) 12377 *404 (PortIoOut 12728 shifting : std_logic := '0'" 12729 ) 12730 ) 12731 *415 (PortIoOut 12378 12732 uid 9389,0 12379 12733 shape (CompositeShape … … 12419 12773 ) 12420 12774 ) 12421 *4 05(Net12775 *416 (Net 12422 12776 uid 9395,0 12423 12777 decl (Decl … … 12435 12789 font "Courier New,8,0" 12436 12790 ) 12437 xt "-103000,46200,-63000,47000" 12438 st "ready : std_logic := '0' 12439 " 12440 ) 12441 ) 12442 *406 (PortIoOut 12791 xt "-103000,47000,-63000,47800" 12792 st "ready : std_logic := '0'" 12793 ) 12794 ) 12795 *417 (PortIoOut 12443 12796 uid 9404,0 12444 12797 shape (CompositeShape … … 12484 12837 ) 12485 12838 ) 12486 *4 07(MWC12839 *418 (MWC 12487 12840 uid 9430,0 12488 12841 optionalChildren [ 12489 *4 08(CptPort12842 *419 (CptPort 12490 12843 uid 9410,0 12491 12844 optionalChildren [ 12492 *4 09(Line12845 *420 (Line 12493 12846 uid 9414,0 12494 12847 layer 5 … … 12553 12906 ) 12554 12907 ) 12555 *4 10(CptPort12908 *421 (CptPort 12556 12909 uid 9415,0 12557 12910 optionalChildren [ 12558 *4 11(Line12911 *422 (Line 12559 12912 uid 9419,0 12560 12913 layer 5 … … 12618 12971 ) 12619 12972 ) 12620 *4 12(CommentGraphic12973 *423 (CommentGraphic 12621 12974 uid 9420,0 12622 12975 shape (PolyLine2D … … 12639 12992 oxt "6000,6000,7000,7000" 12640 12993 ) 12641 *4 13(CommentGraphic12994 *424 (CommentGraphic 12642 12995 uid 9422,0 12643 12996 shape (PolyLine2D … … 12660 13013 oxt "6000,7000,7000,8000" 12661 13014 ) 12662 *4 14(CommentGraphic13015 *425 (CommentGraphic 12663 13016 uid 9424,0 12664 13017 shape (PolyLine2D … … 12681 13034 oxt "6988,7329,7988,7329" 12682 13035 ) 12683 *4 15(CommentGraphic13036 *426 (CommentGraphic 12684 13037 uid 9426,0 12685 13038 shape (PolyLine2D … … 12700 13053 oxt "8000,7000,9000,7000" 12701 13054 ) 12702 *4 16(CommentGraphic13055 *427 (CommentGraphic 12703 13056 uid 9428,0 12704 13057 shape (PolyLine2D … … 12741 13094 stg "VerticalLayoutStrategy" 12742 13095 textVec [ 12743 *4 17(Text13096 *428 (Text 12744 13097 uid 9433,0 12745 13098 va (VaSet … … 12751 13104 blo "-2650,-11100" 12752 13105 ) 12753 *4 18(Text13106 *429 (Text 12754 13107 uid 9434,0 12755 13108 va (VaSet … … 12760 13113 blo "-2650,-10100" 12761 13114 ) 12762 *4 19(Text13115 *430 (Text 12763 13116 uid 9435,0 12764 13117 va (VaSet … … 12805 13158 ) 12806 13159 ) 12807 *4 20(MWC13160 *431 (MWC 12808 13161 uid 9472,0 12809 13162 optionalChildren [ 12810 *4 21(CptPort13163 *432 (CptPort 12811 13164 uid 9481,0 12812 13165 optionalChildren [ 12813 *4 22(Line13166 *433 (Line 12814 13167 uid 9486,0 12815 13168 layer 5 … … 12872 13225 ) 12873 13226 ) 12874 *4 23(CptPort13227 *434 (CptPort 12875 13228 uid 9487,0 12876 13229 optionalChildren [ 12877 *4 24(Line13230 *435 (Line 12878 13231 uid 9492,0 12879 13232 layer 5 … … 12936 13289 ) 12937 13290 ) 12938 *4 25(CommentGraphic13291 *436 (CommentGraphic 12939 13292 uid 9493,0 12940 13293 shape (PolyLine2D … … 12957 13310 oxt "6000,6000,7000,7000" 12958 13311 ) 12959 *4 26(CommentGraphic13312 *437 (CommentGraphic 12960 13313 uid 9495,0 12961 13314 shape (PolyLine2D … … 12978 13331 oxt "6000,7000,7000,8000" 12979 13332 ) 12980 *4 27(CommentGraphic13333 *438 (CommentGraphic 12981 13334 uid 9497,0 12982 13335 shape (PolyLine2D … … 12999 13352 oxt "6988,7329,7988,7329" 13000 13353 ) 13001 *4 28(CommentGraphic13354 *439 (CommentGraphic 13002 13355 uid 9499,0 13003 13356 shape (PolyLine2D … … 13018 13371 oxt "8000,7000,9000,7000" 13019 13372 ) 13020 *4 29(CommentGraphic13373 *440 (CommentGraphic 13021 13374 uid 9501,0 13022 13375 shape (PolyLine2D … … 13059 13412 stg "VerticalLayoutStrategy" 13060 13413 textVec [ 13061 *4 30(Text13414 *441 (Text 13062 13415 uid 9475,0 13063 13416 va (VaSet … … 13069 13422 blo "-2650,-7100" 13070 13423 ) 13071 *4 31(Text13424 *442 (Text 13072 13425 uid 9476,0 13073 13426 va (VaSet … … 13078 13431 blo "-2650,-6100" 13079 13432 ) 13080 *4 32(Text13433 *443 (Text 13081 13434 uid 9477,0 13082 13435 va (VaSet … … 13123 13476 ) 13124 13477 ) 13125 *4 33(PortIoOut13478 *444 (PortIoOut 13126 13479 uid 9523,0 13127 13480 shape (CompositeShape … … 13167 13520 ) 13168 13521 ) 13169 *4 34(PortIoOut13522 *445 (PortIoOut 13170 13523 uid 9545,0 13171 13524 shape (CompositeShape … … 13211 13564 ) 13212 13565 ) 13213 *4 35(Net13566 *446 (Net 13214 13567 uid 9551,0 13215 13568 decl (Decl … … 13225 13578 ) 13226 13579 xt "-103000,35800,-84500,36600" 13227 st "PS_DIR_IN : std_logic 13228 " 13229 ) 13230 ) 13231 *436 (Net 13580 st "PS_DIR_IN : std_logic" 13581 ) 13582 ) 13583 *447 (Net 13232 13584 uid 9553,0 13233 13585 decl (Decl … … 13243 13595 ) 13244 13596 xt "-103000,36600,-84500,37400" 13245 st "PS_DO_IN : std_logic 13246 " 13247 ) 13248 ) 13249 *437 (MWC 13597 st "PS_DO_IN : std_logic" 13598 ) 13599 ) 13600 *448 (MWC 13250 13601 uid 9662,0 13251 13602 optionalChildren [ 13252 *4 38(CptPort13603 *449 (CptPort 13253 13604 uid 9642,0 13254 13605 optionalChildren [ 13255 *4 39(Line13606 *450 (Line 13256 13607 uid 9646,0 13257 13608 layer 5 … … 13312 13663 ) 13313 13664 ) 13314 *4 40(CptPort13665 *451 (CptPort 13315 13666 uid 9647,0 13316 13667 optionalChildren [ 13317 *4 41(Line13668 *452 (Line 13318 13669 uid 9651,0 13319 13670 layer 5 … … 13377 13728 ) 13378 13729 ) 13379 *4 42(CommentGraphic13730 *453 (CommentGraphic 13380 13731 uid 9652,0 13381 13732 shape (PolyLine2D … … 13398 13749 oxt "6000,6000,7000,7000" 13399 13750 ) 13400 *4 43(CommentGraphic13751 *454 (CommentGraphic 13401 13752 uid 9654,0 13402 13753 shape (PolyLine2D … … 13419 13770 oxt "6000,7000,7000,8000" 13420 13771 ) 13421 *4 44(CommentGraphic13772 *455 (CommentGraphic 13422 13773 uid 9656,0 13423 13774 shape (PolyLine2D … … 13440 13791 oxt "6988,7329,7988,7329" 13441 13792 ) 13442 *4 45(CommentGraphic13793 *456 (CommentGraphic 13443 13794 uid 9658,0 13444 13795 shape (PolyLine2D … … 13459 13810 oxt "8000,7000,9000,7000" 13460 13811 ) 13461 *4 46(CommentGraphic13812 *457 (CommentGraphic 13462 13813 uid 9660,0 13463 13814 shape (PolyLine2D … … 13500 13851 stg "VerticalLayoutStrategy" 13501 13852 textVec [ 13502 *4 47(Text13853 *458 (Text 13503 13854 uid 9665,0 13504 13855 va (VaSet … … 13510 13861 blo "28350,900" 13511 13862 ) 13512 *4 48(Text13863 *459 (Text 13513 13864 uid 9666,0 13514 13865 va (VaSet … … 13519 13870 blo "28350,1900" 13520 13871 ) 13521 *4 49(Text13872 *460 (Text 13522 13873 uid 9667,0 13523 13874 va (VaSet … … 13564 13915 ) 13565 13916 ) 13566 *4 50(MWC13917 *461 (MWC 13567 13918 uid 9679,0 13568 13919 optionalChildren [ 13569 *4 51(CptPort13920 *462 (CptPort 13570 13921 uid 9688,0 13571 13922 optionalChildren [ 13572 *4 52(Line13923 *463 (Line 13573 13924 uid 9693,0 13574 13925 layer 5 … … 13628 13979 ) 13629 13980 ) 13630 *4 53(CptPort13981 *464 (CptPort 13631 13982 uid 9694,0 13632 13983 optionalChildren [ 13633 *4 54(Line13984 *465 (Line 13634 13985 uid 9699,0 13635 13986 layer 5 … … 13692 14043 ) 13693 14044 ) 13694 *4 55(CommentGraphic14045 *466 (CommentGraphic 13695 14046 uid 9700,0 13696 14047 shape (PolyLine2D … … 13713 14064 oxt "6000,6000,7000,7000" 13714 14065 ) 13715 *4 56(CommentGraphic14066 *467 (CommentGraphic 13716 14067 uid 9702,0 13717 14068 shape (PolyLine2D … … 13734 14085 oxt "6000,7000,7000,8000" 13735 14086 ) 13736 *4 57(CommentGraphic14087 *468 (CommentGraphic 13737 14088 uid 9704,0 13738 14089 shape (PolyLine2D … … 13755 14106 oxt "6988,7329,7988,7329" 13756 14107 ) 13757 *4 58(CommentGraphic14108 *469 (CommentGraphic 13758 14109 uid 9706,0 13759 14110 shape (PolyLine2D … … 13774 14125 oxt "8000,7000,9000,7000" 13775 14126 ) 13776 *4 59(CommentGraphic14127 *470 (CommentGraphic 13777 14128 uid 9708,0 13778 14129 shape (PolyLine2D … … 13815 14166 stg "VerticalLayoutStrategy" 13816 14167 textVec [ 13817 *4 60(Text14168 *471 (Text 13818 14169 uid 9682,0 13819 14170 va (VaSet … … 13825 14176 blo "28350,5900" 13826 14177 ) 13827 *4 61(Text14178 *472 (Text 13828 14179 uid 9683,0 13829 14180 va (VaSet … … 13834 14185 blo "28350,6900" 13835 14186 ) 13836 *4 62(Text14187 *473 (Text 13837 14188 uid 9684,0 13838 14189 va (VaSet … … 13879 14230 ) 13880 14231 ) 13881 *4 63(MWC14232 *474 (MWC 13882 14233 uid 9710,0 13883 14234 optionalChildren [ 13884 *4 64(CptPort14235 *475 (CptPort 13885 14236 uid 9719,0 13886 14237 optionalChildren [ 13887 *4 65(Line14238 *476 (Line 13888 14239 uid 9724,0 13889 14240 layer 5 … … 13943 14294 ) 13944 14295 ) 13945 *4 66(CptPort14296 *477 (CptPort 13946 14297 uid 9725,0 13947 14298 optionalChildren [ 13948 *4 67(Line14299 *478 (Line 13949 14300 uid 9730,0 13950 14301 layer 5 … … 14007 14358 ) 14008 14359 ) 14009 *4 68(CommentGraphic14360 *479 (CommentGraphic 14010 14361 uid 9731,0 14011 14362 shape (PolyLine2D … … 14028 14379 oxt "6000,6000,7000,7000" 14029 14380 ) 14030 *4 69(CommentGraphic14381 *480 (CommentGraphic 14031 14382 uid 9733,0 14032 14383 shape (PolyLine2D … … 14049 14400 oxt "6000,7000,7000,8000" 14050 14401 ) 14051 *4 70(CommentGraphic14402 *481 (CommentGraphic 14052 14403 uid 9735,0 14053 14404 shape (PolyLine2D … … 14070 14421 oxt "6988,7329,7988,7329" 14071 14422 ) 14072 *4 71(CommentGraphic14423 *482 (CommentGraphic 14073 14424 uid 9737,0 14074 14425 shape (PolyLine2D … … 14089 14440 oxt "8000,7000,9000,7000" 14090 14441 ) 14091 *4 72(CommentGraphic14442 *483 (CommentGraphic 14092 14443 uid 9739,0 14093 14444 shape (PolyLine2D … … 14130 14481 stg "VerticalLayoutStrategy" 14131 14482 textVec [ 14132 *4 73(Text14483 *484 (Text 14133 14484 uid 9713,0 14134 14485 va (VaSet … … 14140 14491 blo "28350,9900" 14141 14492 ) 14142 *4 74(Text14493 *485 (Text 14143 14494 uid 9714,0 14144 14495 va (VaSet … … 14149 14500 blo "28350,10900" 14150 14501 ) 14151 *4 75(Text14502 *486 (Text 14152 14503 uid 9715,0 14153 14504 va (VaSet … … 14194 14545 ) 14195 14546 ) 14196 *4 76(PortIoOut14547 *487 (PortIoOut 14197 14548 uid 9761,0 14198 14549 shape (CompositeShape … … 14238 14589 ) 14239 14590 ) 14240 *4 77(Net14591 *488 (Net 14241 14592 uid 9767,0 14242 14593 decl (Decl … … 14252 14603 ) 14253 14604 xt "-103000,28600,-84500,29400" 14254 st "CLK50_OUT : std_logic 14255 " 14256 ) 14257 ) 14258 *478 (PortIoOut 14605 st "CLK50_OUT : std_logic" 14606 ) 14607 ) 14608 *489 (PortIoOut 14259 14609 uid 9777,0 14260 14610 shape (CompositeShape … … 14300 14650 ) 14301 14651 ) 14302 *4 79(Net14652 *490 (Net 14303 14653 uid 9783,0 14304 14654 decl (Decl … … 14314 14664 ) 14315 14665 xt "-103000,27000,-84500,27800" 14316 st "CLK25_OUT : std_logic 14317 " 14318 ) 14319 ) 14320 *480 (PortIoOut 14666 st "CLK25_OUT : std_logic" 14667 ) 14668 ) 14669 *491 (PortIoOut 14321 14670 uid 9793,0 14322 14671 shape (CompositeShape … … 14362 14711 ) 14363 14712 ) 14364 *4 81(Net14713 *492 (Net 14365 14714 uid 9799,0 14366 14715 decl (Decl … … 14376 14725 ) 14377 14726 xt "-103000,27800,-84500,28600" 14378 st "CLK25_PSOUT : std_logic 14379 " 14380 ) 14381 ) 14382 *482 (Net 14727 st "CLK25_PSOUT : std_logic" 14728 ) 14729 ) 14730 *493 (Net 14383 14731 uid 9941,0 14384 14732 decl (Decl … … 14396 14744 font "Courier New,8,0" 14397 14745 ) 14398 xt "-103000,86600,-35500,87400" 14399 st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift 14400 " 14401 ) 14402 ) 14403 *483 (Net 14746 xt "-103000,91400,-35500,92200" 14747 st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift" 14748 ) 14749 ) 14750 *494 (Net 14404 14751 uid 9949,0 14405 14752 decl (Decl … … 14415 14762 font "Courier New,8,0" 14416 14763 ) 14417 xt "-103000,97000,-59500,97800" 14418 st "SIGNAL srclk_enable : std_logic := '0' 14419 " 14420 ) 14421 ) 14422 *484 (MWC 14764 xt "-103000,103400,-59500,104200" 14765 st "SIGNAL srclk_enable : std_logic := '0'" 14766 ) 14767 ) 14768 *495 (MWC 14423 14769 uid 9957,0 14424 14770 optionalChildren [ 14425 *4 85(CptPort14771 *496 (CptPort 14426 14772 uid 9966,0 14427 14773 optionalChildren [ 14428 *4 86(Line14774 *497 (Line 14429 14775 uid 9970,0 14430 14776 layer 5 … … 14439 14785 ] 14440 14786 ) 14441 *4 87(Property14787 *498 (Property 14442 14788 uid 9971,0 14443 14789 pclass "_MW_GEOM_" … … 14483 14829 ) 14484 14830 ) 14485 *4 88(CptPort14831 *499 (CptPort 14486 14832 uid 9972,0 14487 14833 optionalChildren [ 14488 * 489(Line14834 *500 (Line 14489 14835 uid 9976,0 14490 14836 layer 5 … … 14537 14883 ) 14538 14884 ) 14539 * 490(CptPort14885 *501 (CptPort 14540 14886 uid 9977,0 14541 14887 optionalChildren [ 14542 * 491(Line14888 *502 (Line 14543 14889 uid 9981,0 14544 14890 layer 5 … … 14591 14937 ) 14592 14938 ) 14593 * 492(CommentGraphic14939 *503 (CommentGraphic 14594 14940 uid 9982,0 14595 14941 optionalChildren [ 14596 * 493(Property14942 *504 (Property 14597 14943 uid 9984,0 14598 14944 pclass "_MW_GEOM_" … … 14618 14964 oxt "11000,10000,11000,10000" 14619 14965 ) 14620 * 494(CommentGraphic14966 *505 (CommentGraphic 14621 14967 uid 9985,0 14622 14968 optionalChildren [ 14623 * 495(Property14969 *506 (Property 14624 14970 uid 9987,0 14625 14971 pclass "_MW_GEOM_" … … 14645 14991 oxt "11000,6000,11000,6000" 14646 14992 ) 14647 * 496(Grouping14993 *507 (Grouping 14648 14994 uid 9988,0 14649 14995 optionalChildren [ 14650 * 497(CommentGraphic14996 *508 (CommentGraphic 14651 14997 uid 9990,0 14652 14998 shape (PolyLine2D … … 14669 15015 oxt "9000,6000,11000,10000" 14670 15016 ) 14671 * 498(CommentGraphic15017 *509 (CommentGraphic 14672 15018 uid 9992,0 14673 15019 shape (Arc2D … … 14722 15068 stg "VerticalLayoutStrategy" 14723 15069 textVec [ 14724 * 499(Text15070 *510 (Text 14725 15071 uid 9960,0 14726 15072 va (VaSet … … 14732 15078 blo "-29500,53300" 14733 15079 ) 14734 *5 00(Text15080 *511 (Text 14735 15081 uid 9961,0 14736 15082 va (VaSet … … 14741 15087 blo "-29500,54300" 14742 15088 ) 14743 *5 01(Text15089 *512 (Text 14744 15090 uid 9962,0 14745 15091 va (VaSet … … 14786 15132 ) 14787 15133 ) 14788 *5 02(Net15134 *513 (Net 14789 15135 uid 10008,0 14790 15136 decl (Decl … … 14800 15146 font "Courier New,8,0" 14801 15147 ) 14802 xt "-103000,58600,-59500,59400" 14803 st "SIGNAL SRCLK1 : std_logic := '0' 14804 " 14805 ) 14806 ) 14807 *503 (Wire 15148 xt "-103000,59400,-59500,60200" 15149 st "SIGNAL SRCLK1 : std_logic := '0'" 15150 ) 15151 ) 15152 *514 (Net 15153 uid 10192,0 15154 decl (Decl 15155 n "config_rw_ack" 15156 t "std_logic" 15157 prec "-- --" 15158 preAdd 0 15159 posAdd 0 15160 o 107 15161 suid 227,0 15162 i "'0'" 15163 ) 15164 declText (MLText 15165 uid 10193,0 15166 va (VaSet 15167 font "Courier New,8,0" 15168 ) 15169 xt "-103000,69000,-59500,70600" 15170 st "-- -- 15171 SIGNAL config_rw_ack : std_logic := '0'" 15172 ) 15173 ) 15174 *515 (Net 15175 uid 10200,0 15176 decl (Decl 15177 n "config_rw_ready" 15178 t "std_logic" 15179 prec "-- --" 15180 preAdd 0 15181 posAdd 0 15182 o 108 15183 suid 228,0 15184 i "'0'" 15185 ) 15186 declText (MLText 15187 uid 10201,0 15188 va (VaSet 15189 font "Courier New,8,0" 15190 ) 15191 xt "-103000,70600,-59500,72200" 15192 st "-- -- 15193 SIGNAL config_rw_ready : std_logic := '0'" 15194 ) 15195 ) 15196 *516 (Net 15197 uid 10264,0 15198 decl (Decl 15199 n "s_trigger" 15200 t "std_logic" 15201 o 109 15202 suid 230,0 15203 ) 15204 declText (MLText 15205 uid 10265,0 15206 va (VaSet 15207 font "Courier New,8,0" 15208 ) 15209 xt "-103000,99400,-80500,100200" 15210 st "SIGNAL s_trigger : std_logic" 15211 ) 15212 ) 15213 *517 (Net 15214 uid 10296,0 15215 decl (Decl 15216 n "start_srin_write_8b" 15217 t "std_logic" 15218 o 110 15219 suid 231,0 15220 ) 15221 declText (MLText 15222 uid 10297,0 15223 va (VaSet 15224 font "Courier New,8,0" 15225 ) 15226 xt "-103000,105800,-80500,106600" 15227 st "SIGNAL start_srin_write_8b : std_logic" 15228 ) 15229 ) 15230 *518 (Net 15231 uid 10302,0 15232 decl (Decl 15233 n "srin_write_ack" 15234 t "std_logic" 15235 o 111 15236 suid 232,0 15237 i "'0'" 15238 ) 15239 declText (MLText 15240 uid 10303,0 15241 va (VaSet 15242 font "Courier New,8,0" 15243 ) 15244 xt "-103000,104200,-59500,105000" 15245 st "SIGNAL srin_write_ack : std_logic := '0'" 15246 ) 15247 ) 15248 *519 (Net 15249 uid 10308,0 15250 decl (Decl 15251 n "srin_write_ready" 15252 t "std_logic" 15253 o 112 15254 suid 233,0 15255 i "'0'" 15256 ) 15257 declText (MLText 15258 uid 10309,0 15259 va (VaSet 15260 font "Courier New,8,0" 15261 ) 15262 xt "-103000,105000,-59500,105800" 15263 st "SIGNAL srin_write_ready : std_logic := '0'" 15264 ) 15265 ) 15266 *520 (Net 15267 uid 10314,0 15268 decl (Decl 15269 n "drs_srin_data" 15270 t "std_logic_vector" 15271 b "(7 downto 0)" 15272 o 113 15273 suid 234,0 15274 i "(others => '0')" 15275 ) 15276 declText (MLText 15277 uid 10315,0 15278 va (VaSet 15279 font "Courier New,8,0" 15280 ) 15281 xt "-103000,85800,-53500,86600" 15282 st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0')" 15283 ) 15284 ) 15285 *521 (Net 15286 uid 10320,0 15287 decl (Decl 15288 n "SRIN_out" 15289 t "std_logic" 15290 o 114 15291 suid 235,0 15292 i "'0'" 15293 ) 15294 declText (MLText 15295 uid 10321,0 15296 va (VaSet 15297 font "Courier New,8,0" 15298 ) 15299 xt "-103000,39000,-63000,39800" 15300 st "SRIN_out : std_logic := '0'" 15301 ) 15302 ) 15303 *522 (PortIoOut 15304 uid 10328,0 15305 shape (CompositeShape 15306 uid 10329,0 15307 va (VaSet 15308 vasetType 1 15309 fg "0,0,32768" 15310 ) 15311 optionalChildren [ 15312 (Pentagon 15313 uid 10330,0 15314 sl 0 15315 ro 90 15316 xt "-36000,56625,-34500,57375" 15317 ) 15318 (Line 15319 uid 10331,0 15320 sl 0 15321 ro 90 15322 xt "-34500,57000,-34000,57000" 15323 pts [ 15324 "-34000,57000" 15325 "-34500,57000" 15326 ] 15327 ) 15328 ] 15329 ) 15330 stc 0 15331 sf 1 15332 tg (WTG 15333 uid 10332,0 15334 ps "PortIoTextPlaceStrategy" 15335 stg "STSignalDisplayStrategy" 15336 f (Text 15337 uid 10333,0 15338 va (VaSet 15339 ) 15340 xt "-40700,56500,-37000,57500" 15341 st "SRIN_out" 15342 ju 2 15343 blo "-37000,57300" 15344 tm "WireNameMgr" 15345 ) 15346 ) 15347 ) 15348 *523 (MWC 15349 uid 10380,0 15350 optionalChildren [ 15351 *524 (CptPort 15352 uid 10344,0 15353 optionalChildren [ 15354 *525 (Line 15355 uid 10348,0 15356 layer 5 15357 sl 0 15358 va (VaSet 15359 vasetType 3 15360 ) 15361 xt "-30000,70000,-28409,70000" 15362 pts [ 15363 "-30000,70000" 15364 "-28409,70000" 15365 ] 15366 ) 15367 ] 15368 ps "OnEdgeStrategy" 15369 shape (Triangle 15370 uid 10345,0 15371 ro 90 15372 va (VaSet 15373 vasetType 1 15374 isHidden 1 15375 fg "0,65535,65535" 15376 ) 15377 xt "-30750,69625,-30000,70375" 15378 ) 15379 tg (CPTG 15380 uid 10346,0 15381 ps "CptPortTextPlaceStrategy" 15382 stg "VerticalLayoutStrategy" 15383 f (Text 15384 uid 10347,0 15385 sl 0 15386 va (VaSet 15387 isHidden 1 15388 font "arial,8,0" 15389 ) 15390 xt "-33000,69700,-31200,70700" 15391 st "din1" 15392 blo "-33000,70500" 15393 ) 15394 ) 15395 thePort (LogicalPort 15396 decl (Decl 15397 n "din1" 15398 t "std_logic" 15399 preAdd 0 15400 posAdd 0 15401 o 10 15402 suid 1,0 15403 ) 15404 ) 15405 ) 15406 *526 (CptPort 15407 uid 10349,0 15408 optionalChildren [ 15409 *527 (Property 15410 uid 10353,0 15411 pclass "_MW_GEOM_" 15412 pname "fixed" 15413 ptn "String" 15414 ) 15415 *528 (Line 15416 uid 10354,0 15417 layer 5 15418 sl 0 15419 va (VaSet 15420 vasetType 3 15421 ) 15422 xt "-24999,69000,-24000,69000" 15423 pts [ 15424 "-24000,69000" 15425 "-24999,69000" 15426 ] 15427 ) 15428 ] 15429 ps "OnEdgeStrategy" 15430 shape (Triangle 15431 uid 10350,0 15432 ro 90 15433 va (VaSet 15434 vasetType 1 15435 isHidden 1 15436 fg "0,65535,65535" 15437 ) 15438 xt "-24000,68625,-23250,69375" 15439 ) 15440 tg (CPTG 15441 uid 10351,0 15442 ps "CptPortTextPlaceStrategy" 15443 stg "RightVerticalLayoutStrategy" 15444 f (Text 15445 uid 10352,0 15446 sl 0 15447 va (VaSet 15448 isHidden 1 15449 font "arial,8,0" 15450 ) 15451 xt "-22750,68532,-20950,69532" 15452 st "dout" 15453 ju 2 15454 blo "-20950,69332" 15455 ) 15456 ) 15457 thePort (LogicalPort 15458 m 1 15459 decl (Decl 15460 n "dout" 15461 t "std_logic" 15462 preAdd 0 15463 posAdd 0 15464 o 115 15465 suid 2,0 15466 ) 15467 ) 15468 ) 15469 *529 (CptPort 15470 uid 10355,0 15471 optionalChildren [ 15472 *530 (Line 15473 uid 10359,0 15474 layer 5 15475 sl 0 15476 va (VaSet 15477 vasetType 3 15478 ) 15479 xt "-30000,68000,-28409,68000" 15480 pts [ 15481 "-30000,68000" 15482 "-28409,68000" 15483 ] 15484 ) 15485 ] 15486 ps "OnEdgeStrategy" 15487 shape (Triangle 15488 uid 10356,0 15489 ro 90 15490 va (VaSet 15491 vasetType 1 15492 isHidden 1 15493 fg "0,65535,65535" 15494 ) 15495 xt "-30750,67625,-30000,68375" 15496 ) 15497 tg (CPTG 15498 uid 10357,0 15499 ps "CptPortTextPlaceStrategy" 15500 stg "VerticalLayoutStrategy" 15501 f (Text 15502 uid 10358,0 15503 sl 0 15504 va (VaSet 15505 isHidden 1 15506 font "arial,8,0" 15507 ) 15508 xt "-33115,67294,-31315,68294" 15509 st "din0" 15510 blo "-33115,68094" 15511 ) 15512 ) 15513 thePort (LogicalPort 15514 decl (Decl 15515 n "din0" 15516 t "std_logic" 15517 o 109 15518 suid 3,0 15519 ) 15520 ) 15521 ) 15522 *531 (CommentGraphic 15523 uid 10360,0 15524 shape (Arc2D 15525 pts [ 15526 "-29000,67004" 15527 "-26737,67521" 15528 "-25000,69000" 15529 ] 15530 uid 10361,0 15531 layer 8 15532 sl 0 15533 va (VaSet 15534 vasetType 1 15535 fg "0,65535,65535" 15536 bg "0,65535,65535" 15537 lineColor "26368,26368,26368" 15538 ) 15539 xt "-29000,67003,-25000,69000" 15540 ) 15541 oxt "7000,6003,11000,8000" 15542 ) 15543 *532 (CommentGraphic 15544 uid 10362,0 15545 shape (Arc2D 15546 pts [ 15547 "-25000,69005" 15548 "-26551,70394" 15549 "-29004,70998" 15550 ] 15551 uid 10363,0 15552 layer 0 15553 sl 0 15554 va (VaSet 15555 vasetType 1 15556 fg "0,65535,65535" 15557 bg "0,65535,65535" 15558 lineColor "26368,26368,26368" 15559 ) 15560 xt "-29004,69005,-25000,70999" 15561 ) 15562 oxt "6996,8005,11000,10000" 15563 ) 15564 *533 (Grouping 15565 uid 10364,0 15566 optionalChildren [ 15567 *534 (CommentGraphic 15568 uid 10366,0 15569 optionalChildren [ 15570 *535 (Property 15571 uid 10368,0 15572 pclass "_MW_GEOM_" 15573 pname "arc" 15574 ptn "String" 15575 ) 15576 ] 15577 shape (CustomPolygon 15578 pts [ 15579 "-29000,70998" 15580 "-29000,67000" 15581 "-27817,67211" 15582 "-26048,68156" 15583 "-25000,69000" 15584 "-26952,70132" 15585 "-29000,70998" 15586 ] 15587 uid 10367,0 15588 layer 0 15589 sl 0 15590 va (VaSet 15591 vasetType 1 15592 transparent 1 15593 fg "0,65535,65535" 15594 lineColor "32768,0,32768" 15595 fillStyle 1 15596 ) 15597 xt "-29000,67000,-25000,70998" 15598 ) 15599 oxt "7000,6000,11000,9998" 15600 ) 15601 *536 (CommentGraphic 15602 uid 10369,0 15603 optionalChildren [ 15604 *537 (Property 15605 uid 10371,0 15606 pclass "_MW_GEOM_" 15607 pname "arc" 15608 ptn "String" 15609 ) 15610 ] 15611 shape (Arc2D 15612 pts [ 15613 "-29000,67000" 15614 "-28237,69001" 15615 "-29000,71000" 15616 ] 15617 uid 10370,0 15618 layer 0 15619 sl 0 15620 va (VaSet 15621 vasetType 1 15622 transparent 1 15623 fg "0,65535,65535" 15624 bg "0,65535,65535" 15625 lineColor "26368,26368,26368" 15626 fillStyle 1 15627 ) 15628 xt "-29000,67000,-28236,71000" 15629 ) 15630 oxt "7000,6000,7762,10000" 15631 ) 15632 ] 15633 shape (GroupingShape 15634 uid 10365,0 15635 sl 0 15636 va (VaSet 15637 vasetType 1 15638 fg "65535,65535,65535" 15639 lineStyle 2 15640 lineWidth 2 15641 ) 15642 xt "-29000,67000,-25000,71000" 15643 ) 15644 oxt "7000,6000,11000,10000" 15645 ) 15646 *538 (CommentGraphic 15647 uid 10372,0 15648 shape (PolyLine2D 15649 pts [ 15650 "-25000,69000" 15651 "-25000,69000" 15652 ] 15653 uid 10373,0 15654 layer 0 15655 sl 0 15656 va (VaSet 15657 vasetType 1 15658 transparent 1 15659 fg "49152,49152,49152" 15660 ) 15661 xt "-25000,69000,-25000,69000" 15662 ) 15663 oxt "11000,8000,11000,8000" 15664 ) 15665 *539 (CommentGraphic 15666 uid 10374,0 15667 optionalChildren [ 15668 *540 (Property 15669 uid 10376,0 15670 pclass "_MW_GEOM_" 15671 pname "expand" 15672 ptn "String" 15673 ) 15674 ] 15675 shape (PolyLine2D 15676 pts [ 15677 "-29000,67000" 15678 "-29000,67000" 15679 ] 15680 uid 10375,0 15681 layer 0 15682 sl 0 15683 va (VaSet 15684 vasetType 1 15685 transparent 1 15686 fg "49152,49152,49152" 15687 ) 15688 xt "-29000,67000,-29000,67000" 15689 ) 15690 oxt "7000,6000,7000,6000" 15691 ) 15692 *541 (CommentGraphic 15693 uid 10377,0 15694 optionalChildren [ 15695 *542 (Property 15696 uid 10379,0 15697 pclass "_MW_GEOM_" 15698 pname "expand" 15699 ptn "String" 15700 ) 15701 ] 15702 shape (PolyLine2D 15703 pts [ 15704 "-29000,71000" 15705 "-29000,71000" 15706 ] 15707 uid 10378,0 15708 layer 0 15709 sl 0 15710 va (VaSet 15711 vasetType 1 15712 transparent 1 15713 fg "49152,49152,49152" 15714 ) 15715 xt "-29000,71000,-29000,71000" 15716 ) 15717 oxt "7000,10000,7000,10000" 15718 ) 15719 ] 15720 shape (Rectangle 15721 uid 10381,0 15722 va (VaSet 15723 vasetType 1 15724 transparent 1 15725 fg "65535,65535,65535" 15726 lineWidth -1 15727 ) 15728 xt "-30000,67000,-24000,71000" 15729 fos 1 15730 ) 15731 showPorts 0 15732 oxt "6000,6000,12000,10000" 15733 ttg (MlTextGroup 15734 uid 10382,0 15735 ps "CenterOffsetStrategy" 15736 stg "VerticalLayoutStrategy" 15737 textVec [ 15738 *543 (Text 15739 uid 10383,0 15740 va (VaSet 15741 isHidden 1 15742 font "arial,8,0" 15743 ) 15744 xt "-28500,69500,-23700,70500" 15745 st "moduleware" 15746 blo "-28500,70300" 15747 ) 15748 *544 (Text 15749 uid 10384,0 15750 va (VaSet 15751 font "arial,8,0" 15752 ) 15753 xt "-28500,70500,-27400,71500" 15754 st "or" 15755 blo "-28500,71300" 15756 ) 15757 *545 (Text 15758 uid 10385,0 15759 va (VaSet 15760 font "arial,8,0" 15761 ) 15762 xt "-28500,71500,-26700,72500" 15763 st "U_9" 15764 blo "-28500,72300" 15765 tm "InstanceNameMgr" 15766 ) 15767 ] 15768 ) 15769 ga (GenericAssociation 15770 uid 10386,0 15771 ps "EdgeToEdgeStrategy" 15772 matrix (Matrix 15773 uid 10387,0 15774 text (MLText 15775 uid 10388,0 15776 va (VaSet 15777 font "arial,8,0" 15778 ) 15779 xt "-45000,58000,-45000,58000" 15780 ) 15781 header "" 15782 ) 15783 elements [ 15784 ] 15785 ) 15786 sed 1 15787 awe 1 15788 portVis (PortSigDisplay 15789 sN 0 15790 sTC 0 15791 selT 0 15792 ) 15793 prms (Property 15794 pclass "params" 15795 pname "params" 15796 ptn "String" 15797 ) 15798 de 2 15799 visOptions (mwParamsVisibilityOptions 15800 ) 15801 ) 15802 *546 (Net 15803 uid 10449,0 15804 decl (Decl 15805 n "trigger_out" 15806 t "std_logic" 15807 preAdd 0 15808 posAdd 0 15809 o 115 15810 suid 240,0 15811 ) 15812 declText (MLText 15813 uid 10450,0 15814 va (VaSet 15815 font "Courier New,8,0" 15816 ) 15817 xt "-103000,107400,-80500,108200" 15818 st "SIGNAL trigger_out : std_logic" 15819 ) 15820 ) 15821 *547 (Net 15822 uid 10465,0 15823 lang 2 15824 decl (Decl 15825 n "ram_write_ready_ack" 15826 t "std_logic" 15827 prec "-- --" 15828 preAdd 0 15829 posAdd 0 15830 o 115 15831 suid 242,0 15832 i "'0'" 15833 ) 15834 declText (MLText 15835 uid 10466,0 15836 va (VaSet 15837 font "Courier New,8,0" 15838 ) 15839 xt "-103000,96200,-59500,97800" 15840 st "-- -- 15841 SIGNAL ram_write_ready_ack : std_logic := '0'" 15842 ) 15843 ) 15844 *548 (Wire 14808 15845 uid 322,0 14809 15846 shape (OrthoPolyLine … … 14821 15858 ) 14822 15859 start &26 14823 end &3 1315860 end &324 14824 15861 sat 32 14825 15862 eat 32 … … 14844 15881 on &2 14845 15882 ) 14846 *5 04(Wire15883 *549 (Wire 14847 15884 uid 328,0 14848 15885 shape (OrthoPolyLine … … 14860 15897 ) 14861 15898 start &25 14862 end &3 1215899 end &323 14863 15900 sat 32 14864 15901 eat 32 … … 14883 15920 on &3 14884 15921 ) 14885 *5 05(Wire15922 *550 (Wire 14886 15923 uid 334,0 14887 15924 shape (OrthoPolyLine … … 14899 15936 ) 14900 15937 start &24 14901 end &3 1115938 end &322 14902 15939 sat 32 14903 15940 eat 32 … … 14922 15959 on &4 14923 15960 ) 14924 *5 06(Wire15961 *551 (Wire 14925 15962 uid 364,0 14926 15963 shape (OrthoPolyLine … … 14930 15967 lineWidth 2 14931 15968 ) 14932 xt "91750,49000,12 6250,54000"14933 pts [ 14934 "12 6250,54000"14935 "1 13000,54000"14936 "1 13000,49000"15969 xt "91750,49000,127250,54000" 15970 pts [ 15971 "127250,54000" 15972 "123000,54000" 15973 "123000,49000" 14937 15974 "91750,49000" 14938 15975 ] 14939 15976 ) 14940 start &8 014941 end &3 1515977 start &84 15978 end &326 14942 15979 sat 32 14943 15980 eat 32 … … 14962 15999 on &5 14963 16000 ) 14964 *5 07(Wire16001 *552 (Wire 14965 16002 uid 370,0 14966 16003 shape (OrthoPolyLine … … 14970 16007 lineWidth 2 14971 16008 ) 14972 xt "91750,50000,12 6250,55000"14973 pts [ 14974 "12 6250,55000"14975 "1 12000,55000"14976 "1 12000,50000"16009 xt "91750,50000,127250,55000" 16010 pts [ 16011 "127250,55000" 16012 "124000,55000" 16013 "124000,50000" 14977 16014 "91750,50000" 14978 16015 ] 14979 16016 ) 14980 start & 7914981 end &3 1616017 start &83 16018 end &327 14982 16019 sat 32 14983 16020 eat 32 … … 15002 16039 on &6 15003 16040 ) 15004 *5 08(Wire16041 *553 (Wire 15005 16042 uid 376,0 15006 16043 shape (OrthoPolyLine … … 15009 16046 vasetType 3 15010 16047 ) 15011 xt "14 8750,52000,153000,52000"15012 pts [ 15013 "14 8750,52000"15014 "15 3000,52000"15015 ] 15016 ) 15017 start &7 016048 xt "149750,52000,154000,52000" 16049 pts [ 16050 "149750,52000" 16051 "154000,52000" 16052 ] 16053 ) 16054 start &74 15018 16055 end &14 15019 16056 sat 32 … … 15032 16069 isHidden 1 15033 16070 ) 15034 xt "15 0000,51000,153600,52000"16071 xt "151000,51000,154600,52000" 15035 16072 st "wiz_reset" 15036 blo "15 0000,51800"16073 blo "151000,51800" 15037 16074 tm "WireNameMgr" 15038 16075 ) … … 15040 16077 on &7 15041 16078 ) 15042 *5 09(Wire16079 *554 (Wire 15043 16080 uid 384,0 15044 16081 shape (OrthoPolyLine … … 15048 16085 lineWidth 2 15049 16086 ) 15050 xt "14 8750,60000,153000,60000"15051 pts [ 15052 "14 8750,60000"15053 "15 3000,60000"15054 ] 15055 ) 15056 start &7 116087 xt "149750,60000,154000,60000" 16088 pts [ 16089 "149750,60000" 16090 "154000,60000" 16091 ] 16092 ) 16093 start &75 15057 16094 end &15 15058 16095 sat 32 … … 15072 16109 isHidden 1 15073 16110 ) 15074 xt "15 0000,59000,153400,60000"16111 xt "151000,59000,154400,60000" 15075 16112 st "wiz_addr" 15076 blo "15 0000,59800"16113 blo "151000,59800" 15077 16114 tm "WireNameMgr" 15078 16115 ) … … 15080 16117 on &8 15081 16118 ) 15082 *5 10(Wire16119 *555 (Wire 15083 16120 uid 392,0 15084 16121 shape (OrthoPolyLine … … 15088 16125 lineWidth 2 15089 16126 ) 15090 xt "14 8750,61000,153000,61000"15091 pts [ 15092 "14 8750,61000"15093 "15 3000,61000"15094 ] 15095 ) 15096 start &7 216127 xt "149750,61000,154000,61000" 16128 pts [ 16129 "149750,61000" 16130 "154000,61000" 16131 ] 16132 ) 16133 start &76 15097 16134 end &16 15098 16135 sat 32 … … 15112 16149 isHidden 1 15113 16150 ) 15114 xt "15 0000,60000,153300,61000"16151 xt "151000,60000,154300,61000" 15115 16152 st "wiz_data" 15116 blo "15 0000,60800"16153 blo "151000,60800" 15117 16154 tm "WireNameMgr" 15118 16155 ) … … 15120 16157 on &9 15121 16158 ) 15122 *5 11(Wire16159 *556 (Wire 15123 16160 uid 400,0 15124 16161 shape (OrthoPolyLine … … 15127 16164 vasetType 3 15128 16165 ) 15129 xt "14 8750,53000,153000,53000"15130 pts [ 15131 "14 8750,53000"15132 "15 3000,53000"15133 ] 15134 ) 15135 start &7 316166 xt "149750,53000,154000,53000" 16167 pts [ 16168 "149750,53000" 16169 "154000,53000" 16170 ] 16171 ) 16172 start &77 15136 16173 end &17 15137 16174 sat 32 … … 15150 16187 isHidden 1 15151 16188 ) 15152 xt "15 0000,52000,152700,53000"16189 xt "151000,52000,153700,53000" 15153 16190 st "wiz_cs" 15154 blo "15 0000,52800"16191 blo "151000,52800" 15155 16192 tm "WireNameMgr" 15156 16193 ) … … 15158 16195 on &10 15159 16196 ) 15160 *5 12(Wire16197 *557 (Wire 15161 16198 uid 408,0 15162 16199 shape (OrthoPolyLine … … 15165 16202 vasetType 3 15166 16203 ) 15167 xt "14 8750,54000,153000,54000"15168 pts [ 15169 "14 8750,54000"15170 "15 3000,54000"15171 ] 15172 ) 15173 start &7 416204 xt "149750,54000,154000,54000" 16205 pts [ 16206 "149750,54000" 16207 "154000,54000" 16208 ] 16209 ) 16210 start &78 15174 16211 end &18 15175 16212 sat 32 … … 15188 16225 isHidden 1 15189 16226 ) 15190 xt "15 0000,53000,152700,54000"16227 xt "151000,53000,153700,54000" 15191 16228 st "wiz_wr" 15192 blo "15 0000,53800"16229 blo "151000,53800" 15193 16230 tm "WireNameMgr" 15194 16231 ) … … 15196 16233 on &11 15197 16234 ) 15198 *5 13(Wire16235 *558 (Wire 15199 16236 uid 424,0 15200 16237 shape (OrthoPolyLine … … 15203 16240 vasetType 3 15204 16241 ) 15205 xt "14 8750,55000,153000,55000"15206 pts [ 15207 "14 8750,55000"15208 "15 3000,55000"15209 ] 15210 ) 15211 start &7 516242 xt "149750,55000,154000,55000" 16243 pts [ 16244 "149750,55000" 16245 "154000,55000" 16246 ] 16247 ) 16248 start &79 15212 16249 end &20 15213 16250 sat 32 … … 15226 16263 isHidden 1 15227 16264 ) 15228 xt "15 0000,54000,152600,55000"16265 xt "151000,54000,153600,55000" 15229 16266 st "wiz_rd" 15230 blo "15 0000,54800"16267 blo "151000,54800" 15231 16268 tm "WireNameMgr" 15232 16269 ) … … 15234 16271 on &12 15235 16272 ) 15236 *5 14(Wire16273 *559 (Wire 15237 16274 uid 432,0 15238 16275 shape (OrthoPolyLine … … 15241 16278 vasetType 3 15242 16279 ) 15243 xt "14 8750,56000,153000,56000"15244 pts [ 15245 "15 3000,56000"15246 "14 8750,56000"16280 xt "149750,56000,154000,56000" 16281 pts [ 16282 "154000,56000" 16283 "149750,56000" 15247 16284 ] 15248 16285 ) 15249 16286 start &21 15250 end & 7616287 end &80 15251 16288 sat 32 15252 16289 eat 32 … … 15264 16301 isHidden 1 15265 16302 ) 15266 xt "15 0000,55000,152700,56000"16303 xt "151000,55000,153700,56000" 15267 16304 st "wiz_int" 15268 blo "15 0000,55800"16305 blo "151000,55800" 15269 16306 tm "WireNameMgr" 15270 16307 ) … … 15272 16309 on &13 15273 16310 ) 15274 *5 15(Wire16311 *560 (Wire 15275 16312 uid 1411,0 15276 16313 shape (OrthoPolyLine … … 15286 16323 ] 15287 16324 ) 15288 start &1 5516325 start &162 15289 16326 end &28 15290 16327 sat 32 … … 15309 16346 ) 15310 16347 ) 15311 on &6 515312 ) 15313 *5 16(Wire16348 on &69 16349 ) 16350 *561 (Wire 15314 16351 uid 1425,0 15315 optionalChildren [15316 *517 (BdJunction15317 uid 4391,015318 ps "OnConnectorStrategy"15319 shape (Circle15320 uid 4392,015321 va (VaSet15322 vasetType 115323 )15324 xt "-22400,68600,-21600,69400"15325 radius 40015326 )15327 )15328 ]15329 16352 shape (OrthoPolyLine 15330 16353 uid 1426,0 … … 15332 16355 vasetType 3 15333 16356 ) 15334 xt "- 26000,69000,18250,69000"15335 pts [ 15336 "- 26000,69000"15337 " 18250,69000"15338 ] 15339 ) 15340 start & 6715341 end & 3016357 xt "-32000,70000,-30000,70000" 16358 pts [ 16359 "-32000,70000" 16360 "-30000,70000" 16361 ] 16362 ) 16363 start &71 16364 end &524 15342 16365 es 0 15343 16366 sat 32 … … 15356 16379 isHidden 1 15357 16380 ) 15358 xt " 5000,63000,7800,64000"16381 xt "-38000,69000,-35200,70000" 15359 16382 st "trigger" 15360 blo " 5000,63800"16383 blo "-38000,69800" 15361 16384 tm "WireNameMgr" 15362 16385 ) 15363 16386 ) 15364 on & 6615365 ) 15366 *5 18(Wire16387 on &70 16388 ) 16389 *562 (Wire 15367 16390 uid 1682,0 15368 16391 shape (OrthoPolyLine … … 15378 16401 ] 15379 16402 ) 15380 start &1 5616403 start &163 15381 16404 end &31 15382 16405 sat 32 … … 15401 16424 ) 15402 16425 ) 15403 on &1 0615404 ) 15405 *5 19(Wire16426 on &112 16427 ) 16428 *563 (Wire 15406 16429 uid 1983,0 15407 16430 shape (OrthoPolyLine … … 15419 16442 ] 15420 16443 ) 15421 start &1 0816444 start &114 15422 16445 end &29 15423 16446 sat 32 … … 15440 16463 ) 15441 16464 ) 15442 on &1 1415443 ) 15444 *5 20(Wire16465 on &120 16466 ) 16467 *564 (Wire 15445 16468 uid 2299,0 15446 16469 shape (OrthoPolyLine … … 15458 16481 ] 15459 16482 ) 15460 start &1 1716483 start &123 15461 16484 end &27 15462 16485 sat 32 … … 15480 16503 ) 15481 16504 ) 15482 on &1 1515483 ) 15484 *5 21(Wire16505 on &121 16506 ) 16507 *565 (Wire 15485 16508 uid 2470,0 15486 16509 shape (OrthoPolyLine … … 15489 16512 vasetType 3 15490 16513 ) 15491 xt "103750,68000,12 6250,68000"16514 xt "103750,68000,127250,68000" 15492 16515 pts [ 15493 16516 "103750,68000" 15494 "115000,68000" 15495 "126250,68000" 15496 ] 15497 ) 15498 start &124 15499 end &82 16517 "127250,68000" 16518 ] 16519 ) 16520 start &130 16521 end &86 15500 16522 sat 32 15501 16523 eat 32 … … 15517 16539 ) 15518 16540 ) 15519 on &1 3815520 ) 15521 *5 22(Wire16541 on &145 16542 ) 16543 *566 (Wire 15522 16544 uid 2476,0 15523 16545 shape (OrthoPolyLine … … 15526 16548 vasetType 3 15527 16549 ) 15528 xt "103750,69000,12 6250,69000"16550 xt "103750,69000,127250,69000" 15529 16551 pts [ 15530 16552 "103750,69000" 15531 "115000,69000" 15532 "126250,69000" 15533 ] 15534 ) 15535 start &127 15536 end &81 16553 "127250,69000" 16554 ] 16555 ) 16556 start &133 16557 end &85 15537 16558 sat 32 15538 16559 eat 32 … … 15554 16575 ) 15555 16576 ) 15556 on &1 3915557 ) 15558 *5 23(Wire16577 on &146 16578 ) 16579 *567 (Wire 15559 16580 uid 2482,0 15560 16581 shape (OrthoPolyLine … … 15564 16585 lineWidth 2 15565 16586 ) 15566 xt "103750,70000,12 6250,70000"16587 xt "103750,70000,127250,70000" 15567 16588 pts [ 15568 16589 "103750,70000" 15569 "115000,70000" 15570 "126250,70000" 15571 ] 15572 ) 15573 start &130 15574 end &77 16590 "127250,70000" 16591 ] 16592 ) 16593 start &136 16594 end &81 15575 16595 sat 32 15576 16596 eat 32 … … 15593 16613 ) 15594 16614 ) 15595 on &14 015596 ) 15597 *5 24(Wire16615 on &147 16616 ) 16617 *568 (Wire 15598 16618 uid 2488,0 15599 16619 shape (OrthoPolyLine … … 15603 16623 lineWidth 2 15604 16624 ) 15605 xt "103750,71000,12 6250,71000"16625 xt "103750,71000,127250,71000" 15606 16626 pts [ 15607 16627 "103750,71000" 15608 "115000,71000" 15609 "126250,71000" 15610 ] 15611 ) 15612 start &126 15613 end &78 16628 "127250,71000" 16629 ] 16630 ) 16631 start &132 16632 end &82 15614 16633 sat 32 15615 16634 eat 32 … … 15632 16651 ) 15633 16652 ) 15634 on &14 115635 ) 15636 *5 25(Wire16653 on &148 16654 ) 16655 *569 (Wire 15637 16656 uid 2494,0 15638 16657 shape (OrthoPolyLine … … 15642 16661 lineWidth 2 15643 16662 ) 15644 xt "103750,72000,12 6250,72000"16663 xt "103750,72000,127250,72000" 15645 16664 pts [ 15646 16665 "103750,72000" 15647 "115000,72000" 15648 "126250,72000" 15649 ] 15650 ) 15651 start &125 15652 end &83 16666 "127250,72000" 16667 ] 16668 ) 16669 start &131 16670 end &87 15653 16671 sat 32 15654 16672 eat 32 … … 15671 16689 ) 15672 16690 ) 15673 on &14 215674 ) 15675 *5 26(Wire16691 on &149 16692 ) 16693 *570 (Wire 15676 16694 uid 2500,0 15677 16695 shape (OrthoPolyLine … … 15680 16698 vasetType 3 15681 16699 ) 15682 xt "103750,73000,12 6250,73000"16700 xt "103750,73000,127250,73000" 15683 16701 pts [ 15684 16702 "103750,73000" 15685 "115000,73000" 15686 "126250,73000" 15687 ] 15688 ) 15689 start &128 15690 end &84 16703 "127250,73000" 16704 ] 16705 ) 16706 start &134 16707 end &88 15691 16708 sat 32 15692 16709 eat 32 … … 15708 16725 ) 15709 16726 ) 15710 on &1 4315711 ) 15712 *5 27(Wire16727 on &150 16728 ) 16729 *571 (Wire 15713 16730 uid 2506,0 15714 16731 shape (OrthoPolyLine … … 15717 16734 vasetType 3 15718 16735 ) 15719 xt "103750,74000,12 6250,74000"16736 xt "103750,74000,127250,74000" 15720 16737 pts [ 15721 16738 "103750,74000" 15722 "115000,74000" 15723 "126250,74000" 15724 ] 15725 ) 15726 start &129 15727 end &85 16739 "127250,74000" 16740 ] 16741 ) 16742 start &135 16743 end &89 15728 16744 sat 32 15729 16745 eat 32 … … 15745 16761 ) 15746 16762 ) 15747 on &1 4415748 ) 15749 *5 28(Wire16763 on &151 16764 ) 16765 *572 (Wire 15750 16766 uid 2576,0 15751 16767 shape (OrthoPolyLine … … 15763 16779 ) 15764 16780 start &32 15765 end &12 116781 end &127 15766 16782 sat 32 15767 16783 eat 32 … … 15783 16799 ) 15784 16800 ) 15785 on &1 4515786 ) 15787 *5 29(Wire16801 on &152 16802 ) 16803 *573 (Wire 15788 16804 uid 2582,0 15789 16805 shape (OrthoPolyLine … … 15801 16817 ) 15802 16818 start &33 15803 end &12 216819 end &128 15804 16820 sat 32 15805 16821 eat 32 … … 15821 16837 ) 15822 16838 ) 15823 on &1 4615824 ) 15825 *5 30(Wire16839 on &153 16840 ) 16841 *574 (Wire 15826 16842 uid 2588,0 15827 16843 shape (OrthoPolyLine … … 15833 16849 pts [ 15834 16850 "40750,70000" 15835 "6 4000,70000"15836 "6 4000,75000"16851 "63000,70000" 16852 "63000,75000" 15837 16853 "71250,75000" 15838 16854 ] 15839 16855 ) 15840 start &5 315841 end &12 016856 start &52 16857 end &126 15842 16858 ss 0 15843 16859 sat 32 … … 15860 16876 ) 15861 16877 ) 15862 on &1 4715863 ) 15864 *5 31(Wire16878 on &154 16879 ) 16880 *575 (Wire 15865 16881 uid 2594,0 15866 16882 shape (OrthoPolyLine … … 15872 16888 pts [ 15873 16889 "40750,72000" 15874 "6 2000,72000"15875 "6 2000,77000"16890 "61000,72000" 16891 "61000,77000" 15876 16892 "71250,77000" 15877 16893 ] 15878 16894 ) 15879 start &4 915880 end &1 1916895 start &48 16896 end &125 15881 16897 sat 32 15882 16898 eat 32 … … 15898 16914 ) 15899 16915 ) 15900 on &1 4815901 ) 15902 *5 32(Wire16916 on &155 16917 ) 16918 *576 (Wire 15903 16919 uid 2600,0 15904 16920 shape (OrthoPolyLine … … 15910 16926 pts [ 15911 16927 "40750,74000" 15912 "6 1000,74000"15913 "6 1000,78000"16928 "60000,74000" 16929 "60000,78000" 15914 16930 "71250,78000" 15915 16931 ] 15916 16932 ) 15917 16933 start &34 15918 end &12 316934 end &129 15919 16935 sat 32 15920 16936 eat 32 … … 15936 16952 ) 15937 16953 ) 15938 on &1 4915939 ) 15940 *5 33(Wire16954 on &156 16955 ) 16956 *577 (Wire 15941 16957 uid 2642,0 15942 16958 shape (OrthoPolyLine … … 15949 16965 pts [ 15950 16966 "40750,75000" 15951 " 60000,75000"15952 " 60000,79000"16967 "59000,75000" 16968 "59000,79000" 15953 16969 "71250,79000" 15954 16970 ] 15955 16971 ) 15956 16972 start &36 15957 end &13 216973 end &138 15958 16974 sat 32 15959 16975 eat 32 … … 15976 16992 ) 15977 16993 ) 15978 on &15 015979 ) 15980 *5 34(Wire16994 on &157 16995 ) 16996 *578 (Wire 15981 16997 uid 2778,0 15982 16998 shape (OrthoPolyLine … … 15992 17008 ) 15993 17009 start &37 15994 end &15 217010 end &159 15995 17011 sat 32 15996 17012 eat 32 … … 16014 17030 ) 16015 17031 ) 16016 on &15 116017 ) 16018 *5 35(Wire17032 on &158 17033 ) 17034 *579 (Wire 16019 17035 uid 2786,0 16020 17036 shape (OrthoPolyLine … … 16030 17046 ] 16031 17047 ) 16032 start &1 5316033 end &2 5017048 start &160 17049 end &261 16034 17050 sat 32 16035 17051 eat 32 … … 16054 17070 ) 16055 17071 ) 16056 on &174 16057 ) 16058 *536 (Wire 16059 uid 2876,0 16060 shape (OrthoPolyLine 16061 uid 2877,0 16062 va (VaSet 16063 vasetType 3 16064 ) 16065 xt "-22000,64000,-18750,69000" 16066 pts [ 16067 "-22000,69000" 16068 "-22000,64000" 16069 "-18750,64000" 16070 ] 16071 ) 16072 start &517 16073 end &109 16074 es 0 16075 sat 32 16076 eat 32 16077 st 0 16078 sf 1 16079 tg (WTG 16080 uid 2880,0 16081 ps "ConnStartEndStrategy" 16082 stg "STSignalDisplayStrategy" 16083 f (Text 16084 uid 2881,0 16085 ro 270 16086 va (VaSet 16087 ) 16088 xt "-23000,64200,-22000,67000" 16089 st "trigger" 16090 blo "-22200,67000" 16091 tm "WireNameMgr" 16092 ) 16093 ) 16094 on &66 16095 ) 16096 *537 (Wire 17072 on &181 17073 ) 17074 *580 (Wire 16097 17075 uid 3888,0 16098 17076 optionalChildren [ 16099 *5 38(BdJunction17077 *581 (BdJunction 16100 17078 uid 4230,0 16101 17079 ps "OnConnectorStrategy" … … 16109 17087 ) 16110 17088 ) 16111 *5 39(BdJunction17089 *582 (BdJunction 16112 17090 uid 4244,0 16113 17091 ps "OnConnectorStrategy" … … 16117 17095 vasetType 1 16118 17096 ) 16119 xt "108600, 18600,109400,19400"17097 xt "108600,51600,109400,52400" 16120 17098 radius 400 16121 17099 ) 16122 17100 ) 16123 *5 40(BdJunction17101 *583 (BdJunction 16124 17102 uid 9677,0 16125 17103 ps "OnConnectorStrategy" … … 16140 17118 lineColor "0,0,65535" 16141 17119 ) 16142 xt "-1250,19000,12 6250,52000"17120 xt "-1250,19000,127250,52000" 16143 17121 pts [ 16144 17122 "-1250,19000" 16145 "1 23000,19000"16146 "1 23000,52000"16147 "12 6250,52000"16148 ] 16149 ) 16150 start &3 6816151 end & 6917123 "106000,19000" 17124 "106000,52000" 17125 "127250,52000" 17126 ] 17127 ) 17128 start &379 17129 end &73 16152 17130 sat 32 16153 17131 eat 32 … … 16170 17148 ) 16171 17149 ) 16172 on &17 016173 ) 16174 *5 41(Wire17150 on &177 17151 ) 17152 *584 (Wire 16175 17153 uid 3984,0 16176 17154 optionalChildren [ 16177 *5 42(BdJunction17155 *585 (BdJunction 16178 17156 uid 9751,0 16179 17157 ps "OnConnectorStrategy" … … 16202 17180 ] 16203 17181 ) 16204 start &1 6916205 end &3 8017182 start &176 17183 end &391 16206 17184 sat 32 16207 17185 eat 32 … … 16225 17203 ) 16226 17204 ) 16227 on &1 6816228 ) 16229 *5 43(Wire17205 on &175 17206 ) 17207 *586 (Wire 16230 17208 uid 4042,0 16231 17209 shape (OrthoPolyLine … … 16241 17219 ) 16242 17220 start &1 16243 end &3 7017221 end &381 16244 17222 sat 32 16245 17223 eat 32 … … 16263 17241 ) 16264 17242 ) 16265 on &1 7316266 ) 16267 *5 44(Wire17243 on &180 17244 ) 17245 *587 (Wire 16268 17246 uid 4226,0 16269 17247 shape (OrthoPolyLine … … 16280 17258 ] 16281 17259 ) 16282 start &17 216283 end &5 3817260 start &179 17261 end &581 16284 17262 sat 32 16285 17263 eat 32 … … 16303 17281 ) 16304 17282 ) 16305 on &17 016306 ) 16307 *5 45(Wire17283 on &177 17284 ) 17285 *588 (Wire 16308 17286 uid 4240,0 16309 17287 shape (OrthoPolyLine … … 16313 17291 lineColor "0,0,65535" 16314 17292 ) 16315 xt "91750, 19000,109000,44000"17293 xt "91750,44000,109000,52000" 16316 17294 pts [ 16317 17295 "91750,44000" 16318 17296 "109000,44000" 16319 "109000, 19000"16320 ] 16321 ) 16322 start &3 1416323 end &5 3917297 "109000,52000" 17298 ] 17299 ) 17300 start &325 17301 end &582 16324 17302 sat 32 16325 17303 eat 32 … … 16342 17320 ) 16343 17321 ) 16344 on &17 016345 ) 16346 *5 46(Wire17322 on &177 17323 ) 17324 *589 (Wire 16347 17325 uid 4272,0 16348 17326 shape (OrthoPolyLine … … 16357 17335 ] 16358 17336 ) 16359 start &1 7616360 end &2 4717337 start &183 17338 end &258 16361 17339 sat 32 16362 17340 eat 32 … … 16380 17358 ) 16381 17359 ) 16382 on &1 7516383 ) 16384 *5 47(Wire17360 on &182 17361 ) 17362 *590 (Wire 16385 17363 uid 4401,0 16386 17364 shape (OrthoPolyLine … … 16389 17367 vasetType 3 16390 17368 ) 16391 xt "1750, 53000,18250,53000"17369 xt "1750,49000,18250,53000" 16392 17370 pts [ 16393 17371 "18250,53000" 16394 "1750,53000" 17372 "7000,53000" 17373 "7000,49000" 17374 "1750,49000" 16395 17375 ] 16396 17376 ) 16397 17377 start &40 16398 end & 19517378 end &202 16399 17379 sat 32 16400 17380 eat 32 … … 16416 17396 ) 16417 17397 ) 16418 on &1 7716419 ) 16420 *5 48(Wire17398 on &184 17399 ) 17400 *591 (Wire 16421 17401 uid 4407,0 16422 17402 shape (OrthoPolyLine … … 16425 17405 vasetType 3 16426 17406 ) 16427 xt "1750, 52000,18250,52000"17407 xt "1750,48000,18250,52000" 16428 17408 pts [ 16429 17409 "18250,52000" 16430 "1750,52000" 17410 "8000,52000" 17411 "8000,48000" 17412 "1750,48000" 16431 17413 ] 16432 17414 ) 16433 17415 start &44 16434 end &20 117416 end &208 16435 17417 sat 32 16436 17418 eat 32 … … 16452 17434 ) 16453 17435 ) 16454 on &1 7816455 ) 16456 *5 49(Wire17436 on &185 17437 ) 17438 *592 (Wire 16457 17439 uid 4419,0 16458 17440 shape (OrthoPolyLine … … 16461 17443 vasetType 3 16462 17444 ) 16463 xt "1750, 50000,18250,50000"17445 xt "1750,46000,18250,50000" 16464 17446 pts [ 16465 17447 "18250,50000" 16466 "1750,50000" 17448 "10000,50000" 17449 "10000,46000" 17450 "1750,46000" 16467 17451 ] 16468 17452 ) 16469 17453 start &42 16470 end & 19617454 end &203 16471 17455 sat 32 16472 17456 eat 32 … … 16488 17472 ) 16489 17473 ) 16490 on &1 7916491 ) 16492 *5 50(Wire17474 on &186 17475 ) 17476 *593 (Wire 16493 17477 uid 4537,0 16494 17478 shape (OrthoPolyLine … … 16504 17488 ] 16505 17489 ) 16506 start &3 2616507 end &18 217490 start &337 17491 end &189 16508 17492 sat 32 16509 17493 eat 32 … … 16528 17512 ) 16529 17513 ) 16530 on &18 016531 ) 16532 *5 51(Wire17514 on &187 17515 ) 17516 *594 (Wire 16533 17517 uid 4545,0 16534 17518 shape (OrthoPolyLine … … 16543 17527 ] 16544 17528 ) 16545 start & 29116546 end &1 8317529 start &302 17530 end &190 16547 17531 sat 32 16548 17532 eat 32 … … 16565 17549 ) 16566 17550 ) 16567 on &18 116568 ) 16569 *5 52(Wire17551 on &188 17552 ) 17553 *595 (Wire 16570 17554 uid 4671,0 16571 17555 shape (OrthoPolyLine … … 16580 17564 ] 16581 17565 ) 16582 start &1 8816583 end & 19717566 start &195 17567 end &204 16584 17568 sat 32 16585 17569 eat 32 … … 16603 17587 ) 16604 17588 ) 16605 on &1 8416606 ) 16607 *5 53(Wire17589 on &191 17590 ) 17591 *596 (Wire 16608 17592 uid 4679,0 16609 17593 shape (OrthoPolyLine … … 16618 17602 ] 16619 17603 ) 16620 start &1 8916621 end & 19817604 start &196 17605 end &205 16622 17606 sat 32 16623 17607 eat 32 … … 16641 17625 ) 16642 17626 ) 16643 on &1 8516644 ) 16645 *5 54(Wire17627 on &192 17628 ) 17629 *597 (Wire 16646 17630 uid 4687,0 16647 17631 shape (OrthoPolyLine … … 16656 17640 ] 16657 17641 ) 16658 start &19 016659 end & 19917642 start &197 17643 end &206 16660 17644 sat 32 16661 17645 eat 32 … … 16679 17663 ) 16680 17664 ) 16681 on &1 8616682 ) 16683 *5 55(Wire17665 on &193 17666 ) 17667 *598 (Wire 16684 17668 uid 4695,0 16685 17669 shape (OrthoPolyLine … … 16694 17678 ] 16695 17679 ) 16696 start &19 116697 end &20 017680 start &198 17681 end &207 16698 17682 sat 32 16699 17683 eat 32 … … 16717 17701 ) 16718 17702 ) 16719 on &1 8716720 ) 16721 *5 56(Wire17703 on &194 17704 ) 17705 *599 (Wire 16722 17706 uid 4743,0 16723 17707 shape (OrthoPolyLine … … 16726 17710 vasetType 3 16727 17711 ) 16728 xt "1750,51000,18250,51000" 16729 pts [ 16730 "1750,51000" 17712 xt "1750,47000,18250,51000" 17713 pts [ 17714 "1750,47000" 17715 "9000,47000" 17716 "9000,51000" 16731 17717 "18250,51000" 16732 17718 ] 16733 17719 ) 16734 start &20 217720 start &209 16735 17721 end &43 16736 17722 sat 32 … … 16753 17739 ) 16754 17740 ) 16755 on &19 216756 ) 16757 * 557(Wire17741 on &199 17742 ) 17743 *600 (Wire 16758 17744 uid 4757,0 16759 17745 optionalChildren [ 16760 * 558(BdJunction17746 *601 (BdJunction 16761 17747 uid 6076,0 16762 17748 ps "OnConnectorStrategy" … … 16785 17771 ] 16786 17772 ) 16787 start & 19416788 end * 559(BdJunction17773 start &201 17774 end *602 (BdJunction 16789 17775 uid 6080,0 16790 17776 ps "OnConnectorStrategy" … … 16818 17804 ) 16819 17805 ) 16820 on &17 116821 ) 16822 * 560(Wire17806 on &178 17807 ) 17808 *603 (Wire 16823 17809 uid 4948,0 16824 17810 shape (OrthoPolyLine … … 16833 17819 ] 16834 17820 ) 16835 start &2 0316836 end &2 0917821 start &210 17822 end &221 16837 17823 sat 32 16838 17824 eat 32 … … 16856 17842 ) 16857 17843 ) 16858 on &2 0816859 ) 16860 * 561(Wire17844 on &220 17845 ) 17846 *604 (Wire 16861 17847 uid 4962,0 16862 17848 shape (OrthoPolyLine … … 16871 17857 ] 16872 17858 ) 16873 start &4 8516874 end &2 1117859 start &496 17860 end &223 16875 17861 sat 32 16876 17862 eat 32 … … 16894 17880 ) 16895 17881 ) 16896 on &2 1016897 ) 16898 * 562(Wire17882 on &222 17883 ) 17884 *605 (Wire 16899 17885 uid 5090,0 16900 17886 shape (OrthoPolyLine … … 16904 17890 lineWidth 2 16905 17891 ) 16906 xt "92750,79000,12 6250,100000"16907 pts [ 16908 "12 6250,79000"16909 "1 16000,79000"16910 "1 16000,100000"17892 xt "92750,79000,127250,100000" 17893 pts [ 17894 "127250,79000" 17895 "120000,79000" 17896 "120000,100000" 16911 17897 "92750,100000" 16912 17898 ] 16913 17899 ) 16914 start & 8816915 end &2 1417900 start &92 17901 end &226 16916 17902 sat 32 16917 17903 eat 32 … … 16927 17913 va (VaSet 16928 17914 ) 16929 xt "1 19000,78000,126000,79000"17915 xt "120000,78000,127000,79000" 16930 17916 st "config_addr : (7:0)" 16931 blo "1 19000,78800"17917 blo "120000,78800" 16932 17918 tm "WireNameMgr" 16933 17919 ) 16934 17920 ) 16935 on &2 3016936 ) 16937 * 563(Wire17921 on &242 17922 ) 17923 *606 (Wire 16938 17924 uid 5098,0 16939 17925 shape (OrthoPolyLine … … 16948 17934 ] 16949 17935 ) 16950 start &2 1517936 start &227 16951 17937 sat 32 16952 17938 eat 16 … … 16967 17953 ) 16968 17954 ) 16969 on &2 3116970 ) 16971 * 564(Wire17955 on &243 17956 ) 17957 *607 (Wire 16972 17958 uid 5106,0 16973 17959 shape (OrthoPolyLine … … 16976 17962 vasetType 3 16977 17963 ) 16978 xt "92750,84000,12 6250,106000"17964 xt "92750,84000,127250,106000" 16979 17965 pts [ 16980 17966 "92750,106000" 16981 "12 1000,106000"16982 "12 1000,84000"16983 "12 6250,84000"16984 ] 16985 ) 16986 start &2 1616987 end & 8917967 "124000,106000" 17968 "124000,84000" 17969 "127250,84000" 17970 ] 17971 ) 17972 start &228 17973 end &93 16988 17974 sat 32 16989 17975 eat 32 … … 17004 17990 ) 17005 17991 ) 17006 on &2 3217007 ) 17008 * 565(Wire17992 on &244 17993 ) 17994 *608 (Wire 17009 17995 uid 5114,0 17010 17996 shape (OrthoPolyLine … … 17014 18000 lineWidth 2 17015 18001 ) 17016 xt "92750,80000,12 6250,101000"18002 xt "92750,80000,127250,101000" 17017 18003 pts [ 17018 18004 "92750,101000" 17019 "1 17000,101000"17020 "1 17000,80000"17021 "12 6250,80000"17022 ] 17023 ) 17024 start &2 1717025 end &9 018005 "121000,101000" 18006 "121000,80000" 18007 "127250,80000" 18008 ] 18009 ) 18010 start &229 18011 end &94 17026 18012 sat 32 17027 18013 eat 32 … … 17043 18029 ) 17044 18030 ) 17045 on &2 3317046 ) 17047 * 566(Wire18031 on &245 18032 ) 18033 *609 (Wire 17048 18034 uid 5122,0 17049 18035 shape (OrthoPolyLine … … 17052 18038 vasetType 3 17053 18039 ) 17054 xt "92750,82000,12 6250,104000"17055 pts [ 17056 "12 6250,82000"17057 "1 19000,82000"17058 "1 19000,104000"18040 xt "92750,82000,127250,104000" 18041 pts [ 18042 "127250,82000" 18043 "122000,82000" 18044 "122000,104000" 17059 18045 "92750,104000" 17060 18046 ] 17061 18047 ) 17062 start &9 217063 end &2 1918048 start &96 18049 end &231 17064 18050 sat 32 17065 18051 eat 32 … … 17074 18060 va (VaSet 17075 18061 ) 17076 xt "12 1000,81000,126300,82000"18062 xt "122000,81000,127300,82000" 17077 18063 st "config_wr_en" 17078 blo "12 1000,81800"18064 blo "122000,81800" 17079 18065 tm "WireNameMgr" 17080 18066 ) 17081 18067 ) 17082 on &2 3417083 ) 17084 * 567(Wire18068 on &246 18069 ) 18070 *610 (Wire 17085 18071 uid 5130,0 17086 18072 shape (OrthoPolyLine … … 17089 18075 vasetType 3 17090 18076 ) 17091 xt "92750,83000,12 6250,105000"17092 pts [ 17093 "12 6250,83000"17094 "12 0000,83000"17095 "12 0000,105000"18077 xt "92750,83000,127250,105000" 18078 pts [ 18079 "127250,83000" 18080 "123000,83000" 18081 "123000,105000" 17096 18082 "92750,105000" 17097 18083 ] 17098 18084 ) 17099 start &9 417100 end &2 2118085 start &98 18086 end &233 17101 18087 sat 32 17102 18088 eat 32 … … 17111 18097 va (VaSet 17112 18098 ) 17113 xt "12 1000,82000,126200,83000"18099 xt "122000,82000,127200,83000" 17114 18100 st "config_rd_en" 17115 blo "12 1000,82800"18101 blo "122000,82800" 17116 18102 tm "WireNameMgr" 17117 18103 ) 17118 18104 ) 17119 on &2 3517120 ) 17121 * 568(Wire18105 on &247 18106 ) 18107 *611 (Wire 17122 18108 uid 5138,0 17123 18109 optionalChildren [ 17124 * 569(BdJunction18110 *612 (BdJunction 17125 18111 uid 5400,0 17126 18112 ps "OnConnectorStrategy" … … 17148 18134 ] 17149 18135 ) 17150 start &2 1818136 start &230 17151 18137 end &35 17152 18138 ss 0 … … 17170 18156 ) 17171 18157 ) 17172 on &1 5417173 ) 17174 * 570(Wire18158 on &161 18159 ) 18160 *613 (Wire 17175 18161 uid 5146,0 17176 18162 shape (OrthoPolyLine … … 17185 18171 ] 17186 18172 ) 17187 start &2 2017188 end &2 5818173 start &232 18174 end &269 17189 18175 es 0 17190 18176 sat 32 … … 17206 18192 ) 17207 18193 ) 17208 on &2 3617209 ) 17210 * 571(Wire18194 on &248 18195 ) 18196 *614 (Wire 17211 18197 uid 5168,0 17212 18198 shape (OrthoPolyLine … … 17221 18207 ] 17222 18208 ) 17223 start & 56917224 end &13 118209 start &612 18210 end &137 17225 18211 sat 32 17226 18212 eat 32 … … 17242 18228 ) 17243 18229 ) 17244 on &1 5417245 ) 17246 * 572(Wire18230 on &161 18231 ) 18232 *615 (Wire 17247 18233 uid 5184,0 17248 18234 shape (OrthoPolyLine … … 17259 18245 ] 17260 18246 ) 17261 start &2 2218247 start &234 17262 18248 end &47 17263 18249 sat 32 … … 17279 18265 ) 17280 18266 ) 17281 on &2 3717282 ) 17283 * 573(Wire18267 on &249 18268 ) 18269 *616 (Wire 17284 18270 uid 5190,0 17285 18271 shape (OrthoPolyLine … … 17296 18282 ] 17297 18283 ) 17298 start &2 2318284 start &235 17299 18285 end &46 17300 18286 sat 32 … … 17316 18302 ) 17317 18303 ) 17318 on &2 3817319 ) 17320 * 574(Wire18304 on &250 18305 ) 18306 *617 (Wire 17321 18307 uid 5222,0 17322 18308 shape (OrthoPolyLine … … 17326 18312 lineWidth 2 17327 18313 ) 17328 xt "14 8750,71000,153000,71000"17329 pts [ 17330 "14 8750,71000"17331 "15 3000,71000"17332 ] 17333 ) 17334 start & 8618314 xt "149750,71000,154000,71000" 18315 pts [ 18316 "149750,71000" 18317 "154000,71000" 18318 ] 18319 ) 18320 start &90 17335 18321 end &19 17336 18322 sat 32 … … 17350 18336 isHidden 1 17351 18337 ) 17352 xt "15 0750,70000,152150,71000"18338 xt "151750,70000,153150,71000" 17353 18339 st "led" 17354 blo "15 0750,70800"18340 blo "151750,70800" 17355 18341 tm "WireNameMgr" 17356 18342 ) 17357 18343 ) 17358 on &239 17359 ) 17360 *575 (Wire 17361 uid 5281,0 17362 shape (OrthoPolyLine 17363 uid 5282,0 17364 va (VaSet 17365 vasetType 3 17366 ) 17367 xt "40750,53000,126250,59000" 17368 pts [ 17369 "126250,59000" 17370 "73000,59000" 17371 "73000,53000" 17372 "40750,53000" 17373 ] 17374 ) 17375 start &87 17376 end &48 17377 sat 32 17378 eat 32 17379 st 0 17380 sf 1 17381 si 0 17382 tg (WTG 17383 uid 5283,0 17384 ps "ConnStartEndStrategy" 17385 stg "STSignalDisplayStrategy" 17386 f (Text 17387 uid 5284,0 17388 va (VaSet 17389 ) 17390 xt "121250,58000,124850,59000" 17391 st "s_trigger" 17392 blo "121250,58800" 17393 tm "WireNameMgr" 17394 ) 17395 ) 17396 on &240 17397 ) 17398 *576 (Wire 18344 on &251 18345 ) 18346 *618 (Wire 17399 18347 uid 5404,0 17400 18348 shape (OrthoPolyLine … … 17411 18359 ] 17412 18360 ) 17413 start &2 5917414 end & 5018361 start &270 18362 end &49 17415 18363 sat 32 17416 18364 eat 32 … … 17431 18379 ) 17432 18380 ) 17433 on &2 4317434 ) 17435 * 577(Wire18381 on &254 18382 ) 18383 *619 (Wire 17436 18384 uid 5474,0 17437 18385 shape (OrthoPolyLine … … 17448 18396 ] 17449 18397 ) 17450 start &2 6217451 end &5 218398 start &273 18399 end &51 17452 18400 sat 32 17453 18401 eat 32 … … 17468 18416 ) 17469 18417 ) 17470 on &2 4117471 ) 17472 * 578(Wire18418 on &252 18419 ) 18420 *620 (Wire 17473 18421 uid 5480,0 17474 18422 shape (OrthoPolyLine … … 17485 18433 ] 17486 18434 ) 17487 start &2 6117488 end &5 118435 start &272 18436 end &50 17489 18437 sat 32 17490 18438 eat 32 … … 17505 18453 ) 17506 18454 ) 17507 on &2 4217508 ) 17509 * 579(Wire18455 on &253 18456 ) 18457 *621 (Wire 17510 18458 uid 5582,0 17511 18459 shape (OrthoPolyLine … … 17521 18469 ] 17522 18470 ) 17523 end &2 1318471 end &225 17524 18472 sat 16 17525 18473 eat 32 … … 17540 18488 ) 17541 18489 ) 17542 on &17 017543 ) 17544 * 580(Wire18490 on &177 18491 ) 18492 *622 (Wire 17545 18493 uid 5602,0 17546 18494 optionalChildren [ 17547 & 55917548 * 581(BdJunction18495 &602 18496 *623 (BdJunction 17549 18497 uid 6086,0 17550 18498 ps "OnConnectorStrategy" … … 17576 18524 ) 17577 18525 start &23 17578 end &3 1018526 end &321 17579 18527 sat 32 17580 18528 eat 32 … … 17597 18545 ) 17598 18546 ) 17599 on &17 117600 ) 17601 * 582(Wire18547 on &178 18548 ) 18549 *624 (Wire 17602 18550 uid 5626,0 17603 18551 shape (OrthoPolyLine … … 17613 18561 ) 17614 18562 start &45 17615 end &2 4818563 end &259 17616 18564 sat 32 17617 18565 eat 32 … … 17633 18581 ) 17634 18582 ) 17635 on &2 4517636 ) 17637 * 583(Wire18583 on &256 18584 ) 18585 *625 (Wire 17638 18586 uid 5634,0 17639 18587 shape (OrthoPolyLine … … 17650 18598 ) 17651 18599 start &38 17652 end &2 4918600 end &260 17653 18601 sat 32 17654 18602 eat 32 … … 17671 18619 ) 17672 18620 ) 17673 on &2 4417674 ) 17675 * 584(Wire18621 on &255 18622 ) 18623 *626 (Wire 17676 18624 uid 5646,0 17677 18625 shape (OrthoPolyLine … … 17687 18635 ] 17688 18636 ) 17689 end &2 5118637 end &262 17690 18638 sat 16 17691 18639 eat 32 … … 17707 18655 ) 17708 18656 ) 17709 on &1 6817710 ) 17711 * 585(Wire18657 on &175 18658 ) 18659 *627 (Wire 17712 18660 uid 5745,0 17713 18661 shape (OrthoPolyLine … … 17724 18672 ] 17725 18673 ) 17726 start &5 417727 end &2 6018674 start &53 18675 end &271 17728 18676 sat 32 17729 18677 eat 32 … … 17745 18693 ) 17746 18694 ) 17747 on &2 5517748 ) 17749 * 586(Wire18695 on &266 18696 ) 18697 *628 (Wire 17750 18698 uid 5805,0 17751 18699 shape (OrthoPolyLine … … 17760 18708 ] 17761 18709 ) 17762 end &2 6518710 end &276 17763 18711 sat 16 17764 18712 eat 32 … … 17779 18727 ) 17780 18728 ) 17781 on &17 017782 ) 17783 * 587(Wire18729 on &177 18730 ) 18731 *629 (Wire 17784 18732 uid 5813,0 17785 18733 shape (OrthoPolyLine … … 17794 18742 ] 17795 18743 ) 17796 start &3 4617797 end &2 7618744 start &357 18745 end &287 17798 18746 sat 32 17799 18747 eat 32 … … 17817 18765 ) 17818 18766 ) 17819 on &2 7217820 ) 17821 * 588(Wire18767 on &283 18768 ) 18769 *630 (Wire 17822 18770 uid 5821,0 17823 18771 shape (OrthoPolyLine … … 17832 18780 ] 17833 18781 ) 17834 start &2 6817835 end &2 7718782 start &279 18783 end &288 17836 18784 sat 32 17837 18785 eat 32 … … 17855 18803 ) 17856 18804 ) 17857 on &2 7317858 ) 17859 * 589(Wire18805 on &284 18806 ) 18807 *631 (Wire 17860 18808 uid 5829,0 17861 18809 shape (OrthoPolyLine … … 17870 18818 ] 17871 18819 ) 17872 start &2 6317873 end &2 7818820 start &274 18821 end &289 17874 18822 sat 32 17875 18823 eat 32 … … 17893 18841 ) 17894 18842 ) 17895 on &2 7417896 ) 17897 * 590(Wire18843 on &285 18844 ) 18845 *632 (Wire 17898 18846 uid 5837,0 17899 18847 shape (OrthoPolyLine … … 17909 18857 ] 17910 18858 ) 17911 start &2 6417912 end &2 7918859 start &275 18860 end &290 17913 18861 sat 32 17914 18862 eat 32 … … 17933 18881 ) 17934 18882 ) 17935 on &2 7517936 ) 17937 * 591(Wire18883 on &286 18884 ) 18885 *633 (Wire 17938 18886 uid 5950,0 17939 18887 shape (OrthoPolyLine … … 17942 18890 vasetType 3 17943 18891 ) 17944 xt "40750,54000,12 6250,60000"17945 pts [ 17946 "12 6250,60000"17947 " 72000,60000"17948 " 72000,54000"18892 xt "40750,54000,127250,60000" 18893 pts [ 18894 "127250,60000" 18895 "110000,60000" 18896 "110000,54000" 17949 18897 "40750,54000" 17950 18898 ] 17951 18899 ) 17952 start &9 317953 end &5 618900 start &97 18901 end &55 17954 18902 sat 32 17955 18903 eat 32 … … 17965 18913 va (VaSet 17966 18914 ) 17967 xt "12 0250,59000,124850,60000"18915 xt "121250,59000,125850,60000" 17968 18916 st "new_config" 17969 blo "12 0250,59800"18917 blo "121250,59800" 17970 18918 tm "WireNameMgr" 17971 18919 ) 17972 18920 ) 17973 on &2 8017974 ) 17975 * 592(Wire18921 on &291 18922 ) 18923 *634 (Wire 17976 18924 uid 5962,0 17977 18925 shape (OrthoPolyLine … … 17980 18928 vasetType 3 17981 18929 ) 17982 xt "40750,55000,12 6250,61000"17983 pts [ 17984 "12 6250,61000"17985 " 71000,61000"17986 " 71000,55000"18930 xt "40750,55000,127250,61000" 18931 pts [ 18932 "127250,61000" 18933 "111000,61000" 18934 "111000,55000" 17987 18935 "40750,55000" 17988 18936 ] 17989 18937 ) 17990 start &9 117991 end &5 518938 start &95 18939 end &54 17992 18940 sat 32 17993 18941 eat 32 … … 18003 18951 va (VaSet 18004 18952 ) 18005 xt "1 19250,60000,124850,61000"18953 xt "120250,60000,125850,61000" 18006 18954 st "config_started" 18007 blo "1 19250,60800"18955 blo "120250,60800" 18008 18956 tm "WireNameMgr" 18009 18957 ) 18010 18958 ) 18011 on &2 8118012 ) 18013 * 593(Wire18959 on &292 18960 ) 18961 *635 (Wire 18014 18962 uid 6002,0 18015 18963 shape (OrthoPolyLine … … 18026 18974 ] 18027 18975 ) 18028 start &2 2418029 end &5 718976 start &236 18977 end &56 18030 18978 sat 32 18031 18979 eat 32 … … 18047 18995 ) 18048 18996 ) 18049 on &2 8318050 ) 18051 * 594(Wire18997 on &294 18998 ) 18999 *636 (Wire 18052 19000 uid 6008,0 18053 19001 shape (OrthoPolyLine … … 18064 19012 ] 18065 19013 ) 18066 start &2 6618067 end &5 919014 start &277 19015 end &58 18068 19016 sat 32 18069 19017 eat 32 … … 18085 19033 ) 18086 19034 ) 18087 on &2 8218088 ) 18089 * 595(Wire19035 on &293 19036 ) 19037 *637 (Wire 18090 19038 uid 6018,0 18091 19039 shape (OrthoPolyLine … … 18097 19045 pts [ 18098 19046 "40750,71000" 18099 "6 3000,71000"18100 "6 3000,76000"19047 "62000,71000" 19048 "62000,76000" 18101 19049 "71250,76000" 18102 19050 ] 18103 19051 ) 18104 start &5 818105 end &13 319052 start &57 19053 end &139 18106 19054 sat 32 18107 19055 eat 32 … … 18123 19071 ) 18124 19072 ) 18125 on &2 8418126 ) 18127 * 596(Wire19073 on &295 19074 ) 19075 *638 (Wire 18128 19076 uid 6064,0 18129 19077 shape (OrthoPolyLine … … 18138 19086 ] 18139 19087 ) 18140 end & 6019088 end &59 18141 19089 sat 16 18142 19090 eat 32 … … 18158 19106 ) 18159 19107 ) 18160 on &2 3618161 ) 18162 * 597(Wire19108 on &248 19109 ) 19110 *639 (Wire 18163 19111 uid 6072,0 18164 19112 optionalChildren [ 18165 * 598(BdJunction19113 *640 (BdJunction 18166 19114 uid 9745,0 18167 19115 ps "OnConnectorStrategy" … … 18189 19137 ] 18190 19138 ) 18191 start &3 6918192 end & 55819139 start &380 19140 end &601 18193 19141 sat 32 18194 19142 eat 32 … … 18211 19159 ) 18212 19160 ) 18213 on &17 118214 ) 18215 * 599(Wire19161 on &178 19162 ) 19163 *641 (Wire 18216 19164 uid 6082,0 18217 19165 shape (OrthoPolyLine … … 18228 19176 ] 18229 19177 ) 18230 start &1 1818231 end & 58119178 start &124 19179 end &623 18232 19180 sat 32 18233 19181 eat 32 … … 18250 19198 ) 18251 19199 ) 18252 on &17 118253 ) 18254 *6 00(Wire19200 on &178 19201 ) 19202 *642 (Wire 18255 19203 uid 6160,0 18256 19204 shape (OrthoPolyLine … … 18265 19213 ] 18266 19214 ) 18267 start &2 6718268 end &2 8619215 start &278 19216 end &297 18269 19217 sat 32 18270 19218 eat 32 … … 18288 19236 ) 18289 19237 ) 18290 on &2 8518291 ) 18292 *6 01(Wire19238 on &296 19239 ) 19240 *643 (Wire 18293 19241 uid 6276,0 18294 19242 shape (OrthoPolyLine … … 18303 19251 ] 18304 19252 ) 18305 end &11 019253 end &116 18306 19254 sat 16 18307 19255 eat 32 … … 18322 19270 ) 18323 19271 ) 18324 on &1 6818325 ) 18326 *6 02(Wire19272 on &175 19273 ) 19274 *644 (Wire 18327 19275 uid 6362,0 18328 19276 shape (OrthoPolyLine … … 18331 19279 vasetType 3 18332 19280 ) 18333 xt "14 8750,75000,153000,75000"18334 pts [ 18335 "14 8750,75000"18336 "15 3000,75000"18337 ] 18338 ) 18339 start &9 518340 end &2 8819281 xt "149750,75000,154000,75000" 19282 pts [ 19283 "149750,75000" 19284 "154000,75000" 19285 ] 19286 ) 19287 start &99 19288 end &299 18341 19289 sat 32 18342 19290 eat 32 … … 18354 19302 isHidden 1 18355 19303 ) 18356 xt "15 0000,74000,153000,75000"19304 xt "151000,74000,154000,75000" 18357 19305 st "denable" 18358 blo "15 0000,74800"19306 blo "151000,74800" 18359 19307 tm "WireNameMgr" 18360 19308 ) 18361 19309 ) 18362 on &2 8718363 ) 18364 *6 03(Wire19310 on &298 19311 ) 19312 *645 (Wire 18365 19313 uid 6452,0 18366 19314 shape (OrthoPolyLine … … 18369 19317 vasetType 3 18370 19318 ) 18371 xt "14 8750,76000,154000,76000"18372 pts [ 18373 "14 8750,76000"18374 "15 4000,76000"18375 ] 18376 ) 18377 start & 9619319 xt "149750,76000,155000,76000" 19320 pts [ 19321 "149750,76000" 19322 "155000,76000" 19323 ] 19324 ) 19325 start &100 18378 19326 sat 32 18379 19327 eat 16 … … 18390 19338 va (VaSet 18391 19339 ) 18392 xt "15 5000,76000,160400,77000"19340 xt "156000,76000,161400,77000" 18393 19341 st "dwrite_enable" 18394 blo "15 5000,76800"19342 blo "156000,76800" 18395 19343 tm "WireNameMgr" 18396 19344 ) 18397 19345 ) 18398 on & 28918399 ) 18400 *6 04(Wire19346 on &300 19347 ) 19348 *646 (Wire 18401 19349 uid 6540,0 18402 19350 shape (OrthoPolyLine … … 18411 19359 ] 18412 19360 ) 18413 start & 29419361 start &305 18414 19362 end &41 18415 19363 sat 32 … … 18433 19381 ) 18434 19382 ) 18435 on &3 0818436 ) 18437 *6 05(Wire19383 on &319 19384 ) 19385 *647 (Wire 18438 19386 uid 6548,0 18439 19387 shape (OrthoPolyLine … … 18444 19392 xt "7000,61000,15000,61000" 18445 19393 pts [ 19394 "15000,61000" 18446 19395 "7000,61000" 18447 "15000,61000" 18448 ] 18449 ) 18450 start &296 18451 sat 32 18452 eat 16 19396 ] 19397 ) 19398 end &307 19399 ss 0 19400 es 0 19401 sat 16 19402 eat 32 18453 19403 stc 0 18454 19404 st 0 … … 18463 19413 va (VaSet 18464 19414 ) 18465 xt " 7000,60000,12400,61000"19415 xt "15000,60000,20400,61000" 18466 19416 st "dwrite_enable" 18467 blo " 7000,60800"19417 blo "15000,60800" 18468 19418 tm "WireNameMgr" 18469 19419 ) 18470 19420 ) 18471 on & 28918472 ) 18473 *6 06(Wire19421 on &300 19422 ) 19423 *648 (Wire 18474 19424 uid 8416,0 18475 19425 shape (OrthoPolyLine … … 18478 19428 vasetType 3 18479 19429 ) 18480 xt "103750,75000,12 6250,75000"19430 xt "103750,75000,127250,75000" 18481 19431 pts [ 18482 19432 "103750,75000" 18483 "12 6250,75000"18484 ] 18485 ) 18486 start &1 3418487 end & 9719433 "127250,75000" 19434 ] 19435 ) 19436 start &140 19437 end &101 18488 19438 sat 32 18489 19439 eat 32 … … 18505 19455 ) 18506 19456 ) 18507 on &320 18508 ) 18509 *607 (Wire 18510 uid 8510,0 18511 shape (OrthoPolyLine 18512 uid 8511,0 18513 va (VaSet 18514 vasetType 3 18515 lineWidth 2 18516 ) 18517 xt "92750,110000,102000,110000" 18518 pts [ 18519 "92750,110000" 18520 "102000,110000" 18521 ] 18522 ) 18523 start &225 18524 sat 32 18525 eat 16 18526 sty 1 18527 st 0 18528 sf 1 18529 si 0 18530 tg (WTG 18531 uid 8514,0 18532 ps "ConnStartEndStrategy" 18533 stg "STSignalDisplayStrategy" 18534 f (Text 18535 uid 8515,0 18536 va (VaSet 18537 ) 18538 xt "94000,109000,101200,110000" 18539 st "drs_address : (3:0)" 18540 blo "94000,109800" 18541 tm "WireNameMgr" 18542 ) 18543 ) 18544 on &321 18545 ) 18546 *608 (Wire 18547 uid 8518,0 18548 shape (OrthoPolyLine 18549 uid 8519,0 18550 va (VaSet 18551 vasetType 3 18552 ) 18553 xt "92750,111000,102000,111000" 18554 pts [ 18555 "92750,111000" 18556 "102000,111000" 18557 ] 18558 ) 18559 start &226 18560 sat 32 18561 eat 16 18562 st 0 18563 sf 1 18564 si 0 18565 tg (WTG 18566 uid 8522,0 18567 ps "ConnStartEndStrategy" 18568 stg "STSignalDisplayStrategy" 18569 f (Text 18570 uid 8523,0 18571 va (VaSet 18572 ) 18573 xt "94000,110000,101200,111000" 18574 st "drs_address_mode" 18575 blo "94000,110800" 18576 tm "WireNameMgr" 18577 ) 18578 ) 18579 on &322 18580 ) 18581 *609 (Wire 19457 on &331 19458 ) 19459 *649 (Wire 18582 19460 uid 8577,0 18583 19461 shape (OrthoPolyLine … … 18587 19465 lineWidth 2 18588 19466 ) 18589 xt "7000,57000,18250,57000" 18590 pts [ 18591 "18250,57000" 18592 "7000,57000" 19467 xt "13000,64000,18250,64000" 19468 pts [ 19469 "18250,64000" 19470 "13000,64000" 19471 "13000,64000" 18593 19472 ] 18594 19473 ) … … 18608 19487 va (VaSet 18609 19488 ) 18610 xt "8000, 56000,18400,57000"19489 xt "8000,62000,18400,63000" 18611 19490 st "drs_channel_internal : (3:0)" 18612 blo "8000, 56800"19491 blo "8000,62800" 18613 19492 tm "WireNameMgr" 18614 19493 ) 18615 19494 ) 18616 on &3 4418617 ) 18618 *6 10 (Wire19495 on &355 19496 ) 19497 *650 (Wire 18619 19498 uid 8587,0 18620 19499 shape (OrthoPolyLine … … 18630 19509 ] 18631 19510 ) 18632 end &3 2419511 end &335 18633 19512 sat 16 18634 19513 eat 32 … … 18652 19531 ) 18653 19532 ) 18654 on &3 4418655 ) 18656 *6 11 (Wire19533 on &355 19534 ) 19535 *651 (Wire 18657 19536 uid 8595,0 18658 19537 shape (OrthoPolyLine … … 18668 19547 ] 18669 19548 ) 18670 end &3 2919549 end &340 18671 19550 sat 16 18672 19551 eat 32 … … 18690 19569 ) 18691 19570 ) 18692 on &3 2118693 ) 18694 *6 12 (Wire19571 on &332 19572 ) 19573 *652 (Wire 18695 19574 uid 8603,0 18696 19575 shape (OrthoPolyLine … … 18706 19585 ] 18707 19586 ) 18708 end &3 3119587 end &342 18709 19588 sat 16 18710 19589 eat 32 … … 18727 19606 ) 18728 19607 ) 18729 on &3 2218730 ) 18731 *6 13 (Wire19608 on &333 19609 ) 19610 *653 (Wire 18732 19611 uid 8732,0 18733 19612 shape (OrthoPolyLine … … 18744 19623 ] 18745 19624 ) 18746 start &2 5718747 end &3 5119625 start &268 19626 end &362 18748 19627 sat 32 18749 19628 eat 32 … … 18765 19644 ) 18766 19645 ) 18767 on &3 6318768 ) 18769 *6 14 (Wire19646 on &374 19647 ) 19648 *654 (Wire 18770 19649 uid 8738,0 18771 19650 shape (OrthoPolyLine … … 18780 19659 ] 18781 19660 ) 18782 end &3 4919661 end &360 18783 19662 sat 16 18784 19663 eat 32 … … 18801 19680 ) 18802 19681 ) 18803 on &3 6418804 ) 18805 *6 15 (Wire19682 on &375 19683 ) 19684 *655 (Wire 18806 19685 uid 8752,0 18807 19686 shape (OrthoPolyLine … … 18810 19689 vasetType 3 18811 19690 ) 18812 xt "14 8750,77000,154000,77000"18813 pts [ 18814 "14 8750,77000"18815 "15 4000,77000"18816 ] 18817 ) 18818 start & 9819691 xt "149750,77000,155000,77000" 19692 pts [ 19693 "149750,77000" 19694 "155000,77000" 19695 ] 19696 ) 19697 start &102 18819 19698 sat 32 18820 19699 eat 16 … … 18830 19709 va (VaSet 18831 19710 ) 18832 xt "15 5000,77000,159700,78000"19711 xt "156000,77000,160700,78000" 18833 19712 st "sclk_enable" 18834 blo "15 5000,77800"19713 blo "156000,77800" 18835 19714 tm "WireNameMgr" 18836 19715 ) 18837 19716 ) 18838 on &3 6418839 ) 18840 *6 16 (Wire19717 on &375 19718 ) 19719 *656 (Wire 18841 19720 uid 9006,0 18842 19721 shape (OrthoPolyLine … … 18851 19730 ] 18852 19731 ) 18853 start &6 118854 end &3 6619732 start &60 19733 end &377 18855 19734 sat 32 18856 19735 eat 32 … … 18874 19753 ) 18875 19754 ) 18876 on &3 6518877 ) 18878 *6 17 (Wire19755 on &376 19756 ) 19757 *657 (Wire 18879 19758 uid 9233,0 18880 19759 shape (OrthoPolyLine … … 18883 19762 vasetType 3 18884 19763 ) 18885 xt "14 8750,81000,154000,81000"18886 pts [ 18887 "14 8750,81000"18888 "15 4000,81000"18889 ] 18890 ) 18891 start & 9919764 xt "149750,81000,155000,81000" 19765 pts [ 19766 "149750,81000" 19767 "155000,81000" 19768 ] 19769 ) 19770 start &103 18892 19771 sat 32 18893 19772 eat 16 … … 18903 19782 va (VaSet 18904 19783 ) 18905 xt "15 5000,81000,159900,82000"19784 xt "156000,81000,160900,82000" 18906 19785 st "ps_direction" 18907 blo "15 5000,81800"19786 blo "156000,81800" 18908 19787 tm "WireNameMgr" 18909 19788 ) 18910 19789 ) 18911 on &3 8718912 ) 18913 *6 18 (Wire19790 on &398 19791 ) 19792 *658 (Wire 18914 19793 uid 9241,0 18915 19794 shape (OrthoPolyLine … … 18918 19797 vasetType 3 18919 19798 ) 18920 xt "14 8750,82000,154000,82000"18921 pts [ 18922 "14 8750,82000"18923 "15 4000,82000"18924 ] 18925 ) 18926 start &10 019799 xt "149750,82000,155000,82000" 19800 pts [ 19801 "149750,82000" 19802 "155000,82000" 19803 ] 19804 ) 19805 start &104 18927 19806 sat 32 18928 19807 eat 16 … … 18938 19817 va (VaSet 18939 19818 ) 18940 xt "15 5000,82000,162000,83000"19819 xt "156000,82000,163000,83000" 18941 19820 st "ps_do_phase_shift" 18942 blo "15 5000,82800"19821 blo "156000,82800" 18943 19822 tm "WireNameMgr" 18944 19823 ) 18945 19824 ) 18946 on &3 8818947 ) 18948 *6 19 (Wire19825 on &399 19826 ) 19827 *659 (Wire 18949 19828 uid 9253,0 18950 19829 optionalChildren [ 18951 *6 20 (BdJunction19830 *660 (BdJunction 18952 19831 uid 9507,0 18953 19832 ps "OnConnectorStrategy" … … 18973 19852 ] 18974 19853 ) 18975 end &3 8119854 end &392 18976 19855 sat 16 18977 19856 eat 32 … … 18992 19871 ) 18993 19872 ) 18994 on &3 8718995 ) 18996 *6 21 (Wire19873 on &398 19874 ) 19875 *661 (Wire 18997 19876 uid 9261,0 18998 19877 optionalChildren [ 18999 *6 22 (BdJunction19878 *662 (BdJunction 19000 19879 uid 9513,0 19001 19880 ps "OnConnectorStrategy" … … 19021 19900 ] 19022 19901 ) 19023 end &3 8219902 end &393 19024 19903 sat 16 19025 19904 eat 32 … … 19040 19919 ) 19041 19920 ) 19042 on &3 8819043 ) 19044 *6 23 (Wire19921 on &399 19922 ) 19923 *663 (Wire 19045 19924 uid 9269,0 19046 19925 shape (OrthoPolyLine … … 19055 19934 ] 19056 19935 ) 19057 start &3 7919058 end & 39019936 start &390 19937 end &401 19059 19938 sat 32 19060 19939 eat 32 … … 19078 19957 ) 19079 19958 ) 19080 on & 38919081 ) 19082 *6 24 (Wire19959 on &400 19960 ) 19961 *664 (Wire 19083 19962 uid 9283,0 19084 19963 shape (OrthoPolyLine … … 19093 19972 ] 19094 19973 ) 19095 start &3 7819096 end & 39219974 start &389 19975 end &403 19097 19976 sat 32 19098 19977 eat 32 … … 19116 19995 ) 19117 19996 ) 19118 on & 39119119 ) 19120 *6 25 (Wire19997 on &402 19998 ) 19999 *665 (Wire 19121 20000 uid 9297,0 19122 20001 shape (OrthoPolyLine … … 19131 20010 ] 19132 20011 ) 19133 start &3 7719134 end & 39420012 start &388 20013 end &405 19135 20014 sat 32 19136 20015 eat 32 … … 19154 20033 ) 19155 20034 ) 19156 on & 39319157 ) 19158 *6 26 (Wire20035 on &404 20036 ) 20037 *666 (Wire 19159 20038 uid 9311,0 19160 20039 shape (OrthoPolyLine … … 19169 20048 ] 19170 20049 ) 19171 start &3 7619172 end & 39620050 start &387 20051 end &407 19173 20052 sat 32 19174 20053 eat 32 … … 19192 20071 ) 19193 20072 ) 19194 on & 39519195 ) 19196 *6 27 (Wire20073 on &406 20074 ) 20075 *667 (Wire 19197 20076 uid 9325,0 19198 20077 shape (OrthoPolyLine … … 19207 20086 ] 19208 20087 ) 19209 start &3 7519210 end & 39820088 start &386 20089 end &409 19211 20090 sat 32 19212 20091 eat 32 … … 19230 20109 ) 19231 20110 ) 19232 on & 39719233 ) 19234 *6 28 (Wire20111 on &408 20112 ) 20113 *668 (Wire 19235 20114 uid 9353,0 19236 20115 shape (OrthoPolyLine … … 19245 20124 ] 19246 20125 ) 19247 start &3 7419248 end &4 0020126 start &385 20127 end &411 19249 20128 sat 32 19250 20129 eat 32 … … 19268 20147 ) 19269 20148 ) 19270 on & 39919271 ) 19272 *6 29 (Wire20149 on &410 20150 ) 20151 *669 (Wire 19273 20152 uid 9367,0 19274 20153 shape (OrthoPolyLine … … 19284 20163 ] 19285 20164 ) 19286 start &3 7319287 end &4 0220165 start &384 20166 end &413 19288 20167 sat 32 19289 20168 eat 32 … … 19308 20187 ) 19309 20188 ) 19310 on &4 0119311 ) 19312 *6 30 (Wire20189 on &412 20190 ) 20191 *670 (Wire 19313 20192 uid 9382,0 19314 20193 shape (OrthoPolyLine … … 19323 20202 ] 19324 20203 ) 19325 start &3 7219326 end &4 0420204 start &383 20205 end &415 19327 20206 sat 32 19328 20207 eat 32 … … 19346 20225 ) 19347 20226 ) 19348 on &4 0319349 ) 19350 *6 31 (Wire20227 on &414 20228 ) 20229 *671 (Wire 19351 20230 uid 9397,0 19352 20231 shape (OrthoPolyLine … … 19361 20240 ] 19362 20241 ) 19363 start &3 7119364 end &4 0620242 start &382 20243 end &417 19365 20244 sat 32 19366 20245 eat 32 … … 19384 20263 ) 19385 20264 ) 19386 on &4 0519387 ) 19388 *6 32 (Wire20265 on &416 20266 ) 20267 *672 (Wire 19389 20268 uid 9503,0 19390 20269 shape (OrthoPolyLine … … 19400 20279 ] 19401 20280 ) 19402 start &6 2019403 end &4 2120281 start &660 20282 end &432 19404 20283 sat 32 19405 20284 eat 32 … … 19422 20301 ) 19423 20302 ) 19424 on &3 8719425 ) 19426 *6 33 (Wire20303 on &398 20304 ) 20305 *673 (Wire 19427 20306 uid 9509,0 19428 20307 shape (OrthoPolyLine … … 19438 20317 ] 19439 20318 ) 19440 start &6 2219441 end &4 0820319 start &662 20320 end &419 19442 20321 sat 32 19443 20322 eat 32 … … 19460 20339 ) 19461 20340 ) 19462 on &3 8819463 ) 19464 *6 34 (Wire20341 on &399 20342 ) 20343 *674 (Wire 19465 20344 uid 9517,0 19466 20345 shape (OrthoPolyLine … … 19477 20356 ] 19478 20357 ) 19479 start &4 1019480 end &4 3320358 start &421 20359 end &444 19481 20360 sat 32 19482 20361 eat 32 … … 19500 20379 ) 19501 20380 ) 19502 on &4 3619503 ) 19504 *6 35 (Wire20381 on &447 20382 ) 20383 *675 (Wire 19505 20384 uid 9539,0 19506 20385 shape (OrthoPolyLine … … 19517 20396 ] 19518 20397 ) 19519 start &4 2319520 end &4 3420398 start &434 20399 end &445 19521 20400 sat 32 19522 20401 eat 32 … … 19540 20419 ) 19541 20420 ) 19542 on &4 3519543 ) 19544 *6 36 (Wire20421 on &446 20422 ) 20423 *676 (Wire 19545 20424 uid 9673,0 19546 20425 shape (OrthoPolyLine … … 19556 20435 ] 19557 20436 ) 19558 start &5 4019559 end &4 3820437 start &583 20438 end &449 19560 20439 sat 32 19561 20440 eat 32 … … 19578 20457 ) 19579 20458 ) 19580 on &17 019581 ) 19582 *6 37 (Wire20459 on &177 20460 ) 20461 *677 (Wire 19583 20462 uid 9741,0 19584 20463 shape (OrthoPolyLine … … 19595 20474 ] 19596 20475 ) 19597 start & 59819598 end &4 5120476 start &640 20477 end &462 19599 20478 sat 32 19600 20479 eat 32 … … 19617 20496 ) 19618 20497 ) 19619 on &17 119620 ) 19621 *6 38 (Wire20498 on &178 20499 ) 20500 *678 (Wire 19622 20501 uid 9747,0 19623 20502 shape (OrthoPolyLine … … 19634 20513 ] 19635 20514 ) 19636 start &5 4219637 end &4 6420515 start &585 20516 end &475 19638 20517 sat 32 19639 20518 eat 32 … … 19656 20535 ) 19657 20536 ) 19658 on &1 6819659 ) 19660 *6 39 (Wire20537 on &175 20538 ) 20539 *679 (Wire 19661 20540 uid 9755,0 19662 20541 shape (OrthoPolyLine … … 19671 20550 ] 19672 20551 ) 19673 start &4 4019674 end &4 7620552 start &451 20553 end &487 19675 20554 sat 32 19676 20555 eat 32 … … 19694 20573 ) 19695 20574 ) 19696 on &4 7719697 ) 19698 *6 40 (Wire20575 on &488 20576 ) 20577 *680 (Wire 19699 20578 uid 9771,0 19700 20579 shape (OrthoPolyLine … … 19709 20588 ] 19710 20589 ) 19711 start &4 5319712 end &4 7820590 start &464 20591 end &489 19713 20592 sat 32 19714 20593 eat 32 … … 19732 20611 ) 19733 20612 ) 19734 on &4 7919735 ) 19736 *6 41 (Wire20613 on &490 20614 ) 20615 *681 (Wire 19737 20616 uid 9787,0 19738 20617 shape (OrthoPolyLine … … 19747 20626 ] 19748 20627 ) 19749 start &4 6619750 end &4 8020628 start &477 20629 end &491 19751 20630 sat 32 19752 20631 eat 32 … … 19770 20649 ) 19771 20650 ) 19772 on &4 8119773 ) 19774 *6 42 (Wire20651 on &492 20652 ) 20653 *682 (Wire 19775 20654 uid 9943,0 19776 20655 shape (OrthoPolyLine … … 19779 20658 vasetType 3 19780 20659 ) 19781 xt "14 8750,83000,154000,83000"19782 pts [ 19783 "14 8750,83000"19784 "15 4000,83000"19785 ] 19786 ) 19787 start &10 120660 xt "149750,83000,155000,83000" 20661 pts [ 20662 "149750,83000" 20663 "155000,83000" 20664 ] 20665 ) 20666 start &105 19788 20667 sat 32 19789 20668 eat 16 … … 19799 20678 va (VaSet 19800 20679 ) 19801 xt "15 5000,83000,158300,84000"20680 xt "156000,83000,159300,84000" 19802 20681 st "ps_reset" 19803 blo "15 5000,83800"20682 blo "156000,83800" 19804 20683 tm "WireNameMgr" 19805 20684 ) 19806 20685 ) 19807 on &4 8219808 ) 19809 *6 43 (Wire20686 on &493 20687 ) 20688 *683 (Wire 19810 20689 uid 9951,0 19811 20690 shape (OrthoPolyLine … … 19814 20693 vasetType 3 19815 20694 ) 19816 xt "14 8750,85000,154000,85000"19817 pts [ 19818 "14 8750,85000"19819 "15 4000,85000"19820 ] 19821 ) 19822 start &10 220695 xt "149750,85000,155000,85000" 20696 pts [ 20697 "149750,85000" 20698 "155000,85000" 20699 ] 20700 ) 20701 start &106 19823 20702 sat 32 19824 20703 eat 16 … … 19834 20713 va (VaSet 19835 20714 ) 19836 xt "15 5000,85000,160000,86000"20715 xt "156000,85000,161000,86000" 19837 20716 st "srclk_enable" 19838 blo "15 5000,85800"20717 blo "156000,85800" 19839 20718 tm "WireNameMgr" 19840 20719 ) 19841 20720 ) 19842 on &4 8319843 ) 19844 *6 44 (Wire20721 on &494 20722 ) 20723 *684 (Wire 19845 20724 uid 10010,0 19846 20725 shape (OrthoPolyLine … … 19857 20736 ] 19858 20737 ) 19859 start &2 0419860 end &4 8820738 start &211 20739 end &499 19861 20740 sat 32 19862 20741 eat 32 … … 19878 20757 ) 19879 20758 ) 19880 on &5 0219881 ) 19882 *6 45 (Wire20759 on &513 20760 ) 20761 *685 (Wire 19883 20762 uid 10018,0 19884 20763 shape (OrthoPolyLine … … 19893 20772 ] 19894 20773 ) 19895 end & 49020774 end &501 19896 20775 sat 16 19897 20776 eat 32 … … 19914 20793 ) 19915 20794 ) 19916 on &4 8319917 ) 19918 *6 46 (Wire20795 on &494 20796 ) 20797 *686 (Wire 19919 20798 uid 10036,0 19920 20799 shape (OrthoPolyLine … … 19929 20808 ] 19930 20809 ) 19931 end &3 8320810 end &394 19932 20811 sat 16 19933 20812 eat 32 … … 19948 20827 ) 19949 20828 ) 19950 on &482 20829 on &493 20830 ) 20831 *687 (Wire 20832 uid 10194,0 20833 shape (OrthoPolyLine 20834 uid 10195,0 20835 va (VaSet 20836 vasetType 3 20837 ) 20838 xt "92750,85000,127250,110000" 20839 pts [ 20840 "92750,110000" 20841 "125000,110000" 20842 "125000,85000" 20843 "127250,85000" 20844 ] 20845 ) 20846 start &237 20847 end &107 20848 ss 0 20849 es 0 20850 sat 32 20851 eat 32 20852 st 0 20853 sf 1 20854 si 0 20855 tg (WTG 20856 uid 10198,0 20857 ps "ConnStartEndStrategy" 20858 stg "STSignalDisplayStrategy" 20859 f (Text 20860 uid 10199,0 20861 va (VaSet 20862 ) 20863 xt "94750,109000,100350,110000" 20864 st "config_rw_ack" 20865 blo "94750,109800" 20866 tm "WireNameMgr" 20867 ) 20868 ) 20869 on &514 20870 ) 20871 *688 (Wire 20872 uid 10202,0 20873 shape (OrthoPolyLine 20874 uid 10203,0 20875 va (VaSet 20876 vasetType 3 20877 ) 20878 xt "92750,86000,127250,111000" 20879 pts [ 20880 "92750,111000" 20881 "126000,111000" 20882 "126000,86000" 20883 "127250,86000" 20884 ] 20885 ) 20886 start &238 20887 end &108 20888 sat 32 20889 eat 32 20890 st 0 20891 sf 1 20892 si 0 20893 tg (WTG 20894 uid 10206,0 20895 ps "ConnStartEndStrategy" 20896 stg "STSignalDisplayStrategy" 20897 f (Text 20898 uid 10207,0 20899 va (VaSet 20900 ) 20901 xt "94750,110000,101050,111000" 20902 st "config_rw_ready" 20903 blo "94750,110800" 20904 tm "WireNameMgr" 20905 ) 20906 ) 20907 on &515 20908 ) 20909 *689 (Wire 20910 uid 10266,0 20911 shape (OrthoPolyLine 20912 uid 10267,0 20913 va (VaSet 20914 vasetType 3 20915 ) 20916 xt "121000,64000,127250,64000" 20917 pts [ 20918 "127250,64000" 20919 "124000,64000" 20920 "121000,64000" 20921 ] 20922 ) 20923 start &91 20924 sat 32 20925 eat 16 20926 st 0 20927 sf 1 20928 si 0 20929 tg (WTG 20930 uid 10270,0 20931 ps "ConnStartEndStrategy" 20932 stg "STSignalDisplayStrategy" 20933 f (Text 20934 uid 10271,0 20935 va (VaSet 20936 ) 20937 xt "122000,63000,125600,64000" 20938 st "s_trigger" 20939 blo "122000,63800" 20940 tm "WireNameMgr" 20941 ) 20942 ) 20943 on &516 20944 ) 20945 *690 (Wire 20946 uid 10298,0 20947 shape (OrthoPolyLine 20948 uid 10299,0 20949 va (VaSet 20950 vasetType 3 20951 ) 20952 xt "1750,54000,18250,54000" 20953 pts [ 20954 "1750,54000" 20955 "18250,54000" 20956 ] 20957 ) 20958 start &216 20959 end &62 20960 sat 32 20961 eat 32 20962 st 0 20963 sf 1 20964 si 0 20965 tg (WTG 20966 uid 10300,0 20967 ps "ConnStartEndStrategy" 20968 stg "STSignalDisplayStrategy" 20969 f (Text 20970 uid 10301,0 20971 va (VaSet 20972 ) 20973 xt "3750,53000,10950,54000" 20974 st "start_srin_write_8b" 20975 blo "3750,53800" 20976 tm "WireNameMgr" 20977 ) 20978 ) 20979 on &517 20980 ) 20981 *691 (Wire 20982 uid 10304,0 20983 shape (OrthoPolyLine 20984 uid 10305,0 20985 va (VaSet 20986 vasetType 3 20987 ) 20988 xt "1750,55000,18250,55000" 20989 pts [ 20990 "1750,55000" 20991 "18250,55000" 20992 ] 20993 ) 20994 start &214 20995 end &63 20996 sat 32 20997 eat 32 20998 st 0 20999 sf 1 21000 si 0 21001 tg (WTG 21002 uid 10306,0 21003 ps "ConnStartEndStrategy" 21004 stg "STSignalDisplayStrategy" 21005 f (Text 21006 uid 10307,0 21007 va (VaSet 21008 ) 21009 xt "3750,54000,9350,55000" 21010 st "srin_write_ack" 21011 blo "3750,54800" 21012 tm "WireNameMgr" 21013 ) 21014 ) 21015 on &518 21016 ) 21017 *692 (Wire 21018 uid 10310,0 21019 shape (OrthoPolyLine 21020 uid 10311,0 21021 va (VaSet 21022 vasetType 3 21023 ) 21024 xt "1750,56000,18250,56000" 21025 pts [ 21026 "1750,56000" 21027 "18250,56000" 21028 ] 21029 ) 21030 start &215 21031 end &64 21032 sat 32 21033 eat 32 21034 st 0 21035 sf 1 21036 si 0 21037 tg (WTG 21038 uid 10312,0 21039 ps "ConnStartEndStrategy" 21040 stg "STSignalDisplayStrategy" 21041 f (Text 21042 uid 10313,0 21043 va (VaSet 21044 ) 21045 xt "3750,55000,10050,56000" 21046 st "srin_write_ready" 21047 blo "3750,55800" 21048 tm "WireNameMgr" 21049 ) 21050 ) 21051 on &519 21052 ) 21053 *693 (Wire 21054 uid 10316,0 21055 shape (OrthoPolyLine 21056 uid 10317,0 21057 va (VaSet 21058 vasetType 3 21059 lineWidth 2 21060 ) 21061 xt "1750,57000,18250,57000" 21062 pts [ 21063 "18250,57000" 21064 "1750,57000" 21065 ] 21066 ) 21067 start &61 21068 end &212 21069 sat 32 21070 eat 32 21071 sty 1 21072 st 0 21073 sf 1 21074 si 0 21075 tg (WTG 21076 uid 10318,0 21077 ps "ConnStartEndStrategy" 21078 stg "STSignalDisplayStrategy" 21079 f (Text 21080 uid 10319,0 21081 va (VaSet 21082 ) 21083 xt "4000,56000,12000,57000" 21084 st "drs_srin_data : (7:0)" 21085 blo "4000,56800" 21086 tm "WireNameMgr" 21087 ) 21088 ) 21089 on &520 21090 ) 21091 *694 (Wire 21092 uid 10322,0 21093 shape (OrthoPolyLine 21094 uid 10323,0 21095 va (VaSet 21096 vasetType 3 21097 ) 21098 xt "-34000,57000,-18750,57000" 21099 pts [ 21100 "-18750,57000" 21101 "-34000,57000" 21102 ] 21103 ) 21104 start &213 21105 end &522 21106 sat 32 21107 eat 32 21108 stc 0 21109 st 0 21110 sf 1 21111 si 0 21112 tg (WTG 21113 uid 10326,0 21114 ps "ConnStartEndStrategy" 21115 stg "STSignalDisplayStrategy" 21116 f (Text 21117 uid 10327,0 21118 va (VaSet 21119 isHidden 1 21120 ) 21121 xt "-24000,56000,-20300,57000" 21122 st "SRIN_out" 21123 blo "-24000,56800" 21124 tm "WireNameMgr" 21125 ) 21126 ) 21127 on &521 21128 ) 21129 *695 (Wire 21130 uid 10431,0 21131 shape (OrthoPolyLine 21132 uid 10432,0 21133 va (VaSet 21134 vasetType 3 21135 ) 21136 xt "-34000,68000,-30000,68000" 21137 pts [ 21138 "-34000,68000" 21139 "-30000,68000" 21140 ] 21141 ) 21142 end &529 21143 sat 16 21144 eat 32 21145 stc 0 21146 st 0 21147 sf 1 21148 si 0 21149 tg (WTG 21150 uid 10435,0 21151 ps "ConnStartEndStrategy" 21152 stg "STSignalDisplayStrategy" 21153 f (Text 21154 uid 10436,0 21155 va (VaSet 21156 ) 21157 xt "-33000,67000,-29400,68000" 21158 st "s_trigger" 21159 blo "-33000,67800" 21160 tm "WireNameMgr" 21161 ) 21162 ) 21163 on &516 21164 ) 21165 *696 (Wire 21166 uid 10439,0 21167 optionalChildren [ 21168 *697 (BdJunction 21169 uid 10447,0 21170 ps "OnConnectorStrategy" 21171 shape (Circle 21172 uid 10448,0 21173 va (VaSet 21174 vasetType 1 21175 ) 21176 xt "-21400,68600,-20600,69400" 21177 radius 400 21178 ) 21179 ) 21180 ] 21181 shape (OrthoPolyLine 21182 uid 10440,0 21183 va (VaSet 21184 vasetType 3 21185 ) 21186 xt "-24000,69000,18250,69000" 21187 pts [ 21188 "18250,69000" 21189 "-24000,69000" 21190 ] 21191 ) 21192 start &30 21193 end &526 21194 sat 32 21195 eat 32 21196 st 0 21197 sf 1 21198 si 0 21199 tg (WTG 21200 uid 10441,0 21201 ps "ConnStartEndStrategy" 21202 stg "STSignalDisplayStrategy" 21203 f (Text 21204 uid 10442,0 21205 va (VaSet 21206 ) 21207 xt "14250,68000,18850,69000" 21208 st "trigger_out" 21209 blo "14250,68800" 21210 tm "WireNameMgr" 21211 ) 21212 ) 21213 on &546 21214 ) 21215 *698 (Wire 21216 uid 10443,0 21217 shape (OrthoPolyLine 21218 uid 10444,0 21219 va (VaSet 21220 vasetType 3 21221 ) 21222 xt "-21000,64000,-18750,69000" 21223 pts [ 21224 "-18750,64000" 21225 "-21000,64000" 21226 "-21000,69000" 21227 ] 21228 ) 21229 start &115 21230 end &697 21231 sat 32 21232 eat 32 21233 stc 0 21234 st 0 21235 sf 1 21236 si 0 21237 tg (WTG 21238 uid 10445,0 21239 ps "ConnStartEndStrategy" 21240 stg "STSignalDisplayStrategy" 21241 f (Text 21242 uid 10446,0 21243 va (VaSet 21244 ) 21245 xt "-20000,68000,-15400,69000" 21246 st "trigger_out" 21247 blo "-20000,68800" 21248 tm "WireNameMgr" 21249 ) 21250 ) 21251 on &546 21252 ) 21253 *699 (Wire 21254 uid 10467,0 21255 shape (OrthoPolyLine 21256 uid 10468,0 21257 va (VaSet 21258 vasetType 3 21259 ) 21260 xt "40750,66000,71250,73000" 21261 pts [ 21262 "71250,73000" 21263 "64000,73000" 21264 "64000,66000" 21265 "40750,66000" 21266 ] 21267 ) 21268 start &141 21269 end &65 21270 es 0 21271 sat 32 21272 eat 32 21273 st 0 21274 sf 1 21275 si 0 21276 tg (WTG 21277 uid 10471,0 21278 ps "ConnStartEndStrategy" 21279 stg "STSignalDisplayStrategy" 21280 f (Text 21281 uid 10472,0 21282 va (VaSet 21283 ) 21284 xt "42000,65000,49800,66000" 21285 st "ram_write_ready_ack" 21286 blo "42000,65800" 21287 tm "WireNameMgr" 21288 ) 21289 ) 21290 on &547 19951 21291 ) 19952 21292 ] … … 19962 21302 color "26368,26368,26368" 19963 21303 ) 19964 packageList * 647(PackageList21304 packageList *700 (PackageList 19965 21305 uid 41,0 19966 21306 stg "VerticalLayoutStrategy" 19967 21307 textVec [ 19968 * 648(Text21308 *701 (Text 19969 21309 uid 42,0 19970 21310 va (VaSet … … 19975 21315 blo "-87000,1800" 19976 21316 ) 19977 * 649(MLText21317 *702 (MLText 19978 21318 uid 43,0 19979 21319 va (VaSet … … 20000 21340 stg "VerticalLayoutStrategy" 20001 21341 textVec [ 20002 * 650(Text21342 *703 (Text 20003 21343 uid 45,0 20004 21344 va (VaSet … … 20010 21350 blo "20000,800" 20011 21351 ) 20012 * 651(Text21352 *704 (Text 20013 21353 uid 46,0 20014 21354 va (VaSet … … 20020 21360 blo "20000,1800" 20021 21361 ) 20022 * 652(MLText21362 *705 (MLText 20023 21363 uid 47,0 20024 21364 va (VaSet … … 20030 21370 tm "BdCompilerDirectivesTextMgr" 20031 21371 ) 20032 * 653(Text21372 *706 (Text 20033 21373 uid 48,0 20034 21374 va (VaSet … … 20040 21380 blo "20000,4800" 20041 21381 ) 20042 * 654(MLText21382 *707 (MLText 20043 21383 uid 49,0 20044 21384 va (VaSet … … 20048 21388 tm "BdCompilerDirectivesTextMgr" 20049 21389 ) 20050 * 655(Text21390 *708 (Text 20051 21391 uid 50,0 20052 21392 va (VaSet … … 20058 21398 blo "20000,5800" 20059 21399 ) 20060 * 656(MLText21400 *709 (MLText 20061 21401 uid 51,0 20062 21402 va (VaSet … … 20070 21410 ) 20071 21411 windowSize "1280,0,2561,1024" 20072 viewArea " -71804,-21787,15728,50400"20073 cachedDiagramExtent "-105000,-60500,16 2300,343294"21412 viewArea "1300,44100,167081,180819" 21413 cachedDiagramExtent "-105000,-60500,163300,343294" 20074 21414 pageSetupInfo (PageSetupInfo 20075 21415 ptrCmd "eDocPrintPro,winspool," … … 20096 21436 hasePageBreakOrigin 1 20097 21437 pageBreakOrigin "-73000,0" 20098 lastUid 10 041,021438 lastUid 10547,0 20099 21439 defaultCommentText (CommentText 20100 21440 shape (Rectangle … … 20158 21498 stg "VerticalLayoutStrategy" 20159 21499 textVec [ 20160 * 657(Text21500 *710 (Text 20161 21501 va (VaSet 20162 21502 font "Arial,8,1" … … 20167 21507 tm "BdLibraryNameMgr" 20168 21508 ) 20169 * 658(Text21509 *711 (Text 20170 21510 va (VaSet 20171 21511 font "Arial,8,1" … … 20176 21516 tm "BlkNameMgr" 20177 21517 ) 20178 * 659(Text21518 *712 (Text 20179 21519 va (VaSet 20180 21520 font "Arial,8,1" … … 20227 21567 stg "VerticalLayoutStrategy" 20228 21568 textVec [ 20229 * 660(Text21569 *713 (Text 20230 21570 va (VaSet 20231 21571 font "Arial,8,1" … … 20235 21575 blo "550,4300" 20236 21576 ) 20237 * 661(Text21577 *714 (Text 20238 21578 va (VaSet 20239 21579 font "Arial,8,1" … … 20243 21583 blo "550,5300" 20244 21584 ) 20245 * 662(Text21585 *715 (Text 20246 21586 va (VaSet 20247 21587 font "Arial,8,1" … … 20292 21632 stg "VerticalLayoutStrategy" 20293 21633 textVec [ 20294 * 663(Text21634 *716 (Text 20295 21635 va (VaSet 20296 21636 font "Arial,8,1" … … 20301 21641 tm "BdLibraryNameMgr" 20302 21642 ) 20303 * 664(Text21643 *717 (Text 20304 21644 va (VaSet 20305 21645 font "Arial,8,1" … … 20310 21650 tm "CptNameMgr" 20311 21651 ) 20312 * 665(Text21652 *718 (Text 20313 21653 va (VaSet 20314 21654 font "Arial,8,1" … … 20364 21704 stg "VerticalLayoutStrategy" 20365 21705 textVec [ 20366 * 666(Text21706 *719 (Text 20367 21707 va (VaSet 20368 21708 font "Arial,8,1" … … 20372 21712 blo "500,4300" 20373 21713 ) 20374 * 667(Text21714 *720 (Text 20375 21715 va (VaSet 20376 21716 font "Arial,8,1" … … 20380 21720 blo "500,5300" 20381 21721 ) 20382 * 668(Text21722 *721 (Text 20383 21723 va (VaSet 20384 21724 font "Arial,8,1" … … 20425 21765 stg "VerticalLayoutStrategy" 20426 21766 textVec [ 20427 * 669(Text21767 *722 (Text 20428 21768 va (VaSet 20429 21769 font "Arial,8,1" … … 20433 21773 blo "50,4300" 20434 21774 ) 20435 * 670(Text21775 *723 (Text 20436 21776 va (VaSet 20437 21777 font "Arial,8,1" … … 20441 21781 blo "50,5300" 20442 21782 ) 20443 * 671(Text21783 *724 (Text 20444 21784 va (VaSet 20445 21785 font "Arial,8,1" … … 20482 21822 stg "VerticalLayoutStrategy" 20483 21823 textVec [ 20484 * 672(Text21824 *725 (Text 20485 21825 va (VaSet 20486 21826 font "Arial,8,1" … … 20491 21831 tm "HdlTextNameMgr" 20492 21832 ) 20493 * 673(Text21833 *726 (Text 20494 21834 va (VaSet 20495 21835 font "Arial,8,1" … … 20894 22234 stg "VerticalLayoutStrategy" 20895 22235 textVec [ 20896 * 674(Text22236 *727 (Text 20897 22237 va (VaSet 20898 22238 font "Arial,8,1" … … 20902 22242 blo "14100,20800" 20903 22243 ) 20904 * 675(MLText22244 *728 (MLText 20905 22245 va (VaSet 20906 22246 ) … … 20954 22294 stg "VerticalLayoutStrategy" 20955 22295 textVec [ 20956 * 676(Text22296 *729 (Text 20957 22297 va (VaSet 20958 22298 font "Arial,8,1" … … 20962 22302 blo "14100,20800" 20963 22303 ) 20964 * 677(MLText22304 *730 (MLText 20965 22305 va (VaSet 20966 22306 ) … … 21061 22401 font "Arial,8,1" 21062 22402 ) 21063 xt "-105000,5 5800,-101200,56800"22403 xt "-105000,56600,-101200,57600" 21064 22404 st "Pre User:" 21065 blo "-105000,5 6600"22405 blo "-105000,57400" 21066 22406 ) 21067 22407 preUserText (MLText … … 21078 22418 font "Arial,8,1" 21079 22419 ) 21080 xt "-105000,5 6800,-97900,57800"22420 xt "-105000,57600,-97900,58600" 21081 22421 st "Diagram Signals:" 21082 blo "-105000,5 7600"22422 blo "-105000,58400" 21083 22423 ) 21084 22424 postUserLabel (Text … … 21087 22427 font "Arial,8,1" 21088 22428 ) 21089 xt "-105000,1 05800,-100300,106800"22429 xt "-105000,115400,-100300,116400" 21090 22430 st "Post User:" 21091 blo "-105000,1 06600"22431 blo "-105000,116200" 21092 22432 ) 21093 22433 postUserText (MLText … … 21102 22442 commonDM (CommonDM 21103 22443 ldm (LogicalDM 21104 suid 2 26,022444 suid 242,0 21105 22445 usingSuid 1 21106 emptyRow * 678(LEmptyRow22446 emptyRow *731 (LEmptyRow 21107 22447 ) 21108 22448 uid 54,0 21109 22449 optionalChildren [ 21110 * 679(RefLabelRowHdr21111 ) 21112 * 680(TitleRowHdr21113 ) 21114 * 681(FilterRowHdr21115 ) 21116 * 682(RefLabelColHdr22450 *732 (RefLabelRowHdr 22451 ) 22452 *733 (TitleRowHdr 22453 ) 22454 *734 (FilterRowHdr 22455 ) 22456 *735 (RefLabelColHdr 21117 22457 tm "RefLabelColHdrMgr" 21118 22458 ) 21119 * 683(RowExpandColHdr22459 *736 (RowExpandColHdr 21120 22460 tm "RowExpandColHdrMgr" 21121 22461 ) 21122 * 684(GroupColHdr22462 *737 (GroupColHdr 21123 22463 tm "GroupColHdrMgr" 21124 22464 ) 21125 * 685(NameColHdr22465 *738 (NameColHdr 21126 22466 tm "BlockDiagramNameColHdrMgr" 21127 22467 ) 21128 * 686(ModeColHdr22468 *739 (ModeColHdr 21129 22469 tm "BlockDiagramModeColHdrMgr" 21130 22470 ) 21131 * 687(TypeColHdr22471 *740 (TypeColHdr 21132 22472 tm "BlockDiagramTypeColHdrMgr" 21133 22473 ) 21134 * 688(BoundsColHdr22474 *741 (BoundsColHdr 21135 22475 tm "BlockDiagramBoundsColHdrMgr" 21136 22476 ) 21137 * 689(InitColHdr22477 *742 (InitColHdr 21138 22478 tm "BlockDiagramInitColHdrMgr" 21139 22479 ) 21140 * 690(EolColHdr22480 *743 (EolColHdr 21141 22481 tm "BlockDiagramEolColHdrMgr" 21142 22482 ) 21143 * 691(LeafLogPort22483 *744 (LeafLogPort 21144 22484 port (LogicalPort 21145 22485 m 4 … … 21155 22495 uid 516,0 21156 22496 ) 21157 * 692(LeafLogPort22497 *745 (LeafLogPort 21158 22498 port (LogicalPort 21159 22499 m 4 … … 21168 22508 uid 518,0 21169 22509 ) 21170 * 693(LeafLogPort22510 *746 (LeafLogPort 21171 22511 port (LogicalPort 21172 22512 m 4 … … 21181 22521 uid 520,0 21182 22522 ) 21183 * 694(LeafLogPort22523 *747 (LeafLogPort 21184 22524 port (LogicalPort 21185 22525 m 4 … … 21194 22534 uid 530,0 21195 22535 ) 21196 * 695(LeafLogPort22536 *748 (LeafLogPort 21197 22537 port (LogicalPort 21198 22538 m 4 … … 21207 22547 uid 532,0 21208 22548 ) 21209 * 696(LeafLogPort22549 *749 (LeafLogPort 21210 22550 port (LogicalPort 21211 22551 m 1 … … 21220 22560 uid 534,0 21221 22561 ) 21222 * 697(LeafLogPort22562 *750 (LeafLogPort 21223 22563 port (LogicalPort 21224 22564 m 1 … … 21233 22573 uid 536,0 21234 22574 ) 21235 * 698(LeafLogPort22575 *751 (LeafLogPort 21236 22576 port (LogicalPort 21237 22577 m 2 … … 21246 22586 uid 538,0 21247 22587 ) 21248 * 699(LeafLogPort22588 *752 (LeafLogPort 21249 22589 port (LogicalPort 21250 22590 m 1 … … 21259 22599 uid 540,0 21260 22600 ) 21261 *7 00(LeafLogPort22601 *753 (LeafLogPort 21262 22602 port (LogicalPort 21263 22603 m 1 … … 21272 22612 uid 542,0 21273 22613 ) 21274 *7 01(LeafLogPort22614 *754 (LeafLogPort 21275 22615 port (LogicalPort 21276 22616 m 1 … … 21285 22625 uid 546,0 21286 22626 ) 21287 *7 02(LeafLogPort22627 *755 (LeafLogPort 21288 22628 port (LogicalPort 21289 22629 decl (Decl … … 21296 22636 uid 548,0 21297 22637 ) 21298 *7 03(LeafLogPort22638 *756 (LeafLogPort 21299 22639 port (LogicalPort 21300 22640 decl (Decl … … 21310 22650 uid 1455,0 21311 22651 ) 21312 *7 04(LeafLogPort22652 *757 (LeafLogPort 21313 22653 port (LogicalPort 21314 22654 decl (Decl … … 21323 22663 uid 1457,0 21324 22664 ) 21325 *7 05(LeafLogPort22665 *758 (LeafLogPort 21326 22666 port (LogicalPort 21327 22667 decl (Decl … … 21335 22675 uid 1694,0 21336 22676 ) 21337 *7 06(LeafLogPort22677 *759 (LeafLogPort 21338 22678 port (LogicalPort 21339 22679 lang 2 … … 21351 22691 uid 1993,0 21352 22692 ) 21353 *7 07(LeafLogPort22693 *760 (LeafLogPort 21354 22694 port (LogicalPort 21355 22695 m 4 … … 21366 22706 uid 2305,0 21367 22707 ) 21368 *7 08(LeafLogPort22708 *761 (LeafLogPort 21369 22709 port (LogicalPort 21370 22710 lang 2 … … 21379 22719 uid 2510,0 21380 22720 ) 21381 *7 09(LeafLogPort22721 *762 (LeafLogPort 21382 22722 port (LogicalPort 21383 22723 lang 2 … … 21393 22733 uid 2512,0 21394 22734 ) 21395 *7 10(LeafLogPort22735 *763 (LeafLogPort 21396 22736 port (LogicalPort 21397 22737 lang 2 … … 21408 22748 uid 2514,0 21409 22749 ) 21410 *7 11(LeafLogPort22750 *764 (LeafLogPort 21411 22751 port (LogicalPort 21412 22752 lang 2 … … 21424 22764 uid 2516,0 21425 22765 ) 21426 *7 12(LeafLogPort22766 *765 (LeafLogPort 21427 22767 port (LogicalPort 21428 22768 lang 2 … … 21439 22779 uid 2518,0 21440 22780 ) 21441 *7 13(LeafLogPort22781 *766 (LeafLogPort 21442 22782 port (LogicalPort 21443 22783 lang 2 … … 21453 22793 uid 2520,0 21454 22794 ) 21455 *7 14(LeafLogPort22795 *767 (LeafLogPort 21456 22796 port (LogicalPort 21457 22797 lang 2 … … 21467 22807 uid 2522,0 21468 22808 ) 21469 *7 15(LeafLogPort22809 *768 (LeafLogPort 21470 22810 port (LogicalPort 21471 22811 m 4 … … 21479 22819 uid 2604,0 21480 22820 ) 21481 *7 16(LeafLogPort22821 *769 (LeafLogPort 21482 22822 port (LogicalPort 21483 22823 m 4 … … 21492 22832 uid 2606,0 21493 22833 ) 21494 *7 17(LeafLogPort22834 *770 (LeafLogPort 21495 22835 port (LogicalPort 21496 22836 m 4 … … 21505 22845 uid 2608,0 21506 22846 ) 21507 *7 18(LeafLogPort22847 *771 (LeafLogPort 21508 22848 port (LogicalPort 21509 22849 m 4 … … 21517 22857 uid 2610,0 21518 22858 ) 21519 *7 19(LeafLogPort22859 *772 (LeafLogPort 21520 22860 port (LogicalPort 21521 22861 m 4 … … 21529 22869 uid 2612,0 21530 22870 ) 21531 *7 20(LeafLogPort22871 *773 (LeafLogPort 21532 22872 port (LogicalPort 21533 22873 m 4 … … 21542 22882 uid 2646,0 21543 22883 ) 21544 *7 21(LeafLogPort22884 *774 (LeafLogPort 21545 22885 port (LogicalPort 21546 22886 m 1 … … 21555 22895 uid 2812,0 21556 22896 ) 21557 *7 22(LeafLogPort22897 *775 (LeafLogPort 21558 22898 port (LogicalPort 21559 22899 m 4 … … 21567 22907 uid 2962,0 21568 22908 ) 21569 *7 23(LeafLogPort22909 *776 (LeafLogPort 21570 22910 port (LogicalPort 21571 22911 m 1 … … 21579 22919 uid 3902,0 21580 22920 ) 21581 *7 24(LeafLogPort22921 *777 (LeafLogPort 21582 22922 port (LogicalPort 21583 22923 m 1 … … 21591 22931 uid 4070,0 21592 22932 ) 21593 *7 25(LeafLogPort22933 *778 (LeafLogPort 21594 22934 port (LogicalPort 21595 22935 m 4 … … 21603 22943 uid 4212,0 21604 22944 ) 21605 *7 26(LeafLogPort22945 *779 (LeafLogPort 21606 22946 port (LogicalPort 21607 22947 decl (Decl … … 21614 22954 uid 4234,0 21615 22955 ) 21616 *7 27(LeafLogPort22956 *780 (LeafLogPort 21617 22957 port (LogicalPort 21618 22958 decl (Decl … … 21626 22966 uid 4262,0 21627 22967 ) 21628 *7 28(LeafLogPort22968 *781 (LeafLogPort 21629 22969 port (LogicalPort 21630 22970 decl (Decl … … 21637 22977 uid 4276,0 21638 22978 ) 21639 *7 29(LeafLogPort22979 *782 (LeafLogPort 21640 22980 port (LogicalPort 21641 22981 m 4 … … 21650 22990 uid 4563,0 21651 22991 ) 21652 *7 30(LeafLogPort22992 *783 (LeafLogPort 21653 22993 port (LogicalPort 21654 22994 m 4 … … 21662 23002 uid 4565,0 21663 23003 ) 21664 *7 31(LeafLogPort23004 *784 (LeafLogPort 21665 23005 port (LogicalPort 21666 23006 m 4 … … 21675 23015 uid 4569,0 21676 23016 ) 21677 *7 32(LeafLogPort23017 *785 (LeafLogPort 21678 23018 port (LogicalPort 21679 23019 m 1 … … 21689 23029 uid 4585,0 21690 23030 ) 21691 *7 33(LeafLogPort23031 *786 (LeafLogPort 21692 23032 port (LogicalPort 21693 23033 m 1 … … 21702 23042 uid 4587,0 21703 23043 ) 21704 *7 34(LeafLogPort23044 *787 (LeafLogPort 21705 23045 port (LogicalPort 21706 23046 decl (Decl … … 21713 23053 uid 4733,0 21714 23054 ) 21715 *7 35(LeafLogPort23055 *788 (LeafLogPort 21716 23056 port (LogicalPort 21717 23057 decl (Decl … … 21724 23064 uid 4735,0 21725 23065 ) 21726 *7 36(LeafLogPort23066 *789 (LeafLogPort 21727 23067 port (LogicalPort 21728 23068 decl (Decl … … 21735 23075 uid 4737,0 21736 23076 ) 21737 *7 37(LeafLogPort23077 *790 (LeafLogPort 21738 23078 port (LogicalPort 21739 23079 decl (Decl … … 21746 23086 uid 4739,0 21747 23087 ) 21748 *7 38(LeafLogPort23088 *791 (LeafLogPort 21749 23089 port (LogicalPort 21750 23090 m 4 … … 21758 23098 uid 4749,0 21759 23099 ) 21760 *7 39(LeafLogPort23100 *792 (LeafLogPort 21761 23101 port (LogicalPort 21762 23102 m 1 … … 21771 23111 uid 4974,0 21772 23112 ) 21773 *7 40(LeafLogPort23113 *793 (LeafLogPort 21774 23114 port (LogicalPort 21775 23115 m 1 … … 21784 23124 uid 4976,0 21785 23125 ) 21786 *7 41(LeafLogPort23126 *794 (LeafLogPort 21787 23127 port (LogicalPort 21788 23128 m 4 … … 21797 23137 uid 5198,0 21798 23138 ) 21799 *7 42(LeafLogPort23139 *795 (LeafLogPort 21800 23140 port (LogicalPort 21801 23141 m 4 … … 21809 23149 uid 5200,0 21810 23150 ) 21811 *7 43(LeafLogPort23151 *796 (LeafLogPort 21812 23152 port (LogicalPort 21813 23153 m 4 … … 21821 23161 uid 5202,0 21822 23162 ) 21823 *7 44(LeafLogPort23163 *797 (LeafLogPort 21824 23164 port (LogicalPort 21825 23165 m 4 … … 21834 23174 uid 5204,0 21835 23175 ) 21836 *7 45(LeafLogPort23176 *798 (LeafLogPort 21837 23177 port (LogicalPort 21838 23178 m 4 … … 21846 23186 uid 5206,0 21847 23187 ) 21848 *7 46(LeafLogPort23188 *799 (LeafLogPort 21849 23189 port (LogicalPort 21850 23190 m 4 … … 21858 23198 uid 5208,0 21859 23199 ) 21860 * 747(LeafLogPort23200 *800 (LeafLogPort 21861 23201 port (LogicalPort 21862 23202 m 4 … … 21870 23210 uid 5210,0 21871 23211 ) 21872 * 748(LeafLogPort23212 *801 (LeafLogPort 21873 23213 port (LogicalPort 21874 23214 m 4 … … 21882 23222 uid 5212,0 21883 23223 ) 21884 * 749(LeafLogPort23224 *802 (LeafLogPort 21885 23225 port (LogicalPort 21886 23226 m 4 … … 21894 23234 uid 5214,0 21895 23235 ) 21896 * 750(LeafLogPort23236 *803 (LeafLogPort 21897 23237 port (LogicalPort 21898 23238 m 1 … … 21909 23249 uid 5226,0 21910 23250 ) 21911 * 751(LeafLogPort23251 *804 (LeafLogPort 21912 23252 port (LogicalPort 21913 23253 m 4 21914 23254 decl (Decl 21915 n "s_trigger"21916 t "std_logic"21917 o 6921918 suid 134,021919 i "'0'"21920 )21921 )21922 uid 5285,021923 )21924 *752 (LeafLogPort21925 port (LogicalPort21926 m 421927 decl (Decl21928 23255 n "sensor_ready" 21929 23256 t "std_logic" … … 21934 23261 uid 5502,0 21935 23262 ) 21936 * 753(LeafLogPort23263 *805 (LeafLogPort 21937 23264 port (LogicalPort 21938 23265 m 4 … … 21946 23273 uid 5504,0 21947 23274 ) 21948 * 754(LeafLogPort23275 *806 (LeafLogPort 21949 23276 port (LogicalPort 21950 23277 m 4 … … 21958 23285 uid 5600,0 21959 23286 ) 21960 * 755(LeafLogPort23287 *807 (LeafLogPort 21961 23288 port (LogicalPort 21962 23289 lang 10 … … 21972 23299 uid 5642,0 21973 23300 ) 21974 * 756(LeafLogPort23301 *808 (LeafLogPort 21975 23302 port (LogicalPort 21976 23303 m 4 … … 21984 23311 uid 5644,0 21985 23312 ) 21986 * 757(LeafLogPort23313 *809 (LeafLogPort 21987 23314 port (LogicalPort 21988 23315 m 4 … … 21997 23324 uid 5751,0 21998 23325 ) 21999 * 758(LeafLogPort23326 *810 (LeafLogPort 22000 23327 port (LogicalPort 22001 23328 m 1 … … 22009 23336 uid 5867,0 22010 23337 ) 22011 * 759(LeafLogPort23338 *811 (LeafLogPort 22012 23339 port (LogicalPort 22013 23340 m 2 … … 22023 23350 uid 5869,0 22024 23351 ) 22025 * 760(LeafLogPort23352 *812 (LeafLogPort 22026 23353 port (LogicalPort 22027 23354 m 1 … … 22035 23362 uid 5871,0 22036 23363 ) 22037 * 761(LeafLogPort23364 *813 (LeafLogPort 22038 23365 port (LogicalPort 22039 23366 m 1 … … 22048 23375 uid 5873,0 22049 23376 ) 22050 * 762(LeafLogPort23377 *814 (LeafLogPort 22051 23378 port (LogicalPort 22052 23379 m 4 … … 22061 23388 uid 5966,0 22062 23389 ) 22063 * 763(LeafLogPort23390 *815 (LeafLogPort 22064 23391 port (LogicalPort 22065 23392 m 4 … … 22073 23400 uid 5968,0 22074 23401 ) 22075 * 764(LeafLogPort23402 *816 (LeafLogPort 22076 23403 port (LogicalPort 22077 23404 m 4 … … 22086 23413 uid 6022,0 22087 23414 ) 22088 * 765(LeafLogPort23415 *817 (LeafLogPort 22089 23416 port (LogicalPort 22090 23417 m 4 … … 22099 23426 uid 6024,0 22100 23427 ) 22101 * 766(LeafLogPort23428 *818 (LeafLogPort 22102 23429 port (LogicalPort 22103 23430 m 4 … … 22111 23438 uid 6026,0 22112 23439 ) 22113 * 767(LeafLogPort23440 *819 (LeafLogPort 22114 23441 port (LogicalPort 22115 23442 m 1 … … 22124 23451 uid 6172,0 22125 23452 ) 22126 * 768(LeafLogPort23453 *820 (LeafLogPort 22127 23454 port (LogicalPort 22128 23455 m 1 … … 22139 23466 uid 6374,0 22140 23467 ) 22141 * 769(LeafLogPort23468 *821 (LeafLogPort 22142 23469 port (LogicalPort 22143 23470 m 4 … … 22152 23479 uid 6464,0 22153 23480 ) 22154 * 770(LeafLogPort23481 *822 (LeafLogPort 22155 23482 port (LogicalPort 22156 23483 m 4 … … 22165 23492 uid 6554,0 22166 23493 ) 22167 * 771(LeafLogPort23494 *823 (LeafLogPort 22168 23495 port (LogicalPort 22169 23496 lang 2 … … 22178 23505 uid 8420,0 22179 23506 ) 22180 * 772(LeafLogPort23507 *824 (LeafLogPort 22181 23508 port (LogicalPort 22182 23509 m 4 … … 22192 23519 uid 8609,0 22193 23520 ) 22194 * 773(LeafLogPort23521 *825 (LeafLogPort 22195 23522 port (LogicalPort 22196 23523 m 4 … … 22204 23531 uid 8611,0 22205 23532 ) 22206 * 774(LeafLogPort23533 *826 (LeafLogPort 22207 23534 port (LogicalPort 22208 23535 m 4 … … 22218 23545 uid 8613,0 22219 23546 ) 22220 * 775(LeafLogPort23547 *827 (LeafLogPort 22221 23548 port (LogicalPort 22222 23549 m 4 … … 22230 23557 uid 8758,0 22231 23558 ) 22232 * 776(LeafLogPort23559 *828 (LeafLogPort 22233 23560 port (LogicalPort 22234 23561 m 4 … … 22242 23569 uid 8760,0 22243 23570 ) 22244 * 777(LeafLogPort23571 *829 (LeafLogPort 22245 23572 port (LogicalPort 22246 23573 m 1 … … 22255 23582 uid 9018,0 22256 23583 ) 22257 * 778(LeafLogPort23584 *830 (LeafLogPort 22258 23585 port (LogicalPort 22259 23586 m 4 … … 22270 23597 uid 9247,0 22271 23598 ) 22272 * 779(LeafLogPort23599 *831 (LeafLogPort 22273 23600 port (LogicalPort 22274 23601 m 4 … … 22286 23613 uid 9249,0 22287 23614 ) 22288 * 780(LeafLogPort23615 *832 (LeafLogPort 22289 23616 port (LogicalPort 22290 23617 m 1 … … 22298 23625 uid 9555,0 22299 23626 ) 22300 * 781(LeafLogPort23627 *833 (LeafLogPort 22301 23628 port (LogicalPort 22302 23629 m 1 … … 22310 23637 uid 9557,0 22311 23638 ) 22312 * 782(LeafLogPort23639 *834 (LeafLogPort 22313 23640 port (LogicalPort 22314 23641 m 1 … … 22322 23649 uid 9559,0 22323 23650 ) 22324 * 783(LeafLogPort23651 *835 (LeafLogPort 22325 23652 port (LogicalPort 22326 23653 m 1 … … 22334 23661 uid 9561,0 22335 23662 ) 22336 * 784(LeafLogPort23663 *836 (LeafLogPort 22337 23664 port (LogicalPort 22338 23665 m 1 … … 22346 23673 uid 9563,0 22347 23674 ) 22348 * 785(LeafLogPort23675 *837 (LeafLogPort 22349 23676 port (LogicalPort 22350 23677 m 1 … … 22360 23687 uid 9567,0 22361 23688 ) 22362 * 786(LeafLogPort23689 *838 (LeafLogPort 22363 23690 port (LogicalPort 22364 23691 m 1 … … 22376 23703 uid 9569,0 22377 23704 ) 22378 * 787(LeafLogPort23705 *839 (LeafLogPort 22379 23706 port (LogicalPort 22380 23707 m 1 … … 22392 23719 uid 9571,0 22393 23720 ) 22394 * 788(LeafLogPort23721 *840 (LeafLogPort 22395 23722 port (LogicalPort 22396 23723 m 1 … … 22407 23734 uid 9573,0 22408 23735 ) 22409 * 789(LeafLogPort23736 *841 (LeafLogPort 22410 23737 port (LogicalPort 22411 23738 m 1 … … 22419 23746 uid 9575,0 22420 23747 ) 22421 * 790(LeafLogPort23748 *842 (LeafLogPort 22422 23749 port (LogicalPort 22423 23750 m 1 … … 22431 23758 uid 9577,0 22432 23759 ) 22433 * 791(LeafLogPort23760 *843 (LeafLogPort 22434 23761 port (LogicalPort 22435 23762 m 1 … … 22443 23770 uid 9801,0 22444 23771 ) 22445 * 792(LeafLogPort23772 *844 (LeafLogPort 22446 23773 port (LogicalPort 22447 23774 m 1 … … 22455 23782 uid 9803,0 22456 23783 ) 22457 * 793(LeafLogPort23784 *845 (LeafLogPort 22458 23785 port (LogicalPort 22459 23786 m 1 … … 22467 23794 uid 9805,0 22468 23795 ) 22469 * 794(LeafLogPort23796 *846 (LeafLogPort 22470 23797 port (LogicalPort 22471 23798 m 4 … … 22482 23809 uid 10024,0 22483 23810 ) 22484 * 795(LeafLogPort23811 *847 (LeafLogPort 22485 23812 port (LogicalPort 22486 23813 m 4 … … 22495 23822 uid 10026,0 22496 23823 ) 22497 * 796(LeafLogPort23824 *848 (LeafLogPort 22498 23825 port (LogicalPort 22499 23826 m 4 … … 22507 23834 ) 22508 23835 uid 10028,0 23836 ) 23837 *849 (LeafLogPort 23838 port (LogicalPort 23839 m 4 23840 decl (Decl 23841 n "config_rw_ack" 23842 t "std_logic" 23843 prec "-- --" 23844 preAdd 0 23845 posAdd 0 23846 o 107 23847 suid 227,0 23848 i "'0'" 23849 ) 23850 ) 23851 uid 10208,0 23852 ) 23853 *850 (LeafLogPort 23854 port (LogicalPort 23855 m 4 23856 decl (Decl 23857 n "config_rw_ready" 23858 t "std_logic" 23859 prec "-- --" 23860 preAdd 0 23861 posAdd 0 23862 o 108 23863 suid 228,0 23864 i "'0'" 23865 ) 23866 ) 23867 uid 10210,0 23868 ) 23869 *851 (LeafLogPort 23870 port (LogicalPort 23871 m 4 23872 decl (Decl 23873 n "s_trigger" 23874 t "std_logic" 23875 o 109 23876 suid 230,0 23877 ) 23878 ) 23879 uid 10294,0 23880 ) 23881 *852 (LeafLogPort 23882 port (LogicalPort 23883 m 4 23884 decl (Decl 23885 n "start_srin_write_8b" 23886 t "std_logic" 23887 o 110 23888 suid 231,0 23889 ) 23890 ) 23891 uid 10334,0 23892 ) 23893 *853 (LeafLogPort 23894 port (LogicalPort 23895 m 4 23896 decl (Decl 23897 n "srin_write_ack" 23898 t "std_logic" 23899 o 111 23900 suid 232,0 23901 i "'0'" 23902 ) 23903 ) 23904 uid 10336,0 23905 ) 23906 *854 (LeafLogPort 23907 port (LogicalPort 23908 m 4 23909 decl (Decl 23910 n "srin_write_ready" 23911 t "std_logic" 23912 o 112 23913 suid 233,0 23914 i "'0'" 23915 ) 23916 ) 23917 uid 10338,0 23918 ) 23919 *855 (LeafLogPort 23920 port (LogicalPort 23921 m 4 23922 decl (Decl 23923 n "drs_srin_data" 23924 t "std_logic_vector" 23925 b "(7 downto 0)" 23926 o 113 23927 suid 234,0 23928 i "(others => '0')" 23929 ) 23930 ) 23931 uid 10340,0 23932 ) 23933 *856 (LeafLogPort 23934 port (LogicalPort 23935 m 1 23936 decl (Decl 23937 n "SRIN_out" 23938 t "std_logic" 23939 o 114 23940 suid 235,0 23941 i "'0'" 23942 ) 23943 ) 23944 uid 10342,0 23945 ) 23946 *857 (LeafLogPort 23947 port (LogicalPort 23948 m 4 23949 decl (Decl 23950 n "trigger_out" 23951 t "std_logic" 23952 preAdd 0 23953 posAdd 0 23954 o 115 23955 suid 240,0 23956 ) 23957 ) 23958 uid 10473,0 23959 ) 23960 *858 (LeafLogPort 23961 port (LogicalPort 23962 lang 2 23963 m 4 23964 decl (Decl 23965 n "ram_write_ready_ack" 23966 t "std_logic" 23967 prec "-- --" 23968 preAdd 0 23969 posAdd 0 23970 o 115 23971 suid 242,0 23972 i "'0'" 23973 ) 23974 ) 23975 uid 10475,0 22509 23976 ) 22510 23977 ] … … 22515 23982 uid 67,0 22516 23983 optionalChildren [ 22517 * 797(Sheet23984 *859 (Sheet 22518 23985 sheetRow (SheetRow 22519 23986 headerVa (MVa … … 22532 23999 font "Tahoma,10,0" 22533 24000 ) 22534 emptyMRCItem * 798(MRCItem22535 litem & 67822536 pos 1 0624001 emptyMRCItem *860 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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak
r9912 r10073 224 224 uid 9957,0 225 225 ) 226 (Instance 227 name "U_9" 228 duLibraryName "moduleware" 229 duName "or" 230 elements [ 231 ] 232 mwi 1 233 uid 10380,0 234 ) 226 235 ] 227 236 libraryRefs [ … … 239 248 (vvPair 240 249 variable "HDLDir" 241 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"250 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" 242 251 ) 243 252 (vvPair 244 253 variable "HDSDir" 245 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"254 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 246 255 ) 247 256 (vvPair 248 257 variable "SideDataDesignDir" 249 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info"258 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info" 250 259 ) 251 260 (vvPair 252 261 variable "SideDataUserDir" 253 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user"262 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user" 254 263 ) 255 264 (vvPair 256 265 variable "SourceDir" 257 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"266 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 258 267 ) 259 268 (vvPair … … 271 280 (vvPair 272 281 variable "d" 273 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main"282 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main" 274 283 ) 275 284 (vvPair 276 285 variable "d_logical" 277 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_main"286 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main" 278 287 ) 279 288 (vvPair 280 289 variable "date" 281 value " 30.08.2010"290 value "04.01.2011" 282 291 ) 283 292 (vvPair 284 293 variable "day" 285 value " Mo"294 value "Di" 286 295 ) 287 296 (vvPair 288 297 variable "day_long" 289 value " Montag"298 value "Dienstag" 290 299 ) 291 300 (vvPair 292 301 variable "dd" 293 value " 30"302 value "04" 294 303 ) 295 304 (vvPair … … 355 364 (vvPair 356 365 variable "mm" 357 value "0 8"366 value "01" 358 367 ) 359 368 (vvPair … … 363 372 (vvPair 364 373 variable "month" 365 value " Aug"374 value "Jan" 366 375 ) 367 376 (vvPair 368 377 variable "month_long" 369 value " August"378 value "Januar" 370 379 ) 371 380 (vvPair 372 381 variable "p" 373 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd"382 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd" 374 383 ) 375 384 (vvPair 376 385 variable "p_logical" 377 value "C:\\ FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd"386 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd" 378 387 ) 379 388 (vvPair … … 431 440 (vvPair 432 441 variable "time" 433 value "1 0:42:05"&nbs