Changeset 10075 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib
- Timestamp:
- 01/04/11 17:21:15 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib
- Files:
-
- 12 edited
-
hdl/fad_board_struct.vhd (modified) (3 diffs)
-
hdl/fad_main_struct.vhd (modified) (4 diffs)
-
hdl/led_controller_bahavior.vhd (modified) (3 diffs)
-
hds/.cache.dat (modified) ( previous)
-
hds/.xrf/fad_board_struct.xrf (modified) (2 diffs)
-
hds/.xrf/fad_main_struct.xrf (modified) (1 diff)
-
hds/@f@a@d_@board/struct.bd (modified) (85 diffs)
-
hds/@f@a@d_@board/struct.bd.bak (modified) (79 diffs)
-
hds/@f@a@d_@board/symbol.sb (modified) (2 diffs)
-
hds/@f@a@d_main/struct.bd (modified) (137 diffs)
-
hds/@f@a@d_main/struct.bd.bak (modified) (137 diffs)
-
hds/@f@a@d_main/symbol.sb (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10074 r10075 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 5:02:5604.01.20115 -- at - 18:14:37 04.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 79 79 -- Created: 80 80 -- by - dneise.UNKNOWN (E5B-LABOR6) 81 -- at - 1 5:02:5604.01.201181 -- at - 18:14:37 04.01.2011 82 82 -- 83 83 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 319 319 drs_channel_id => drs_channel_id, 320 320 drs_dwrite => DWRITE, 321 green => GREEN_LED,321 green => RED_LED, 322 322 led => D_T, 323 323 mosi => MOSI, 324 324 offset => OPEN, 325 325 ready => ready, 326 red => RED_LED,326 red => GREEN_LED, 327 327 sclk => S_CLK, 328 328 sensor_cs => sensor_cs, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10074 r10075 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 5:02:55 04.01.20115 -- at - 18:14:35 04.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 80 80 -- Created: 81 81 -- by - dneise.UNKNOWN (E5B-LABOR6) 82 -- at - 1 5:02:5504.01.201182 -- at - 18:14:36 04.01.2011 83 83 -- 84 84 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 323 323 COMPONENT led_controller 324 324 GENERIC ( 325 HEARTBEAT_DIVIDER : integer := 5000; -- 100kHz @ 50 MHz 326 WAITING_DIVIDER : integer := 50000000 -- 10Hz @ 50 MHz 325 HEARTBEAT_PWM_DIVIDER : integer := 500; -- 1kHz @ 50 MHz 326 MAX_DELAY : integer := 100; 327 WAITING_DIVIDER : integer := 500000000 -- 1Hz @ 50 MHz 327 328 ); 328 329 PORT ( … … 618 619 U_10 : led_controller 619 620 GENERIC MAP ( 620 HEARTBEAT_DIVIDER => 25000000, -- 2Hz @ 50 MHz 621 WAITING_DIVIDER => 5000000 -- 10Hz @ 50 MHz 621 HEARTBEAT_PWM_DIVIDER => 50000, -- 10kHz @ 50 MHz 622 MAX_DELAY => 100, 623 WAITING_DIVIDER => 50000000 -- 1Hz @ 50 MHz 622 624 ) 623 625 PORT MAP ( -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/led_controller_bahavior.vhd
r10074 r10075 21 21 ENTITY led_controller IS 22 22 GENERIC( 23 HEARTBEAT_DIVIDER : integer := 5000; -- 100kHz @ 50 MHz 24 WAITING_DIVIDER : integer := 50000000 -- 10Hz @ 50 MHz 23 HEARTBEAT_PWM_DIVIDER : integer := 500; -- 1kHz @ 50 MHz 24 MAX_DELAY : integer := 100; 25 WAITING_DIVIDER : integer := 500000000 -- 1Hz @ 50 MHz 25 26 ); 26 27 PORT( … … 116 117 -- can be switched off with heartbeat_en high 117 118 heartbeat : process (CLK) 118 variable Z: integer range 0 to HEARTBEAT_DIVIDER - 1 := 0; 119 variable X: integer range 1 to HEARTBEAT_DIVIDER - 2 := 1; 120 variable A: integer range 0 to 1000 := 0; 119 variable Z: integer range 0 to HEARTBEAT_PWM_DIVIDER - 1 := 0; 120 variable ON_TIME: integer range 0 to HEARTBEAT_PWM_DIVIDER - 1 := 0; 121 variable DELAY: integer range 0 to MAX_DELAY - 1 := 0; 122 variable DIR : std_logic := '1'; 121 123 122 124 begin 123 125 if rising_edge(CLK) then 124 if (Z < HEARTBEAT_ DIVIDER - 1) then126 if (Z < HEARTBEAT_PWM_DIVIDER - 1) then 125 127 Z := Z + 1; 126 128 else 127 129 Z := 0; 128 end if; 129 if (Z = 0) then 130 red_loc <= '1'; 131 if (A < 999) then 132 A := A + 1; 130 if (DELAY < MAX_DELAY - 1) then 131 DELAY := DELAY + 1; 133 132 else 134 A:= 0;133 DELAY := 0; 135 134 end if; 136 135 end if; 137 if (A = 0) then 138 if (X < HEARTBEAT_DIVIDER - 2) then 139 X := X + 1; 140 else 141 X := 1; 142 end if; 143 end if; 144 if (Z = X) then 136 137 138 if (Z = 0) then 139 if (DIR = '0') then -- count up 140 if (ON_TIME < HEARTBEAT_PWM_DIVIDER - 11) then 141 ON_TIME := ON_TIME + 10; 142 else 143 DIR := '1'; 144 end if; 145 else -- DIR is '1' -- count down 146 if (ON_TIME > 10) then 147 ON_TIME := ON_TIME - 10; 148 else 149 DIR := '0'; 150 end if; 151 end if; 152 end if; 153 154 if (Z = 0) then 155 red_loc <= '1'; 156 end if; 157 if (Z = ON_TIME) then 145 158 red_loc <= '0'; 146 159 end if; … … 154 167 begin 155 168 if rising_edge(CLK) then 156 if (Y < HEARTBEAT_DIVIDER - 1) then169 if (Y < WAITING_DIVIDER - 1) then 157 170 Y := Y + 1; 158 171 else -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf
r10074 r10075 606 606 DESIGN @f@a@d_@board 607 607 VIEW struct.bd 608 GRAPHIC 125 59,0 320 0608 GRAPHIC 12573,0 320 0 609 609 DESIGN @f@a@d_@board 610 610 VIEW struct.bd … … 618 618 DESIGN @f@a@d_@board 619 619 VIEW struct.bd 620 GRAPHIC 125 73,0 325 0620 GRAPHIC 12559,0 325 0 621 621 DESIGN @f@a@d_@board 622 622 VIEW struct.bd -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf
r10074 r10075 668 668 DESIGN @f@a@d_main 669 669 VIEW struct.bd 670 GRAPHIC 1 0675,0 322 0671 DESIGN @f@a@d_main 672 VIEW struct.bd 673 GRAPHIC 1 0682,0 323 1674 DESIGN @f@a@d_main 675 VIEW struct.bd 676 NO_GRAPHIC 33 5677 DESIGN @f@a@d_main 678 VIEW struct.bd 679 GRAPHIC 2311,0 33 70680 DESIGN memory_manager 681 VIEW symbol.sb 682 GRAPHIC 14,0 33 81683 DESIGN memory_manager 684 VIEW beha 685 GRAPHIC 138,0 34 30686 DESIGN memory_manager 687 VIEW beha 688 GRAPHIC 194,0 34 40689 DESIGN memory_manager 690 VIEW beha 691 GRAPHIC 349,0 34 50692 DESIGN memory_manager 693 VIEW beha 694 GRAPHIC 949,0 34 60695 DESIGN memory_manager 696 VIEW beha 697 GRAPHIC 569,0 34 80698 DESIGN memory_manager 699 VIEW beha 700 GRAPHIC 224,0 35 00701 DESIGN memory_manager 702 VIEW beha 703 GRAPHIC 254,0 35 10704 DESIGN memory_manager 705 VIEW beha 706 GRAPHIC 804,0 35 20707 DESIGN memory_manager 708 VIEW beha 709 GRAPHIC 433,0 35 30710 DESIGN memory_manager 711 VIEW beha 712 GRAPHIC 622,0 35 40713 DESIGN memory_manager 714 VIEW beha 715 GRAPHIC 289,0 35 50716 DESIGN memory_manager 717 VIEW beha 718 GRAPHIC 309,0 35 60719 DESIGN memory_manager 720 VIEW beha 721 GRAPHIC 284,0 35 70722 DESIGN memory_manager 723 VIEW beha 724 GRAPHIC 294,0 35 80725 DESIGN memory_manager 726 VIEW beha 727 GRAPHIC 304,0 3 590728 DESIGN memory_manager 729 VIEW beha 730 GRAPHIC 299,0 36 00731 DESIGN memory_manager 732 VIEW beha 733 GRAPHIC 379,0 36 10734 DESIGN memory_manager 735 VIEW beha 736 GRAPHIC 915,0 36 20737 DESIGN memory_manager 738 VIEW beha 739 GRAPHIC 51,0 36 30740 DESIGN @f@a@d_main 741 VIEW struct.bd 742 GRAPHIC 5793,0 36 60670 GRAPHIC 11209,0 322 0 671 DESIGN @f@a@d_main 672 VIEW struct.bd 673 GRAPHIC 11216,0 323 1 674 DESIGN @f@a@d_main 675 VIEW struct.bd 676 NO_GRAPHIC 336 677 DESIGN @f@a@d_main 678 VIEW struct.bd 679 GRAPHIC 2311,0 338 0 680 DESIGN memory_manager 681 VIEW symbol.sb 682 GRAPHIC 14,0 339 1 683 DESIGN memory_manager 684 VIEW beha 685 GRAPHIC 138,0 344 0 686 DESIGN memory_manager 687 VIEW beha 688 GRAPHIC 194,0 345 0 689 DESIGN memory_manager 690 VIEW beha 691 GRAPHIC 349,0 346 0 692 DESIGN memory_manager 693 VIEW beha 694 GRAPHIC 949,0 347 0 695 DESIGN memory_manager 696 VIEW beha 697 GRAPHIC 569,0 349 0 698 DESIGN memory_manager 699 VIEW beha 700 GRAPHIC 224,0 351 0 701 DESIGN memory_manager 702 VIEW beha 703 GRAPHIC 254,0 352 0 704 DESIGN memory_manager 705 VIEW beha 706 GRAPHIC 804,0 353 0 707 DESIGN memory_manager 708 VIEW beha 709 GRAPHIC 433,0 354 0 710 DESIGN memory_manager 711 VIEW beha 712 GRAPHIC 622,0 355 0 713 DESIGN memory_manager 714 VIEW beha 715 GRAPHIC 289,0 356 0 716 DESIGN memory_manager 717 VIEW beha 718 GRAPHIC 309,0 357 0 719 DESIGN memory_manager 720 VIEW beha 721 GRAPHIC 284,0 358 0 722 DESIGN memory_manager 723 VIEW beha 724 GRAPHIC 294,0 359 0 725 DESIGN memory_manager 726 VIEW beha 727 GRAPHIC 304,0 360 0 728 DESIGN memory_manager 729 VIEW beha 730 GRAPHIC 299,0 361 0 731 DESIGN memory_manager 732 VIEW beha 733 GRAPHIC 379,0 362 0 734 DESIGN memory_manager 735 VIEW beha 736 GRAPHIC 915,0 363 0 737 DESIGN memory_manager 738 VIEW beha 739 GRAPHIC 51,0 364 0 740 DESIGN @f@a@d_main 741 VIEW struct.bd 742 GRAPHIC 5793,0 367 0 743 743 DESIGN spi_interface 744 744 VIEW symbol.sb 745 GRAPHIC 1121,0 36 80745 GRAPHIC 1121,0 369 0 746 746 DESIGN spi_interface 747 747 VIEW symbol.sb 748 GRAPHIC 326,0 3 690748 GRAPHIC 326,0 370 0 749 749 DESIGN spi_interface 750 750 VIEW symbol.sb 751 GRAPHIC 197,0 37 00751 GRAPHIC 197,0 371 0 752 752 DESIGN spi_interface 753 753 VIEW symbol.sb 754 GRAPHIC 321,0 37 10754 GRAPHIC 321,0 372 0 755 755 DESIGN spi_interface 756 756 VIEW symbol.sb 757 GRAPHIC 1198,0 37 20757 GRAPHIC 1198,0 373 0 758 758 DESIGN spi_interface 759 759 VIEW symbol.sb 760 GRAPHIC 1017,0 37 30760 GRAPHIC 1017,0 374 0 761 761 DESIGN spi_interface 762 762 VIEW symbol.sb 763 GRAPHIC 1229,0 37 40763 GRAPHIC 1229,0 375 0 764 764 DESIGN spi_interface 765 765 VIEW symbol.sb 766 GRAPHIC 126,0 37 50766 GRAPHIC 126,0 376 0 767 767 DESIGN spi_interface 768 768 VIEW symbol.sb 769 GRAPHIC 819,0 37 60769 GRAPHIC 819,0 377 0 770 770 DESIGN spi_interface 771 771 VIEW symbol.sb 772 GRAPHIC 1022,0 37 70772 GRAPHIC 1022,0 378 0 773 773 DESIGN spi_interface 774 774 VIEW symbol.sb 775 GRAPHIC 824,0 37 80775 GRAPHIC 824,0 379 0 776 776 DESIGN spi_interface 777 777 VIEW symbol.sb 778 GRAPHIC 1283,0 3 790779 DESIGN @f@a@d_main 780 VIEW struct.bd 781 GRAPHIC 1768,0 38 20778 GRAPHIC 1283,0 380 0 779 DESIGN @f@a@d_main 780 VIEW struct.bd 781 GRAPHIC 1768,0 383 0 782 782 DESIGN trigger_counter 783 783 VIEW beha 784 GRAPHIC 48,0 38 40784 GRAPHIC 48,0 385 0 785 785 DESIGN trigger_counter 786 786 VIEW beha 787 GRAPHIC 53,0 38 50787 GRAPHIC 53,0 386 0 788 788 DESIGN trigger_counter 789 789 VIEW beha 790 GRAPHIC 148,0 38 60791 DESIGN @f@a@d_main 792 VIEW struct.bd 793 GRAPHIC 1606,0 3 890794 DESIGN w5300_modul 795 VIEW symbol.sb 796 GRAPHIC 14,0 39 01797 DESIGN w5300_modul 798 VIEW @behavioral 799 GRAPHIC 48,0 39 40800 DESIGN w5300_modul 801 VIEW @behavioral 802 GRAPHIC 53,0 39 50803 DESIGN w5300_modul 804 VIEW @behavioral 805 GRAPHIC 58,0 39 60806 DESIGN w5300_modul 807 VIEW @behavioral 808 GRAPHIC 63,0 39 70809 DESIGN w5300_modul 810 VIEW @behavioral 811 GRAPHIC 68,0 39 80812 DESIGN w5300_modul 813 VIEW @behavioral 814 GRAPHIC 73,0 3990815 DESIGN w5300_modul 816 VIEW @behavioral 817 GRAPHIC 491,0 40 00818 DESIGN w5300_modul 819 VIEW @behavioral 820 GRAPHIC 83,0 40 10821 DESIGN w5300_modul 822 VIEW @behavioral 823 GRAPHIC 88,0 40 20824 DESIGN w5300_modul 825 VIEW @behavioral 826 GRAPHIC 93,0 40 30827 DESIGN w5300_modul 828 VIEW @behavioral 829 GRAPHIC 98,0 40 40830 DESIGN w5300_modul 831 VIEW @behavioral 832 GRAPHIC 103,0 40 50833 DESIGN w5300_modul 834 VIEW @behavioral 835 GRAPHIC 108,0 40 60836 DESIGN w5300_modul 837 VIEW @behavioral 838 GRAPHIC 113,0 40 70839 DESIGN w5300_modul 840 VIEW @behavioral 841 GRAPHIC 885,0 40 80842 DESIGN w5300_modul 843 VIEW @behavioral 844 GRAPHIC 118,0 4 090845 DESIGN w5300_modul 846 VIEW @behavioral 847 GRAPHIC 353,0 41 00848 DESIGN w5300_modul 849 VIEW @behavioral 850 GRAPHIC 348,0 41 10851 DESIGN w5300_modul 852 VIEW @behavioral 853 GRAPHIC 385,0 41 20854 DESIGN w5300_modul 855 VIEW @behavioral 856 GRAPHIC 521,0 41 30857 DESIGN w5300_modul 858 VIEW @behavioral 859 GRAPHIC 576,0 41 40860 DESIGN w5300_modul 861 VIEW @behavioral 862 GRAPHIC 566,0 41 50863 DESIGN w5300_modul 864 VIEW @behavioral 865 GRAPHIC 551,0 41 60866 DESIGN w5300_modul 867 VIEW @behavioral 868 GRAPHIC 561,0 41 70869 DESIGN w5300_modul 870 VIEW @behavioral 871 GRAPHIC 571,0 41 80872 DESIGN w5300_modul 873 VIEW @behavioral 874 GRAPHIC 640,0 4 190875 DESIGN w5300_modul 876 VIEW @behavioral 877 GRAPHIC 1052,0 42 00878 DESIGN w5300_modul 879 VIEW @behavioral 880 GRAPHIC 1057,0 42 20881 DESIGN w5300_modul 882 VIEW @behavioral 883 GRAPHIC 556,0 42 40884 DESIGN w5300_modul 885 VIEW @behavioral 886 GRAPHIC 670,0 42 60887 DESIGN w5300_modul 888 VIEW @behavioral 889 GRAPHIC 723,0 42 70890 DESIGN w5300_modul 891 VIEW @behavioral 892 GRAPHIC 917,0 42 80893 DESIGN w5300_modul 894 VIEW @behavioral 895 GRAPHIC 949,0 4 290896 DESIGN w5300_modul 897 VIEW @behavioral 898 GRAPHIC 954,0 43 00899 DESIGN w5300_modul 900 VIEW @behavioral 901 GRAPHIC 988,0 43 10902 DESIGN w5300_modul 903 VIEW @behavioral 904 GRAPHIC 1020,0 43 20905 DESIGN w5300_modul 906 VIEW @behavioral 907 GRAPHIC 1096,0 43 30908 DESIGN w5300_modul 909 VIEW @behavioral 910 GRAPHIC 1091,0 43 40790 GRAPHIC 148,0 387 0 791 DESIGN @f@a@d_main 792 VIEW struct.bd 793 GRAPHIC 1606,0 390 0 794 DESIGN w5300_modul 795 VIEW symbol.sb 796 GRAPHIC 14,0 391 1 797 DESIGN w5300_modul 798 VIEW @behavioral 799 GRAPHIC 48,0 395 0 800 DESIGN w5300_modul 801 VIEW @behavioral 802 GRAPHIC 53,0 396 0 803 DESIGN w5300_modul 804 VIEW @behavioral 805 GRAPHIC 58,0 397 0 806 DESIGN w5300_modul 807 VIEW @behavioral 808 GRAPHIC 63,0 398 0 809 DESIGN w5300_modul 810 VIEW @behavioral 811 GRAPHIC 68,0 399 0 812 DESIGN w5300_modul 813 VIEW @behavioral 814 GRAPHIC 73,0 400 0 815 DESIGN w5300_modul 816 VIEW @behavioral 817 GRAPHIC 491,0 401 0 818 DESIGN w5300_modul 819 VIEW @behavioral 820 GRAPHIC 83,0 402 0 821 DESIGN w5300_modul 822 VIEW @behavioral 823 GRAPHIC 88,0 403 0 824 DESIGN w5300_modul 825 VIEW @behavioral 826 GRAPHIC 93,0 404 0 827 DESIGN w5300_modul 828 VIEW @behavioral 829 GRAPHIC 98,0 405 0 830 DESIGN w5300_modul 831 VIEW @behavioral 832 GRAPHIC 103,0 406 0 833 DESIGN w5300_modul 834 VIEW @behavioral 835 GRAPHIC 108,0 407 0 836 DESIGN w5300_modul 837 VIEW @behavioral 838 GRAPHIC 113,0 408 0 839 DESIGN w5300_modul 840 VIEW @behavioral 841 GRAPHIC 885,0 409 0 842 DESIGN w5300_modul 843 VIEW @behavioral 844 GRAPHIC 118,0 410 0 845 DESIGN w5300_modul 846 VIEW @behavioral 847 GRAPHIC 353,0 411 0 848 DESIGN w5300_modul 849 VIEW @behavioral 850 GRAPHIC 348,0 412 0 851 DESIGN w5300_modul 852 VIEW @behavioral 853 GRAPHIC 385,0 413 0 854 DESIGN w5300_modul 855 VIEW @behavioral 856 GRAPHIC 521,0 414 0 857 DESIGN w5300_modul 858 VIEW @behavioral 859 GRAPHIC 576,0 415 0 860 DESIGN w5300_modul 861 VIEW @behavioral 862 GRAPHIC 566,0 416 0 863 DESIGN w5300_modul 864 VIEW @behavioral 865 GRAPHIC 551,0 417 0 866 DESIGN w5300_modul 867 VIEW @behavioral 868 GRAPHIC 561,0 418 0 869 DESIGN w5300_modul 870 VIEW @behavioral 871 GRAPHIC 571,0 419 0 872 DESIGN w5300_modul 873 VIEW @behavioral 874 GRAPHIC 640,0 420 0 875 DESIGN w5300_modul 876 VIEW @behavioral 877 GRAPHIC 1052,0 421 0 878 DESIGN w5300_modul 879 VIEW @behavioral 880 GRAPHIC 1057,0 423 0 881 DESIGN w5300_modul 882 VIEW @behavioral 883 GRAPHIC 556,0 425 0 884 DESIGN w5300_modul 885 VIEW @behavioral 886 GRAPHIC 670,0 427 0 887 DESIGN w5300_modul 888 VIEW @behavioral 889 GRAPHIC 723,0 428 0 890 DESIGN w5300_modul 891 VIEW @behavioral 892 GRAPHIC 917,0 429 0 893 DESIGN w5300_modul 894 VIEW @behavioral 895 GRAPHIC 949,0 430 0 896 DESIGN w5300_modul 897 VIEW @behavioral 898 GRAPHIC 954,0 431 0 899 DESIGN w5300_modul 900 VIEW @behavioral 901 GRAPHIC 988,0 432 0 902 DESIGN w5300_modul 903 VIEW @behavioral 904 GRAPHIC 1020,0 433 0 905 DESIGN w5300_modul 906 VIEW @behavioral 907 GRAPHIC 1096,0 434 0 908 DESIGN w5300_modul 909 VIEW @behavioral 910 GRAPHIC 1091,0 435 0 911 911 LIBRARY FACT_FAD_lib 912 912 DESIGN @f@a@d_main 913 913 VIEW struct.bd 914 NO_GRAPHIC 43 7915 DESIGN @f@a@d_main 916 VIEW struct.bd 917 GRAPHIC 5678,0 44 00918 DESIGN @f@a@d_main 919 VIEW struct.bd 920 GRAPHIC 9175,0 44 10921 DESIGN @f@a@d_main 922 VIEW struct.bd 923 GRAPHIC 5072,0 44 20924 DESIGN @f@a@d_main 925 VIEW struct.bd 926 GRAPHIC 8277,0 44 30927 DESIGN @f@a@d_main 928 VIEW struct.bd 929 GRAPHIC 1399,0 44 40930 DESIGN @f@a@d_main 931 VIEW struct.bd 932 GRAPHIC 4903,0 44 50933 DESIGN @f@a@d_main 934 VIEW struct.bd 935 GRAPHIC 1 0675,0 4460936 DESIGN @f@a@d_main 937 VIEW struct.bd 938 GRAPHIC 2311,0 44 70939 DESIGN @f@a@d_main 940 VIEW struct.bd 941 GRAPHIC 5793,0 44 80942 DESIGN @f@a@d_main 943 VIEW struct.bd 944 GRAPHIC 1768,0 4 490945 DESIGN @f@a@d_main 946 VIEW struct.bd 947 GRAPHIC 1606,0 45 00948 DESIGN @f@a@d_main 949 VIEW struct.bd 950 NO_GRAPHIC 45 3951 DESIGN @f@a@d_main 952 VIEW struct.bd 953 GRAPHIC 6529,0 45 50954 DESIGN @f@a@d_main 955 VIEW struct.bd 956 GRAPHIC 9957,0 45 80957 DESIGN @f@a@d_main 958 VIEW struct.bd 959 GRAPHIC 8721,0 46 10960 DESIGN @f@a@d_main 961 VIEW struct.bd 962 GRAPHIC 9430,0 46 40963 DESIGN @f@a@d_main 964 VIEW struct.bd 965 GRAPHIC 9472,0 46 70966 DESIGN @f@a@d_main 967 VIEW struct.bd 968 GRAPHIC 9662,0 47 00969 DESIGN @f@a@d_main 970 VIEW struct.bd 971 GRAPHIC 9679,0 47 30972 DESIGN @f@a@d_main 973 VIEW struct.bd 974 GRAPHIC 9710,0 47 60975 DESIGN @f@a@d_main 976 VIEW struct.bd 977 GRAPHIC 8562,0 4 790978 DESIGN @f@a@d_main 979 VIEW struct.bd 980 GRAPHIC 10380,0 49 00981 DESIGN @f@a@d_main 982 VIEW struct.bd 983 NO_GRAPHIC 49 3984 DESIGN @f@a@d_main 985 VIEW struct.bd 986 GRAPHIC 5678,0 49 50987 DESIGN @f@a@d_main 988 VIEW struct.bd 989 GRAPHIC 5646,0 49 70990 DESIGN @f@a@d_main 991 VIEW struct.bd 992 GRAPHIC 4272,0 49 80993 DESIGN @f@a@d_main 994 VIEW struct.bd 995 GRAPHIC 2786,0 4990996 DESIGN @f@a@d_main 997 VIEW struct.bd 998 GRAPHIC 5626,0 50 00999 DESIGN @f@a@d_main 1000 VIEW struct.bd 1001 GRAPHIC 5634,0 50 101002 DESIGN @f@a@d_main 1003 VIEW struct.bd 1004 GRAPHIC 9175,0 50 301005 DESIGN @f@a@d_main 1006 VIEW struct.bd 1007 GRAPHIC 4042,0 50 501008 DESIGN @f@a@d_main 1009 VIEW struct.bd 1010 GRAPHIC 10036,0 50 601011 DESIGN @f@a@d_main 1012 VIEW struct.bd 1013 GRAPHIC 9253,0 50 701014 DESIGN @f@a@d_main 1015 VIEW struct.bd 1016 GRAPHIC 9261,0 50 801017 DESIGN @f@a@d_main 1018 VIEW struct.bd 1019 GRAPHIC 6072,0 5 0901020 DESIGN @f@a@d_main 1021 VIEW struct.bd 1022 GRAPHIC 3984,0 51 001023 DESIGN @f@a@d_main 1024 VIEW struct.bd 1025 GRAPHIC 3888,0 51 101026 DESIGN @f@a@d_main 1027 VIEW struct.bd 1028 GRAPHIC 9353,0 51 201029 DESIGN @f@a@d_main 1030 VIEW struct.bd 1031 GRAPHIC 9269,0 51 301032 DESIGN @f@a@d_main 1033 VIEW struct.bd 1034 GRAPHIC 9325,0 51 401035 DESIGN @f@a@d_main 1036 VIEW struct.bd 1037 GRAPHIC 9283,0 51 501038 DESIGN @f@a@d_main 1039 VIEW struct.bd 1040 GRAPHIC 9311,0 51 601041 DESIGN @f@a@d_main 1042 VIEW struct.bd 1043 GRAPHIC 9297,0 51 701044 DESIGN @f@a@d_main 1045 VIEW struct.bd 1046 GRAPHIC 9367,0 51 801047 DESIGN @f@a@d_main 1048 VIEW struct.bd 1049 GRAPHIC 9397,0 5 1901050 DESIGN @f@a@d_main 1051 VIEW struct.bd 1052 GRAPHIC 9382,0 52 001053 DESIGN @f@a@d_main 1054 VIEW struct.bd 1055 GRAPHIC 5072,0 52 201056 DESIGN @f@a@d_main 1057 VIEW struct.bd 1058 GRAPHIC 5582,0 52 401059 DESIGN @f@a@d_main 1060 VIEW struct.bd 1061 GRAPHIC 5090,0 52 501062 DESIGN @f@a@d_main 1063 VIEW struct.bd 1064 GRAPHIC 5130,0 52 601065 DESIGN @f@a@d_main 1066 VIEW struct.bd 1067 GRAPHIC 5184,0 52 701068 DESIGN @f@a@d_main 1069 VIEW struct.bd 1070 GRAPHIC 5122,0 52 801071 DESIGN @f@a@d_main 1072 VIEW struct.bd 1073 GRAPHIC 5106,0 5 2901074 DESIGN @f@a@d_main 1075 VIEW struct.bd 1076 GRAPHIC 5098,0 53 001077 DESIGN @f@a@d_main 1078 VIEW struct.bd 1079 GRAPHIC 5190,0 53 101080 DESIGN @f@a@d_main 1081 VIEW struct.bd 1082 GRAPHIC 10194,0 53 201083 DESIGN @f@a@d_main 1084 VIEW struct.bd 1085 GRAPHIC 10202,0 53 301086 DESIGN @f@a@d_main 1087 VIEW struct.bd 1088 GRAPHIC 6002,0 53 401089 DESIGN @f@a@d_main 1090 VIEW struct.bd 1091 GRAPHIC 5146,0 53 501092 DESIGN @f@a@d_main 1093 VIEW struct.bd 1094 GRAPHIC 5138,0 53 601095 DESIGN @f@a@d_main 1096 VIEW struct.bd 1097 GRAPHIC 5114,0 53 701098 DESIGN @f@a@d_main 1099 VIEW struct.bd 1100 GRAPHIC 8277,0 5 3901101 DESIGN @f@a@d_main 1102 VIEW struct.bd 1103 GRAPHIC 5602,0 54 101104 DESIGN @f@a@d_main 1105 VIEW struct.bd 1106 GRAPHIC 334,0 54 201107 DESIGN @f@a@d_main 1108 VIEW struct.bd 1109 GRAPHIC 328,0 54 301110 DESIGN @f@a@d_main 1111 VIEW struct.bd 1112 GRAPHIC 322,0 54 401113 DESIGN @f@a@d_main 1114 VIEW struct.bd 1115 GRAPHIC 4240,0 54 501116 DESIGN @f@a@d_main 1117 VIEW struct.bd 1118 GRAPHIC 364,0 54 601119 DESIGN @f@a@d_main 1120 VIEW struct.bd 1121 GRAPHIC 370,0 54 701122 DESIGN @f@a@d_main 1123 VIEW struct.bd 1124 GRAPHIC 1399,0 5 4901125 DESIGN @f@a@d_main 1126 VIEW struct.bd 1127 GRAPHIC 1406,0 55 011128 DESIGN @f@a@d_main 1129 VIEW struct.bd 1130 GRAPHIC 5602,0 55 401131 DESIGN @f@a@d_main 1132 VIEW struct.bd 1133 GRAPHIC 334,0 55 501134 DESIGN @f@a@d_main 1135 VIEW struct.bd 1136 GRAPHIC 328,0 55 601137 DESIGN @f@a@d_main 1138 VIEW struct.bd 1139 GRAPHIC 322,0 55 701140 DESIGN @f@a@d_main 1141 VIEW struct.bd 1142 GRAPHIC 2299,0 55 801143 DESIGN @f@a@d_main 1144 VIEW struct.bd 1145 GRAPHIC 2576,0 5 5901146 DESIGN @f@a@d_main 1147 VIEW struct.bd 1148 GRAPHIC 2582,0 56 001149 DESIGN @f@a@d_main 1150 VIEW struct.bd 1151 GRAPHIC 10467,0 56 101152 DESIGN @f@a@d_main 1153 VIEW struct.bd 1154 GRAPHIC 2588,0 56 201155 DESIGN @f@a@d_main 1156 VIEW struct.bd 1157 GRAPHIC 5184,0 56 301158 DESIGN @f@a@d_main 1159 VIEW struct.bd 1160 GRAPHIC 5745,0 56 401161 DESIGN @f@a@d_main 1162 VIEW struct.bd 1163 GRAPHIC 2594,0 56 501164 DESIGN @f@a@d_main 1165 VIEW struct.bd 1166 GRAPHIC 5190,0 56 601167 DESIGN @f@a@d_main 1168 VIEW struct.bd 1169 GRAPHIC 5404,0 56 701170 DESIGN @f@a@d_main 1171 VIEW struct.bd 1172 GRAPHIC 6018,0 56 801173 DESIGN @f@a@d_main 1174 VIEW struct.bd 1175 GRAPHIC 6002,0 5 6901176 DESIGN @f@a@d_main 1177 VIEW struct.bd 1178 GRAPHIC 6008,0 57 001179 DESIGN @f@a@d_main 1180 VIEW struct.bd 1181 GRAPHIC 5138,0 57 101182 DESIGN @f@a@d_main 1183 VIEW struct.bd 1184 GRAPHIC 2600,0 57 201185 DESIGN @f@a@d_main 1186 VIEW struct.bd 1187 GRAPHIC 5480,0 57 301188 DESIGN @f@a@d_main 1189 VIEW struct.bd 1190 GRAPHIC 5474,0 57 401191 DESIGN @f@a@d_main 1192 VIEW struct.bd 1193 GRAPHIC 6064,0 57 501194 DESIGN @f@a@d_main 1195 VIEW struct.bd 1196 GRAPHIC 2642,0 57 601197 DESIGN @f@a@d_main 1198 VIEW struct.bd 1199 GRAPHIC 1411,0 57 701200 DESIGN @f@a@d_main 1201 VIEW struct.bd 1202 GRAPHIC 1682,0 57 801203 DESIGN @f@a@d_main 1204 VIEW struct.bd 1205 GRAPHIC 1983,0 5 7901206 DESIGN @f@a@d_main 1207 VIEW struct.bd 1208 GRAPHIC 10439,0 58 001209 DESIGN @f@a@d_main 1210 VIEW struct.bd 1211 GRAPHIC 5950,0 58 101212 DESIGN @f@a@d_main 1213 VIEW struct.bd 1214 GRAPHIC 5962,0 58 201215 DESIGN @f@a@d_main 1216 VIEW struct.bd 1217 GRAPHIC 5626,0 58 301218 DESIGN @f@a@d_main 1219 VIEW struct.bd 1220 GRAPHIC 2778,0 58 401221 DESIGN @f@a@d_main 1222 VIEW struct.bd 1223 GRAPHIC 9006,0 58 501224 DESIGN @f@a@d_main 1225 VIEW struct.bd 1226 GRAPHIC 5634,0 58 601227 DESIGN @f@a@d_main 1228 VIEW struct.bd 1229 GRAPHIC 8577,0 58 701230 DESIGN @f@a@d_main 1231 VIEW struct.bd 1232 GRAPHIC 6540,0 58 801233 DESIGN @f@a@d_main 1234 VIEW struct.bd 1235 GRAPHIC 4401,0 5 8901236 DESIGN @f@a@d_main 1237 VIEW struct.bd 1238 GRAPHIC 4419,0 59 001239 DESIGN @f@a@d_main 1240 VIEW struct.bd 1241 GRAPHIC 10298,0 59 101242 DESIGN @f@a@d_main 1243 VIEW struct.bd 1244 GRAPHIC 10304,0 59 201245 DESIGN @f@a@d_main 1246 VIEW struct.bd 1247 GRAPHIC 10316,0 59 301248 DESIGN @f@a@d_main 1249 VIEW struct.bd 1250 GRAPHIC 10310,0 59 401251 DESIGN @f@a@d_main 1252 VIEW struct.bd 1253 GRAPHIC 4743,0 59 501254 DESIGN @f@a@d_main 1255 VIEW struct.bd 1256 GRAPHIC 4407,0 59 601257 DESIGN @f@a@d_main 1258 VIEW struct.bd 1259 GRAPHIC 4903,0 59 801260 DESIGN @f@a@d_main 1261 VIEW struct.bd 1262 GRAPHIC 4757,0 60 001263 DESIGN @f@a@d_main 1264 VIEW struct.bd 1265 GRAPHIC 4401,0 60 101266 DESIGN @f@a@d_main 1267 VIEW struct.bd 1268 GRAPHIC 4419,0 60 201269 DESIGN @f@a@d_main 1270 VIEW struct.bd 1271 GRAPHIC 4671,0 60 301272 DESIGN @f@a@d_main 1273 VIEW struct.bd 1274 GRAPHIC 4679,0 60 401275 DESIGN @f@a@d_main 1276 VIEW struct.bd 1277 GRAPHIC 4687,0 60 501278 DESIGN @f@a@d_main 1279 VIEW struct.bd 1280 GRAPHIC 4695,0 60 601281 DESIGN @f@a@d_main 1282 VIEW struct.bd 1283 GRAPHIC 4407,0 60 701284 DESIGN @f@a@d_main 1285 VIEW struct.bd 1286 GRAPHIC 4743,0 60 801287 DESIGN @f@a@d_main 1288 VIEW struct.bd 1289 GRAPHIC 10298,0 6 0901290 DESIGN @f@a@d_main 1291 VIEW struct.bd 1292 GRAPHIC 10310,0 61 001293 DESIGN @f@a@d_main 1294 VIEW struct.bd 1295 GRAPHIC 10304,0 61 101296 DESIGN @f@a@d_main 1297 VIEW struct.bd 1298 GRAPHIC 10316,0 61 201299 DESIGN @f@a@d_main 1300 VIEW struct.bd 1301 GRAPHIC 10322,0 61 301302 DESIGN @f@a@d_main 1303 VIEW struct.bd 1304 GRAPHIC 4948,0 61 401305 DESIGN @f@a@d_main 1306 VIEW struct.bd 1307 GRAPHIC 10010,0 61 501308 DESIGN @f@a@d_main 1309 VIEW struct.bd 1310 GRAPHIC 1 0675,0 61701311 DESIGN @f@a@d_main 1312 VIEW struct.bd 1313 GRAPHIC 1 0682,0 61811314 DESIGN @f@a@d_main 1315 VIEW struct.bd 1316 GRAPHIC 10699,0 62 301317 DESIGN @f@a@d_main 1318 VIEW struct.bd 1319 GRAPHIC 10723,0 62 401320 DESIGN @f@a@d_main 1321 VIEW struct.bd 1322 GRAPHIC 10737,0 62 501323 DESIGN @f@a@d_main 1324 VIEW struct.bd 1325 GRAPHIC 10751,0 62 601326 DESIGN @f@a@d_main 1327 VIEW struct.bd 1328 GRAPHIC 10707,0 62 701329 DESIGN @f@a@d_main 1330 VIEW struct.bd 1331 GRAPHIC 10685,0 6 2801332 DESIGN @f@a@d_main 1333 VIEW struct.bd 1334 GRAPHIC 10691,0 6 2901335 DESIGN @f@a@d_main 1336 VIEW struct.bd 1337 GRAPHIC 2311,0 63 101338 DESIGN @f@a@d_main 1339 VIEW struct.bd 1340 GRAPHIC 2318,0 63 211341 DESIGN @f@a@d_main 1342 VIEW struct.bd 1343 GRAPHIC 6082,0 63 701344 DESIGN @f@a@d_main 1345 VIEW struct.bd 1346 GRAPHIC 2588,0 6 3801347 DESIGN @f@a@d_main 1348 VIEW struct.bd 1349 GRAPHIC 2582,0 6 3901350 DESIGN @f@a@d_main 1351 VIEW struct.bd 1352 GRAPHIC 10467,0 64 001353 DESIGN @f@a@d_main 1354 VIEW struct.bd 1355 GRAPHIC 5168,0 64 101356 DESIGN @f@a@d_main 1357 VIEW struct.bd 1358 GRAPHIC 2576,0 64 201359 DESIGN @f@a@d_main 1360 VIEW struct.bd 1361 GRAPHIC 2594,0 64 301362 DESIGN @f@a@d_main 1363 VIEW struct.bd 1364 GRAPHIC 6018,0 64 401365 DESIGN @f@a@d_main 1366 VIEW struct.bd 1367 GRAPHIC 2600,0 64 501368 DESIGN @f@a@d_main 1369 VIEW struct.bd 1370 GRAPHIC 2642,0 64 601371 DESIGN @f@a@d_main 1372 VIEW struct.bd 1373 GRAPHIC 2488,0 64 701374 DESIGN @f@a@d_main 1375 VIEW struct.bd 1376 GRAPHIC 2482,0 6 4801377 DESIGN @f@a@d_main 1378 VIEW struct.bd 1379 GRAPHIC 2494,0 6 4901380 DESIGN @f@a@d_main 1381 VIEW struct.bd 1382 GRAPHIC 2476,0 65 001383 DESIGN @f@a@d_main 1384 VIEW struct.bd 1385 GRAPHIC 2506,0 65 101386 DESIGN @f@a@d_main 1387 VIEW struct.bd 1388 GRAPHIC 2500,0 65 201389 DESIGN @f@a@d_main 1390 VIEW struct.bd 1391 GRAPHIC 2470,0 65 301392 DESIGN @f@a@d_main 1393 VIEW struct.bd 1394 GRAPHIC 8416,0 65 401395 DESIGN @f@a@d_main 1396 VIEW struct.bd 1397 GRAPHIC 2299,0 65 501398 DESIGN @f@a@d_main 1399 VIEW struct.bd 1400 GRAPHIC 5793,0 65 701401 DESIGN @f@a@d_main 1402 VIEW struct.bd 1403 GRAPHIC 5805,0 6 5901404 DESIGN @f@a@d_main 1405 VIEW struct.bd 1406 GRAPHIC 5745,0 66 001407 DESIGN @f@a@d_main 1408 VIEW struct.bd 1409 GRAPHIC 5146,0 66 101410 DESIGN @f@a@d_main 1411 VIEW struct.bd 1412 GRAPHIC 5404,0 66 201413 DESIGN @f@a@d_main 1414 VIEW struct.bd 1415 GRAPHIC 6008,0 66 301416 DESIGN @f@a@d_main 1417 VIEW struct.bd 1418 GRAPHIC 5829,0 66 401419 DESIGN @f@a@d_main 1420 VIEW struct.bd 1421 GRAPHIC 6160,0 66 501422 DESIGN @f@a@d_main 1423 VIEW struct.bd 1424 GRAPHIC 8732,0 66 601425 DESIGN @f@a@d_main 1426 VIEW struct.bd 1427 GRAPHIC 5480,0 66 701428 DESIGN @f@a@d_main 1429 VIEW struct.bd 1430 GRAPHIC 5837,0 6 6801431 DESIGN @f@a@d_main 1432 VIEW struct.bd 1433 GRAPHIC 5474,0 6 6901434 DESIGN @f@a@d_main 1435 VIEW struct.bd 1436 GRAPHIC 5821,0 67 001437 DESIGN @f@a@d_main 1438 VIEW struct.bd 1439 GRAPHIC 1768,0 67 201440 DESIGN @f@a@d_main 1441 VIEW struct.bd 1442 GRAPHIC 1983,0 67 401443 DESIGN @f@a@d_main 1444 VIEW struct.bd 1445 GRAPHIC 10443,0 67 501446 DESIGN @f@a@d_main 1447 VIEW struct.bd 1448 GRAPHIC 6276,0 67 601449 DESIGN @f@a@d_main 1450 VIEW struct.bd 1451 GRAPHIC 1606,0 6 7801452 DESIGN @f@a@d_main 1453 VIEW struct.bd 1454 GRAPHIC 1613,0 6 7911455 DESIGN @f@a@d_main 1456 VIEW struct.bd 1457 GRAPHIC 3888,0 68 301458 DESIGN @f@a@d_main 1459 VIEW struct.bd 1460 GRAPHIC 376,0 68 401461 DESIGN @f@a@d_main 1462 VIEW struct.bd 1463 GRAPHIC 384,0 68 501464 DESIGN @f@a@d_main 1465 VIEW struct.bd 1466 GRAPHIC 392,0 68 601467 DESIGN @f@a@d_main 1468 VIEW struct.bd 1469 GRAPHIC 400,0 68 701470 DESIGN @f@a@d_main 1471 VIEW struct.bd 1472 GRAPHIC 408,0 6 8801473 DESIGN @f@a@d_main 1474 VIEW struct.bd 1475 GRAPHIC 5222,0 6 8901476 DESIGN @f@a@d_main 1477 VIEW struct.bd 1478 GRAPHIC 424,0 69 001479 DESIGN @f@a@d_main 1480 VIEW struct.bd 1481 GRAPHIC 432,0 69 101482 DESIGN @f@a@d_main 1483 VIEW struct.bd 1484 GRAPHIC 2482,0 69 201485 DESIGN @f@a@d_main 1486 VIEW struct.bd 1487 GRAPHIC 2488,0 69 301488 DESIGN @f@a@d_main 1489 VIEW struct.bd 1490 GRAPHIC 370,0 69 401491 DESIGN @f@a@d_main 1492 VIEW struct.bd 1493 GRAPHIC 364,0 69 501494 DESIGN @f@a@d_main 1495 VIEW struct.bd 1496 GRAPHIC 2476,0 69 601497 DESIGN @f@a@d_main 1498 VIEW struct.bd 1499 GRAPHIC 8416,0 69 701500 DESIGN @f@a@d_main 1501 VIEW struct.bd 1502 GRAPHIC 2470,0 69801503 DESIGN @f@a@d_main 1504 VIEW struct.bd 1505 GRAPHIC 2506,0 69901506 DESIGN @f@a@d_main 1507 VIEW struct.bd 1508 GRAPHIC 2500,0 70 001509 DESIGN @f@a@d_main 1510 VIEW struct.bd 1511 GRAPHIC 2494,0 70 101512 DESIGN @f@a@d_main 1513 VIEW struct.bd 1514 GRAPHIC 10266,0 70 201515 DESIGN @f@a@d_main 1516 VIEW struct.bd 1517 GRAPHIC 5950,0 70 301518 DESIGN @f@a@d_main 1519 VIEW struct.bd 1520 GRAPHIC 5962,0 70 401521 DESIGN @f@a@d_main 1522 VIEW struct.bd 1523 GRAPHIC 5090,0 70 501524 DESIGN @f@a@d_main 1525 VIEW struct.bd 1526 GRAPHIC 5114,0 70 601527 DESIGN @f@a@d_main 1528 VIEW struct.bd 1529 GRAPHIC 5122,0 70 701530 DESIGN @f@a@d_main 1531 VIEW struct.bd 1532 GRAPHIC 5130,0 7 0801533 DESIGN @f@a@d_main 1534 VIEW struct.bd 1535 GRAPHIC 10194,0 7 0901536 DESIGN @f@a@d_main 1537 VIEW struct.bd 1538 GRAPHIC 10202,0 71 001539 DESIGN @f@a@d_main 1540 VIEW struct.bd 1541 GRAPHIC 5106,0 71 101542 DESIGN @f@a@d_main 1543 VIEW struct.bd 1544 GRAPHIC 6362,0 71 201545 DESIGN @f@a@d_main 1546 VIEW struct.bd 1547 GRAPHIC 6452,0 71 301548 DESIGN @f@a@d_main 1549 VIEW struct.bd 1550 GRAPHIC 8752,0 71 401551 DESIGN @f@a@d_main 1552 VIEW struct.bd 1553 GRAPHIC 9233,0 71 501554 DESIGN @f@a@d_main 1555 VIEW struct.bd 1556 GRAPHIC 9241,0 71 601557 DESIGN @f@a@d_main 1558 VIEW struct.bd 1559 GRAPHIC 9943,0 71 701560 DESIGN @f@a@d_main 1561 VIEW struct.bd 1562 GRAPHIC 9951,0 7 1801563 DESIGN @f@a@d_main 1564 VIEW struct.bd 1565 GRAPHIC 10637,0 7 1901566 DESIGN @f@a@d_main 1567 VIEW struct.bd 1568 GRAPHIC 10629,0 72 001569 DESIGN @f@a@d_main 1570 VIEW struct.bd 1571 GRAPHIC 6276,0 72 401572 DESIGN @f@a@d_main 1573 VIEW struct.bd 1574 GRAPHIC 3888,0 72 501575 DESIGN @f@a@d_main 1576 VIEW struct.bd 1577 NO_GRAPHIC 72 7914 NO_GRAPHIC 438 915 DESIGN @f@a@d_main 916 VIEW struct.bd 917 GRAPHIC 5678,0 441 0 918 DESIGN @f@a@d_main 919 VIEW struct.bd 920 GRAPHIC 9175,0 442 0 921 DESIGN @f@a@d_main 922 VIEW struct.bd 923 GRAPHIC 5072,0 443 0 924 DESIGN @f@a@d_main 925 VIEW struct.bd 926 GRAPHIC 8277,0 444 0 927 DESIGN @f@a@d_main 928 VIEW struct.bd 929 GRAPHIC 1399,0 445 0 930 DESIGN @f@a@d_main 931 VIEW struct.bd 932 GRAPHIC 4903,0 446 0 933 DESIGN @f@a@d_main 934 VIEW struct.bd 935 GRAPHIC 11209,0 447 0 936 DESIGN @f@a@d_main 937 VIEW struct.bd 938 GRAPHIC 2311,0 448 0 939 DESIGN @f@a@d_main 940 VIEW struct.bd 941 GRAPHIC 5793,0 449 0 942 DESIGN @f@a@d_main 943 VIEW struct.bd 944 GRAPHIC 1768,0 450 0 945 DESIGN @f@a@d_main 946 VIEW struct.bd 947 GRAPHIC 1606,0 451 0 948 DESIGN @f@a@d_main 949 VIEW struct.bd 950 NO_GRAPHIC 454 951 DESIGN @f@a@d_main 952 VIEW struct.bd 953 GRAPHIC 6529,0 456 0 954 DESIGN @f@a@d_main 955 VIEW struct.bd 956 GRAPHIC 9957,0 459 0 957 DESIGN @f@a@d_main 958 VIEW struct.bd 959 GRAPHIC 8721,0 462 0 960 DESIGN @f@a@d_main 961 VIEW struct.bd 962 GRAPHIC 9430,0 465 0 963 DESIGN @f@a@d_main 964 VIEW struct.bd 965 GRAPHIC 9472,0 468 0 966 DESIGN @f@a@d_main 967 VIEW struct.bd 968 GRAPHIC 9662,0 471 0 969 DESIGN @f@a@d_main 970 VIEW struct.bd 971 GRAPHIC 9679,0 474 0 972 DESIGN @f@a@d_main 973 VIEW struct.bd 974 GRAPHIC 9710,0 477 0 975 DESIGN @f@a@d_main 976 VIEW struct.bd 977 GRAPHIC 8562,0 480 0 978 DESIGN @f@a@d_main 979 VIEW struct.bd 980 GRAPHIC 10380,0 491 0 981 DESIGN @f@a@d_main 982 VIEW struct.bd 983 NO_GRAPHIC 494 984 DESIGN @f@a@d_main 985 VIEW struct.bd 986 GRAPHIC 5678,0 496 0 987 DESIGN @f@a@d_main 988 VIEW struct.bd 989 GRAPHIC 5646,0 498 0 990 DESIGN @f@a@d_main 991 VIEW struct.bd 992 GRAPHIC 4272,0 499 0 993 DESIGN @f@a@d_main 994 VIEW struct.bd 995 GRAPHIC 2786,0 500 0 996 DESIGN @f@a@d_main 997 VIEW struct.bd 998 GRAPHIC 5626,0 501 0 999 DESIGN @f@a@d_main 1000 VIEW struct.bd 1001 GRAPHIC 5634,0 502 0 1002 DESIGN @f@a@d_main 1003 VIEW struct.bd 1004 GRAPHIC 9175,0 504 0 1005 DESIGN @f@a@d_main 1006 VIEW struct.bd 1007 GRAPHIC 4042,0 506 0 1008 DESIGN @f@a@d_main 1009 VIEW struct.bd 1010 GRAPHIC 10036,0 507 0 1011 DESIGN @f@a@d_main 1012 VIEW struct.bd 1013 GRAPHIC 9253,0 508 0 1014 DESIGN @f@a@d_main 1015 VIEW struct.bd 1016 GRAPHIC 9261,0 509 0 1017 DESIGN @f@a@d_main 1018 VIEW struct.bd 1019 GRAPHIC 6072,0 510 0 1020 DESIGN @f@a@d_main 1021 VIEW struct.bd 1022 GRAPHIC 3984,0 511 0 1023 DESIGN @f@a@d_main 1024 VIEW struct.bd 1025 GRAPHIC 3888,0 512 0 1026 DESIGN @f@a@d_main 1027 VIEW struct.bd 1028 GRAPHIC 9353,0 513 0 1029 DESIGN @f@a@d_main 1030 VIEW struct.bd 1031 GRAPHIC 9269,0 514 0 1032 DESIGN @f@a@d_main 1033 VIEW struct.bd 1034 GRAPHIC 9325,0 515 0 1035 DESIGN @f@a@d_main 1036 VIEW struct.bd 1037 GRAPHIC 9283,0 516 0 1038 DESIGN @f@a@d_main 1039 VIEW struct.bd 1040 GRAPHIC 9311,0 517 0 1041 DESIGN @f@a@d_main 1042 VIEW struct.bd 1043 GRAPHIC 9297,0 518 0 1044 DESIGN @f@a@d_main 1045 VIEW struct.bd 1046 GRAPHIC 9367,0 519 0 1047 DESIGN @f@a@d_main 1048 VIEW struct.bd 1049 GRAPHIC 9397,0 520 0 1050 DESIGN @f@a@d_main 1051 VIEW struct.bd 1052 GRAPHIC 9382,0 521 0 1053 DESIGN @f@a@d_main 1054 VIEW struct.bd 1055 GRAPHIC 5072,0 523 0 1056 DESIGN @f@a@d_main 1057 VIEW struct.bd 1058 GRAPHIC 5582,0 525 0 1059 DESIGN @f@a@d_main 1060 VIEW struct.bd 1061 GRAPHIC 5090,0 526 0 1062 DESIGN @f@a@d_main 1063 VIEW struct.bd 1064 GRAPHIC 5130,0 527 0 1065 DESIGN @f@a@d_main 1066 VIEW struct.bd 1067 GRAPHIC 5184,0 528 0 1068 DESIGN @f@a@d_main 1069 VIEW struct.bd 1070 GRAPHIC 5122,0 529 0 1071 DESIGN @f@a@d_main 1072 VIEW struct.bd 1073 GRAPHIC 5106,0 530 0 1074 DESIGN @f@a@d_main 1075 VIEW struct.bd 1076 GRAPHIC 5098,0 531 0 1077 DESIGN @f@a@d_main 1078 VIEW struct.bd 1079 GRAPHIC 5190,0 532 0 1080 DESIGN @f@a@d_main 1081 VIEW struct.bd 1082 GRAPHIC 10194,0 533 0 1083 DESIGN @f@a@d_main 1084 VIEW struct.bd 1085 GRAPHIC 10202,0 534 0 1086 DESIGN @f@a@d_main 1087 VIEW struct.bd 1088 GRAPHIC 6002,0 535 0 1089 DESIGN @f@a@d_main 1090 VIEW struct.bd 1091 GRAPHIC 5146,0 536 0 1092 DESIGN @f@a@d_main 1093 VIEW struct.bd 1094 GRAPHIC 5138,0 537 0 1095 DESIGN @f@a@d_main 1096 VIEW struct.bd 1097 GRAPHIC 5114,0 538 0 1098 DESIGN @f@a@d_main 1099 VIEW struct.bd 1100 GRAPHIC 8277,0 540 0 1101 DESIGN @f@a@d_main 1102 VIEW struct.bd 1103 GRAPHIC 5602,0 542 0 1104 DESIGN @f@a@d_main 1105 VIEW struct.bd 1106 GRAPHIC 334,0 543 0 1107 DESIGN @f@a@d_main 1108 VIEW struct.bd 1109 GRAPHIC 328,0 544 0 1110 DESIGN @f@a@d_main 1111 VIEW struct.bd 1112 GRAPHIC 322,0 545 0 1113 DESIGN @f@a@d_main 1114 VIEW struct.bd 1115 GRAPHIC 4240,0 546 0 1116 DESIGN @f@a@d_main 1117 VIEW struct.bd 1118 GRAPHIC 364,0 547 0 1119 DESIGN @f@a@d_main 1120 VIEW struct.bd 1121 GRAPHIC 370,0 548 0 1122 DESIGN @f@a@d_main 1123 VIEW struct.bd 1124 GRAPHIC 1399,0 550 0 1125 DESIGN @f@a@d_main 1126 VIEW struct.bd 1127 GRAPHIC 1406,0 551 1 1128 DESIGN @f@a@d_main 1129 VIEW struct.bd 1130 GRAPHIC 5602,0 555 0 1131 DESIGN @f@a@d_main 1132 VIEW struct.bd 1133 GRAPHIC 334,0 556 0 1134 DESIGN @f@a@d_main 1135 VIEW struct.bd 1136 GRAPHIC 328,0 557 0 1137 DESIGN @f@a@d_main 1138 VIEW struct.bd 1139 GRAPHIC 322,0 558 0 1140 DESIGN @f@a@d_main 1141 VIEW struct.bd 1142 GRAPHIC 2299,0 559 0 1143 DESIGN @f@a@d_main 1144 VIEW struct.bd 1145 GRAPHIC 2576,0 560 0 1146 DESIGN @f@a@d_main 1147 VIEW struct.bd 1148 GRAPHIC 2582,0 561 0 1149 DESIGN @f@a@d_main 1150 VIEW struct.bd 1151 GRAPHIC 10467,0 562 0 1152 DESIGN @f@a@d_main 1153 VIEW struct.bd 1154 GRAPHIC 2588,0 563 0 1155 DESIGN @f@a@d_main 1156 VIEW struct.bd 1157 GRAPHIC 5184,0 564 0 1158 DESIGN @f@a@d_main 1159 VIEW struct.bd 1160 GRAPHIC 5745,0 565 0 1161 DESIGN @f@a@d_main 1162 VIEW struct.bd 1163 GRAPHIC 2594,0 566 0 1164 DESIGN @f@a@d_main 1165 VIEW struct.bd 1166 GRAPHIC 5190,0 567 0 1167 DESIGN @f@a@d_main 1168 VIEW struct.bd 1169 GRAPHIC 5404,0 568 0 1170 DESIGN @f@a@d_main 1171 VIEW struct.bd 1172 GRAPHIC 6018,0 569 0 1173 DESIGN @f@a@d_main 1174 VIEW struct.bd 1175 GRAPHIC 6002,0 570 0 1176 DESIGN @f@a@d_main 1177 VIEW struct.bd 1178 GRAPHIC 6008,0 571 0 1179 DESIGN @f@a@d_main 1180 VIEW struct.bd 1181 GRAPHIC 5138,0 572 0 1182 DESIGN @f@a@d_main 1183 VIEW struct.bd 1184 GRAPHIC 2600,0 573 0 1185 DESIGN @f@a@d_main 1186 VIEW struct.bd 1187 GRAPHIC 5480,0 574 0 1188 DESIGN @f@a@d_main 1189 VIEW struct.bd 1190 GRAPHIC 5474,0 575 0 1191 DESIGN @f@a@d_main 1192 VIEW struct.bd 1193 GRAPHIC 6064,0 576 0 1194 DESIGN @f@a@d_main 1195 VIEW struct.bd 1196 GRAPHIC 2642,0 577 0 1197 DESIGN @f@a@d_main 1198 VIEW struct.bd 1199 GRAPHIC 1411,0 578 0 1200 DESIGN @f@a@d_main 1201 VIEW struct.bd 1202 GRAPHIC 1682,0 579 0 1203 DESIGN @f@a@d_main 1204 VIEW struct.bd 1205 GRAPHIC 1983,0 580 0 1206 DESIGN @f@a@d_main 1207 VIEW struct.bd 1208 GRAPHIC 10439,0 581 0 1209 DESIGN @f@a@d_main 1210 VIEW struct.bd 1211 GRAPHIC 5950,0 582 0 1212 DESIGN @f@a@d_main 1213 VIEW struct.bd 1214 GRAPHIC 5962,0 583 0 1215 DESIGN @f@a@d_main 1216 VIEW struct.bd 1217 GRAPHIC 5626,0 584 0 1218 DESIGN @f@a@d_main 1219 VIEW struct.bd 1220 GRAPHIC 2778,0 585 0 1221 DESIGN @f@a@d_main 1222 VIEW struct.bd 1223 GRAPHIC 9006,0 586 0 1224 DESIGN @f@a@d_main 1225 VIEW struct.bd 1226 GRAPHIC 5634,0 587 0 1227 DESIGN @f@a@d_main 1228 VIEW struct.bd 1229 GRAPHIC 8577,0 588 0 1230 DESIGN @f@a@d_main 1231 VIEW struct.bd 1232 GRAPHIC 6540,0 589 0 1233 DESIGN @f@a@d_main 1234 VIEW struct.bd 1235 GRAPHIC 4401,0 590 0 1236 DESIGN @f@a@d_main 1237 VIEW struct.bd 1238 GRAPHIC 4419,0 591 0 1239 DESIGN @f@a@d_main 1240 VIEW struct.bd 1241 GRAPHIC 10298,0 592 0 1242 DESIGN @f@a@d_main 1243 VIEW struct.bd 1244 GRAPHIC 10304,0 593 0 1245 DESIGN @f@a@d_main 1246 VIEW struct.bd 1247 GRAPHIC 10316,0 594 0 1248 DESIGN @f@a@d_main 1249 VIEW struct.bd 1250 GRAPHIC 10310,0 595 0 1251 DESIGN @f@a@d_main 1252 VIEW struct.bd 1253 GRAPHIC 4743,0 596 0 1254 DESIGN @f@a@d_main 1255 VIEW struct.bd 1256 GRAPHIC 4407,0 597 0 1257 DESIGN @f@a@d_main 1258 VIEW struct.bd 1259 GRAPHIC 4903,0 599 0 1260 DESIGN @f@a@d_main 1261 VIEW struct.bd 1262 GRAPHIC 4757,0 601 0 1263 DESIGN @f@a@d_main 1264 VIEW struct.bd 1265 GRAPHIC 4401,0 602 0 1266 DESIGN @f@a@d_main 1267 VIEW struct.bd 1268 GRAPHIC 4419,0 603 0 1269 DESIGN @f@a@d_main 1270 VIEW struct.bd 1271 GRAPHIC 4671,0 604 0 1272 DESIGN @f@a@d_main 1273 VIEW struct.bd 1274 GRAPHIC 4679,0 605 0 1275 DESIGN @f@a@d_main 1276 VIEW struct.bd 1277 GRAPHIC 4687,0 606 0 1278 DESIGN @f@a@d_main 1279 VIEW struct.bd 1280 GRAPHIC 4695,0 607 0 1281 DESIGN @f@a@d_main 1282 VIEW struct.bd 1283 GRAPHIC 4407,0 608 0 1284 DESIGN @f@a@d_main 1285 VIEW struct.bd 1286 GRAPHIC 4743,0 609 0 1287 DESIGN @f@a@d_main 1288 VIEW struct.bd 1289 GRAPHIC 10298,0 610 0 1290 DESIGN @f@a@d_main 1291 VIEW struct.bd 1292 GRAPHIC 10310,0 611 0 1293 DESIGN @f@a@d_main 1294 VIEW struct.bd 1295 GRAPHIC 10304,0 612 0 1296 DESIGN @f@a@d_main 1297 VIEW struct.bd 1298 GRAPHIC 10316,0 613 0 1299 DESIGN @f@a@d_main 1300 VIEW struct.bd 1301 GRAPHIC 10322,0 614 0 1302 DESIGN @f@a@d_main 1303 VIEW struct.bd 1304 GRAPHIC 4948,0 615 0 1305 DESIGN @f@a@d_main 1306 VIEW struct.bd 1307 GRAPHIC 10010,0 616 0 1308 DESIGN @f@a@d_main 1309 VIEW struct.bd 1310 GRAPHIC 11209,0 618 0 1311 DESIGN @f@a@d_main 1312 VIEW struct.bd 1313 GRAPHIC 11216,0 619 1 1314 DESIGN @f@a@d_main 1315 VIEW struct.bd 1316 GRAPHIC 10699,0 625 0 1317 DESIGN @f@a@d_main 1318 VIEW struct.bd 1319 GRAPHIC 10723,0 626 0 1320 DESIGN @f@a@d_main 1321 VIEW struct.bd 1322 GRAPHIC 10737,0 627 0 1323 DESIGN @f@a@d_main 1324 VIEW struct.bd 1325 GRAPHIC 10751,0 628 0 1326 DESIGN @f@a@d_main 1327 VIEW struct.bd 1328 GRAPHIC 10707,0 629 0 1329 DESIGN @f@a@d_main 1330 VIEW struct.bd 1331 GRAPHIC 10685,0 630 0 1332 DESIGN @f@a@d_main 1333 VIEW struct.bd 1334 GRAPHIC 10691,0 631 0 1335 DESIGN @f@a@d_main 1336 VIEW struct.bd 1337 GRAPHIC 2311,0 633 0 1338 DESIGN @f@a@d_main 1339 VIEW struct.bd 1340 GRAPHIC 2318,0 634 1 1341 DESIGN @f@a@d_main 1342 VIEW struct.bd 1343 GRAPHIC 6082,0 639 0 1344 DESIGN @f@a@d_main 1345 VIEW struct.bd 1346 GRAPHIC 2588,0 640 0 1347 DESIGN @f@a@d_main 1348 VIEW struct.bd 1349 GRAPHIC 2582,0 641 0 1350 DESIGN @f@a@d_main 1351 VIEW struct.bd 1352 GRAPHIC 10467,0 642 0 1353 DESIGN @f@a@d_main 1354 VIEW struct.bd 1355 GRAPHIC 5168,0 643 0 1356 DESIGN @f@a@d_main 1357 VIEW struct.bd 1358 GRAPHIC 2576,0 644 0 1359 DESIGN @f@a@d_main 1360 VIEW struct.bd 1361 GRAPHIC 2594,0 645 0 1362 DESIGN @f@a@d_main 1363 VIEW struct.bd 1364 GRAPHIC 6018,0 646 0 1365 DESIGN @f@a@d_main 1366 VIEW struct.bd 1367 GRAPHIC 2600,0 647 0 1368 DESIGN @f@a@d_main 1369 VIEW struct.bd 1370 GRAPHIC 2642,0 648 0 1371 DESIGN @f@a@d_main 1372 VIEW struct.bd 1373 GRAPHIC 2488,0 649 0 1374 DESIGN @f@a@d_main 1375 VIEW struct.bd 1376 GRAPHIC 2482,0 650 0 1377 DESIGN @f@a@d_main 1378 VIEW struct.bd 1379 GRAPHIC 2494,0 651 0 1380 DESIGN @f@a@d_main 1381 VIEW struct.bd 1382 GRAPHIC 2476,0 652 0 1383 DESIGN @f@a@d_main 1384 VIEW struct.bd 1385 GRAPHIC 2506,0 653 0 1386 DESIGN @f@a@d_main 1387 VIEW struct.bd 1388 GRAPHIC 2500,0 654 0 1389 DESIGN @f@a@d_main 1390 VIEW struct.bd 1391 GRAPHIC 2470,0 655 0 1392 DESIGN @f@a@d_main 1393 VIEW struct.bd 1394 GRAPHIC 8416,0 656 0 1395 DESIGN @f@a@d_main 1396 VIEW struct.bd 1397 GRAPHIC 2299,0 657 0 1398 DESIGN @f@a@d_main 1399 VIEW struct.bd 1400 GRAPHIC 5793,0 659 0 1401 DESIGN @f@a@d_main 1402 VIEW struct.bd 1403 GRAPHIC 5805,0 661 0 1404 DESIGN @f@a@d_main 1405 VIEW struct.bd 1406 GRAPHIC 5745,0 662 0 1407 DESIGN @f@a@d_main 1408 VIEW struct.bd 1409 GRAPHIC 5146,0 663 0 1410 DESIGN @f@a@d_main 1411 VIEW struct.bd 1412 GRAPHIC 5404,0 664 0 1413 DESIGN @f@a@d_main 1414 VIEW struct.bd 1415 GRAPHIC 6008,0 665 0 1416 DESIGN @f@a@d_main 1417 VIEW struct.bd 1418 GRAPHIC 5829,0 666 0 1419 DESIGN @f@a@d_main 1420 VIEW struct.bd 1421 GRAPHIC 6160,0 667 0 1422 DESIGN @f@a@d_main 1423 VIEW struct.bd 1424 GRAPHIC 8732,0 668 0 1425 DESIGN @f@a@d_main 1426 VIEW struct.bd 1427 GRAPHIC 5480,0 669 0 1428 DESIGN @f@a@d_main 1429 VIEW struct.bd 1430 GRAPHIC 5837,0 670 0 1431 DESIGN @f@a@d_main 1432 VIEW struct.bd 1433 GRAPHIC 5474,0 671 0 1434 DESIGN @f@a@d_main 1435 VIEW struct.bd 1436 GRAPHIC 5821,0 672 0 1437 DESIGN @f@a@d_main 1438 VIEW struct.bd 1439 GRAPHIC 1768,0 674 0 1440 DESIGN @f@a@d_main 1441 VIEW struct.bd 1442 GRAPHIC 1983,0 676 0 1443 DESIGN @f@a@d_main 1444 VIEW struct.bd 1445 GRAPHIC 10443,0 677 0 1446 DESIGN @f@a@d_main 1447 VIEW struct.bd 1448 GRAPHIC 6276,0 678 0 1449 DESIGN @f@a@d_main 1450 VIEW struct.bd 1451 GRAPHIC 1606,0 680 0 1452 DESIGN @f@a@d_main 1453 VIEW struct.bd 1454 GRAPHIC 1613,0 681 1 1455 DESIGN @f@a@d_main 1456 VIEW struct.bd 1457 GRAPHIC 3888,0 685 0 1458 DESIGN @f@a@d_main 1459 VIEW struct.bd 1460 GRAPHIC 376,0 686 0 1461 DESIGN @f@a@d_main 1462 VIEW struct.bd 1463 GRAPHIC 384,0 687 0 1464 DESIGN @f@a@d_main 1465 VIEW struct.bd 1466 GRAPHIC 392,0 688 0 1467 DESIGN @f@a@d_main 1468 VIEW struct.bd 1469 GRAPHIC 400,0 689 0 1470 DESIGN @f@a@d_main 1471 VIEW struct.bd 1472 GRAPHIC 408,0 690 0 1473 DESIGN @f@a@d_main 1474 VIEW struct.bd 1475 GRAPHIC 5222,0 691 0 1476 DESIGN @f@a@d_main 1477 VIEW struct.bd 1478 GRAPHIC 424,0 692 0 1479 DESIGN @f@a@d_main 1480 VIEW struct.bd 1481 GRAPHIC 432,0 693 0 1482 DESIGN @f@a@d_main 1483 VIEW struct.bd 1484 GRAPHIC 2482,0 694 0 1485 DESIGN @f@a@d_main 1486 VIEW struct.bd 1487 GRAPHIC 2488,0 695 0 1488 DESIGN @f@a@d_main 1489 VIEW struct.bd 1490 GRAPHIC 370,0 696 0 1491 DESIGN @f@a@d_main 1492 VIEW struct.bd 1493 GRAPHIC 364,0 697 0 1494 DESIGN @f@a@d_main 1495 VIEW struct.bd 1496 GRAPHIC 2476,0 698 0 1497 DESIGN @f@a@d_main 1498 VIEW struct.bd 1499 GRAPHIC 8416,0 699 0 1500 DESIGN @f@a@d_main 1501 VIEW struct.bd 1502 GRAPHIC 2470,0 700 0 1503 DESIGN @f@a@d_main 1504 VIEW struct.bd 1505 GRAPHIC 2506,0 701 0 1506 DESIGN @f@a@d_main 1507 VIEW struct.bd 1508 GRAPHIC 2500,0 702 0 1509 DESIGN @f@a@d_main 1510 VIEW struct.bd 1511 GRAPHIC 2494,0 703 0 1512 DESIGN @f@a@d_main 1513 VIEW struct.bd 1514 GRAPHIC 10266,0 704 0 1515 DESIGN @f@a@d_main 1516 VIEW struct.bd 1517 GRAPHIC 5950,0 705 0 1518 DESIGN @f@a@d_main 1519 VIEW struct.bd 1520 GRAPHIC 5962,0 706 0 1521 DESIGN @f@a@d_main 1522 VIEW struct.bd 1523 GRAPHIC 5090,0 707 0 1524 DESIGN @f@a@d_main 1525 VIEW struct.bd 1526 GRAPHIC 5114,0 708 0 1527 DESIGN @f@a@d_main 1528 VIEW struct.bd 1529 GRAPHIC 5122,0 709 0 1530 DESIGN @f@a@d_main 1531 VIEW struct.bd 1532 GRAPHIC 5130,0 710 0 1533 DESIGN @f@a@d_main 1534 VIEW struct.bd 1535 GRAPHIC 10194,0 711 0 1536 DESIGN @f@a@d_main 1537 VIEW struct.bd 1538 GRAPHIC 10202,0 712 0 1539 DESIGN @f@a@d_main 1540 VIEW struct.bd 1541 GRAPHIC 5106,0 713 0 1542 DESIGN @f@a@d_main 1543 VIEW struct.bd 1544 GRAPHIC 6362,0 714 0 1545 DESIGN @f@a@d_main 1546 VIEW struct.bd 1547 GRAPHIC 6452,0 715 0 1548 DESIGN @f@a@d_main 1549 VIEW struct.bd 1550 GRAPHIC 8752,0 716 0 1551 DESIGN @f@a@d_main 1552 VIEW struct.bd 1553 GRAPHIC 9233,0 717 0 1554 DESIGN @f@a@d_main 1555 VIEW struct.bd 1556 GRAPHIC 9241,0 718 0 1557 DESIGN @f@a@d_main 1558 VIEW struct.bd 1559 GRAPHIC 9943,0 719 0 1560 DESIGN @f@a@d_main 1561 VIEW struct.bd 1562 GRAPHIC 9951,0 720 0 1563 DESIGN @f@a@d_main 1564 VIEW struct.bd 1565 GRAPHIC 10637,0 721 0 1566 DESIGN @f@a@d_main 1567 VIEW struct.bd 1568 GRAPHIC 10629,0 722 0 1569 DESIGN @f@a@d_main 1570 VIEW struct.bd 1571 GRAPHIC 6276,0 726 0 1572 DESIGN @f@a@d_main 1573 VIEW struct.bd 1574 GRAPHIC 3888,0 727 0 1575 DESIGN @f@a@d_main 1576 VIEW struct.bd 1577 NO_GRAPHIC 729 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd
r10074 r10075 297 297 (vvPair 298 298 variable "time" 299 value "1 3:01:09"299 value "18:14:31" 300 300 ) 301 301 (vvPair … … 2757 2757 ) 2758 2758 xt "39000,62400,67500,63200" 2759 st "SIGNAL board_id : std_logic_vector(3 downto 0)" 2759 st "SIGNAL board_id : std_logic_vector(3 downto 0) 2760 " 2760 2761 ) 2761 2762 ) … … 2775 2776 ) 2776 2777 xt "39000,63200,67500,64000" 2777 st "SIGNAL crate_id : std_logic_vector(1 downto 0)" 2778 st "SIGNAL crate_id : std_logic_vector(1 downto 0) 2779 " 2778 2780 ) 2779 2781 ) … … 3098 3100 ) 3099 3101 xt "39000,61600,63000,62400" 3100 st "SIGNAL adc_data_array : adc_data_array_type" 3102 st "SIGNAL adc_data_array : adc_data_array_type 3103 " 3101 3104 ) 3102 3105 ) … … 3116 3119 ) 3117 3120 xt "39000,35800,67500,36600" 3118 st "RSRLOAD : std_logic := '0'" 3121 st "RSRLOAD : std_logic := '0' 3122 " 3119 3123 ) 3120 3124 ) … … 3179 3183 ) 3180 3184 xt "39000,60000,71000,60800" 3181 st "SIGNAL SRCLK : std_logic := '0'" 3185 st "SIGNAL SRCLK : std_logic := '0' 3186 " 3182 3187 ) 3183 3188 ) … … 3197 3202 ) 3198 3203 xt "39000,66400,67500,67200" 3199 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" 3204 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0) 3205 " 3200 3206 ) 3201 3207 ) … … 3214 3220 ) 3215 3221 xt "39000,23000,54000,23800" 3216 st "DAC_CS : std_logic" 3222 st "DAC_CS : std_logic 3223 " 3217 3224 ) 3218 3225 ) … … 3278 3285 ) 3279 3286 xt "39000,15800,54000,16600" 3280 st "X_50M : STD_LOGIC" 3287 st "X_50M : STD_LOGIC 3288 " 3281 3289 ) 3282 3290 ) … … 3295 3303 ) 3296 3304 xt "39000,14200,54000,15000" 3297 st "TRG : STD_LOGIC" 3305 st "TRG : STD_LOGIC 3306 " 3298 3307 ) 3299 3308 ) … … 3404 3413 ) 3405 3414 xt "39000,19000,64000,19800" 3406 st "A_CLK : std_logic_vector(3 downto 0)" 3415 st "A_CLK : std_logic_vector(3 downto 0) 3416 " 3407 3417 ) 3408 3418 ) … … 3421 3431 ) 3422 3432 xt "39000,51200,57500,52000" 3423 st "SIGNAL CLK_25_PS : std_logic" 3433 st "SIGNAL CLK_25_PS : std_logic 3434 " 3424 3435 ) 3425 3436 ) … … 3485 3496 ) 3486 3497 xt "39000,30200,54000,31000" 3487 st "OE_ADC : STD_LOGIC" 3498 st "OE_ADC : STD_LOGIC 3499 " 3488 3500 ) 3489 3501 ) … … 3548 3560 ) 3549 3561 xt "39000,7000,64000,7800" 3550 st "A_OTR : std_logic_vector(3 DOWNTO 0)" 3562 st "A_OTR : std_logic_vector(3 DOWNTO 0) 3563 " 3551 3564 ) 3552 3565 ) … … 3837 3850 ) 3838 3851 xt "39000,3800,64500,4600" 3839 st "A0_D : std_logic_vector(11 DOWNTO 0)" 3852 st "A0_D : std_logic_vector(11 DOWNTO 0) 3853 " 3840 3854 ) 3841 3855 ) … … 3855 3869 ) 3856 3870 xt "39000,4600,64500,5400" 3857 st "A1_D : std_logic_vector(11 DOWNTO 0)" 3871 st "A1_D : std_logic_vector(11 DOWNTO 0) 3872 " 3858 3873 ) 3859 3874 ) … … 3873 3888 ) 3874 3889 xt "39000,5400,64500,6200" 3875 st "A2_D : std_logic_vector(11 DOWNTO 0)" 3890 st "A2_D : std_logic_vector(11 DOWNTO 0) 3891 " 3876 3892 ) 3877 3893 ) … … 3891 3907 ) 3892 3908 xt "39000,6200,64500,7000" 3893 st "A3_D : std_logic_vector(11 DOWNTO 0)" 3909 st "A3_D : std_logic_vector(11 DOWNTO 0) 3910 " 3894 3911 ) 3895 3912 ) … … 3999 4016 ) 4000 4017 xt "39000,19800,54000,20600" 4001 st "D0_SRCLK : STD_LOGIC" 4018 st "D0_SRCLK : STD_LOGIC 4019 " 4002 4020 ) 4003 4021 ) … … 4016 4034 ) 4017 4035 xt "39000,20600,54000,21400" 4018 st "D1_SRCLK : STD_LOGIC" 4036 st "D1_SRCLK : STD_LOGIC 4037 " 4019 4038 ) 4020 4039 ) … … 4033 4052 ) 4034 4053 xt "39000,21400,54000,22200" 4035 st "D2_SRCLK : STD_LOGIC" 4054 st "D2_SRCLK : STD_LOGIC 4055 " 4036 4056 ) 4037 4057 ) … … 4050 4070 ) 4051 4071 xt "39000,22200,54000,23000" 4052 st "D3_SRCLK : STD_LOGIC" 4072 st "D3_SRCLK : STD_LOGIC 4073 " 4053 4074 ) 4054 4075 ) … … 4247 4268 ) 4248 4269 xt "39000,7800,54000,8600" 4249 st "D0_SROUT : std_logic" 4270 st "D0_SROUT : std_logic 4271 " 4250 4272 ) 4251 4273 ) … … 4264 4286 ) 4265 4287 xt "39000,8600,54000,9400" 4266 st "D1_SROUT : std_logic" 4288 st "D1_SROUT : std_logic 4289 " 4267 4290 ) 4268 4291 ) … … 4281 4304 ) 4282 4305 xt "39000,9400,54000,10200" 4283 st "D2_SROUT : std_logic" 4306 st "D2_SROUT : std_logic 4307 " 4284 4308 ) 4285 4309 ) … … 4298 4322 ) 4299 4323 xt "39000,10200,54000,11000" 4300 st "D3_SROUT : std_logic" 4324 st "D3_SROUT : std_logic 4325 " 4301 4326 ) 4302 4327 ) … … 4362 4387 ) 4363 4388 xt "39000,25400,73500,26200" 4364 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0')" 4389 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0') 4390 " 4365 4391 ) 4366 4392 ) … … 4425 4451 ) 4426 4452 xt "39000,24600,67500,25400" 4427 st "DWRITE : std_logic := '0'" 4453 st "DWRITE : std_logic := '0' 4454 " 4428 4455 ) 4429 4456 ) … … 4753 4780 ) 4754 4781 xt "39000,38200,54000,39000" 4755 st "T0_CS : std_logic" 4782 st "T0_CS : std_logic 4783 " 4756 4784 ) 4757 4785 ) … … 4770 4798 ) 4771 4799 xt "39000,39000,54000,39800" 4772 st "T1_CS : std_logic" 4800 st "T1_CS : std_logic 4801 " 4773 4802 ) 4774 4803 ) … … 4787 4816 ) 4788 4817 xt "39000,39800,54000,40600" 4789 st "T2_CS : std_logic" 4818 st "T2_CS : std_logic 4819 " 4790 4820 ) 4791 4821 ) … … 4804 4834 ) 4805 4835 xt "39000,40600,54000,41400" 4806 st "T3_CS : std_logic" 4836 st "T3_CS : std_logic 4837 " 4807 4838 ) 4808 4839 ) … … 4865 4896 ) 4866 4897 xt "39000,37400,54000,38200" 4867 st "S_CLK : std_logic" 4898 st "S_CLK : std_logic 4899 " 4868 4900 ) 4869 4901 ) … … 4883 4915 ) 4884 4916 xt "39000,42200,64000,43000" 4885 st "W_A : std_logic_vector(9 DOWNTO 0)" 4917 st "W_A : std_logic_vector(9 DOWNTO 0) 4918 " 4886 4919 ) 4887 4920 ) … … 4901 4934 ) 4902 4935 xt "39000,47000,64500,47800" 4903 st "W_D : std_logic_vector(15 DOWNTO 0)" 4936 st "W_D : std_logic_vector(15 DOWNTO 0) 4937 " 4904 4938 ) 4905 4939 ) … … 4919 4953 ) 4920 4954 xt "39000,44600,67500,45400" 4921 st "W_RES : std_logic := '1'" 4955 st "W_RES : std_logic := '1' 4956 " 4922 4957 ) 4923 4958 ) … … 4937 4972 ) 4938 4973 xt "39000,43800,67500,44600" 4939 st "W_RD : std_logic := '1'" 4974 st "W_RD : std_logic := '1' 4975 " 4940 4976 ) 4941 4977 ) … … 4955 4991 ) 4956 4992 xt "39000,45400,67500,46200" 4957 st "W_WR : std_logic := '1'" 4993 st "W_WR : std_logic := '1' 4994 " 4958 4995 ) 4959 4996 ) … … 4972 5009 ) 4973 5010 xt "39000,15000,54000,15800" 4974 st "W_INT : std_logic" 5011 st "W_INT : std_logic 5012 " 4975 5013 ) 4976 5014 ) … … 4990 5028 ) 4991 5029 xt "39000,43000,67500,43800" 4992 st "W_CS : std_logic := '1'" 5030 st "W_CS : std_logic := '1' 5031 " 4993 5032 ) 4994 5033 ) … … 5050 5089 ) 5051 5090 xt "39000,29400,67500,30200" 5052 st "MOSI : std_logic := '0'" 5091 st "MOSI : std_logic := '0' 5092 " 5053 5093 ) 5054 5094 ) … … 5113 5153 ) 5114 5154 xt "39000,46200,54000,47000" 5115 st "MISO : std_logic" 5155 st "MISO : std_logic 5156 " 5116 5157 ) 5117 5158 ) … … 5539 5580 ) 5540 5581 xt "39000,41400,54000,42200" 5541 st "TRG_V : std_logic" 5582 st "TRG_V : std_logic 5583 " 5542 5584 ) 5543 5585 ) … … 5556 5598 ) 5557 5599 xt "39000,33400,54000,34200" 5558 st "RS485_C_RE : std_logic" 5600 st "RS485_C_RE : std_logic 5601 " 5559 5602 ) 5560 5603 ) … … 5573 5616 ) 5574 5617 xt "39000,31800,54000,32600" 5575 st "RS485_C_DE : std_logic" 5618 st "RS485_C_DE : std_logic 5619 " 5576 5620 ) 5577 5621 ) … … 5590 5634 ) 5591 5635 xt "39000,35000,54000,35800" 5592 st "RS485_E_RE : std_logic" 5636 st "RS485_E_RE : std_logic 5637 " 5593 5638 ) 5594 5639 ) … … 5607 5652 ) 5608 5653 xt "39000,34200,54000,35000" 5609 st "RS485_E_DE : std_logic" 5654 st "RS485_E_DE : std_logic 5655 " 5610 5656 ) 5611 5657 ) … … 5625 5671 ) 5626 5672 xt "39000,23800,67500,24600" 5627 st "DENABLE : std_logic := '0'" 5673 st "DENABLE : std_logic := '0' 5674 " 5628 5675 ) 5629 5676 ) … … 5642 5689 ) 5643 5690 xt "39000,27800,54000,28600" 5644 st "EE_CS : std_logic" 5691 st "EE_CS : std_logic 5692 " 5645 5693 ) 5646 5694 ) … … 5885 5933 ) 5886 5934 xt "39000,26200,73500,27000" 5887 st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 5935 st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 5936 " 5888 5937 ) 5889 5938 ) … … 5948 5997 ) 5949 5998 xt "39000,11000,64000,11800" 5950 st "D_PLLLCK : std_logic_vector(3 DOWNTO 0)" 5999 st "D_PLLLCK : std_logic_vector(3 DOWNTO 0) 6000 " 5951 6001 ) 5952 6002 ) … … 6011 6061 ) 6012 6062 xt "39000,27000,73500,27800" 6013 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0')" 6063 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0') 6064 " 6014 6065 ) 6015 6066 ) … … 6250 6301 ) 6251 6302 xt "39000,17400,73500,18200" 6252 st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 6303 st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 6304 " 6253 6305 ) 6254 6306 ) … … 6267 6319 ) 6268 6320 xt "39000,64800,57500,65600" 6269 st "SIGNAL dummy : std_logic" 6321 st "SIGNAL dummy : std_logic 6322 " 6270 6323 ) 6271 6324 ) … … 6603 6656 ) 6604 6657 xt "39000,64000,77000,64800" 6605 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 6658 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6659 " 6606 6660 ) 6607 6661 ) … … 6620 6674 ) 6621 6675 xt "39000,52800,57500,53600" 6622 st "SIGNAL CLK_50 : std_logic" 6676 st "SIGNAL CLK_50 : std_logic 6677 " 6623 6678 ) 6624 6679 ) … … 7004 7059 ) 7005 7060 xt "39000,52000,57500,52800" 7006 st "SIGNAL CLK_25_PS1 : std_logic" 7061 st "SIGNAL CLK_25_PS1 : std_logic 7062 " 7007 7063 ) 7008 7064 ) … … 7022 7078 ) 7023 7079 xt "39000,60800,71000,61600" 7024 st "SIGNAL adc_clk_en : std_logic := '0'" 7080 st "SIGNAL adc_clk_en : std_logic := '0' 7081 " 7025 7082 ) 7026 7083 ) … … 7085 7142 ) 7086 7143 xt "39000,16600,73500,17400" 7087 st "A0_T : std_logic_vector(7 DOWNTO 0) := (others => '0')" 7144 st "A0_T : std_logic_vector(7 DOWNTO 0) := (others => '0') 7145 " 7088 7146 ) 7089 7147 ) … … 7207 7265 ) 7208 7266 xt "39000,50400,57500,51200" 7209 st "SIGNAL CLK50_OUT : std_logic" 7267 st "SIGNAL CLK50_OUT : std_logic 7268 " 7210 7269 ) 7211 7270 ) … … 7224 7283 ) 7225 7284 xt "39000,48800,57500,49600" 7226 st "SIGNAL CLK25_OUT : std_logic" 7285 st "SIGNAL CLK25_OUT : std_logic 7286 " 7227 7287 ) 7228 7288 ) … … 7241 7301 ) 7242 7302 xt "39000,49600,57500,50400" 7243 st "SIGNAL CLK25_PSOUT : std_logic" 7303 st "SIGNAL CLK25_PSOUT : std_logic 7304 " 7244 7305 ) 7245 7306 ) … … 7258 7319 ) 7259 7320 xt "39000,58400,57500,59200" 7260 st "SIGNAL PS_DIR_IN : std_logic" 7321 st "SIGNAL PS_DIR_IN : std_logic 7322 " 7261 7323 ) 7262 7324 ) … … 7275 7337 ) 7276 7338 xt "39000,59200,57500,60000" 7277 st "SIGNAL PS_DO_IN : std_logic" 7339 st "SIGNAL PS_DO_IN : std_logic 7340 " 7278 7341 ) 7279 7342 ) … … 7292 7355 ) 7293 7356 xt "39000,56800,57500,57600" 7294 st "SIGNAL PSEN_OUT : std_logic" 7357 st "SIGNAL PSEN_OUT : std_logic 7358 " 7295 7359 ) 7296 7360 ) … … 7309 7373 ) 7310 7374 xt "39000,57600,57500,58400" 7311 st "SIGNAL PSINCDEC_OUT : std_logic" 7375 st "SIGNAL PSINCDEC_OUT : std_logic 7376 " 7312 7377 ) 7313 7378 ) … … 7328 7393 ) 7329 7394 xt "39000,53600,57500,54400" 7330 st "SIGNAL DCM_locked : std_logic" 7395 st "SIGNAL DCM_locked : std_logic 7396 " 7331 7397 ) 7332 7398 ) … … 7348 7414 ) 7349 7415 xt "39000,65600,71000,66400" 7350 st "SIGNAL ready : std_logic := '0'" 7416 st "SIGNAL ready : std_logic := '0' 7417 " 7351 7418 ) 7352 7419 ) … … 7370 7437 xt "39000,67200,71000,68800" 7371 7438 st "-- status: 7372 SIGNAL shifting : std_logic := '0'" 7439 SIGNAL shifting : std_logic := '0' 7440 " 7373 7441 ) 7374 7442 ) … … 7387 7455 ) 7388 7456 xt "39000,56000,57500,56800" 7389 st "SIGNAL PSDONE_extraOUT : std_logic" 7457 st "SIGNAL PSDONE_extraOUT : std_logic 7458 " 7390 7459 ) 7391 7460 ) … … 7404 7473 ) 7405 7474 xt "39000,55200,57500,56000" 7406 st "SIGNAL PSCLK_OUT : std_logic" 7475 st "SIGNAL PSCLK_OUT : std_logic 7476 " 7407 7477 ) 7408 7478 ) … … 7421 7491 ) 7422 7492 xt "39000,54400,57500,55200" 7423 st "SIGNAL LOCKED_extraOUT : std_logic" 7493 st "SIGNAL LOCKED_extraOUT : std_logic 7494 " 7424 7495 ) 7425 7496 ) … … 7483 7554 ) 7484 7555 xt "39000,11800,54000,12600" 7485 st "RS485_C_DI : std_logic" 7556 st "RS485_C_DI : std_logic 7557 " 7486 7558 ) 7487 7559 ) … … 7544 7616 ) 7545 7617 xt "39000,32600,54000,33400" 7546 st "RS485_C_DO : std_logic" 7618 st "RS485_C_DO : std_logic 7619 " 7547 7620 ) 7548 7621 ) … … 7606 7679 ) 7607 7680 xt "39000,12600,54000,13400" 7608 st "RS485_E_DI : std_logic" 7681 st "RS485_E_DI : std_logic 7682 " 7609 7683 ) 7610 7684 ) … … 7623 7697 ) 7624 7698 xt "39000,13400,54000,14200" 7625 st "RS485_E_DO : std_logic" 7699 st "RS485_E_DO : std_logic 7700 " 7626 7701 ) 7627 7702 ) … … 7729 7804 ) 7730 7805 xt "39000,36600,67500,37400" 7731 st "SRIN : std_logic := '0'" 7806 st "SRIN : std_logic := '0' 7807 " 7732 7808 ) 7733 7809 ) … … 7878 7954 ) 7879 7955 xt "39000,18200,54000,19000" 7880 st "AMBER_LED : std_logic" 7956 st "AMBER_LED : std_logic 7957 " 7881 7958 ) 7882 7959 ) … … 7895 7972 ) 7896 7973 xt "39000,28600,54000,29400" 7897 st "GREEN_LED : std_logic" 7974 st "GREEN_LED : std_logic 7975 " 7898 7976 ) 7899 7977 ) … … 7912 7990 ) 7913 7991 xt "39000,31000,54000,31800" 7914 st "RED_LED : std_logic" 7992 st "RED_LED : std_logic 7993 " 7915 7994 ) 7916 7995 ) … … 11351 11430 vasetType 3 11352 11431 ) 11353 xt "80750,142000,87000,14 2000"11354 pts [ 11355 "80750,14 2000"11432 xt "80750,142000,87000,143000" 11433 pts [ 11434 "80750,143000" 11356 11435 "87000,142000" 11357 11436 ] 11358 11437 ) 11359 start &6 111438 start &62 11360 11439 end &262 11361 ss 011362 11440 sat 32 11363 11441 eat 32 … … 11374 11452 isHidden 1 11375 11453 ) 11376 xt "83000,14 1000,88100,142000"11454 xt "83000,142000,88100,143000" 11377 11455 st "GREEN_LED" 11378 blo "83000,14 1800"11456 blo "83000,142800" 11379 11457 tm "WireNameMgr" 11380 11458 ) … … 11389 11467 vasetType 3 11390 11468 ) 11391 xt "80750,14 3000,87000,143000"11392 pts [ 11393 "80750,14 3000"11469 xt "80750,142000,87000,143000" 11470 pts [ 11471 "80750,142000" 11394 11472 "87000,143000" 11395 11473 ] 11396 11474 ) 11397 start &6 211475 start &61 11398 11476 end &263 11399 11477 sat 32 … … 11411 11489 isHidden 1 11412 11490 ) 11413 xt "83000,14 2000,87000,143000"11491 xt "83000,141000,87000,142000" 11414 11492 st "RED_LED" 11415 blo "83000,14 2800"11493 blo "83000,141800" 11416 11494 tm "WireNameMgr" 11417 11495 ) … … 11548 11626 hasePageBreakOrigin 1 11549 11627 pageBreakOrigin "0,0" 11550 lastUid 12 773,011628 lastUid 12954,0 11551 11629 defaultCommentText (CommentText 11552 11630 shape (Rectangle -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak
r10074 r10075 2757 2757 ) 2758 2758 xt "39000,62400,67500,63200" 2759 st "SIGNAL board_id : std_logic_vector(3 downto 0) 2760 " 2759 st "SIGNAL board_id : std_logic_vector(3 downto 0)" 2761 2760 ) 2762 2761 ) … … 2776 2775 ) 2777 2776 xt "39000,63200,67500,64000" 2778 st "SIGNAL crate_id : std_logic_vector(1 downto 0) 2779 " 2777 st "SIGNAL crate_id : std_logic_vector(1 downto 0)" 2780 2778 ) 2781 2779 ) … … 3100 3098 ) 3101 3099 xt "39000,61600,63000,62400" 3102 st "SIGNAL adc_data_array : adc_data_array_type 3103 " 3100 st "SIGNAL adc_data_array : adc_data_array_type" 3104 3101 ) 3105 3102 ) … … 3119 3116 ) 3120 3117 xt "39000,35800,67500,36600" 3121 st "RSRLOAD : std_logic := '0' 3122 " 3118 st "RSRLOAD : std_logic := '0'" 3123 3119 ) 3124 3120 ) … … 3183 3179 ) 3184 3180 xt "39000,60000,71000,60800" 3185 st "SIGNAL SRCLK : std_logic := '0' 3186 " 3181 st "SIGNAL SRCLK : std_logic := '0'" 3187 3182 ) 3188 3183 ) … … 3202 3197 ) 3203 3198 xt "39000,66400,67500,67200" 3204 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0) 3205 " 3199 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" 3206 3200 ) 3207 3201 ) … … 3220 3214 ) 3221 3215 xt "39000,23000,54000,23800" 3222 st "DAC_CS : std_logic 3223 " 3216 st "DAC_CS : std_logic" 3224 3217 ) 3225 3218 ) … … 3285 3278 ) 3286 3279 xt "39000,15800,54000,16600" 3287 st "X_50M : STD_LOGIC 3288 " 3280 st "X_50M : STD_LOGIC" 3289 3281 ) 3290 3282 ) … … 3303 3295 ) 3304 3296 xt "39000,14200,54000,15000" 3305 st "TRG : STD_LOGIC 3306 " 3297 st "TRG : STD_LOGIC" 3307 3298 ) 3308 3299 ) … … 3413 3404 ) 3414 3405 xt "39000,19000,64000,19800" 3415 st "A_CLK : std_logic_vector(3 downto 0) 3416 " 3406 st "A_CLK : std_logic_vector(3 downto 0)" 3417 3407 ) 3418 3408 ) … … 3431 3421 ) 3432 3422 xt "39000,51200,57500,52000" 3433 st "SIGNAL CLK_25_PS : std_logic 3434 " 3423 st "SIGNAL CLK_25_PS : std_logic" 3435 3424 ) 3436 3425 ) … … 3496 3485 ) 3497 3486 xt "39000,30200,54000,31000" 3498 st "OE_ADC : STD_LOGIC 3499 " 3487 st "OE_ADC : STD_LOGIC" 3500 3488 ) 3501 3489 ) … … 3560 3548 ) 3561 3549 xt "39000,7000,64000,7800" 3562 st "A_OTR : std_logic_vector(3 DOWNTO 0) 3563 " 3550 st "A_OTR : std_logic_vector(3 DOWNTO 0)" 3564 3551 ) 3565 3552 ) … … 3850 3837 ) 3851 3838 xt "39000,3800,64500,4600" 3852 st "A0_D : std_logic_vector(11 DOWNTO 0) 3853 " 3839 st "A0_D : std_logic_vector(11 DOWNTO 0)" 3854 3840 ) 3855 3841 ) … … 3869 3855 ) 3870 3856 xt "39000,4600,64500,5400" 3871 st "A1_D : std_logic_vector(11 DOWNTO 0) 3872 " 3857 st "A1_D : std_logic_vector(11 DOWNTO 0)" 3873 3858 ) 3874 3859 ) … … 3888 3873 ) 3889 3874 xt "39000,5400,64500,6200" 3890 st "A2_D : std_logic_vector(11 DOWNTO 0) 3891 " 3875 st "A2_D : std_logic_vector(11 DOWNTO 0)" 3892 3876 ) 3893 3877 ) … … 3907 3891 ) 3908 3892 xt "39000,6200,64500,7000" 3909 st "A3_D : std_logic_vector(11 DOWNTO 0) 3910 " 3893 st "A3_D : std_logic_vector(11 DOWNTO 0)" 3911 3894 ) 3912 3895 ) … … 4016 3999 ) 4017 4000 xt "39000,19800,54000,20600" 4018 st "D0_SRCLK : STD_LOGIC 4019 " 4001 st "D0_SRCLK : STD_LOGIC" 4020 4002 ) 4021 4003 ) … … 4034 4016 ) 4035 4017 xt "39000,20600,54000,21400" 4036 st "D1_SRCLK : STD_LOGIC 4037 " 4018 st "D1_SRCLK : STD_LOGIC" 4038 4019 ) 4039 4020 ) … … 4052 4033 ) 4053 4034 xt "39000,21400,54000,22200" 4054 st "D2_SRCLK : STD_LOGIC 4055 " 4035 st "D2_SRCLK : STD_LOGIC" 4056 4036 ) 4057 4037 ) … … 4070 4050 ) 4071 4051 xt "39000,22200,54000,23000" 4072 st "D3_SRCLK : STD_LOGIC 4073 " 4052 st "D3_SRCLK : STD_LOGIC" 4074 4053 ) 4075 4054 ) … … 4268 4247 ) 4269 4248 xt "39000,7800,54000,8600" 4270 st "D0_SROUT : std_logic 4271 " 4249 st "D0_SROUT : std_logic" 4272 4250 ) 4273 4251 ) … … 4286 4264 ) 4287 4265 xt "39000,8600,54000,9400" 4288 st "D1_SROUT : std_logic 4289 " 4266 st "D1_SROUT : std_logic" 4290 4267 ) 4291 4268 ) … … 4304 4281 ) 4305 4282 xt "39000,9400,54000,10200" 4306 st "D2_SROUT : std_logic 4307 " 4283 st "D2_SROUT : std_logic" 4308 4284 ) 4309 4285 ) … … 4322 4298 ) 4323 4299 xt "39000,10200,54000,11000" 4324 st "D3_SROUT : std_logic 4325 " 4300 st "D3_SROUT : std_logic" 4326 4301 ) 4327 4302 ) … … 4387 4362 ) 4388 4363 xt "39000,25400,73500,26200" 4389 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0') 4390 " 4364 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0')" 4391 4365 ) 4392 4366 ) … … 4451 4425 ) 4452 4426 xt "39000,24600,67500,25400" 4453 st "DWRITE : std_logic := '0' 4454 " 4427 st "DWRITE : std_logic := '0'" 4455 4428 ) 4456 4429 ) … … 4780 4753 ) 4781 4754 xt "39000,38200,54000,39000" 4782 st "T0_CS : std_logic 4783 " 4755 st "T0_CS : std_logic" 4784 4756 ) 4785 4757 ) … … 4798 4770 ) 4799 4771 xt "39000,39000,54000,39800" 4800 st "T1_CS : std_logic 4801 " 4772 st "T1_CS : std_logic" 4802 4773 ) 4803 4774 ) … … 4816 4787 ) 4817 4788 xt "39000,39800,54000,40600" 4818 st "T2_CS : std_logic 4819 " 4789 st "T2_CS : std_logic" 4820 4790 ) 4821 4791 ) … … 4834 4804 ) 4835 4805 xt "39000,40600,54000,41400" 4836 st "T3_CS : std_logic 4837 " 4806 st "T3_CS : std_logic" 4838 4807 ) 4839 4808 ) … … 4896 4865 ) 4897 4866 xt "39000,37400,54000,38200" 4898 st "S_CLK : std_logic 4899 " 4867 st "S_CLK : std_logic" 4900 4868 ) 4901 4869 ) … … 4915 4883 ) 4916 4884 xt "39000,42200,64000,43000" 4917 st "W_A : std_logic_vector(9 DOWNTO 0) 4918 " 4885 st "W_A : std_logic_vector(9 DOWNTO 0)" 4919 4886 ) 4920 4887 ) … … 4934 4901 ) 4935 4902 xt "39000,47000,64500,47800" 4936 st "W_D : std_logic_vector(15 DOWNTO 0) 4937 " 4903 st "W_D : std_logic_vector(15 DOWNTO 0)" 4938 4904 ) 4939 4905 ) … … 4953 4919 ) 4954 4920 xt "39000,44600,67500,45400" 4955 st "W_RES : std_logic := '1' 4956 " 4921 st "W_RES : std_logic := '1'" 4957 4922 ) 4958 4923 ) … … 4972 4937 ) 4973 4938 xt "39000,43800,67500,44600" 4974 st "W_RD : std_logic := '1' 4975 " 4939 st "W_RD : std_logic := '1'" 4976 4940 ) 4977 4941 ) … … 4991 4955 ) 4992 4956 xt "39000,45400,67500,46200" 4993 st "W_WR : std_logic := '1' 4994 " 4957 st "W_WR : std_logic := '1'" 4995 4958 ) 4996 4959 ) … … 5009 4972 ) 5010 4973 xt "39000,15000,54000,15800" 5011 st "W_INT : std_logic 5012 " 4974 st "W_INT : std_logic" 5013 4975 ) 5014 4976 ) … … 5028 4990 ) 5029 4991 xt "39000,43000,67500,43800" 5030 st "W_CS : std_logic := '1' 5031 " 4992 st "W_CS : std_logic := '1'" 5032 4993 ) 5033 4994 ) … … 5089 5050 ) 5090 5051 xt "39000,29400,67500,30200" 5091 st "MOSI : std_logic := '0' 5092 " 5052 st "MOSI : std_logic := '0'" 5093 5053 ) 5094 5054 ) … … 5153 5113 ) 5154 5114 xt "39000,46200,54000,47000" 5155 st "MISO : std_logic 5156 " 5115 st "MISO : std_logic" 5157 5116 ) 5158 5117 ) … … 5580 5539 ) 5581 5540 xt "39000,41400,54000,42200" 5582 st "TRG_V : std_logic 5583 " 5541 st "TRG_V : std_logic" 5584 5542 ) 5585 5543 ) … … 5598 5556 ) 5599 5557 xt "39000,33400,54000,34200" 5600 st "RS485_C_RE : std_logic 5601 " 5558 st "RS485_C_RE : std_logic" 5602 5559 ) 5603 5560 ) … … 5616 5573 ) 5617 5574 xt "39000,31800,54000,32600" 5618 st "RS485_C_DE : std_logic 5619 " 5575 st "RS485_C_DE : std_logic" 5620 5576 ) 5621 5577 ) … … 5634 5590 ) 5635 5591 xt "39000,35000,54000,35800" 5636 st "RS485_E_RE : std_logic 5637 " 5592 st "RS485_E_RE : std_logic" 5638 5593 ) 5639 5594 ) … … 5652 5607 ) 5653 5608 xt "39000,34200,54000,35000" 5654 st "RS485_E_DE : std_logic 5655 " 5609 st "RS485_E_DE : std_logic" 5656 5610 ) 5657 5611 ) … … 5671 5625 ) 5672 5626 xt "39000,23800,67500,24600" 5673 st "DENABLE : std_logic := '0' 5674 " 5627 st "DENABLE : std_logic := '0'" 5675 5628 ) 5676 5629 ) … … 5689 5642 ) 5690 5643 xt "39000,27800,54000,28600" 5691 st "EE_CS : std_logic 5692 " 5644 st "EE_CS : std_logic" 5693 5645 ) 5694 5646 ) … … 5933 5885 ) 5934 5886 xt "39000,26200,73500,27000" 5935 st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 5936 " 5887 st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 5937 5888 ) 5938 5889 ) … … 5997 5948 ) 5998 5949 xt "39000,11000,64000,11800" 5999 st "D_PLLLCK : std_logic_vector(3 DOWNTO 0) 6000 " 5950 st "D_PLLLCK : std_logic_vector(3 DOWNTO 0)" 6001 5951 ) 6002 5952 ) … … 6061 6011 ) 6062 6012 xt "39000,27000,73500,27800" 6063 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0') 6064 " 6013 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0')" 6065 6014 ) 6066 6015 ) … … 6301 6250 ) 6302 6251 xt "39000,17400,73500,18200" 6303 st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 6304 " 6252 st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 6305 6253 ) 6306 6254 ) … … 6319 6267 ) 6320 6268 xt "39000,64800,57500,65600" 6321 st "SIGNAL dummy : std_logic 6322 " 6269 st "SIGNAL dummy : std_logic" 6323 6270 ) 6324 6271 ) … … 6656 6603 ) 6657 6604 xt "39000,64000,77000,64800" 6658 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6659 " 6605 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 6660 6606 ) 6661 6607 ) … … 6674 6620 ) 6675 6621 xt "39000,52800,57500,53600" 6676 st "SIGNAL CLK_50 : std_logic 6677 " 6622 st "SIGNAL CLK_50 : std_logic" 6678 6623 ) 6679 6624 ) … … 7059 7004 ) 7060 7005 xt "39000,52000,57500,52800" 7061 st "SIGNAL CLK_25_PS1 : std_logic 7062 " 7006 st "SIGNAL CLK_25_PS1 : std_logic" 7063 7007 ) 7064 7008 ) … … 7078 7022 ) 7079 7023 xt "39000,60800,71000,61600" 7080 st "SIGNAL adc_clk_en : std_logic := '0' 7081 " 7024 st "SIGNAL adc_clk_en : std_logic := '0'" 7082 7025 ) 7083 7026 ) … … 7142 7085 ) 7143 7086 xt "39000,16600,73500,17400" 7144 st "A0_T : std_logic_vector(7 DOWNTO 0) := (others => '0') 7145 " 7087 st "A0_T : std_logic_vector(7 DOWNTO 0) := (others => '0')" 7146 7088 ) 7147 7089 ) … … 7265 7207 ) 7266 7208 xt "39000,50400,57500,51200" 7267 st "SIGNAL CLK50_OUT : std_logic 7268 " 7209 st "SIGNAL CLK50_OUT : std_logic" 7269 7210 ) 7270 7211 ) … … 7283 7224 ) 7284 7225 xt "39000,48800,57500,49600" 7285 st "SIGNAL CLK25_OUT : std_logic 7286 " 7226 st "SIGNAL CLK25_OUT : std_logic" 7287 7227 ) 7288 7228 ) … … 7301 7241 ) 7302 7242 xt "39000,49600,57500,50400" 7303 st "SIGNAL CLK25_PSOUT : std_logic 7304 " 7243 st "SIGNAL CLK25_PSOUT : std_logic" 7305 7244 ) 7306 7245 ) … … 7319 7258 ) 7320 7259 xt "39000,58400,57500,59200" 7321 st "SIGNAL PS_DIR_IN : std_logic 7322 " 7260 st "SIGNAL PS_DIR_IN : std_logic" 7323 7261 ) 7324 7262 ) … … 7337 7275 ) 7338 7276 xt "39000,59200,57500,60000" 7339 st "SIGNAL PS_DO_IN : std_logic 7340 " 7277 st "SIGNAL PS_DO_IN : std_logic" 7341 7278 ) 7342 7279 ) … … 7355 7292 ) 7356 7293 xt "39000,56800,57500,57600" 7357 st "SIGNAL PSEN_OUT : std_logic 7358 " 7294 st "SIGNAL PSEN_OUT : std_logic" 7359 7295 ) 7360 7296 ) … … 7373 7309 ) 7374 7310 xt "39000,57600,57500,58400" 7375 st "SIGNAL PSINCDEC_OUT : std_logic 7376 " 7311 st "SIGNAL PSINCDEC_OUT : std_logic" 7377 7312 ) 7378 7313 ) … … 7393 7328 ) 7394 7329 xt "39000,53600,57500,54400" 7395 st "SIGNAL DCM_locked : std_logic 7396 " 7330 st "SIGNAL DCM_locked : std_logic" 7397 7331 ) 7398 7332 ) … … 7414 7348 ) 7415 7349 xt "39000,65600,71000,66400" 7416 st "SIGNAL ready : std_logic := '0' 7417 " 7350 st "SIGNAL ready : std_logic := '0'" 7418 7351 ) 7419 7352 ) … … 7437 7370 xt "39000,67200,71000,68800" 7438 7371 st "-- status: 7439 SIGNAL shifting : std_logic := '0' 7440 " 7372 SIGNAL shifting : std_logic := '0'" 7441 7373 ) 7442 7374 ) … … 7455 7387 ) 7456 7388 xt "39000,56000,57500,56800" 7457 st "SIGNAL PSDONE_extraOUT : std_logic 7458 " 7389 st "SIGNAL PSDONE_extraOUT : std_logic" 7459 7390 ) 7460 7391 ) … … 7473 7404 ) 7474 7405 xt "39000,55200,57500,56000" 7475 st "SIGNAL PSCLK_OUT : std_logic 7476 " 7406 st "SIGNAL PSCLK_OUT : std_logic" 7477 7407 ) 7478 7408 ) … … 7491 7421 ) 7492 7422 xt "39000,54400,57500,55200" 7493 st "SIGNAL LOCKED_extraOUT : std_logic 7494 " 7423 st "SIGNAL LOCKED_extraOUT : std_logic" 7495 7424 ) 7496 7425 ) … … 7554 7483 ) 7555 7484 xt "39000,11800,54000,12600" 7556 st "RS485_C_DI : std_logic 7557 " 7485 st "RS485_C_DI : std_logic" 7558 7486 ) 7559 7487 ) … … 7616 7544 ) 7617 7545 xt "39000,32600,54000,33400" 7618 st "RS485_C_DO : std_logic 7619 " 7546 st "RS485_C_DO : std_logic" 7620 7547 ) 7621 7548 ) … … 7679 7606 ) 7680 7607 xt "39000,12600,54000,13400" 7681 st "RS485_E_DI : std_logic 7682 " 7608 st "RS485_E_DI : std_logic" 7683 7609 ) 7684 7610 ) … … 7697 7623 ) 7698 7624 xt "39000,13400,54000,14200" 7699 st "RS485_E_DO : std_logic 7700 " 7625 st "RS485_E_DO : std_logic" 7701 7626 ) 7702 7627 ) … … 7804 7729 ) 7805 7730 xt "39000,36600,67500,37400" 7806 st "SRIN : std_logic := '0' 7807 " 7731 st "SRIN : std_logic := '0'" 7808 7732 ) 7809 7733 ) … … 7954 7878 ) 7955 7879 xt "39000,18200,54000,19000" 7956 st "AMBER_LED : std_logic 7957 " 7880 st "AMBER_LED : std_logic" 7958 7881 ) 7959 7882 ) … … 7972 7895 ) 7973 7896 xt "39000,28600,54000,29400" 7974 st "GREEN_LED : std_logic 7975 " 7897 st "GREEN_LED : std_logic" 7976 7898 ) 7977 7899 ) … … 7990 7912 ) 7991 7913 xt "39000,31000,54000,31800" 7992 st "RED_LED : std_logic 7993 " 7914 st "RED_LED : std_logic" 7994 7915 ) 7995 7916 ) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb
r10074 r10075 1535 1535 (vvPair 1536 1536 variable "time" 1537 value "1 3:01:09"1537 value "18:14:31" 1538 1538 ) 1539 1539 (vvPair … … 4852 4852 ) 4853 4853 ) 4854 lastUid 40 70,04854 lastUid 4093,0 4855 4855 activeModelName "Symbol:CDM" 4856 4856 ) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd
r10074 r10075 239 239 elements [ 240 240 (GiElement 241 name "HEARTBEAT_ DIVIDER"241 name "HEARTBEAT_PWM_DIVIDER" 242 242 type "integer" 243 value "25000000" 244 e "-- 2Hz @ 50 MHz" 243 value "50000" 244 e "-- 10kHz @ 50 MHz" 245 ) 246 (GiElement 247 name "MAX_DELAY" 248 type "integer" 249 value "100" 245 250 ) 246 251 (GiElement 247 252 name "WAITING_DIVIDER" 248 253 type "integer" 249 value "5000000 "250 e "-- 1 0Hz @ 50 MHz"254 value "50000000" 255 e "-- 1Hz @ 50 MHz" 251 256 ) 252 257 ] 253 258 mwi 0 254 uid 1 0675,0259 uid 11209,0 255 260 ) 256 261 ] … … 461 466 (vvPair 462 467 variable "time" 463 value "1 5:59:32"468 value "18:05:35" 464 469 ) 465 470 (vvPair … … 553 558 ) 554 559 xt "-103000,118600,-59500,119400" 555 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\" 556 " 560 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\"" 557 561 ) 558 562 ) … … 572 576 ) 573 577 xt "-103000,64200,-63000,65000" 574 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 575 " 578 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 576 579 ) 577 580 ) … … 591 594 ) 592 595 xt "-103000,81800,-70500,82600" 593 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0) 594 " 596 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0)" 595 597 ) 596 598 ) … … 610 612 ) 611 613 xt "-103000,94600,-63000,95400" 612 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) 613 " 614 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)" 614 615 ) 615 616 ) … … 629 630 ) 630 631 xt "-103000,95400,-70500,96200" 631 st "SIGNAL ram_data : std_logic_vector(15 downto 0) 632 " 632 st "SIGNAL ram_data : std_logic_vector(15 downto 0)" 633 633 ) 634 634 ) … … 648 648 ) 649 649 xt "-103000,55800,-63000,56600" 650 st "wiz_reset : std_logic := '1' 651 " 650 st "wiz_reset : std_logic := '1'" 652 651 ) 653 652 ) … … 667 666 ) 668 667 xt "-103000,53400,-74500,54200" 669 st "wiz_addr : std_logic_vector(9 DOWNTO 0) 670 " 668 st "wiz_addr : std_logic_vector(9 DOWNTO 0)" 671 669 ) 672 670 ) … … 686 684 ) 687 685 xt "-103000,58200,-74000,59000" 688 st "wiz_data : std_logic_vector(15 DOWNTO 0) 689 " 686 st "wiz_data : std_logic_vector(15 DOWNTO 0)" 690 687 ) 691 688 ) … … 705 702 ) 706 703 xt "-103000,54200,-63000,55000" 707 st "wiz_cs : std_logic := '1' 708 " 704 st "wiz_cs : std_logic := '1'" 709 705 ) 710 706 ) … … 724 720 ) 725 721 xt "-103000,56600,-63000,57400" 726 st "wiz_wr : std_logic := '1' 727 " 722 st "wiz_wr : std_logic := '1'" 728 723 ) 729 724 ) … … 743 738 ) 744 739 xt "-103000,55000,-63000,55800" 745 st "wiz_rd : std_logic := '1' 746 " 740 st "wiz_rd : std_logic := '1'" 747 741 ) 748 742 ) … … 761 755 ) 762 756 xt "-103000,26200,-84500,27000" 763 st "wiz_int : std_logic 764 " 757 st "wiz_int : std_logic" 765 758 ) 766 759 ) … … 2779 2772 ) 2780 2773 xt "-103000,23800,-74500,24600" 2781 st "board_id : std_logic_vector(3 downto 0) 2782 " 2774 st "board_id : std_logic_vector(3 downto 0)" 2783 2775 ) 2784 2776 ) … … 2799 2791 ) 2800 2792 xt "-103000,25400,-84500,26200" 2801 st "trigger : std_logic 2802 " 2793 st "trigger : std_logic" 2803 2794 ) 2804 2795 ) … … 4373 4364 ) 4374 4365 xt "-103000,24600,-74500,25400" 4375 st "crate_id : std_logic_vector(1 downto 0) 4376 " 4366 st "crate_id : std_logic_vector(1 downto 0)" 4377 4367 ) 4378 4368 ) … … 4595 4585 ) 4596 4586 xt "-103000,110600,-70500,111400" 4597 st "SIGNAL trigger_id : std_logic_vector(47 downto 0) 4598 " 4587 st "SIGNAL trigger_id : std_logic_vector(47 downto 0)" 4599 4588 ) 4600 4589 ) … … 4616 4605 ) 4617 4606 xt "-103000,96200,-63000,97000" 4618 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 4619 " 4607 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 4620 4608 ) 4621 4609 ) … … 5467 5455 ) 5468 5456 xt "-103000,113000,-80500,113800" 5469 st "SIGNAL wiz_busy : std_logic 5470 " 5457 st "SIGNAL wiz_busy : std_logic" 5471 5458 ) 5472 5459 ) … … 5487 5474 ) 5488 5475 xt "-103000,115400,-59500,116200" 5489 st "SIGNAL wiz_write_ea : std_logic := '0' 5490 " 5476 st "SIGNAL wiz_write_ea : std_logic := '0'" 5491 5477 ) 5492 5478 ) … … 5508 5494 ) 5509 5495 xt "-103000,117800,-53500,118600" 5510 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') 5511 " 5496 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0')" 5512 5497 ) 5513 5498 ) … … 5530 5515 ) 5531 5516 xt "-103000,114600,-53500,115400" 5532 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') 5533 " 5517 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')" 5534 5518 ) 5535 5519 ) … … 5551 5535 ) 5552 5536 xt "-103000,113800,-53500,114600" 5553 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') 5554 " 5537 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0')" 5555 5538 ) 5556 5539 ) … … 5571 5554 ) 5572 5555 xt "-103000,116200,-59500,117000" 5573 st "SIGNAL wiz_write_end : std_logic := '0' 5574 " 5556 st "SIGNAL wiz_write_end : std_logic := '0'" 5575 5557 ) 5576 5558 ) … … 5591 5573 ) 5592 5574 xt "-103000,117000,-59500,117800" 5593 st "SIGNAL wiz_write_header : std_logic := '0' 5594 " 5575 st "SIGNAL wiz_write_header : std_logic := '0'" 5595 5576 ) 5596 5577 ) … … 5609 5590 ) 5610 5591 xt "-103000,97000,-80500,97800" 5611 st "SIGNAL ram_write_ea : std_logic 5612 " 5592 st "SIGNAL ram_write_ea : std_logic" 5613 5593 ) 5614 5594 ) … … 5628 5608 ) 5629 5609 xt "-103000,97800,-59500,98600" 5630 st "SIGNAL ram_write_ready : std_logic := '0' 5631 " 5610 st "SIGNAL ram_write_ready : std_logic := '0'" 5632 5611 ) 5633 5612 ) … … 5647 5626 ) 5648 5627 xt "-103000,74600,-59500,75400" 5649 st "SIGNAL config_start : std_logic := '0' 5650 " 5628 st "SIGNAL config_start : std_logic := '0'" 5651 5629 ) 5652 5630 ) … … 5665 5643 ) 5666 5644 xt "-103000,69000,-80500,69800" 5667 st "SIGNAL config_ready : std_logic 5668 " 5645 st "SIGNAL config_ready : std_logic" 5669 5646 ) 5670 5647 ) … … 5683 5660 ) 5684 5661 xt "-103000,101000,-79000,101800" 5685 st "SIGNAL roi_max : roi_max_type 5686 " 5662 st "SIGNAL roi_max : roi_max_type" 5687 5663 ) 5688 5664 ) … … 5702 5678 ) 5703 5679 xt "-103000,91400,-70500,92200" 5704 st "SIGNAL package_length : std_logic_vector(15 downto 0) 5705 " 5680 st "SIGNAL package_length : std_logic_vector(15 downto 0)" 5706 5681 ) 5707 5682 ) … … 5721 5696 ) 5722 5697 xt "-103000,40600,-63000,41400" 5723 st "adc_oeb : std_logic := '1' 5724 " 5698 st "adc_oeb : std_logic := '1'" 5725 5699 ) 5726 5700 ) … … 5829 5803 ) 5830 5804 xt "-103000,100200,-78000,101000" 5831 st "SIGNAL roi_array : roi_array_type 5832 " 5805 st "SIGNAL roi_array : roi_array_type" 5833 5806 ) 5834 5807 ) … … 6263 6236 ) 6264 6237 xt "-103000,29400,-84500,30200" 6265 st "CLK_25_PS : std_logic 6266 " 6238 st "CLK_25_PS : std_logic" 6267 6239 ) 6268 6240 ) … … 6326 6298 ) 6327 6299 xt "-103000,30200,-84500,31000" 6328 st "CLK_50 : std_logic 6329 " 6300 st "CLK_50 : std_logic" 6330 6301 ) 6331 6302 ) … … 6344 6315 ) 6345 6316 xt "-103000,61000,-80500,61800" 6346 st "SIGNAL CLK_25 : std_logic 6347 " 6317 st "SIGNAL CLK_25 : std_logic" 6348 6318 ) 6349 6319 ) … … 6407 6377 ) 6408 6378 xt "-103000,18200,-84500,19000" 6409 st "CLK : std_logic 6410 " 6379 st "CLK : std_logic" 6411 6380 ) 6412 6381 ) … … 6426 6395 ) 6427 6396 xt "-103000,23000,-74500,23800" 6428 st "adc_otr_array : std_logic_vector(3 DOWNTO 0) 6429 " 6397 st "adc_otr_array : std_logic_vector(3 DOWNTO 0)" 6430 6398 ) 6431 6399 ) … … 6444 6412 ) 6445 6413 xt "-103000,22200,-79000,23000" 6446 st "adc_data_array : adc_data_array_type 6447 " 6414 st "adc_data_array : adc_data_array_type" 6448 6415 ) 6449 6416 ) … … 6508 6475 ) 6509 6476 xt "-103000,85000,-59500,85800" 6510 st "SIGNAL drs_clk_en : std_logic := '0' 6511 " 6477 st "SIGNAL drs_clk_en : std_logic := '0'" 6512 6478 ) 6513 6479 ) … … 6526 6492 ) 6527 6493 xt "-103000,87400,-74500,88200" 6528 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type 6529 " 6494 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type" 6530 6495 ) 6531 6496 ) … … 6545 6510 ) 6546 6511 xt "-103000,85800,-59500,86600" 6547 st "SIGNAL drs_read_s_cell : std_logic := '0' 6548 " 6512 st "SIGNAL drs_read_s_cell : std_logic := '0'" 6549 6513 ) 6550 6514 ) … … 6565 6529 ) 6566 6530 xt "-103000,43800,-57000,44600" 6567 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6568 " 6531 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 6569 6532 ) 6570 6533 ) … … 6584 6547 ) 6585 6548 xt "-103000,44600,-63000,45400" 6586 st "drs_dwrite : std_logic := '1' 6587 " 6549 st "drs_dwrite : std_logic := '1'" 6588 6550 ) 6589 6551 ) … … 6692 6654 ) 6693 6655 xt "-103000,19000,-84500,19800" 6694 st "SROUT_in_0 : std_logic 6695 " 6656 st "SROUT_in_0 : std_logic" 6696 6657 ) 6697 6658 ) … … 6710 6671 ) 6711 6672 xt "-103000,19800,-84500,20600" 6712 st "SROUT_in_1 : std_logic 6713 " 6673 st "SROUT_in_1 : std_logic" 6714 6674 ) 6715 6675 ) … … 6728 6688 ) 6729 6689 xt "-103000,20600,-84500,21400" 6730 st "SROUT_in_2 : std_logic 6731 " 6690 st "SROUT_in_2 : std_logic" 6732 6691 ) 6733 6692 ) … … 6746 6705 ) 6747 6706 xt "-103000,21400,-84500,22200" 6748 st "SROUT_in_3 : std_logic 6749 " 6707 st "SROUT_in_3 : std_logic" 6750 6708 ) 6751 6709 ) … … 6944 6902 ) 6945 6903 xt "-103000,86600,-80500,87400" 6946 st "SIGNAL drs_read_s_cell_ready : std_logic 6947 " 6904 st "SIGNAL drs_read_s_cell_ready : std_logic" 6948 6905 ) 6949 6906 ) … … 7600 7557 ) 7601 7558 xt "-103000,37400,-63000,38200" 7602 st "RSRLOAD : std_logic := '0' 7603 " 7559 st "RSRLOAD : std_logic := '0'" 7604 7560 ) 7605 7561 ) … … 7664 7620 ) 7665 7621 xt "-103000,38200,-63000,39000" 7666 st "SRCLK : std_logic := '0' 7667 " 7622 st "SRCLK : std_logic := '0'" 7668 7623 ) 7669 7624 ) … … 8318 8273 ) 8319 8274 xt "-103000,65000,-71000,65800" 8320 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0) 8321 " 8275 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0)" 8322 8276 ) 8323 8277 ) … … 8336 8290 ) 8337 8291 xt "-103000,67400,-80500,68200" 8338 st "SIGNAL config_data_valid : std_logic 8339 " 8292 st "SIGNAL config_data_valid : std_logic" 8340 8293 ) 8341 8294 ) … … 8354 8307 ) 8355 8308 xt "-103000,65800,-80500,66600" 8356 st "SIGNAL config_busy : std_logic 8357 " 8309 st "SIGNAL config_busy : std_logic" 8358 8310 ) 8359 8311 ) … … 8373 8325 ) 8374 8326 xt "-103000,66600,-70500,67400" 8375 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0) 8376 " 8327 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0)" 8377 8328 ) 8378 8329 ) … … 8391 8342 ) 8392 8343 xt "-103000,80200,-80500,81000" 8393 st "SIGNAL config_wr_en : std_logic 8394 " 8344 st "SIGNAL config_wr_en : std_logic" 8395 8345 ) 8396 8346 ) … … 8409 8359 ) 8410 8360 xt "-103000,68200,-80500,69000" 8411 st "SIGNAL config_rd_en : std_logic 8412 " 8361 st "SIGNAL config_rd_en : std_logic" 8413 8362 ) 8414 8363 ) … … 8427 8376 ) 8428 8377 xt "-103000,81000,-78000,81800" 8429 st "SIGNAL dac_array : dac_array_type 8430 " 8378 st "SIGNAL dac_array : dac_array_type" 8431 8379 ) 8432 8380 ) … … 8445 8393 ) 8446 8394 xt "-103000,75400,-80500,76200" 8447 st "SIGNAL config_start_cm : std_logic 8448 " 8395 st "SIGNAL config_start_cm : std_logic" 8449 8396 ) 8450 8397 ) … … 8463 8410 ) 8464 8411 xt "-103000,69800,-80500,70600" 8465 st "SIGNAL config_ready_cm : std_logic 8466 " 8412 st "SIGNAL config_ready_cm : std_logic" 8467 8413 ) 8468 8414 ) … … 8484 8430 ) 8485 8431 xt "-103000,46200,-57000,47000" 8486 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 8487 " 8432 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 8488 8433 ) 8489 8434 ) … … 8502 8447 ) 8503 8448 xt "-103000,105000,-80500,105800" 8504 st "SIGNAL sensor_ready : std_logic 8505 " 8449 st "SIGNAL sensor_ready : std_logic" 8506 8450 ) 8507 8451 ) … … 8520 8464 ) 8521 8465 xt "-103000,104200,-76500,105000" 8522 st "SIGNAL sensor_array : sensor_array_type 8523 " 8466 st "SIGNAL sensor_array : sensor_array_type" 8524 8467 ) 8525 8468 ) … … 8538 8481 ) 8539 8482 xt "-103000,70600,-80500,71400" 8540 st "SIGNAL config_ready_spi : std_logic 8541 " 8483 st "SIGNAL config_ready_spi : std_logic" 8542 8484 ) 8543 8485 ) … … 8558 8500 ) 8559 8501 xt "-103000,63400,-71000,64200" 8560 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0) 8561 " 8502 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0)" 8562 8503 ) 8563 8504 ) … … 8576 8517 ) 8577 8518 xt "-103000,62600,-75500,63400" 8578 st "SIGNAL adc_data_array_int : adc_data_array_type 8579 " 8519 st "SIGNAL adc_data_array_int : adc_data_array_type" 8580 8520 ) 8581 8521 ) … … 8867 8807 ) 8868 8808 xt "-103000,76200,-59500,77000" 8869 st "SIGNAL config_start_spi : std_logic := '0' 8870 " 8809 st "SIGNAL config_start_spi : std_logic := '0'" 8871 8810 ) 8872 8811 ) … … 9401 9340 ) 9402 9341 xt "-103000,50200,-84500,51000" 9403 st "sclk : std_logic 9404 " 9342 st "sclk : std_logic" 9405 9343 ) 9406 9344 ) … … 9421 9359 ) 9422 9360 xt "-103000,57400,-84500,58200" 9423 st "sio : std_logic 9424 " 9361 st "sio : std_logic" 9425 9362 ) 9426 9363 ) … … 9439 9376 ) 9440 9377 xt "-103000,42200,-84500,43000" 9441 st "dac_cs : std_logic 9442 " 9378 st "dac_cs : std_logic" 9443 9379 ) 9444 9380 ) … … 9458 9394 ) 9459 9395 xt "-103000,51000,-74500,51800" 9460 st "sensor_cs : std_logic_vector(3 DOWNTO 0) 9461 " 9396 st "sensor_cs : std_logic_vector(3 DOWNTO 0)" 9462 9397 ) 9463 9398 ) … … 9657 9592 ) 9658 9593 xt "-103000,90600,-59500,91400" 9659 st "SIGNAL new_config : std_logic := '0' 9660 " 9594 st "SIGNAL new_config : std_logic := '0'" 9661 9595 ) 9662 9596 ) … … 9675 9609 ) 9676 9610 xt "-103000,77000,-80500,77800" 9677 st "SIGNAL config_started : std_logic 9678 " 9611 st "SIGNAL config_started : std_logic" 9679 9612 ) 9680 9613 ) … … 9694 9627 ) 9695 9628 xt "-103000,79400,-59500,80200" 9696 st "SIGNAL config_started_spi : std_logic := '0' 9697 " 9629 st "SIGNAL config_started_spi : std_logic := '0'" 9698 9630 ) 9699 9631 ) … … 9713 9645 ) 9714 9646 xt "-103000,77800,-59500,78600" 9715 st "SIGNAL config_started_cu : std_logic := '0' 9716 " 9647 st "SIGNAL config_started_cu : std_logic := '0'" 9717 9648 ) 9718 9649 ) … … 9731 9662 ) 9732 9663 xt "-103000,78600,-80500,79400" 9733 st "SIGNAL config_started_mm : std_logic 9734 " 9664 st "SIGNAL config_started_mm : std_logic" 9735 9665 ) 9736 9666 ) … … 9750 9680 ) 9751 9681 xt "-103000,47000,-63000,47800" 9752 st "mosi : std_logic := '0' 9753 " 9682 st "mosi : std_logic := '0'" 9754 9683 ) 9755 9684 ) … … 9816 9745 ) 9817 9746 xt "-103000,43000,-49500,43800" 9818 st "denable : std_logic := '0' -- default domino wave off 9819 " 9747 st "denable : std_logic := '0' -- default domino wave off" 9820 9748 ) 9821 9749 ) … … 9879 9807 ) 9880 9808 xt "-103000,89800,-59500,90600" 9881 st "SIGNAL dwrite_enable : std_logic := '1' 9882 " 9809 st "SIGNAL dwrite_enable : std_logic := '1'" 9883 9810 ) 9884 9811 ) … … 10267 10194 ) 10268 10195 xt "-103000,89000,-59500,89800" 10269 st "SIGNAL dwrite : std_logic := '1' 10270 " 10196 st "SIGNAL dwrite : std_logic := '1'" 10271 10197 ) 10272 10198 ) … … 10642 10568 ) 10643 10569 xt "-103000,112200,-80500,113000" 10644 st "SIGNAL wiz_ack : std_logic 10645 " 10570 st "SIGNAL wiz_ack : std_logic" 10646 10571 ) 10647 10572 ) … … 10662 10587 ) 10663 10588 xt "-103000,82600,-53500,83400" 10664 st "SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0') 10665 " 10589 st "SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0')" 10666 10590 ) 10667 10591 ) … … 10680 10604 ) 10681 10605 xt "-103000,83400,-80500,84200" 10682 st "SIGNAL drs_address_mode : std_logic 10683 " 10606 st "SIGNAL drs_address_mode : std_logic" 10684 10607 ) 10685 10608 ) … … 11228 11151 ) 11229 11152 xt "-103000,84200,-53500,85000" 11230 st "SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0') 11231 " 11153 st "SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0')" 11232 11154 ) 11233 11155 ) … … 11612 11534 ) 11613 11535 xt "-103000,102600,-80500,103400" 11614 st "SIGNAL sclk1 : std_logic 11615 " 11536 st "SIGNAL sclk1 : std_logic" 11616 11537 ) 11617 11538 ) … … 11630 11551 ) 11631 11552 xt "-103000,103400,-80500,104200" 11632 st "SIGNAL sclk_enable : std_logic 11633 " 11553 st "SIGNAL sclk_enable : std_logic" 11634 11554 ) 11635 11555 ) … … 11649 11569 ) 11650 11570 xt "-103000,39800,-63000,40600" 11651 st "adc_clk_en : std_logic := '0' 11652 " 11571 st "adc_clk_en : std_logic := '0'" 11653 11572 ) 11654 11573 ) … … 12429 12348 ) 12430 12349 xt "-103000,92200,-44000,93000" 12431 st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards 12432 " 12350 st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards" 12433 12351 ) 12434 12352 ) … … 12451 12369 ) 12452 12370 xt "-103000,93000,-43000,93800" 12453 st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once 12454 " 12371 st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once" 12455 12372 ) 12456 12373 ) … … 12469 12386 ) 12470 12387 xt "-103000,31800,-84500,32600" 12471 st "LOCKED_extraOUT : std_logic 12472 " 12388 st "LOCKED_extraOUT : std_logic" 12473 12389 ) 12474 12390 ) … … 12531 12447 ) 12532 12448 xt "-103000,33400,-84500,34200" 12533 st "PSDONE_extraOUT : std_logic 12534 " 12449 st "PSDONE_extraOUT : std_logic" 12535 12450 ) 12536 12451 ) … … 12593 12508 ) 12594 12509 xt "-103000,35000,-84500,35800" 12595 st "PSINCDEC_OUT : std_logic 12596 " 12510 st "PSINCDEC_OUT : std_logic" 12597 12511 ) 12598 12512 ) … … 12655 12569 ) 12656 12570 xt "-103000,34200,-84500,35000" 12657 st "PSEN_OUT : std_logic 12658 " 12571 st "PSEN_OUT : std_logic" 12659 12572 ) 12660 12573 ) … … 12717 12630 ) 12718 12631 xt "-103000,32600,-84500,33400" 12719 st "PSCLK_OUT : std_logic 12720 " 12632 st "PSCLK_OUT : std_logic" 12721 12633 ) 12722 12634 ) … … 12781 12693 ) 12782 12694 xt "-103000,31000,-84500,31800" 12783 st "DCM_locked : std_logic 12784 " 12695 st "DCM_locked : std_logic" 12785 12696 ) 12786 12697 ) … … 12847 12758 ) 12848 12759 xt "-103000,47800,-57000,48600" 12849 st "offset : std_logic_vector(7 downto 0) := (OTHERS => '0') 12850 " 12760 st "offset : std_logic_vector(7 downto 0) := (OTHERS => '0')" 12851 12761 ) 12852 12762 ) … … 12914 12824 xt "-103000,51800,-63000,53400" 12915 12825 st "-- status: 12916 shifting : std_logic := '0' 12917 " 12826 shifting : std_logic := '0'" 12918 12827 ) 12919 12828 ) … … 12979 12888 ) 12980 12889 xt "-103000,48600,-63000,49400" 12981 st "ready : std_logic := '0' 12982 " 12890 st "ready : std_logic := '0'" 12983 12891 ) 12984 12892 ) … … 13768 13676 ) 13769 13677 xt "-103000,35800,-84500,36600" 13770 st "PS_DIR_IN : std_logic 13771 " 13678 st "PS_DIR_IN : std_logic" 13772 13679 ) 13773 13680 ) … … 13786 13693 ) 13787 13694 xt "-103000,36600,-84500,37400" 13788 st "PS_DO_IN : std_logic 13789 " 13695 st "PS_DO_IN : std_logic" 13790 13696 ) 13791 13697 ) … … 14795 14701 ) 14796 14702 xt "-103000,28600,-84500,29400" 14797 st "CLK50_OUT : std_logic 14798 " 14703 st "CLK50_OUT : std_logic" 14799 14704 ) 14800 14705 ) … … 14857 14762 ) 14858 14763 xt "-103000,27000,-84500,27800" 14859 st "CLK25_OUT : std_logic 14860 " 14764 st "CLK25_OUT : std_logic" 14861 14765 ) 14862 14766 ) … … 14919 14823 ) 14920 14824 xt "-103000,27800,-84500,28600" 14921 st "CLK25_PSOUT : std_logic 14922 " 14825 st "CLK25_PSOUT : std_logic" 14923 14826 ) 14924 14827 ) … … 14940 14843 ) 14941 14844 xt "-103000,93800,-35500,94600" 14942 st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift 14943 " 14845 st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift" 14944 14846 ) 14945 14847 ) … … 14959 14861 ) 14960 14862 xt "-103000,107400,-59500,108200" 14961 st "SIGNAL srclk_enable : std_logic := '0' 14962 " 14863 st "SIGNAL srclk_enable : std_logic := '0'" 14963 14864 ) 14964 14865 ) … … 15344 15245 ) 15345 15246 xt "-103000,61800,-59500,62600" 15346 st "SIGNAL SRCLK1 : std_logic := '0' 15347 " 15247 st "SIGNAL SRCLK1 : std_logic := '0'" 15348 15248 ) 15349 15249 ) … … 15367 15267 xt "-103000,71400,-59500,73000" 15368 15268 st "-- -- 15369 SIGNAL config_rw_ack : std_logic := '0' 15370 " 15269 SIGNAL config_rw_ack : std_logic := '0'" 15371 15270 ) 15372 15271 ) … … 15390 15289 xt "-103000,73000,-59500,74600" 15391 15290 st "-- -- 15392 SIGNAL config_rw_ready : std_logic := '0' 15393 " 15291 SIGNAL config_rw_ready : std_logic := '0'" 15394 15292 ) 15395 15293 ) … … 15408 15306 ) 15409 15307 xt "-103000,101800,-80500,102600" 15410 st "SIGNAL s_trigger : std_logic 15411 " 15308 st "SIGNAL s_trigger : std_logic" 15412 15309 ) 15413 15310 ) … … 15426 15323 ) 15427 15324 xt "-103000,109800,-80500,110600" 15428 st "SIGNAL start_srin_write_8b : std_logic 15429 " 15325 st "SIGNAL start_srin_write_8b : std_logic" 15430 15326 ) 15431 15327 ) … … 15445 15341 ) 15446 15342 xt "-103000,108200,-59500,109000" 15447 st "SIGNAL srin_write_ack : std_logic := '0' 15448 " 15343 st "SIGNAL srin_write_ack : std_logic := '0'" 15449 15344 ) 15450 15345 ) … … 15464 15359 ) 15465 15360 xt "-103000,109000,-59500,109800" 15466 st "SIGNAL srin_write_ready : std_logic := '0' 15467 " 15361 st "SIGNAL srin_write_ready : std_logic := '0'" 15468 15362 ) 15469 15363 ) … … 15484 15378 ) 15485 15379 xt "-103000,88200,-53500,89000" 15486 st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0') 15487 " 15380 st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0')" 15488 15381 ) 15489 15382 ) … … 15503 15396 ) 15504 15397 xt "-103000,39000,-63000,39800" 15505 st "SRIN_out : std_logic := '0' 15506 " 15398 st "SRIN_out : std_logic := '0'" 15507 15399 ) 15508 15400 ) … … 16022 15914 ) 16023 15915 xt "-103000,111400,-80500,112200" 16024 st "SIGNAL trigger_out : std_logic 16025 " 15916 st "SIGNAL trigger_out : std_logic" 16026 15917 ) 16027 15918 ) … … 16046 15937 xt "-103000,98600,-59500,100200" 16047 15938 st "-- -- 16048 SIGNAL ram_write_ready_ack : std_logic := '0' 16049 " 15939 SIGNAL ram_write_ready_ack : std_logic := '0'" 16050 15940 ) 16051 15941 ) … … 16064 15954 ) 16065 15955 xt "-103000,105800,-80500,106600" 16066 st "SIGNAL socks_connected : std_logic 16067 " 15956 st "SIGNAL socks_connected : std_logic" 16068 15957 ) 16069 15958 ) … … 16082 15971 ) 16083 15972 xt "-103000,106600,-80500,107400" 16084 st "SIGNAL socks_waiting : std_logic 16085 " 16086 ) 16087 ) 16088 *552 (SaComponent 16089 uid 10675,0 16090 optionalChildren [ 16091 *553 (CptPort 16092 uid 10643,0 16093 ps "OnEdgeStrategy" 16094 shape (Triangle 16095 uid 10644,0 16096 ro 90 16097 va (VaSet 16098 vasetType 1 16099 fg "0,65535,0" 16100 ) 16101 xt "128250,125625,129000,126375" 16102 ) 16103 tg (CPTG 16104 uid 10645,0 16105 ps "CptPortTextPlaceStrategy" 16106 stg "VerticalLayoutStrategy" 16107 f (Text 16108 uid 10646,0 16109 va (VaSet 16110 ) 16111 xt "130000,125500,131900,126500" 16112 st "CLK" 16113 blo "130000,126300" 16114 ) 16115 ) 16116 thePort (LogicalPort 16117 decl (Decl 16118 n "CLK" 16119 t "std_logic" 16120 o 1 16121 ) 16122 ) 16123 ) 16124 *554 (CptPort 16125 uid 10647,0 16126 ps "OnEdgeStrategy" 16127 shape (Triangle 16128 uid 10648,0 16129 ro 90 16130 va (VaSet 16131 vasetType 1 16132 fg "0,65535,0" 16133 ) 16134 xt "147000,125625,147750,126375" 16135 ) 16136 tg (CPTG 16137 uid 10649,0 16138 ps "CptPortTextPlaceStrategy" 16139 stg "RightVerticalLayoutStrategy" 16140 f (Text 16141 uid 10650,0 16142 va (VaSet 16143 ) 16144 xt "143600,125500,146000,126500" 16145 st "green" 16146 ju 2 16147 blo "146000,126300" 16148 ) 16149 ) 16150 thePort (LogicalPort 16151 m 1 16152 decl (Decl 16153 n "green" 16154 t "std_logic" 16155 o 2 16156 ) 16157 ) 16158 ) 16159 *555 (CptPort 16160 uid 10651,0 16161 ps "OnEdgeStrategy" 16162 shape (Triangle 16163 uid 10652,0 16164 ro 90 16165 va (VaSet 16166 vasetType 1 16167 fg "0,65535,0" 16168 ) 16169 xt "147000,126625,147750,127375" 16170 ) 16171 tg (CPTG 16172 uid 10653,0 16173 ps "CptPortTextPlaceStrategy" 16174 stg "RightVerticalLayoutStrategy" 16175 f (Text 16176 uid 10654,0 16177 va (VaSet 16178 ) 16179 xt "143500,126500,146000,127500" 16180 st "amber" 16181 ju 2 16182 blo "146000,127300" 16183 ) 16184 ) 16185 thePort (LogicalPort 16186 m 1 16187 decl (Decl 16188 n "amber" 16189 t "std_logic" 16190 o 3 16191 ) 16192 ) 16193 ) 16194 *556 (CptPort 16195 uid 10655,0 16196 ps "OnEdgeStrategy" 16197 shape (Triangle 16198 uid 10656,0 16199 ro 90 16200 va (VaSet 16201 vasetType 1 16202 fg "0,65535,0" 16203 ) 16204 xt "147000,127625,147750,128375" 16205 ) 16206 tg (CPTG 16207 uid 10657,0 16208 ps "CptPortTextPlaceStrategy" 16209 stg "RightVerticalLayoutStrategy" 16210 f (Text 16211 uid 10658,0 16212 va (VaSet 16213 ) 16214 xt "144500,127500,146000,128500" 16215 st "red" 16216 ju 2 16217 blo "146000,128300" 16218 ) 16219 ) 16220 thePort (LogicalPort 16221 m 1 16222 decl (Decl 16223 n "red" 16224 t "std_logic" 16225 o 4 16226 ) 16227 ) 16228 ) 16229 *557 (CptPort 16230 uid 10659,0 16231 ps "OnEdgeStrategy" 16232 shape (Triangle 16233 uid 10660,0 16234 ro 90 16235 va (VaSet 16236 vasetType 1 16237 fg "0,65535,0" 16238 ) 16239 xt "128250,126625,129000,127375" 16240 ) 16241 tg (CPTG 16242 uid 10661,0 16243 ps "CptPortTextPlaceStrategy" 16244 stg "VerticalLayoutStrategy" 16245 f (Text 16246 uid 10662,0 16247 va (VaSet 16248 ) 16249 xt "130000,126500,132800,127500" 16250 st "trigger" 16251 blo "130000,127300" 16252 ) 16253 ) 16254 thePort (LogicalPort 16255 decl (Decl 16256 n "trigger" 16257 t "std_logic" 16258 o 5 16259 ) 16260 ) 16261 ) 16262 *558 (CptPort 16263 uid 10663,0 16264 ps "OnEdgeStrategy" 16265 shape (Triangle 16266 uid 10664,0 16267 ro 90 16268 va (VaSet 16269 vasetType 1 16270 fg "0,65535,0" 16271 ) 16272 xt "128250,127625,129000,128375" 16273 ) 16274 tg (CPTG 16275 uid 10665,0 16276 ps "CptPortTextPlaceStrategy" 16277 stg "VerticalLayoutStrategy" 16278 f (Text 16279 uid 10666,0 16280 va (VaSet 16281 ) 16282 xt "130000,127500,135500,128500" 16283 st "socks_waiting" 16284 blo "130000,128300" 16285 ) 16286 ) 16287 thePort (LogicalPort 16288 decl (Decl 16289 n "socks_waiting" 16290 t "std_logic" 16291 o 6 16292 ) 16293 ) 16294 ) 16295 *559 (CptPort 16296 uid 10667,0 16297 ps "OnEdgeStrategy" 16298 shape (Triangle 16299 uid 10668,0 16300 ro 90 16301 va (VaSet 16302 vasetType 1 16303 fg "0,65535,0" 16304 ) 16305 xt "128250,128625,129000,129375" 16306 ) 16307 tg (CPTG 16308 uid 10669,0 16309 ps "CptPortTextPlaceStrategy" 16310 stg "VerticalLayoutStrategy" 16311 f (Text 16312 uid 10670,0 16313 va (VaSet 16314 ) 16315 xt "130000,128500,136500,129500" 16316 st "socks_connected" 16317 blo "130000,129300" 16318 ) 16319 ) 16320 thePort (LogicalPort 16321 decl (Decl 16322 n "socks_connected" 16323 t "std_logic" 16324 o 7 16325 ) 16326 ) 16327 ) 16328 ] 16329 shape (Rectangle 16330 uid 10676,0 16331 va (VaSet 16332 vasetType 1 16333 fg "0,65535,0" 16334 lineColor "0,32896,0" 16335 lineWidth 2 16336 ) 16337 xt "129000,125000,147000,131000" 16338 ) 16339 oxt "0,0,8000,10000" 16340 ttg (MlTextGroup 16341 uid 10677,0 16342 ps "CenterOffsetStrategy" 16343 stg "VerticalLayoutStrategy" 16344 textVec [ 16345 *560 (Text 16346 uid 10678,0 16347 va (VaSet 16348 font "Arial,8,1" 16349 ) 16350 xt "130900,131000,137100,132000" 16351 st "FACT_FAD_lib" 16352 blo "130900,131800" 16353 tm "BdLibraryNameMgr" 16354 ) 16355 *561 (Text 16356 uid 10679,0 16357 va (VaSet 16358 font "Arial,8,1" 16359 ) 16360 xt "130900,132000,136800,133000" 16361 st "led_controller" 16362 blo "130900,132800" 16363 tm "CptNameMgr" 16364 ) 16365 *562 (Text 16366 uid 10680,0 16367 va (VaSet 16368 font "Arial,8,1" 16369 ) 16370 xt "130900,133000,133100,134000" 16371 st "U_10" 16372 blo "130900,133800" 16373 tm "InstanceNameMgr" 16374 ) 16375 ] 16376 ) 16377 ga (GenericAssociation 16378 uid 10681,0 16379 ps "EdgeToEdgeStrategy" 16380 matrix (Matrix 16381 uid 10682,0 16382 text (MLText 16383 uid 10683,0 16384 va (VaSet 16385 font "Courier New,8,0" 16386 ) 16387 xt "129000,123400,161500,125000" 16388 st "HEARTBEAT_DIVIDER = 25000000 ( integer ) -- 2Hz @ 50 MHz 16389 WAITING_DIVIDER = 5000000 ( integer ) -- 10Hz @ 50 MHz " 16390 ) 16391 header "" 16392 ) 16393 elements [ 16394 (GiElement 16395 name "HEARTBEAT_DIVIDER" 16396 type "integer" 16397 value "25000000" 16398 e "-- 2Hz @ 50 MHz" 16399 ) 16400 (GiElement 16401 name "WAITING_DIVIDER" 16402 type "integer" 16403 value "5000000" 16404 e "-- 10Hz @ 50 MHz" 16405 ) 16406 ] 16407 ) 16408 viewicon (ZoomableIcon 16409 uid 10684,0 16410 sl 0 16411 va (VaSet 16412 vasetType 1 16413 fg "49152,49152,49152" 16414 ) 16415 xt "129250,129250,130750,130750" 16416 iconName "VhdlFileViewIcon.png" 16417 iconMaskName "VhdlFileViewIcon.msk" 16418 ftype 10 16419 ) 16420 ordering 1 16421 viewiconposition 0 16422 portVis (PortSigDisplay 16423 ) 16424 archFileType "UNKNOWN" 16425 ) 16426 *563 (Net 15973 st "SIGNAL socks_waiting : std_logic" 15974 ) 15975 ) 15976 *552 (Net 16427 15977 uid 10721,0 16428 15978 decl (Decl … … 16438 15988 ) 16439 15989 xt "-103000,45400,-84500,46200" 16440 st "green : std_logic 16441 " 16442 ) 16443 ) 16444 *564 (PortIoOut 15990 st "green : std_logic" 15991 ) 15992 ) 15993 *553 (PortIoOut 16445 15994 uid 10729,0 16446 15995 shape (CompositeShape … … 16486 16035 ) 16487 16036 ) 16488 *5 65(Net16037 *554 (Net 16489 16038 uid 10735,0 16490 16039 decl (Decl … … 16500 16049 ) 16501 16050 xt "-103000,41400,-84500,42200" 16502 st "amber : std_logic 16503 " 16504 ) 16505 ) 16506 *566 (PortIoOut 16051 st "amber : std_logic" 16052 ) 16053 ) 16054 *555 (PortIoOut 16507 16055 uid 10743,0 16508 16056 shape (CompositeShape … … 16548 16096 ) 16549 16097 ) 16550 *5 67(Net16098 *556 (Net 16551 16099 uid 10749,0 16552 16100 decl (Decl … … 16562 16110 ) 16563 16111 xt "-103000,49400,-84500,50200" 16564 st "red : std_logic 16565 " 16566 ) 16567 ) 16568 *568 (PortIoOut 16112 st "red : std_logic" 16113 ) 16114 ) 16115 *557 (PortIoOut 16569 16116 uid 10757,0 16570 16117 shape (CompositeShape … … 16609 16156 ) 16610 16157 ) 16158 ) 16159 *558 (SaComponent 16160 uid 11209,0 16161 optionalChildren [ 16162 *559 (CptPort 16163 uid 11181,0 16164 ps "OnEdgeStrategy" 16165 shape (Triangle 16166 uid 11182,0 16167 ro 90 16168 va (VaSet 16169 vasetType 1 16170 fg "0,65535,0" 16171 ) 16172 xt "128250,125625,129000,126375" 16173 ) 16174 tg (CPTG 16175 uid 11183,0 16176 ps "CptPortTextPlaceStrategy" 16177 stg "VerticalLayoutStrategy" 16178 f (Text 16179 uid 11184,0 16180 va (VaSet 16181 ) 16182 xt "130000,125500,131900,126500" 16183 st "CLK" 16184 blo "130000,126300" 16185 ) 16186 ) 16187 thePort (LogicalPort 16188 decl (Decl 16189 n "CLK" 16190 t "std_logic" 16191 o 1 16192 ) 16193 ) 16194 ) 16195 *560 (CptPort 16196 uid 11185,0 16197 ps "OnEdgeStrategy" 16198 shape (Triangle 16199 uid 11186,0 16200 ro 90 16201 va (VaSet 16202 vasetType 1 16203 fg "0,65535,0" 16204 ) 16205 xt "147000,125625,147750,126375" 16206 ) 16207 tg (CPTG 16208 uid 11187,0 16209 ps "CptPortTextPlaceStrategy" 16210 stg "RightVerticalLayoutStrategy" 16211 f (Text 16212 uid 11188,0 16213 va (VaSet 16214 ) 16215 xt "143600,125500,146000,126500" 16216 st "green" 16217 ju 2 16218 blo "146000,126300" 16219 ) 16220 ) 16221 thePort (LogicalPort 16222 m 1 16223 decl (Decl 16224 n "green" 16225 t "std_logic" 16226 o 2 16227 ) 16228 ) 16229 ) 16230 *561 (CptPort 16231 uid 11189,0 16232 ps "OnEdgeStrategy" 16233 shape (Triangle 16234 uid 11190,0 16235 ro 90 16236 va (VaSet 16237 vasetType 1 16238 fg "0,65535,0" 16239 ) 16240 xt "147000,126625,147750,127375" 16241 ) 16242 tg (CPTG 16243 uid 11191,0 16244 ps "CptPortTextPlaceStrategy" 16245 stg "RightVerticalLayoutStrategy" 16246 f (Text 16247 uid 11192,0 16248 va (VaSet 16249 ) 16250 xt "143500,126500,146000,127500" 16251 st "amber" 16252 ju 2 16253 blo "146000,127300" 16254 ) 16255 ) 16256 thePort (LogicalPort 16257 m 1 16258 decl (Decl 16259 n "amber" 16260 t "std_logic" 16261 o 3 16262 ) 16263 ) 16264 ) 16265 *562 (CptPort 16266 uid 11193,0 16267 ps "OnEdgeStrategy" 16268 shape (Triangle 16269 uid 11194,0 16270 ro 90 16271 va (VaSet 16272 vasetType 1 16273 fg "0,65535,0" 16274 ) 16275 xt "147000,127625,147750,128375" 16276 ) 16277 tg (CPTG 16278 uid 11195,0 16279 ps "CptPortTextPlaceStrategy" 16280 stg "RightVerticalLayoutStrategy" 16281 f (Text 16282 uid 11196,0 16283 va (VaSet 16284 ) 16285 xt "144500,127500,146000,128500" 16286 st "red" 16287 ju 2 16288 blo "146000,128300" 16289 ) 16290 ) 16291 thePort (LogicalPort 16292 m 1 16293 decl (Decl 16294 n "red" 16295 t "std_logic" 16296 o 4 16297 ) 16298 ) 16299 ) 16300 *563 (CptPort 16301 uid 11197,0 16302 ps "OnEdgeStrategy" 16303 shape (Triangle 16304 uid 11198,0 16305 ro 90 16306 va (VaSet 16307 vasetType 1 16308 fg "0,65535,0" 16309 ) 16310 xt "128250,126625,129000,127375" 16311 ) 16312 tg (CPTG 16313 uid 11199,0 16314 ps "CptPortTextPlaceStrategy" 16315 stg "VerticalLayoutStrategy" 16316 f (Text 16317 uid 11200,0 16318 va (VaSet 16319 ) 16320 xt "130000,126500,132800,127500" 16321 st "trigger" 16322 blo "130000,127300" 16323 ) 16324 ) 16325 thePort (LogicalPort 16326 decl (Decl 16327 n "trigger" 16328 t "std_logic" 16329 o 5 16330 ) 16331 ) 16332 ) 16333 *564 (CptPort 16334 uid 11201,0 16335 ps "OnEdgeStrategy" 16336 shape (Triangle 16337 uid 11202,0 16338 ro 90 16339 va (VaSet 16340 vasetType 1 16341 fg "0,65535,0" 16342 ) 16343 xt "128250,127625,129000,128375" 16344 ) 16345 tg (CPTG 16346 uid 11203,0 16347 ps "CptPortTextPlaceStrategy" 16348 stg "VerticalLayoutStrategy" 16349 f (Text 16350 uid 11204,0 16351 va (VaSet 16352 ) 16353 xt "130000,127500,135500,128500" 16354 st "socks_waiting" 16355 blo "130000,128300" 16356 ) 16357 ) 16358 thePort (LogicalPort 16359 decl (Decl 16360 n "socks_waiting" 16361 t "std_logic" 16362 o 6 16363 ) 16364 ) 16365 ) 16366 *565 (CptPort 16367 uid 11205,0 16368 ps "OnEdgeStrategy" 16369 shape (Triangle 16370 uid 11206,0 16371 ro 90 16372 va (VaSet 16373 vasetType 1 16374 fg "0,65535,0" 16375 ) 16376 xt "128250,128625,129000,129375" 16377 ) 16378 tg (CPTG 16379 uid 11207,0 16380 ps "CptPortTextPlaceStrategy" 16381 stg "VerticalLayoutStrategy" 16382 f (Text 16383 uid 11208,0 16384 va (VaSet 16385 ) 16386 xt "130000,128500,136500,129500" 16387 st "socks_connected" 16388 blo "130000,129300" 16389 ) 16390 ) 16391 thePort (LogicalPort 16392 decl (Decl 16393 n "socks_connected" 16394 t "std_logic" 16395 o 7 16396 ) 16397 ) 16398 ) 16399 ] 16400 shape (Rectangle 16401 uid 11210,0 16402 va (VaSet 16403 vasetType 1 16404 fg "0,65535,0" 16405 lineColor "0,32896,0" 16406 lineWidth 2 16407 ) 16408 xt "129000,125000,147000,131000" 16409 ) 16410 oxt "0,0,8000,10000" 16411 ttg (MlTextGroup 16412 uid 11211,0 16413 ps "CenterOffsetStrategy" 16414 stg "VerticalLayoutStrategy" 16415 textVec [ 16416 *566 (Text 16417 uid 11212,0 16418 va (VaSet 16419 font "Arial,8,1" 16420 ) 16421 xt "130900,131000,137100,132000" 16422 st "FACT_FAD_lib" 16423 blo "130900,131800" 16424 tm "BdLibraryNameMgr" 16425 ) 16426 *567 (Text 16427 uid 11213,0 16428 va (VaSet 16429 font "Arial,8,1" 16430 ) 16431 xt "130900,132000,136800,133000" 16432 st "led_controller" 16433 blo "130900,132800" 16434 tm "CptNameMgr" 16435 ) 16436 *568 (Text 16437 uid 11214,0 16438 va (VaSet 16439 font "Arial,8,1" 16440 ) 16441 xt "130900,133000,133100,134000" 16442 st "U_10" 16443 blo "130900,133800" 16444 tm "InstanceNameMgr" 16445 ) 16446 ] 16447 ) 16448 ga (GenericAssociation 16449 uid 11215,0 16450 ps "EdgeToEdgeStrategy" 16451 matrix (Matrix 16452 uid 11216,0 16453 text (MLText 16454 uid 11217,0 16455 va (VaSet 16456 font "Courier New,8,0" 16457 ) 16458 xt "129000,122600,164000,125000" 16459 st "HEARTBEAT_PWM_DIVIDER = 50000 ( integer ) -- 10kHz @ 50 MHz 16460 MAX_DELAY = 100 ( integer ) 16461 WAITING_DIVIDER = 50000000 ( integer ) -- 1Hz @ 50 MHz 16462 " 16463 ) 16464 header "" 16465 ) 16466 elements [ 16467 (GiElement 16468 name "HEARTBEAT_PWM_DIVIDER" 16469 type "integer" 16470 value "50000" 16471 e "-- 10kHz @ 50 MHz" 16472 ) 16473 (GiElement 16474 name "MAX_DELAY" 16475 type "integer" 16476 value "100" 16477 ) 16478 (GiElement 16479 name "WAITING_DIVIDER" 16480 type "integer" 16481 value "50000000" 16482 e "-- 1Hz @ 50 MHz" 16483 ) 16484 ] 16485 ) 16486 viewicon (ZoomableIcon 16487 uid 11218,0 16488 sl 0 16489 va (VaSet 16490 vasetType 1 16491 fg "49152,49152,49152" 16492 ) 16493 xt "129250,129250,130750,130750" 16494 iconName "VhdlFileViewIcon.png" 16495 iconMaskName "VhdlFileViewIcon.msk" 16496 ftype 10 16497 ) 16498 ordering 1 16499 viewiconposition 0 16500 portVis (PortSigDisplay 16501 ) 16502 archFileType "UNKNOWN" 16611 16503 ) 16612 16504 *569 (Wire … … 22141 22033 ] 22142 22034 ) 22143 end &5 5822035 end &564 22144 22036 sat 16 22145 22037 eat 32 … … 22176 22068 ] 22177 22069 ) 22178 end &5 5922070 end &565 22179 22071 sat 16 22180 22072 eat 32 … … 22212 22104 ] 22213 22105 ) 22214 end &55 322106 end &559 22215 22107 sat 16 22216 22108 eat 32 … … 22247 22139 ] 22248 22140 ) 22249 end &5 5722141 end &563 22250 22142 sat 16 22251 22143 eat 32 … … 22282 22174 ] 22283 22175 ) 22284 start &5 5422285 end &5 6422176 start &560 22177 end &553 22286 22178 sat 32 22287 22179 eat 32 … … 22305 22197 ) 22306 22198 ) 22307 on &5 6322199 on &552 22308 22200 ) 22309 22201 *728 (Wire … … 22320 22212 ] 22321 22213 ) 22322 start &5 5522323 end &5 6622214 start &561 22215 end &555 22324 22216 sat 32 22325 22217 eat 32 … … 22343 22235 ) 22344 22236 ) 22345 on &5 6522237 on &554 22346 22238 ) 22347 22239 *729 (Wire … … 22358 22250 ] 22359 22251 ) 22360 start &5 5622361 end &5 6822252 start &562 22253 end &557 22362 22254 sat 32 22363 22255 eat 32 … … 22381 22273 ) 22382 22274 ) 22383 on &5 6722275 on &556 22384 22276 ) 22385 22277 ] … … 22504 22396 windowSize "1280,0,2561,1024" 22505 22397 viewArea "107600,77300,192480,147300" 22506 cachedDiagramExtent "-105000,-60500,16 3300,343294"22398 cachedDiagramExtent "-105000,-60500,164000,343294" 22507 22399 pageSetupInfo (PageSetupInfo 22508 22400 ptrCmd "eDocPrintPro,winspool," … … 22529 22421 hasePageBreakOrigin 1 22530 22422 pageBreakOrigin "-73000,0" 22531 lastUid 1 0893,022423 lastUid 11301,0 22532 22424 defaultCommentText (CommentText 22533 22425 shape (Rectangle -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak
r10074 r10075 239 239 elements [ 240 240 (GiElement 241 name "HEARTBEAT_ DIVIDER"241 name "HEARTBEAT_PWM_DIVIDER" 242 242 type "integer" 243 value "25000000" 244 e "-- 2Hz @ 50 MHz" 243 value "500" 244 e "-- 10kHz @ 50 MHz" 245 ) 246 (GiElement 247 name "MAX_DELAY" 248 type "integer" 249 value "100" 245 250 ) 246 251 (GiElement 247 252 name "WAITING_DIVIDER" 248 253 type "integer" 249 value "5000000 "250 e "-- 1 0Hz @ 50 MHz"254 value "50000000" 255 e "-- 1Hz @ 50 MHz" 251 256 ) 252 257 ] 253 258 mwi 0 254 uid 1 0675,0259 uid 11209,0 255 260 ) 256 261 ] … … 461 466 (vvPair 462 467 variable "time" 463 value "1 2:17:30"468 value "17:54:26" 464 469 ) 465 470 (vvPair … … 553 558 ) 554 559 xt "-103000,118600,-59500,119400" 555 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\" 556 " 560 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\"" 557 561 ) 558 562 ) … … 572 576 ) 573 577 xt "-103000,64200,-63000,65000" 574 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 575 " 578 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 576 579 ) 577 580 ) … … 591 594 ) 592 595 xt "-103000,81800,-70500,82600" 593 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0) 594 " 596 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0)" 595 597 ) 596 598 ) … … 610 612 ) 611 613 xt "-103000,94600,-63000,95400" 612 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) 613 " 614 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)" 614 615 ) 615 616 ) … … 629 630 ) 630 631 xt "-103000,95400,-70500,96200" 631 st "SIGNAL ram_data : std_logic_vector(15 downto 0) 632 " 632 st "SIGNAL ram_data : std_logic_vector(15 downto 0)" 633 633 ) 634 634 ) … … 648 648 ) 649 649 xt "-103000,55800,-63000,56600" 650 st "wiz_reset : std_logic := '1' 651 " 650 st "wiz_reset : std_logic := '1'" 652 651 ) 653 652 ) … … 667 666 ) 668 667 xt "-103000,53400,-74500,54200" 669 st "wiz_addr : std_logic_vector(9 DOWNTO 0) 670 " 668 st "wiz_addr : std_logic_vector(9 DOWNTO 0)" 671 669 ) 672 670 ) … … 686 684 ) 687 685 xt "-103000,58200,-74000,59000" 688 st "wiz_data : std_logic_vector(15 DOWNTO 0) 689 " 686 st "wiz_data : std_logic_vector(15 DOWNTO 0)" 690 687 ) 691 688 ) … … 705 702 ) 706 703 xt "-103000,54200,-63000,55000" 707 st "wiz_cs : std_logic := '1' 708 " 704 st "wiz_cs : std_logic := '1'" 709 705 ) 710 706 ) … … 724 720 ) 725 721 xt "-103000,56600,-63000,57400" 726 st "wiz_wr : std_logic := '1' 727 " 722 st "wiz_wr : std_logic := '1'" 728 723 ) 729 724 ) … … 743 738 ) 744 739 xt "-103000,55000,-63000,55800" 745 st "wiz_rd : std_logic := '1' 746 " 740 st "wiz_rd : std_logic := '1'" 747 741 ) 748 742 ) … … 761 755 ) 762 756 xt "-103000,26200,-84500,27000" 763 st "wiz_int : std_logic 764 " 757 st "wiz_int : std_logic" 765 758 ) 766 759 ) … … 2779 2772 ) 2780 2773 xt "-103000,23800,-74500,24600" 2781 st "board_id : std_logic_vector(3 downto 0) 2782 " 2774 st "board_id : std_logic_vector(3 downto 0)" 2783 2775 ) 2784 2776 ) … … 2799 2791 ) 2800 2792 xt "-103000,25400,-84500,26200" 2801 st "trigger : std_logic 2802 " 2793 st "trigger : std_logic" 2803 2794 ) 2804 2795 ) … … 4373 4364 ) 4374 4365 xt "-103000,24600,-74500,25400" 4375 st "crate_id : std_logic_vector(1 downto 0) 4376 " 4366 st "crate_id : std_logic_vector(1 downto 0)" 4377 4367 ) 4378 4368 ) … … 4595 4585 ) 4596 4586 xt "-103000,110600,-70500,111400" 4597 st "SIGNAL trigger_id : std_logic_vector(47 downto 0) 4598 " 4587 st "SIGNAL trigger_id : std_logic_vector(47 downto 0)" 4599 4588 ) 4600 4589 ) … … 4616 4605 ) 4617 4606 xt "-103000,96200,-63000,97000" 4618 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 4619 " 4607 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 4620 4608 ) 4621 4609 ) … … 5467 5455 ) 5468 5456 xt "-103000,113000,-80500,113800" 5469 st "SIGNAL wiz_busy : std_logic 5470 " 5457 st "SIGNAL wiz_busy : std_logic" 5471 5458 ) 5472 5459 ) … … 5487 5474 ) 5488 5475 xt "-103000,115400,-59500,116200" 5489 st "SIGNAL wiz_write_ea : std_logic := '0' 5490 " 5476 st "SIGNAL wiz_write_ea : std_logic := '0'" 5491 5477 ) 5492 5478 ) … … 5508 5494 ) 5509 5495 xt "-103000,117800,-53500,118600" 5510 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') 5511 " 5496 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0')" 5512 5497 ) 5513 5498 ) … … 5530 5515 ) 5531 5516 xt "-103000,114600,-53500,115400" 5532 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') 5533 " 5517 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')" 5534 5518 ) 5535 5519 ) … … 5551 5535 ) 5552 5536 xt "-103000,113800,-53500,114600" 5553 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') 5554 " 5537 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0')" 5555 5538 ) 5556 5539 ) … … 5571 5554 ) 5572 5555 xt "-103000,116200,-59500,117000" 5573 st "SIGNAL wiz_write_end : std_logic := '0' 5574 " 5556 st "SIGNAL wiz_write_end : std_logic := '0'" 5575 5557 ) 5576 5558 ) … … 5591 5573 ) 5592 5574 xt "-103000,117000,-59500,117800" 5593 st "SIGNAL wiz_write_header : std_logic := '0' 5594 " 5575 st "SIGNAL wiz_write_header : std_logic := '0'" 5595 5576 ) 5596 5577 ) … … 5609 5590 ) 5610 5591 xt "-103000,97000,-80500,97800" 5611 st "SIGNAL ram_write_ea : std_logic 5612 " 5592 st "SIGNAL ram_write_ea : std_logic" 5613 5593 ) 5614 5594 ) … … 5628 5608 ) 5629 5609 xt "-103000,97800,-59500,98600" 5630 st "SIGNAL ram_write_ready : std_logic := '0' 5631 " 5610 st "SIGNAL ram_write_ready : std_logic := '0'" 5632 5611 ) 5633 5612 ) … … 5647 5626 ) 5648 5627 xt "-103000,74600,-59500,75400" 5649 st "SIGNAL config_start : std_logic := '0' 5650 " 5628 st "SIGNAL config_start : std_logic := '0'" 5651 5629 ) 5652 5630 ) … … 5665 5643 ) 5666 5644 xt "-103000,69000,-80500,69800" 5667 st "SIGNAL config_ready : std_logic 5668 " 5645 st "SIGNAL config_ready : std_logic" 5669 5646 ) 5670 5647 ) … … 5683 5660 ) 5684 5661 xt "-103000,101000,-79000,101800" 5685 st "SIGNAL roi_max : roi_max_type 5686 " 5662 st "SIGNAL roi_max : roi_max_type" 5687 5663 ) 5688 5664 ) … … 5702 5678 ) 5703 5679 xt "-103000,91400,-70500,92200" 5704 st "SIGNAL package_length : std_logic_vector(15 downto 0) 5705 " 5680 st "SIGNAL package_length : std_logic_vector(15 downto 0)" 5706 5681 ) 5707 5682 ) … … 5721 5696 ) 5722 5697 xt "-103000,40600,-63000,41400" 5723 st "adc_oeb : std_logic := '1' 5724 " 5698 st "adc_oeb : std_logic := '1'" 5725 5699 ) 5726 5700 ) … … 5829 5803 ) 5830 5804 xt "-103000,100200,-78000,101000" 5831 st "SIGNAL roi_array : roi_array_type 5832 " 5805 st "SIGNAL roi_array : roi_array_type" 5833 5806 ) 5834 5807 ) … … 6263 6236 ) 6264 6237 xt "-103000,29400,-84500,30200" 6265 st "CLK_25_PS : std_logic 6266 " 6238 st "CLK_25_PS : std_logic" 6267 6239 ) 6268 6240 ) … … 6326 6298 ) 6327 6299 xt "-103000,30200,-84500,31000" 6328 st "CLK_50 : std_logic 6329 " 6300 st "CLK_50 : std_logic" 6330 6301 ) 6331 6302 ) … … 6344 6315 ) 6345 6316 xt "-103000,61000,-80500,61800" 6346 st "SIGNAL CLK_25 : std_logic 6347 " 6317 st "SIGNAL CLK_25 : std_logic" 6348 6318 ) 6349 6319 ) … … 6407 6377 ) 6408 6378 xt "-103000,18200,-84500,19000" 6409 st "CLK : std_logic 6410 " 6379 st "CLK : std_logic" 6411 6380 ) 6412 6381 ) … … 6426 6395 ) 6427 6396 xt "-103000,23000,-74500,23800" 6428 st "adc_otr_array : std_logic_vector(3 DOWNTO 0) 6429 " 6397 st "adc_otr_array : std_logic_vector(3 DOWNTO 0)" 6430 6398 ) 6431 6399 ) … … 6444 6412 ) 6445 6413 xt "-103000,22200,-79000,23000" 6446 st "adc_data_array : adc_data_array_type 6447 " 6414 st "adc_data_array : adc_data_array_type" 6448 6415 ) 6449 6416 ) … … 6508 6475 ) 6509 6476 xt "-103000,85000,-59500,85800" 6510 st "SIGNAL drs_clk_en : std_logic := '0' 6511 " 6477 st "SIGNAL drs_clk_en : std_logic := '0'" 6512 6478 ) 6513 6479 ) … … 6526 6492 ) 6527 6493 xt "-103000,87400,-74500,88200" 6528 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type 6529 " 6494 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type" 6530 6495 ) 6531 6496 ) … … 6545 6510 ) 6546 6511 xt "-103000,85800,-59500,86600" 6547 st "SIGNAL drs_read_s_cell : std_logic := '0' 6548 " 6512 st "SIGNAL drs_read_s_cell : std_logic := '0'" 6549 6513 ) 6550 6514 ) … … 6565 6529 ) 6566 6530 xt "-103000,43800,-57000,44600" 6567 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6568 " 6531 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 6569 6532 ) 6570 6533 ) … … 6584 6547 ) 6585 6548 xt "-103000,44600,-63000,45400" 6586 st "drs_dwrite : std_logic := '1' 6587 " 6549 st "drs_dwrite : std_logic := '1'" 6588 6550 ) 6589 6551 ) … … 6692 6654 ) 6693 6655 xt "-103000,19000,-84500,19800" 6694 st "SROUT_in_0 : std_logic 6695 " 6656 st "SROUT_in_0 : std_logic" 6696 6657 ) 6697 6658 ) … … 6710 6671 ) 6711 6672 xt "-103000,19800,-84500,20600" 6712 st "SROUT_in_1 : std_logic 6713 " 6673 st "SROUT_in_1 : std_logic" 6714 6674 ) 6715 6675 ) … … 6728 6688 ) 6729 6689 xt "-103000,20600,-84500,21400" 6730 st "SROUT_in_2 : std_logic 6731 " 6690 st "SROUT_in_2 : std_logic" 6732 6691 ) 6733 6692 ) … … 6746 6705 ) 6747 6706 xt "-103000,21400,-84500,22200" 6748 st "SROUT_in_3 : std_logic 6749 " 6707 st "SROUT_in_3 : std_logic" 6750 6708 ) 6751 6709 ) … … 6944 6902 ) 6945 6903 xt "-103000,86600,-80500,87400" 6946 st "SIGNAL drs_read_s_cell_ready : std_logic 6947 " 6904 st "SIGNAL drs_read_s_cell_ready : std_logic" 6948 6905 ) 6949 6906 ) … … 7600 7557 ) 7601 7558 xt "-103000,37400,-63000,38200" 7602 st "RSRLOAD : std_logic := '0' 7603 " 7559 st "RSRLOAD : std_logic := '0'" 7604 7560 ) 7605 7561 ) … … 7664 7620 ) 7665 7621 xt "-103000,38200,-63000,39000" 7666 st "SRCLK : std_logic := '0' 7667 " 7622 st "SRCLK : std_logic := '0'" 7668 7623 ) 7669 7624 ) … … 8318 8273 ) 8319 8274 xt "-103000,65000,-71000,65800" 8320 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0) 8321 " 8275 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0)" 8322 8276 ) 8323 8277 ) … … 8336 8290 ) 8337 8291 xt "-103000,67400,-80500,68200" 8338 st "SIGNAL config_data_valid : std_logic 8339 " 8292 st "SIGNAL config_data_valid : std_logic" 8340 8293 ) 8341 8294 ) … … 8354 8307 ) 8355 8308 xt "-103000,65800,-80500,66600" 8356 st "SIGNAL config_busy : std_logic 8357 " 8309 st "SIGNAL config_busy : std_logic" 8358 8310 ) 8359 8311 ) … … 8373 8325 ) 8374 8326 xt "-103000,66600,-70500,67400" 8375 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0) 8376 " 8327 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0)" 8377 8328 ) 8378 8329 ) … … 8391 8342 ) 8392 8343 xt "-103000,80200,-80500,81000" 8393 st "SIGNAL config_wr_en : std_logic 8394 " 8344 st "SIGNAL config_wr_en : std_logic" 8395 8345 ) 8396 8346 ) … … 8409 8359 ) 8410 8360 xt "-103000,68200,-80500,69000" 8411 st "SIGNAL config_rd_en : std_logic 8412 " 8361 st "SIGNAL config_rd_en : std_logic" 8413 8362 ) 8414 8363 ) … … 8427 8376 ) 8428 8377 xt "-103000,81000,-78000,81800" 8429 st "SIGNAL dac_array : dac_array_type 8430 " 8378 st "SIGNAL dac_array : dac_array_type" 8431 8379 ) 8432 8380 ) … … 8445 8393 ) 8446 8394 xt "-103000,75400,-80500,76200" 8447 st "SIGNAL config_start_cm : std_logic 8448 " 8395 st "SIGNAL config_start_cm : std_logic" 8449 8396 ) 8450 8397 ) … … 8463 8410 ) 8464 8411 xt "-103000,69800,-80500,70600" 8465 st "SIGNAL config_ready_cm : std_logic 8466 " 8412 st "SIGNAL config_ready_cm : std_logic" 8467 8413 ) 8468 8414 ) … … 8484 8430 ) 8485 8431 xt "-103000,46200,-57000,47000" 8486 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 8487 " 8432 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 8488 8433 ) 8489 8434 ) … … 8502 8447 ) 8503 8448 xt "-103000,105000,-80500,105800" 8504 st "SIGNAL sensor_ready : std_logic 8505 " 8449 st "SIGNAL sensor_ready : std_logic" 8506 8450 ) 8507 8451 ) … … 8520 8464 ) 8521 8465 xt "-103000,104200,-76500,105000" 8522 st "SIGNAL sensor_array : sensor_array_type 8523 " 8466 st "SIGNAL sensor_array : sensor_array_type" 8524 8467 ) 8525 8468 ) … … 8538 8481 ) 8539 8482 xt "-103000,70600,-80500,71400" 8540 st "SIGNAL config_ready_spi : std_logic 8541 " 8483 st "SIGNAL config_ready_spi : std_logic" 8542 8484 ) 8543 8485 ) … … 8558 8500 ) 8559 8501 xt "-103000,63400,-71000,64200" 8560 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0) 8561 " 8502 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0)" 8562 8503 ) 8563 8504 ) … … 8576 8517 ) 8577 8518 xt "-103000,62600,-75500,63400" 8578 st "SIGNAL adc_data_array_int : adc_data_array_type 8579 " 8519 st "SIGNAL adc_data_array_int : adc_data_array_type" 8580 8520 ) 8581 8521 ) … … 8867 8807 ) 8868 8808 xt "-103000,76200,-59500,77000" 8869 st "SIGNAL config_start_spi : std_logic := '0' 8870 " 8809 st "SIGNAL config_start_spi : std_logic := '0'" 8871 8810 ) 8872 8811 ) … … 9401 9340 ) 9402 9341 xt "-103000,50200,-84500,51000" 9403 st "sclk : std_logic 9404 " 9342 st "sclk : std_logic" 9405 9343 ) 9406 9344 ) … … 9421 9359 ) 9422 9360 xt "-103000,57400,-84500,58200" 9423 st "sio : std_logic 9424 " 9361 st "sio : std_logic" 9425 9362 ) 9426 9363 ) … … 9439 9376 ) 9440 9377 xt "-103000,42200,-84500,43000" 9441 st "dac_cs : std_logic 9442 " 9378 st "dac_cs : std_logic" 9443 9379 ) 9444 9380 ) … … 9458 9394 ) 9459 9395 xt "-103000,51000,-74500,51800" 9460 st "sensor_cs : std_logic_vector(3 DOWNTO 0) 9461 " 9396 st "sensor_cs : std_logic_vector(3 DOWNTO 0)" 9462 9397 ) 9463 9398 ) … … 9657 9592 ) 9658 9593 xt "-103000,90600,-59500,91400" 9659 st "SIGNAL new_config : std_logic := '0' 9660 " 9594 st "SIGNAL new_config : std_logic := '0'" 9661 9595 ) 9662 9596 ) … … 9675 9609 ) 9676 9610 xt "-103000,77000,-80500,77800" 9677 st "SIGNAL config_started : std_logic 9678 " 9611 st "SIGNAL config_started : std_logic" 9679 9612 ) 9680 9613 ) … … 9694 9627 ) 9695 9628 xt "-103000,79400,-59500,80200" 9696 st "SIGNAL config_started_spi : std_logic := '0' 9697 " 9629 st "SIGNAL config_started_spi : std_logic := '0'" 9698 9630 ) 9699 9631 ) … … 9713 9645 ) 9714 9646 xt "-103000,77800,-59500,78600" 9715 st "SIGNAL config_started_cu : std_logic := '0' 9716 " 9647 st "SIGNAL config_started_cu : std_logic := '0'" 9717 9648 ) 9718 9649 ) … … 9731 9662 ) 9732 9663 xt "-103000,78600,-80500,79400" 9733 st "SIGNAL config_started_mm : std_logic 9734 " 9664 st "SIGNAL config_started_mm : std_logic" 9735 9665 ) 9736 9666 ) … … 9750 9680 ) 9751 9681 xt "-103000,47000,-63000,47800" 9752 st "mosi : std_logic := '0' 9753 " 9682 st "mosi : std_logic := '0'" 9754 9683 ) 9755 9684 ) … … 9816 9745 ) 9817 9746 xt "-103000,43000,-49500,43800" 9818 st "denable : std_logic := '0' -- default domino wave off 9819 " 9747 st "denable : std_logic := '0' -- default domino wave off" 9820 9748 ) 9821 9749 ) … … 9879 9807 ) 9880 9808 xt "-103000,89800,-59500,90600" 9881 st "SIGNAL dwrite_enable : std_logic := '1' 9882 " 9809 st "SIGNAL dwrite_enable : std_logic := '1'" 9883 9810 ) 9884 9811 ) … … 10267 10194 ) 10268 10195 xt "-103000,89000,-59500,89800" 10269 st "SIGNAL dwrite : std_logic := '1' 10270 " 10196 st "SIGNAL dwrite : std_logic := '1'" 10271 10197 ) 10272 10198 ) … … 10642 10568 ) 10643 10569 xt "-103000,112200,-80500,113000" 10644 st "SIGNAL wiz_ack : std_logic 10645 " 10570 st "SIGNAL wiz_ack : std_logic" 10646 10571 ) 10647 10572 ) … … 10662 10587 ) 10663 10588 xt "-103000,82600,-53500,83400" 10664 st "SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0') 10665 " 10589 st "SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0')" 10666 10590 ) 10667 10591 ) … … 10680 10604 ) 10681 10605 xt "-103000,83400,-80500,84200" 10682 st "SIGNAL drs_address_mode : std_logic 10683 " 10606 st "SIGNAL drs_address_mode : std_logic" 10684 10607 ) 10685 10608 ) … … 11228 11151 ) 11229 11152 xt "-103000,84200,-53500,85000" 11230 st "SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0') 11231 " 11153 st "SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0')" 11232 11154 ) 11233 11155 ) … … 11612 11534 ) 11613 11535 xt "-103000,102600,-80500,103400" 11614 st "SIGNAL sclk1 : std_logic 11615 " 11536 st "SIGNAL sclk1 : std_logic" 11616 11537 ) 11617 11538 ) … … 11630 11551 ) 11631 11552 xt "-103000,103400,-80500,104200" 11632 st "SIGNAL sclk_enable : std_logic 11633 " 11553 st "SIGNAL sclk_enable : std_logic" 11634 11554 ) 11635 11555 ) … … 11649 11569 ) 11650 11570 xt "-103000,39800,-63000,40600" 11651 st "adc_clk_en : std_logic := '0' 11652 " 11571 st "adc_clk_en : std_logic := '0'" 11653 11572 ) 11654 11573 ) … … 12429 12348 ) 12430 12349 xt "-103000,92200,-44000,93000" 12431 st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards 12432 " 12350 st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards" 12433 12351 ) 12434 12352 ) … … 12451 12369 ) 12452 12370 xt "-103000,93000,-43000,93800" 12453 st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once 12454 " 12371 st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once" 12455 12372 ) 12456 12373 ) … … 12469 12386 ) 12470 12387 xt "-103000,31800,-84500,32600" 12471 st "LOCKED_extraOUT : std_logic 12472 " 12388 st "LOCKED_extraOUT : std_logic" 12473 12389 ) 12474 12390 ) … … 12531 12447 ) 12532 12448 xt "-103000,33400,-84500,34200" 12533 st "PSDONE_extraOUT : std_logic 12534 " 12449 st "PSDONE_extraOUT : std_logic" 12535 12450 ) 12536 12451 ) … … 12593 12508 ) 12594 12509 xt "-103000,35000,-84500,35800" 12595 st "PSINCDEC_OUT : std_logic 12596 " 12510 st "PSINCDEC_OUT : std_logic" 12597 12511 ) 12598 12512 ) … … 12655 12569 ) 12656 12570 xt "-103000,34200,-84500,35000" 12657 st "PSEN_OUT : std_logic 12658 " 12571 st "PSEN_OUT : std_logic" 12659 12572 ) 12660 12573 ) … … 12717 12630 ) 12718 12631 xt "-103000,32600,-84500,33400" 12719 st "PSCLK_OUT : std_logic 12720 " 12632 st "PSCLK_OUT : std_logic" 12721 12633 ) 12722 12634 ) … … 12781 12693 ) 12782 12694 xt "-103000,31000,-84500,31800" 12783 st "DCM_locked : std_logic 12784 " 12695 st "DCM_locked : std_logic" 12785 12696 ) 12786 12697 ) … … 12847 12758 ) 12848 12759 xt "-103000,47800,-57000,48600" 12849 st "offset : std_logic_vector(7 downto 0) := (OTHERS => '0') 12850 " 12760 st "offset : std_logic_vector(7 downto 0) := (OTHERS => '0')" 12851 12761 ) 12852 12762 ) … … 12914 12824 xt "-103000,51800,-63000,53400" 12915 12825 st "-- status: 12916 shifting : std_logic := '0' 12917 " 12826 shifting : std_logic := '0'" 12918 12827 ) 12919 12828 ) … … 12979 12888 ) 12980 12889 xt "-103000,48600,-63000,49400" 12981 st "ready : std_logic := '0' 12982 " 12890 st "ready : std_logic := '0'" 12983 12891 ) 12984 12892 ) … … 13768 13676 ) 13769 13677 xt "-103000,35800,-84500,36600" 13770 st "PS_DIR_IN : std_logic 13771 " 13678 st "PS_DIR_IN : std_logic" 13772 13679 ) 13773 13680 ) … … 13786 13693 ) 13787 13694 xt "-103000,36600,-84500,37400" 13788 st "PS_DO_IN : std_logic 13789 " 13695 st "PS_DO_IN : std_logic" 13790 13696 ) 13791 13697 ) … … 14795 14701 ) 14796 14702 xt "-103000,28600,-84500,29400" 14797 st "CLK50_OUT : std_logic 14798 " 14703 st "CLK50_OUT : std_logic" 14799 14704 ) 14800 14705 ) … … 14857 14762 ) 14858 14763 xt "-103000,27000,-84500,27800" 14859 st "CLK25_OUT : std_logic 14860 " 14764 st "CLK25_OUT : std_logic" 14861 14765 ) 14862 14766 ) … … 14919 14823 ) 14920 14824 xt "-103000,27800,-84500,28600" 14921 st "CLK25_PSOUT : std_logic 14922 " 14825 st "CLK25_PSOUT : std_logic" 14923 14826 ) 14924 14827 ) … … 14940 14843 ) 14941 14844 xt "-103000,93800,-35500,94600" 14942 st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift 14943 " 14845 st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift" 14944 14846 ) 14945 14847 ) … … 14959 14861 ) 14960 14862 xt "-103000,107400,-59500,108200" 14961 st "SIGNAL srclk_enable : std_logic := '0' 14962 " 14863 st "SIGNAL srclk_enable : std_logic := '0'" 14963 14864 ) 14964 14865 ) … … 15344 15245 ) 15345 15246 xt "-103000,61800,-59500,62600" 15346 st "SIGNAL SRCLK1 : std_logic := '0' 15347 " 15247 st "SIGNAL SRCLK1 : std_logic := '0'" 15348 15248 ) 15349 15249 ) … … 15367 15267 xt "-103000,71400,-59500,73000" 15368 15268 st "-- -- 15369 SIGNAL config_rw_ack : std_logic := '0' 15370 " 15269 SIGNAL config_rw_ack : std_logic := '0'" 15371 15270 ) 15372 15271 ) … … 15390 15289 xt "-103000,73000,-59500,74600" 15391 15290 st "-- -- 15392 SIGNAL config_rw_ready : std_logic := '0' 15393 " 15291 SIGNAL config_rw_ready : std_logic := '0'" 15394 15292 ) 15395 15293 ) … … 15408 15306 ) 15409 15307 xt "-103000,101800,-80500,102600" 15410 st "SIGNAL s_trigger : std_logic 15411 " 15308 st "SIGNAL s_trigger : std_logic" 15412 15309 ) 15413 15310 ) … … 15426 15323 ) 15427 15324 xt "-103000,109800,-80500,110600" 15428 st "SIGNAL start_srin_write_8b : std_logic 15429 " 15325 st "SIGNAL start_srin_write_8b : std_logic" 15430 15326 ) 15431 15327 ) … … 15445 15341 ) 15446 15342 xt "-103000,108200,-59500,109000" 15447 st "SIGNAL srin_write_ack : std_logic := '0' 15448 " 15343 st "SIGNAL srin_write_ack : std_logic := '0'" 15449 15344 ) 15450 15345 ) … … 15464 15359 ) 15465 15360 xt "-103000,109000,-59500,109800" 15466 st "SIGNAL srin_write_ready : std_logic := '0' 15467 " 15361 st "SIGNAL srin_write_ready : std_logic := '0'" 15468 15362 ) 15469 15363 ) … … 15484 15378 ) 15485 15379 xt "-103000,88200,-53500,89000" 15486 st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0') 15487 " 15380 st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0')" 15488 15381 ) 15489 15382 ) … … 15503 15396 ) 15504 15397 xt "-103000,39000,-63000,39800" 15505 st "SRIN_out : std_logic := '0' 15506 " 15398 st "SRIN_out : std_logic := '0'" 15507 15399 ) 15508 15400 ) … … 16022 15914 ) 16023 15915 xt "-103000,111400,-80500,112200" 16024 st "SIGNAL trigger_out : std_logic 16025 " 15916 st "SIGNAL trigger_out : std_logic" 16026 15917 ) 16027 15918 ) … … 16046 15937 xt "-103000,98600,-59500,100200" 16047 15938 st "-- -- 16048 SIGNAL ram_write_ready_ack : std_logic := '0' 16049 " 15939 SIGNAL ram_write_ready_ack : std_logic := '0'" 16050 15940 ) 16051 15941 ) … … 16064 15954 ) 16065 15955 xt "-103000,105800,-80500,106600" 16066 st "SIGNAL socks_connected : std_logic 16067 " 15956 st "SIGNAL socks_connected : std_logic" 16068 15957 ) 16069 15958 ) … … 16082 15971 ) 16083 15972 xt "-103000,106600,-80500,107400" 16084 st "SIGNAL socks_waiting : std_logic 16085 " 16086 ) 16087 ) 16088 *552 (SaComponent 16089 uid 10675,0 16090 optionalChildren [ 16091 *553 (CptPort 16092 uid 10643,0 16093 ps "OnEdgeStrategy" 16094 shape (Triangle 16095 uid 10644,0 16096 ro 90 16097 va (VaSet 16098 vasetType 1 16099 fg "0,65535,0" 16100 ) 16101 xt "128250,125625,129000,126375" 16102 ) 16103 tg (CPTG 16104 uid 10645,0 16105 ps "CptPortTextPlaceStrategy" 16106 stg "VerticalLayoutStrategy" 16107 f (Text 16108 uid 10646,0 16109 va (VaSet 16110 ) 16111 xt "130000,125500,131900,126500" 16112 st "CLK" 16113 blo "130000,126300" 16114 ) 16115 ) 16116 thePort (LogicalPort 16117 decl (Decl 16118 n "CLK" 16119 t "std_logic" 16120 o 1 16121 ) 16122 ) 16123 ) 16124 *554 (CptPort 16125 uid 10647,0 16126 ps "OnEdgeStrategy" 16127 shape (Triangle 16128 uid 10648,0 16129 ro 90 16130 va (VaSet 16131 vasetType 1 16132 fg "0,65535,0" 16133 ) 16134 xt "147000,125625,147750,126375" 16135 ) 16136 tg (CPTG 16137 uid 10649,0 16138 ps "CptPortTextPlaceStrategy" 16139 stg "RightVerticalLayoutStrategy" 16140 f (Text 16141 uid 10650,0 16142 va (VaSet 16143 ) 16144 xt "143600,125500,146000,126500" 16145 st "green" 16146 ju 2 16147 blo "146000,126300" 16148 ) 16149 ) 16150 thePort (LogicalPort 16151 m 1 16152 decl (Decl 16153 n "green" 16154 t "std_logic" 16155 o 2 16156 ) 16157 ) 16158 ) 16159 *555 (CptPort 16160 uid 10651,0 16161 ps "OnEdgeStrategy" 16162 shape (Triangle 16163 uid 10652,0 16164 ro 90 16165 va (VaSet 16166 vasetType 1 16167 fg "0,65535,0" 16168 ) 16169 xt "147000,126625,147750,127375" 16170 ) 16171 tg (CPTG 16172 uid 10653,0 16173 ps "CptPortTextPlaceStrategy" 16174 stg "RightVerticalLayoutStrategy" 16175 f (Text 16176 uid 10654,0 16177 va (VaSet 16178 ) 16179 xt "143500,126500,146000,127500" 16180 st "amber" 16181 ju 2 16182 blo "146000,127300" 16183 ) 16184 ) 16185 thePort (LogicalPort 16186 m 1 16187 decl (Decl 16188 n "amber" 16189 t "std_logic" 16190 o 3 16191 ) 16192 ) 16193 ) 16194 *556 (CptPort 16195 uid 10655,0 16196 ps "OnEdgeStrategy" 16197 shape (Triangle 16198 uid 10656,0 16199 ro 90 16200 va (VaSet 16201 vasetType 1 16202 fg "0,65535,0" 16203 ) 16204 xt "147000,127625,147750,128375" 16205 ) 16206 tg (CPTG 16207 uid 10657,0 16208 ps "CptPortTextPlaceStrategy" 16209 stg "RightVerticalLayoutStrategy" 16210 f (Text 16211 uid 10658,0 16212 va (VaSet 16213 ) 16214 xt "144500,127500,146000,128500" 16215 st "red" 16216 ju 2 16217 blo "146000,128300" 16218 ) 16219 ) 16220 thePort (LogicalPort 16221 m 1 16222 decl (Decl 16223 n "red" 16224 t "std_logic" 16225 o 4 16226 ) 16227 ) 16228 ) 16229 *557 (CptPort 16230 uid 10659,0 16231 ps "OnEdgeStrategy" 16232 shape (Triangle 16233 uid 10660,0 16234 ro 90 16235 va (VaSet 16236 vasetType 1 16237 fg "0,65535,0" 16238 ) 16239 xt "128250,126625,129000,127375" 16240 ) 16241 tg (CPTG 16242 uid 10661,0 16243 ps "CptPortTextPlaceStrategy" 16244 stg "VerticalLayoutStrategy" 16245 f (Text 16246 uid 10662,0 16247 va (VaSet 16248 ) 16249 xt "130000,126500,132800,127500" 16250 st "trigger" 16251 blo "130000,127300" 16252 ) 16253 ) 16254 thePort (LogicalPort 16255 decl (Decl 16256 n "trigger" 16257 t "std_logic" 16258 o 5 16259 ) 16260 ) 16261 ) 16262 *558 (CptPort 16263 uid 10663,0 16264 ps "OnEdgeStrategy" 16265 shape (Triangle 16266 uid 10664,0 16267 ro 90 16268 va (VaSet 16269 vasetType 1 16270 fg "0,65535,0" 16271 ) 16272 xt "128250,127625,129000,128375" 16273 ) 16274 tg (CPTG 16275 uid 10665,0 16276 ps "CptPortTextPlaceStrategy" 16277 stg "VerticalLayoutStrategy" 16278 f (Text 16279 uid 10666,0 16280 va (VaSet 16281 ) 16282 xt "130000,127500,135500,128500" 16283 st "socks_waiting" 16284 blo "130000,128300" 16285 ) 16286 ) 16287 thePort (LogicalPort 16288 decl (Decl 16289 n "socks_waiting" 16290 t "std_logic" 16291 o 6 16292 ) 16293 ) 16294 ) 16295 *559 (CptPort 16296 uid 10667,0 16297 ps "OnEdgeStrategy" 16298 shape (Triangle 16299 uid 10668,0 16300 ro 90 16301 va (VaSet 16302 vasetType 1 16303 fg "0,65535,0" 16304 ) 16305 xt "128250,128625,129000,129375" 16306 ) 16307 tg (CPTG 16308 uid 10669,0 16309 ps "CptPortTextPlaceStrategy" 16310 stg "VerticalLayoutStrategy" 16311 f (Text 16312 uid 10670,0 16313 va (VaSet 16314 ) 16315 xt "130000,128500,136500,129500" 16316 st "socks_connected" 16317 blo "130000,129300" 16318 ) 16319 ) 16320 thePort (LogicalPort 16321 decl (Decl 16322 n "socks_connected" 16323 t "std_logic" 16324 o 7 16325 ) 16326 ) 16327 ) 16328 ] 16329 shape (Rectangle 16330 uid 10676,0 16331 va (VaSet 16332 vasetType 1 16333 fg "0,65535,0" 16334 lineColor "0,32896,0" 16335 lineWidth 2 16336 ) 16337 xt "129000,125000,147000,131000" 16338 ) 16339 oxt "0,0,8000,10000" 16340 ttg (MlTextGroup 16341 uid 10677,0 16342 ps "CenterOffsetStrategy" 16343 stg "VerticalLayoutStrategy" 16344 textVec [ 16345 *560 (Text 16346 uid 10678,0 16347 va (VaSet 16348 font "Arial,8,1" 16349 ) 16350 xt "130900,131000,137100,132000" 16351 st "FACT_FAD_lib" 16352 blo "130900,131800" 16353 tm "BdLibraryNameMgr" 16354 ) 16355 *561 (Text 16356 uid 10679,0 16357 va (VaSet 16358 font "Arial,8,1" 16359 ) 16360 xt "130900,132000,136800,133000" 16361 st "led_controller" 16362 blo "130900,132800" 16363 tm "CptNameMgr" 16364 ) 16365 *562 (Text 16366 uid 10680,0 16367 va (VaSet 16368 font "Arial,8,1" 16369 ) 16370 xt "130900,133000,133100,134000" 16371 st "U_10" 16372 blo "130900,133800" 16373 tm "InstanceNameMgr" 16374 ) 16375 ] 16376 ) 16377 ga (GenericAssociation 16378 uid 10681,0 16379 ps "EdgeToEdgeStrategy" 16380 matrix (Matrix 16381 uid 10682,0 16382 text (MLText 16383 uid 10683,0 16384 va (VaSet 16385 font "Courier New,8,0" 16386 ) 16387 xt "129000,123400,161500,125000" 16388 st "HEARTBEAT_DIVIDER = 25000000 ( integer ) -- 2Hz @ 50 MHz 16389 WAITING_DIVIDER = 5000000 ( integer ) -- 10Hz @ 50 MHz " 16390 ) 16391 header "" 16392 ) 16393 elements [ 16394 (GiElement 16395 name "HEARTBEAT_DIVIDER" 16396 type "integer" 16397 value "25000000" 16398 e "-- 2Hz @ 50 MHz" 16399 ) 16400 (GiElement 16401 name "WAITING_DIVIDER" 16402 type "integer" 16403 value "5000000" 16404 e "-- 10Hz @ 50 MHz" 16405 ) 16406 ] 16407 ) 16408 viewicon (ZoomableIcon 16409 uid 10684,0 16410 sl 0 16411 va (VaSet 16412 vasetType 1 16413 fg "49152,49152,49152" 16414 ) 16415 xt "129250,129250,130750,130750" 16416 iconName "VhdlFileViewIcon.png" 16417 iconMaskName "VhdlFileViewIcon.msk" 16418 ftype 10 16419 ) 16420 ordering 1 16421 viewiconposition 0 16422 portVis (PortSigDisplay 16423 ) 16424 archFileType "UNKNOWN" 16425 ) 16426 *563 (Net 15973 st "SIGNAL socks_waiting : std_logic" 15974 ) 15975 ) 15976 *552 (Net 16427 15977 uid 10721,0 16428 15978 decl (Decl … … 16438 15988 ) 16439 15989 xt "-103000,45400,-84500,46200" 16440 st "green : std_logic 16441 " 16442 ) 16443 ) 16444 *564 (PortIoOut 15990 st "green : std_logic" 15991 ) 15992 ) 15993 *553 (PortIoOut 16445 15994 uid 10729,0 16446 15995 shape (CompositeShape … … 16486 16035 ) 16487 16036 ) 16488 *5 65(Net16037 *554 (Net 16489 16038 uid 10735,0 16490 16039 decl (Decl … … 16500 16049 ) 16501 16050 xt "-103000,41400,-84500,42200" 16502 st "amber : std_logic 16503 " 16504 ) 16505 ) 16506 *566 (PortIoOut 16051 st "amber : std_logic" 16052 ) 16053 ) 16054 *555 (PortIoOut 16507 16055 uid 10743,0 16508 16056 shape (CompositeShape … … 16548 16096 ) 16549 16097 ) 16550 *5 67(Net16098 *556 (Net 16551 16099 uid 10749,0 16552 16100 decl (Decl … … 16562 16110 ) 16563 16111 xt "-103000,49400,-84500,50200" 16564 st "red : std_logic 16565 " 16566 ) 16567 ) 16568 *568 (PortIoOut 16112 st "red : std_logic" 16113 ) 16114 ) 16115 *557 (PortIoOut 16569 16116 uid 10757,0 16570 16117 shape (CompositeShape … … 16609 16156 ) 16610 16157 ) 16158 ) 16159 *558 (SaComponent 16160 uid 11209,0 16161 optionalChildren [ 16162 *559 (CptPort 16163 uid 11181,0 16164 ps "OnEdgeStrategy" 16165 shape (Triangle 16166 uid 11182,0 16167 ro 90 16168 va (VaSet 16169 vasetType 1 16170 fg "0,65535,0" 16171 ) 16172 xt "128250,125625,129000,126375" 16173 ) 16174 tg (CPTG 16175 uid 11183,0 16176 ps "CptPortTextPlaceStrategy" 16177 stg "VerticalLayoutStrategy" 16178 f (Text 16179 uid 11184,0 16180 va (VaSet 16181 ) 16182 xt "130000,125500,131900,126500" 16183 st "CLK" 16184 blo "130000,126300" 16185 ) 16186 ) 16187 thePort (LogicalPort 16188 decl (Decl 16189 n "CLK" 16190 t "std_logic" 16191 o 1 16192 ) 16193 ) 16194 ) 16195 *560 (CptPort 16196 uid 11185,0 16197 ps "OnEdgeStrategy" 16198 shape (Triangle 16199 uid 11186,0 16200 ro 90 16201 va (VaSet 16202 vasetType 1 16203 fg "0,65535,0" 16204 ) 16205 xt "147000,125625,147750,126375" 16206 ) 16207 tg (CPTG 16208 uid 11187,0 16209 ps "CptPortTextPlaceStrategy" 16210 stg "RightVerticalLayoutStrategy" 16211 f (Text 16212 uid 11188,0 16213 va (VaSet 16214 ) 16215 xt "143600,125500,146000,126500" 16216 st "green" 16217 ju 2 16218 blo "146000,126300" 16219 ) 16220 ) 16221 thePort (LogicalPort 16222 m 1 16223 decl (Decl 16224 n "green" 16225 t "std_logic" 16226 o 2 16227 ) 16228 ) 16229 ) 16230 *561 (CptPort 16231 uid 11189,0 16232 ps "OnEdgeStrategy" 16233 shape (Triangle 16234 uid 11190,0 16235 ro 90 16236 va (VaSet 16237 vasetType 1 16238 fg "0,65535,0" 16239 ) 16240 xt "147000,126625,147750,127375" 16241 ) 16242 tg (CPTG 16243 uid 11191,0 16244 ps "CptPortTextPlaceStrategy" 16245 stg "RightVerticalLayoutStrategy" 16246 f (Text 16247 uid 11192,0 16248 va (VaSet 16249 ) 16250 xt "143500,126500,146000,127500" 16251 st "amber" 16252 ju 2 16253 blo "146000,127300" 16254 ) 16255 ) 16256 thePort (LogicalPort 16257 m 1 16258 decl (Decl 16259 n "amber" 16260 t "std_logic" 16261 o 3 16262 ) 16263 ) 16264 ) 16265 *562 (CptPort 16266 uid 11193,0 16267 ps "OnEdgeStrategy" 16268 shape (Triangle 16269 uid 11194,0 16270 ro 90 16271 va (VaSet 16272 vasetType 1 16273 fg "0,65535,0" 16274 ) 16275 xt "147000,127625,147750,128375" 16276 ) 16277 tg (CPTG 16278 uid 11195,0 16279 ps "CptPortTextPlaceStrategy" 16280 stg "RightVerticalLayoutStrategy" 16281 f (Text 16282 uid 11196,0 16283 va (VaSet 16284 ) 16285 xt "144500,127500,146000,128500" 16286 st "red" 16287 ju 2 16288 blo "146000,128300" 16289 ) 16290 ) 16291 thePort (LogicalPort 16292 m 1 16293 decl (Decl 16294 n "red" 16295 t "std_logic" 16296 o 4 16297 ) 16298 ) 16299 ) 16300 *563 (CptPort 16301 uid 11197,0 16302 ps "OnEdgeStrategy" 16303 shape (Triangle 16304 uid 11198,0 16305 ro 90 16306 va (VaSet 16307 vasetType 1 16308 fg "0,65535,0" 16309 ) 16310 xt "128250,126625,129000,127375" 16311 ) 16312 tg (CPTG 16313 uid 11199,0 16314 ps "CptPortTextPlaceStrategy" 16315 stg "VerticalLayoutStrategy" 16316 f (Text 16317 uid 11200,0 16318 va (VaSet 16319 ) 16320 xt "130000,126500,132800,127500" 16321 st "trigger" 16322 blo "130000,127300" 16323 ) 16324 ) 16325 thePort (LogicalPort 16326 decl (Decl 16327 n "trigger" 16328 t "std_logic" 16329 o 5 16330 ) 16331 ) 16332 ) 16333 *564 (CptPort 16334 uid 11201,0 16335 ps "OnEdgeStrategy" 16336 shape (Triangle 16337 uid 11202,0 16338 ro 90 16339 va (VaSet 16340 vasetType 1 16341 fg "0,65535,0" 16342 ) 16343 xt "128250,127625,129000,128375" 16344 ) 16345 tg (CPTG 16346 uid 11203,0 16347 ps "CptPortTextPlaceStrategy" 16348 stg "VerticalLayoutStrategy" 16349 f (Text 16350 uid 11204,0 16351 va (VaSet 16352 ) 16353 xt "130000,127500,135500,128500" 16354 st "socks_waiting" 16355 blo "130000,128300" 16356 ) 16357 ) 16358 thePort (LogicalPort 16359 decl (Decl 16360 n "socks_waiting" 16361 t "std_logic" 16362 o 6 16363 ) 16364 ) 16365 ) 16366 *565 (CptPort 16367 uid 11205,0 16368 ps "OnEdgeStrategy" 16369 shape (Triangle 16370 uid 11206,0 16371 ro 90 16372 va (VaSet 16373 vasetType 1 16374 fg "0,65535,0" 16375 ) 16376 xt "128250,128625,129000,129375" 16377 ) 16378 tg (CPTG 16379 uid 11207,0 16380 ps "CptPortTextPlaceStrategy" 16381 stg "VerticalLayoutStrategy" 16382 f (Text 16383 uid 11208,0 16384 va (VaSet 16385 ) 16386 xt "130000,128500,136500,129500" 16387 st "socks_connected" 16388 blo "130000,129300" 16389 ) 16390 ) 16391 thePort (LogicalPort 16392 decl (Decl 16393 n "socks_connected" 16394 t "std_logic" 16395 o 7 16396 ) 16397 ) 16398 ) 16399 ] 16400 shape (Rectangle 16401 uid 11210,0 16402 va (VaSet 16403 vasetType 1 16404 fg "0,65535,0" 16405 lineColor "0,32896,0" 16406 lineWidth 2 16407 ) 16408 xt "129000,125000,147000,131000" 16409 ) 16410 oxt "0,0,8000,10000" 16411 ttg (MlTextGroup 16412 uid 11211,0 16413 ps "CenterOffsetStrategy" 16414 stg "VerticalLayoutStrategy" 16415 textVec [ 16416 *566 (Text 16417 uid 11212,0 16418 va (VaSet 16419 font "Arial,8,1" 16420 ) 16421 xt "130900,131000,137100,132000" 16422 st "FACT_FAD_lib" 16423 blo "130900,131800" 16424 tm "BdLibraryNameMgr" 16425 ) 16426 *567 (Text 16427 uid 11213,0 16428 va (VaSet 16429 font "Arial,8,1" 16430 ) 16431 xt "130900,132000,136800,133000" 16432 st "led_controller" 16433 blo "130900,132800" 16434 tm "CptNameMgr" 16435 ) 16436 *568 (Text 16437 uid 11214,0 16438 va (VaSet 16439 font "Arial,8,1" 16440 ) 16441 xt "130900,133000,133100,134000" 16442 st "U_10" 16443 blo "130900,133800" 16444 tm "InstanceNameMgr" 16445 ) 16446 ] 16447 ) 16448 ga (GenericAssociation 16449 uid 11215,0 16450 ps "EdgeToEdgeStrategy" 16451 matrix (Matrix 16452 uid 11216,0 16453 text (MLText 16454 uid 11217,0 16455 va (VaSet 16456 font "Courier New,8,0" 16457 ) 16458 xt "129000,122600,164000,125000" 16459 st "HEARTBEAT_PWM_DIVIDER = 500 ( integer ) -- 10kHz @ 50 MHz 16460 MAX_DELAY = 100 ( integer ) 16461 WAITING_DIVIDER = 50000000 ( integer ) -- 1Hz @ 50 MHz 16462 " 16463 ) 16464 header "" 16465 ) 16466 elements [ 16467 (GiElement 16468 name "HEARTBEAT_PWM_DIVIDER" 16469 type "integer" 16470 value "500" 16471 e "-- 10kHz @ 50 MHz" 16472 ) 16473 (GiElement 16474 name "MAX_DELAY" 16475 type "integer" 16476 value "100" 16477 ) 16478 (GiElement 16479 name "WAITING_DIVIDER" 16480 type "integer" 16481 value "50000000" 16482 e "-- 1Hz @ 50 MHz" 16483 ) 16484 ] 16485 ) 16486 viewicon (ZoomableIcon 16487 uid 11218,0 16488 sl 0 16489 va (VaSet 16490 vasetType 1 16491 fg "49152,49152,49152" 16492 ) 16493 xt "129250,129250,130750,130750" 16494 iconName "VhdlFileViewIcon.png" 16495 iconMaskName "VhdlFileViewIcon.msk" 16496 ftype 10 16497 ) 16498 ordering 1 16499 viewiconposition 0 16500 portVis (PortSigDisplay 16501 ) 16502 archFileType "UNKNOWN" 16611 16503 ) 16612 16504 *569 (Wire … … 22141 22033 ] 22142 22034 ) 22143 end &5 5822035 end &564 22144 22036 sat 16 22145 22037 eat 32 … … 22176 22068 ] 22177 22069 ) 22178 end &5 5922070 end &565 22179 22071 sat 16 22180 22072 eat 32 … … 22212 22104 ] 22213 22105 ) 22214 end &55 322106 end &559 22215 22107 sat 16 22216 22108 eat 32 … … 22247 22139 ] 22248 22140 ) 22249 end &5 5722141 end &563 22250 22142 sat 16 22251 22143 eat 32 … … 22282 22174 ] 22283 22175 ) 22284 start &5 5422285 end &5 6422176 start &560 22177 end &553 22286 22178 sat 32 22287 22179 eat 32 … … 22305 22197 ) 22306 22198 ) 22307 on &5 6322199 on &552 22308 22200 ) 22309 22201 *728 (Wire … … 22320 22212 ] 22321 22213 ) 22322 start &5 5522323 end &5 6622214 start &561 22215 end &555 22324 22216 sat 32 22325 22217 eat 32 … … 22343 22235 ) 22344 22236 ) 22345 on &5 6522237 on &554 22346 22238 ) 22347 22239 *729 (Wire … … 22358 22250 ] 22359 22251 ) 22360 start &5 5622361 end &5 6822252 start &562 22253 end &557 22362 22254 sat 32 22363 22255 eat 32 … … 22381 22273 ) 22382 22274 ) 22383 on &5 6722275 on &556 22384 22276 ) 22385 22277 ] … … 22503 22395 ) 22504 22396 windowSize "1280,0,2561,1024" 22505 viewArea "107 560,77269,192440,147269"22506 cachedDiagramExtent "-105000,-60500,16 3300,343294"22397 viewArea "107600,77300,192480,147300" 22398 cachedDiagramExtent "-105000,-60500,164000,343294" 22507 22399 pageSetupInfo (PageSetupInfo 22508 22400 ptrCmd "eDocPrintPro,winspool," … … 22529 22421 hasePageBreakOrigin 1 22530 22422 pageBreakOrigin "-73000,0" 22531 lastUid 1 0772,022423 lastUid 11218,0 22532 22424 defaultCommentText (CommentText 22533 22425 shape (Rectangle -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb
r10074 r10075 1483 1483 (vvPair 1484 1484 variable "time" 1485 value "1 5:59:32"1485 value "18:05:35" 1486 1486 ) 1487 1487 (vvPair … … 4457 4457 ) 4458 4458 ) 4459 lastUid 4966,04459 lastUid 5081,0 4460 4460 okToSyncOnLoad 1 4461 4461 OkToSyncGenericsOnLoad 1
Note:
See TracChangeset
for help on using the changeset viewer.
