Changeset 10075 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Timestamp:
- 01/04/11 17:21:15 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10074 r10075 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 5:02:5604.01.20115 -- at - 18:14:37 04.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 79 79 -- Created: 80 80 -- by - dneise.UNKNOWN (E5B-LABOR6) 81 -- at - 1 5:02:5604.01.201181 -- at - 18:14:37 04.01.2011 82 82 -- 83 83 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 319 319 drs_channel_id => drs_channel_id, 320 320 drs_dwrite => DWRITE, 321 green => GREEN_LED,321 green => RED_LED, 322 322 led => D_T, 323 323 mosi => MOSI, 324 324 offset => OPEN, 325 325 ready => ready, 326 red => RED_LED,326 red => GREEN_LED, 327 327 sclk => S_CLK, 328 328 sensor_cs => sensor_cs, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10074 r10075 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 5:02:55 04.01.20115 -- at - 18:14:35 04.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 80 80 -- Created: 81 81 -- by - dneise.UNKNOWN (E5B-LABOR6) 82 -- at - 1 5:02:5504.01.201182 -- at - 18:14:36 04.01.2011 83 83 -- 84 84 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 323 323 COMPONENT led_controller 324 324 GENERIC ( 325 HEARTBEAT_DIVIDER : integer := 5000; -- 100kHz @ 50 MHz 326 WAITING_DIVIDER : integer := 50000000 -- 10Hz @ 50 MHz 325 HEARTBEAT_PWM_DIVIDER : integer := 500; -- 1kHz @ 50 MHz 326 MAX_DELAY : integer := 100; 327 WAITING_DIVIDER : integer := 500000000 -- 1Hz @ 50 MHz 327 328 ); 328 329 PORT ( … … 618 619 U_10 : led_controller 619 620 GENERIC MAP ( 620 HEARTBEAT_DIVIDER => 25000000, -- 2Hz @ 50 MHz 621 WAITING_DIVIDER => 5000000 -- 10Hz @ 50 MHz 621 HEARTBEAT_PWM_DIVIDER => 50000, -- 10kHz @ 50 MHz 622 MAX_DELAY => 100, 623 WAITING_DIVIDER => 50000000 -- 1Hz @ 50 MHz 622 624 ) 623 625 PORT MAP ( -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/led_controller_bahavior.vhd
r10074 r10075 21 21 ENTITY led_controller IS 22 22 GENERIC( 23 HEARTBEAT_DIVIDER : integer := 5000; -- 100kHz @ 50 MHz 24 WAITING_DIVIDER : integer := 50000000 -- 10Hz @ 50 MHz 23 HEARTBEAT_PWM_DIVIDER : integer := 500; -- 1kHz @ 50 MHz 24 MAX_DELAY : integer := 100; 25 WAITING_DIVIDER : integer := 500000000 -- 1Hz @ 50 MHz 25 26 ); 26 27 PORT( … … 116 117 -- can be switched off with heartbeat_en high 117 118 heartbeat : process (CLK) 118 variable Z: integer range 0 to HEARTBEAT_DIVIDER - 1 := 0; 119 variable X: integer range 1 to HEARTBEAT_DIVIDER - 2 := 1; 120 variable A: integer range 0 to 1000 := 0; 119 variable Z: integer range 0 to HEARTBEAT_PWM_DIVIDER - 1 := 0; 120 variable ON_TIME: integer range 0 to HEARTBEAT_PWM_DIVIDER - 1 := 0; 121 variable DELAY: integer range 0 to MAX_DELAY - 1 := 0; 122 variable DIR : std_logic := '1'; 121 123 122 124 begin 123 125 if rising_edge(CLK) then 124 if (Z < HEARTBEAT_ DIVIDER - 1) then126 if (Z < HEARTBEAT_PWM_DIVIDER - 1) then 125 127 Z := Z + 1; 126 128 else 127 129 Z := 0; 128 end if; 129 if (Z = 0) then 130 red_loc <= '1'; 131 if (A < 999) then 132 A := A + 1; 130 if (DELAY < MAX_DELAY - 1) then 131 DELAY := DELAY + 1; 133 132 else 134 A:= 0;133 DELAY := 0; 135 134 end if; 136 135 end if; 137 if (A = 0) then 138 if (X < HEARTBEAT_DIVIDER - 2) then 139 X := X + 1; 140 else 141 X := 1; 142 end if; 143 end if; 144 if (Z = X) then 136 137 138 if (Z = 0) then 139 if (DIR = '0') then -- count up 140 if (ON_TIME < HEARTBEAT_PWM_DIVIDER - 11) then 141 ON_TIME := ON_TIME + 10; 142 else 143 DIR := '1'; 144 end if; 145 else -- DIR is '1' -- count down 146 if (ON_TIME > 10) then 147 ON_TIME := ON_TIME - 10; 148 else 149 DIR := '0'; 150 end if; 151 end if; 152 end if; 153 154 if (Z = 0) then 155 red_loc <= '1'; 156 end if; 157 if (Z = ON_TIME) then 145 158 red_loc <= '0'; 146 159 end if; … … 154 167 begin 155 168 if rising_edge(CLK) then 156 if (Y < HEARTBEAT_DIVIDER - 1) then169 if (Y < WAITING_DIVIDER - 1) then 157 170 Y := Y + 1; 158 171 else
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