Changeset 10074 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Timestamp:
- 01/04/11 15:02:07 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 1 added
- 8 edited
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clock_generator_var_ps_struct.vhd (modified) (2 diffs)
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fad_board.ucf (modified) (1 diff)
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fad_board.ucf.bak (modified) (3 diffs)
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fad_board_struct.vhd (modified) (9 diffs)
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fad_main_struct.vhd (modified) (9 diffs)
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led_controller_bahavior.vhd (added)
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phase_shifter.vhd.bak (modified) (1 diff)
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w5300_modul.vhd (modified) (5 diffs)
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w5300_modul.vhd.bak (modified) (21 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd
r10073 r10074 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 4:00:25 01.10.20105 -- at - 12:35:56 04.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 41 41 -- Created: 42 42 -- by - dneise.UNKNOWN (E5B-LABOR6) 43 -- at - 1 4:00:25 01.10.201043 -- at - 12:35:56 04.01.2011 44 44 -- 45 45 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf
r10073 r10074 253 253 # LEDs 254 254 ####################################################### 255 NET LED<0> LOC = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2;256 NET LED<1> LOC = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 2;257 NET LED<2> LOC = AD20 | IOSTANDARD=LVCMOS33 | DRIVE = 2;258 259 255 NET AMBER_LED LOC = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2; #schematic: LED_3 D3 AMBER 256 NET GREEN_LED LOC = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 2; #schematic: LED_0 D1 GREEN 257 NET RED_LED LOC = AD20 | IOSTANDARD=LVCMOS33 | DRIVE = 2;#schematic: LED_2 D2 RED 258 259 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf.bak
r9912 r10074 25 25 NET RS485_C_DE LOC = C5 | IOSTANDARD=LVCMOS33; #ok 26 26 NET RS485_C_RE LOC = C6 | IOSTANDARD=LVCMOS33; #ok 27 #NET RS485_C_DO LOC = C7 | IOSTANDARD=LVCMOS33; #ok28 #NET RS485_C_DI LOC = C8 | IOSTANDARD=LVCMOS33; #ok27 NET RS485_C_DO LOC = C7 | IOSTANDARD=LVCMOS33; #ok 28 NET RS485_C_DI LOC = C8 | IOSTANDARD=LVCMOS33; #ok 29 29 30 30 NET RS485_E_DE LOC = D20 | IOSTANDARD=LVCMOS33; #ok 31 31 NET RS485_E_RE LOC = D21 | IOSTANDARD=LVCMOS33; #ok 32 #NET RS485_E_DO LOC = D22 | IOSTANDARD=LVCMOS33; #ok33 #NET RS485_E_DI LOC = D23 | IOSTANDARD=LVCMOS33; #ok32 NET RS485_E_DO LOC = D22 | IOSTANDARD=LVCMOS33; #ok 33 NET RS485_E_DI LOC = D23 | IOSTANDARD=LVCMOS33; #ok 34 34 35 35 … … 230 230 NET A1_T<3> LOC = AC14 | IOSTANDARD=LVCMOS33; #ok 231 231 NET A1_T<4> LOC = AC15 | IOSTANDARD=LVCMOS33; #ok 232 #NET A1_T<5> LOC = AB16 | IOSTANDARD=LVCMOS33; #ok233 #NET A1_T<6> LOC = AC16 | IOSTANDARD=LVCMOS33; #ok234 #NET A1_T<7> LOC = AB18 | IOSTANDARD=LVCMOS33; #ok232 NET A1_T<5> LOC = AB16 | IOSTANDARD=LVCMOS33; #ok 233 NET A1_T<6> LOC = AC16 | IOSTANDARD=LVCMOS33; #ok 234 NET A1_T<7> LOC = AB18 | IOSTANDARD=LVCMOS33; #ok 235 235 236 236 … … 253 253 # LEDs 254 254 ####################################################### 255 NET LED<0> LOC = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2;256 NET LED<1> LOC = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 2;257 NET LED<2> LOC = AD20 | IOSTANDARD=LVCMOS33 | DRIVE = 2;258 259 255 NET AMBER_LED LOC = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2; #schematic: LED_3 D3 AMBER 256 NET GREEN_LED LOC = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 1; #schematic: LED_0 D1 GREEN 257 NET RED_LED LOC = AD20 | IOSTANDARD=LVCMOS33 | DRIVE = 2;#schematic: LED_2 D2 RED 258 259 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10073 r10074 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 7:00:27 03.01.20115 -- at - 15:02:56 04.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 29 29 W_INT : IN std_logic; 30 30 X_50M : IN STD_LOGIC; 31 A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 32 A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 31 A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 32 A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 33 AMBER_LED : OUT std_logic; 33 34 A_CLK : OUT std_logic_vector (3 DOWNTO 0); 34 35 D0_SRCLK : OUT STD_LOGIC; … … 37 38 D3_SRCLK : OUT STD_LOGIC; 38 39 DAC_CS : OUT std_logic; 39 DENABLE : OUT std_logic 40 DWRITE : OUT std_logic 41 D_A : OUT std_logic_vector (3 DOWNTO 0) 42 D_T : OUT std_logic_vector (7 DOWNTO 0) 43 D_T2 : OUT std_logic_vector (3 DOWNTO 0) 40 DENABLE : OUT std_logic := '0'; 41 DWRITE : OUT std_logic := '0'; 42 D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 43 D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 44 D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 44 45 EE_CS : OUT std_logic; 45 LED : OUT std_logic_vector ( 2 DOWNTO 0 ) := (others => '1');46 MOSI : OUT std_logic 46 GREEN_LED : OUT std_logic; 47 MOSI : OUT std_logic := '0'; 47 48 OE_ADC : OUT STD_LOGIC; 49 RED_LED : OUT std_logic; 48 50 RS485_C_DE : OUT std_logic; 49 51 RS485_C_DO : OUT std_logic; … … 51 53 RS485_E_DE : OUT std_logic; 52 54 RS485_E_RE : OUT std_logic; 53 RSRLOAD : OUT std_logic 54 SRIN : OUT std_logic 55 RSRLOAD : OUT std_logic := '0'; 56 SRIN : OUT std_logic := '0'; 55 57 S_CLK : OUT std_logic; 56 58 T0_CS : OUT std_logic; … … 60 62 TRG_V : OUT std_logic; 61 63 W_A : OUT std_logic_vector (9 DOWNTO 0); 62 W_CS : OUT std_logic 63 W_RD : OUT std_logic 64 W_RES : OUT std_logic 65 W_WR : OUT std_logic 64 W_CS : OUT std_logic := '1'; 65 W_RD : OUT std_logic := '1'; 66 W_RES : OUT std_logic := '1'; 67 W_WR : OUT std_logic := '1'; 66 68 MISO : INOUT std_logic; 67 69 W_D : INOUT std_logic_vector (15 DOWNTO 0) … … 77 79 -- Created: 78 80 -- by - dneise.UNKNOWN (E5B-LABOR6) 79 -- at - 1 7:00:27 03.01.201181 -- at - 15:02:56 04.01.2011 80 82 -- 81 83 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 159 161 adc_clk_en : OUT std_logic := '0'; 160 162 adc_oeb : OUT std_logic := '1'; 163 amber : OUT std_logic ; 161 164 dac_cs : OUT std_logic ; 162 165 denable : OUT std_logic := '0'; -- default domino wave off 163 166 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 164 167 drs_dwrite : OUT std_logic := '1'; 168 green : OUT std_logic ; 165 169 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 166 170 mosi : OUT std_logic := '0'; 167 171 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 168 172 ready : OUT std_logic := '0'; 173 red : OUT std_logic ; 169 174 sclk : OUT std_logic ; 170 175 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); … … 238 243 239 244 EE_CS <= '1'; 240 -- LEDs are low active241 LED(0) <= '1';242 LED(1) <= '0'; -- on243 LED(2) <= '1';244 245 246 247 245 248 246 -- HDL Embedded Text Block 7 eb1 … … 316 314 adc_clk_en => adc_clk_en, 317 315 adc_oeb => OE_ADC, 316 amber => AMBER_LED, 318 317 dac_cs => dummy, 319 318 denable => DENABLE, 320 319 drs_channel_id => drs_channel_id, 321 320 drs_dwrite => DWRITE, 321 green => GREEN_LED, 322 322 led => D_T, 323 323 mosi => MOSI, 324 324 offset => OPEN, 325 325 ready => ready, 326 red => RED_LED, 326 327 sclk => S_CLK, 327 328 sensor_cs => sensor_cs, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10073 r10074 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 7:00:23 03.01.20115 -- at - 15:02:55 04.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 47 47 adc_clk_en : OUT std_logic := '0'; 48 48 adc_oeb : OUT std_logic := '1'; 49 amber : OUT std_logic; 49 50 dac_cs : OUT std_logic; 50 51 denable : OUT std_logic := '0'; -- default domino wave off 51 52 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 52 53 drs_dwrite : OUT std_logic := '1'; 54 green : OUT std_logic; 53 55 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 54 56 mosi : OUT std_logic := '0'; 55 57 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 56 58 ready : OUT std_logic := '0'; 59 red : OUT std_logic; 57 60 sclk : OUT std_logic; 58 61 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); … … 77 80 -- Created: 78 81 -- by - dneise.UNKNOWN (E5B-LABOR6) 79 -- at - 1 7:00:24 03.01.201182 -- at - 15:02:55 04.01.2011 80 83 -- 81 84 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 157 160 SIGNAL sensor_array : sensor_array_type; 158 161 SIGNAL sensor_ready : std_logic; 162 SIGNAL socks_connected : std_logic; 163 SIGNAL socks_waiting : std_logic; 159 164 SIGNAL srclk_enable : std_logic := '0'; 160 165 SIGNAL srin_write_ack : std_logic := '0'; … … 316 321 ); 317 322 END COMPONENT; 323 COMPONENT led_controller 324 GENERIC ( 325 HEARTBEAT_DIVIDER : integer := 5000; -- 100kHz @ 50 MHz 326 WAITING_DIVIDER : integer := 50000000 -- 10Hz @ 50 MHz 327 ); 328 PORT ( 329 CLK : IN std_logic; 330 socks_connected : IN std_logic; 331 socks_waiting : IN std_logic; 332 trigger : IN std_logic; 333 amber : OUT std_logic; 334 green : OUT std_logic; 335 red : OUT std_logic 336 ); 337 END COMPONENT; 318 338 COMPONENT memory_manager 319 339 GENERIC ( … … 411 431 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once 412 432 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift 413 srclk_enable : OUT std_logic := '1' -- default SRCLK on. 433 srclk_enable : OUT std_logic := '1'; -- default SRCLK on. 434 socks_waiting : OUT std_logic ; 435 socks_connected : OUT std_logic 414 436 ); 415 437 END COMPONENT; … … 423 445 FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator; 424 446 FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser; 447 FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller; 425 448 FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager; 426 449 FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface; … … 593 616 SRCLK => SRCLK1 594 617 ); 618 U_10 : led_controller 619 GENERIC MAP ( 620 HEARTBEAT_DIVIDER => 25000000, -- 2Hz @ 50 MHz 621 WAITING_DIVIDER => 5000000 -- 10Hz @ 50 MHz 622 ) 623 PORT MAP ( 624 CLK => CLK_50_internal, 625 green => green, 626 amber => amber, 627 red => red, 628 trigger => trigger_out, 629 socks_waiting => socks_waiting, 630 socks_connected => socks_connected 631 ); 595 632 I_main_memory_manager : memory_manager 596 633 GENERIC MAP ( … … 680 717 ps_do_phase_shift => ps_do_phase_shift, 681 718 ps_reset => ps_reset, 682 srclk_enable => srclk_enable 719 srclk_enable => srclk_enable, 720 socks_waiting => socks_waiting, 721 socks_connected => socks_connected 683 722 ); 684 723 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd.bak
r9912 r10074 138 138 PSEN <= '0'; 139 139 if (PSDONE = '1') then 140 next_state <= READY_STATE;140 next_state <= READY_STATE; 141 141 else 142 next_state <= READY_STATE;142 next_state <= WAITINGFORDONE; 143 143 end if; 144 144 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10072 r10074 49 49 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 50 50 data_valid : IN std_logic; 51 51 data_valid_ack : OUT std_logic := '0'; 52 52 busy : OUT std_logic := '1'; 53 53 write_header_flag, write_end_flag : IN std_logic; … … 74 74 ps_reset : out std_logic := '0'; -- pulse this to reset the variable phase shift 75 75 76 srclk_enable : out std_logic := '1' -- default SRCLK on. 76 srclk_enable : out std_logic := '1'; -- default SRCLK on. 77 78 socks_waiting : out std_logic; 79 socks_connected: out std_logic 77 80 ); 78 81 … … 238 241 busy <= '1'; 239 242 zaehler <= zaehler + 1; 243 socks_waiting <= '0'; 244 socks_connected <= '0'; 240 245 wiz_reset <= '0'; 241 246 -- led <= X"FF"; … … 432 437 433 438 when ESTABLISH => 439 socks_waiting <= '1'; 440 socks_connected <= '0'; 434 441 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; 435 442 state_init <= READ_REG; … … 463 470 -- main "loop" 464 471 when MAIN => 472 socks_waiting <= '0'; 473 socks_connected <= '1'; 474 465 475 ps_do_phase_shift <= '0'; 466 476 ps_reset <= '0'; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd.bak
r9912 r10074 49 49 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 50 50 data_valid : IN std_logic; 51 data_valid_ack : OUT std_logic := '0';51 data_valid_ack : OUT std_logic := '0'; 52 52 busy : OUT std_logic := '1'; 53 53 write_header_flag, write_end_flag : IN std_logic; … … 60 60 config_wr_en : out std_logic := '0'; 61 61 config_rd_en : out std_logic := '0'; 62 -- -- 63 config_rw_ack, config_rw_ready : in std_logic; 64 -- -- 62 65 config_busy : in std_logic; 63 66 … … 69 72 ps_direction : out std_logic := '1'; -- default phase shift upwards 70 73 ps_do_phase_shift : out std_logic := '0'; --pulse this to phase shift once 71 ps_reset : out std_logic := '0' -- pulse this to reset the variable phase shift 74 ps_reset : out std_logic := '0'; -- pulse this to reset the variable phase shift 75 76 srclk_enable : out std_logic := '1' -- default SRCLK on. 72 77 ); 73 78 … … 80 85 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, 81 86 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 82 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA);83 type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_0 6, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,87 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA); 88 type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, 84 89 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3); 85 90 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); … … 118 123 signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0'); 119 124 signal chk_recv_cntr : integer range 0 to 10000 := 0; 125 126 -- -- 127 signal wait_cntr : integer range 0 to 10000 := 0; 128 -- -- 129 120 130 signal rx_packets_cnt : std_logic_vector (15 downto 0); 121 131 signal next_packet_data : std_logic := '0'; … … 131 141 signal local_fifo_channels : std_logic_vector (3 downto 0); 132 142 143 signal data_valid_int : std_logic := '0'; 144 145 -- only for debugging 146 --signal error_cnt : std_logic_vector (7 downto 0) := (others => '0'); 147 --signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0'); 148 149 133 150 begin 134 151 … … 136 153 RST_TIME <= X"00120"; 137 154 --synthesis translate_on 155 138 156 139 157 w5300_init_proc : process (clk, int) … … 218 236 -- reset W5300 219 237 when RESET => 238 busy <= '1'; 220 239 zaehler <= zaehler + 1; 221 240 wiz_reset <= '0'; 222 led <= X"FF";241 -- led <= X"FF"; 223 242 if (zaehler >= X"00064") then -- wait 2µs 224 243 wiz_reset <= '1'; … … 354 373 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8); 355 374 state_init <= WRITE_REG; 356 next_state <= TIMEOUT;357 when TIMEOUT =>358 par_addr <= W5300_RTR;359 par_data <= X"07D0"; -- 0x07D0 = 200ms360 state_init <= WRITE_REG;361 next_state <= RETRY;362 when RETRY =>363 par_addr <= W5300_RCR;364 par_data <= X"0008";365 state_init <= WRITE_REG;366 375 next_state <= SI; 376 -- when TIMEOUT => 377 -- par_addr <= W5300_RTR; 378 -- par_data <= X"07D0"; -- 0x07D0 = 200ms 379 -- state_init <= WRITE_REG; 380 -- next_state <= RETRY; 381 -- when RETRY => 382 -- par_addr <= W5300_RCR; 383 -- par_data <= X"0008"; 384 -- state_init <= WRITE_REG; 385 -- next_state <= SI; 386 -- 367 387 368 388 -- Socket Init … … 416 436 next_state <= EST1; 417 437 when EST1 => 418 led <= data_read (7 downto 0); 438 -- led <= data_read (7 downto 0); 439 -- led <= X"00"; 419 440 case data_read (7 downto 0) is 420 441 when X"17" => -- established … … 432 453 433 454 when CONFIG => 434 455 -- led <= X"F0"; 435 456 new_config <= '1'; 436 457 if (config_started = '1') then 437 led <= X"0F";458 -- led <= X"0F"; 438 459 new_config <= '0'; 439 busy <= '0';440 460 state_init <= MAIN; 441 461 end if; … … 446 466 ps_reset <= '0'; 447 467 if (trigger_stop = '1') then 448 s_trigger <= '0'; 449 end if; 468 s_trigger <= '0'; 469 end if; 470 data_valid_ack <= '0'; 471 state_init <= MAIN1; 472 data_valid_int <= data_valid; 473 when MAIN1 => 450 474 if (chk_recv_cntr = 1000) then 451 475 chk_recv_cntr <= 0; … … 454 478 busy <= '1'; 455 479 else 456 busy <= '0';457 data_valid_ack <= '0';458 480 chk_recv_cntr <= chk_recv_cntr + 1; 459 if (data_valid = '1') then 460 data_valid_ack <= '1'; 461 local_write_length <= write_length; 462 local_ram_start_addr <= ram_start_addr; 463 local_ram_addr <= (others => '0'); 464 local_write_header_flag <= write_header_flag; 465 local_write_end_flag <= write_end_flag; 466 local_fifo_channels <= fifo_channels; 467 next_state <= MAIN; 468 state_init <= WRITE_DATA; 469 busy <= '1'; 470 end if; 471 end if; 481 state_init <= MAIN2; 482 end if; 483 when MAIN2 => 484 busy <= '0'; 485 if (data_valid = '1') then 486 data_valid_int <= '0'; 487 busy <= '1'; 488 local_write_length <= write_length; 489 local_ram_start_addr <= ram_start_addr; 490 local_ram_addr <= (others => '0'); 491 local_write_header_flag <= write_header_flag; 492 local_write_end_flag <= write_end_flag; 493 local_fifo_channels <= fifo_channels; 494 -- data_valid_ack <= '1'; 495 -- next_state <= MAIN; 496 -- state_init <= WRITE_DATA; 497 state_init <= MAIN3; 498 else 499 state_init <= MAIN1; 500 end if; 501 when MAIN3 => 502 -- led <= local_ram_start_addr (7 downto 0); 503 data_valid_ack <= '1'; 504 next_state <= MAIN; 505 state_init <= WRITE_DATA; 506 472 507 473 508 -- read data from socket 0 … … 505 540 else 506 541 state_read_data <= RD_END; 507 -- if (new_config_flag = '1') then508 -- new_config_flag <= '0';509 -- state_init <= CONFIG;510 -- else511 -- busy <= '0';512 -- state_init <= MAIN;513 -- end if;514 542 end if; 515 543 when RD_6 => 516 led <= data_read (15 downto 8);544 -- led <= data_read (15 downto 8); 517 545 -- read command 518 546 if (next_packet_data = '0') then … … 521 549 trigger_stop <= '1'; 522 550 s_trigger <= '1'; 523 state_read_data <= RD_ WAIT;551 state_read_data <= RD_5; 524 552 when CMD_DWRITE_RUN => 525 553 dwrite_enable <= '1'; 526 state_read_data <= RD_ WAIT;554 state_read_data <= RD_5; 527 555 when CMD_DWRITE_STOP => 528 556 dwrite_enable <= '0'; 529 state_read_data <= RD_ WAIT;557 state_read_data <= RD_5; 530 558 when CMD_SCLK_ON => 531 559 sclk_enable <= '1'; 532 state_read_data <= RD_ WAIT;560 state_read_data <= RD_5; 533 561 when CMD_SCLK_OFF => 534 562 sclk_enable <= '0'; 535 state_read_data <= RD_ WAIT;563 state_read_data <= RD_5; 536 564 when CMD_DENABLE => 537 565 denable <= '1'; 538 state_read_data <= RD_ WAIT;566 state_read_data <= RD_5; 539 567 when CMD_DDISABLE => 540 568 denable <= '0'; 541 state_read_data <= RD_ WAIT;569 state_read_data <= RD_5; 542 570 when CMD_TRIGGER_C => 543 571 trigger_stop <= '0'; 544 572 s_trigger <= '1'; 545 state_read_data <= RD_ WAIT;573 state_read_data <= RD_5; 546 574 when CMD_TRIGGER_S => 547 575 trigger_stop <= '1'; 548 state_read_data <= RD_ WAIT;576 state_read_data <= RD_5; 549 577 -- phase shift commands here: 550 578 when CMD_PS_DO => 551 579 ps_do_phase_shift <= '1'; 552 state_read_data <= RD_ WAIT;580 state_read_data <= RD_5; 553 581 when CMD_PS_DIRINC => 554 582 ps_direction <= '1'; 555 state_read_data <= RD_ WAIT;583 state_read_data <= RD_5; 556 584 when CMD_PS_RESET => 557 585 ps_reset <= '1'; 558 state_read_data <= RD_WAIT; 586 state_read_data <= RD_5; 587 when CMD_SRCLK_ON => 588 srclk_enable <= '1'; 589 state_read_data <= RD_5; 590 when CMD_SRCLK_OFF => 591 srclk_enable <= '0'; 592 state_read_data <= RD_5; 559 593 when CMD_PS_DIRDEC => 560 594 ps_direction <= '0'; 561 state_read_data <= RD_ WAIT;595 state_read_data <= RD_5; 562 596 when CMD_WRITE => 563 597 next_packet_data <= '1'; … … 578 612 end if; 579 613 when RD_WAIT => 580 state_read_data <= RD_WAIT1; 614 if (config_rw_ack = '1') then 615 state_read_data <= RD_WAIT1; 616 end if; 581 617 when RD_WAIT1 => 582 config_data <= (others => 'Z'); 583 config_wr_en <= '0'; 584 state_read_data <= RD_5; 618 if (config_rw_ready = '1') then 619 config_data <= (others => 'Z'); 620 config_wr_en <= '0'; 621 state_read_data <= RD_5; 622 end if; 585 623 when RD_END => 586 624 par_addr <= W5300_S0_CR; … … 591 629 next_state <= CONFIG; 592 630 else 593 -- busy <= '0';594 631 next_state <= MAIN; 595 632 end if; … … 611 648 if (local_write_header_flag = '1') then 612 649 local_socket_nr <= ram_data (2 downto 0); 650 -- local_socket_nr <= "000"; 613 651 end if; 614 652 next_state_tmp <= next_state; … … 632 670 state_write <= WR_04; 633 671 when WR_04 => 634 if (socket_tx_free (16 downto 0) < write_length_bytes) then 672 673 -- led <= socket_tx_free (15 downto 8); 674 675 -- if (socket_tx_free (16 downto 0) < write_length_bytes) then 676 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then 635 677 state_write <= WR_01; 636 678 else … … 743 785 state_init <= WRITE_REG; 744 786 next_state <= WRITE_DATA; 745 state_write <= WR_05 ;787 state_write <= WR_05a; 746 788 747 789 -- End Write End Package Flag 790 791 -- Wait???? 792 when WR_05a => 793 if (wait_cntr < 10) then -- 3000 works??? 794 wait_cntr <= wait_cntr + 1; 795 else 796 wait_cntr <= 0; 797 state_write <= WR_05b; 798 end if; 799 when WR_05b => 800 state_write <= WR_05; 748 801 749 802 --Send FIFO … … 765 818 state_write <= WR_08; 766 819 when others => 767 -- busy <= '0';768 820 state_init <= next_state_tmp; 769 821 state_write <= WR_START;
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