Changeset 10073 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Timestamp:
- 01/04/11 10:03:04 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 8 edited
-
clock_generator_var_ps_struct.vhd (modified) (2 diffs)
-
control_unit_struct.vhd (modified) (5 diffs)
-
data_generator.vhd (modified) (1 diff)
-
data_generator.vhd.bak (modified) (10 diffs)
-
fad_board.ucf (modified) (1 diff)
-
fad_board_struct.vhd (modified) (7 diffs)
-
fad_main_struct.vhd (modified) (24 diffs)
-
spi_interface_struct.vhd (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd
r9912 r10073 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 0:49:24 30.08.20105 -- at - 14:00:25 01.10.2010 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 41 41 -- Created: 42 42 -- by - dneise.UNKNOWN (E5B-LABOR6) 43 -- at - 1 0:49:25 30.08.201043 -- at - 14:00:25 01.10.2010 44 44 -- 45 45 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd
r9912 r10073 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 09:42:04 30.07.20105 -- at - 17:00:23 03.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 23 23 config_data_valid : OUT std_logic; 24 24 config_ready : OUT std_logic; 25 -- -- 26 config_rw_ack : OUT std_logic := '0'; 27 -- -- 28 config_rw_ready : OUT std_logic := '0'; 25 29 config_started : OUT std_logic := '0'; 26 30 dac_array : OUT dac_array_type; 27 drs_address : OUT std_logic_vector (3 DOWNTO 0);28 drs_address_mode : OUT std_logic;29 31 roi_array : OUT roi_array_type; 30 32 config_data : INOUT std_logic_vector (15 DOWNTO 0) … … 40 42 -- Created: 41 43 -- by - dneise.UNKNOWN (E5B-LABOR6) 42 -- at - 09:42:04 30.07.201044 -- at - 17:00:23 03.01.2011 43 45 -- 44 46 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 91 93 config_data_valid : OUT std_logic := '0'; 92 94 config_busy : OUT std_logic := '0'; 95 -- -- 96 config_rw_ack : OUT std_logic := '0'; 97 -- -- 98 config_rw_ready : OUT std_logic := '0'; 99 -- -- 93 100 ram_addr : OUT std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0); 94 101 ram_data_in : OUT std_logic_vector (15 DOWNTO 0); 95 102 ram_write_en : OUT std_logic_vector (0 DOWNTO 0); 96 103 dac_array : OUT dac_array_type ; 97 roi_array : OUT roi_array_type ; 98 drs_address : OUT std_logic_vector (3 DOWNTO 0); 99 drs_address_mode : OUT std_logic 104 roi_array : OUT roi_array_type 100 105 ); 101 106 END COMPONENT; … … 137 142 config_data_valid => config_data_valid, 138 143 config_busy => config_busy, 144 config_rw_ack => config_rw_ack, 145 config_rw_ready => config_rw_ready, 139 146 ram_addr => ram_addr, 140 147 ram_data_in => ram_data_in, 141 148 ram_write_en => ram_wren, 142 149 dac_array => dac_array, 143 roi_array => roi_array, 144 drs_address => drs_address, 145 drs_address_mode => drs_address_mode 150 roi_array => roi_array 146 151 ); 147 152 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10072 r10073 142 142 when CONFIG4 => 143 143 drs_channel_id <= DRS_WRITE_SHIFT_REG; 144 drs_srin_data <= "1 0101010";144 drs_srin_data <= "11111111"; 145 145 drs_srin_write_8b <= '1'; 146 146 if (drs_srin_write_ack = '1') then -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak
r10072 r10073 25 25 ); 26 26 port( 27 -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 28 27 29 clk : in std_logic; 28 30 data_out : out std_logic_vector (63 downto 0); … … 32 34 ram_write_ea : in std_logic; 33 35 ram_write_ready : out std_logic := '0'; 36 -- -- 37 ram_write_ready_ack : IN std_logic; 38 -- -- 34 39 config_start_mm, config_start_cm, config_start_spi : out std_logic := '0'; 35 40 config_ready_mm, config_ready_cm, config_ready_spi : in std_logic; … … 45 50 trigger_id : in std_logic_vector (47 downto 0); 46 51 trigger : in std_logic; 47 s_trigger : in std_logic;52 -- s_trigger : in std_logic; 48 53 new_config : in std_logic; 49 54 config_started : out std_logic := '0'; … … 55 60 drs_dwrite : out std_logic := '1'; 56 61 drs_clk_en, drs_read_s_cell : out std_logic := '0'; 62 63 drs_srin_write_8b : out std_logic := '0'; 64 drs_srin_write_ack : in std_logic; 65 drs_srin_data : out std_logic_vector (7 downto 0) := (others => '0'); 66 drs_srin_write_ready : in std_logic; 67 57 68 drs_read_s_cell_ready : in std_logic; 58 69 drs_s_cell_array : in drs_s_cell_array_type … … 62 73 architecture Behavioral of data_generator is 63 74 64 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,75 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES, 65 76 WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT, 66 77 WRITE_END_FLAG, WRITE_DATA_STOP, … … 76 87 signal adc_wait_cnt : integer range 0 to 7 := 0; 77 88 78 signal trigger_flag : std_logic := '0'; 79 89 signal trigger_flag :std_logic := '0'; 90 signal ram_write_ea_flag : std_logic := '0'; 91 signal new_config_int : std_logic := '0'; 92 93 signal roi_max_int : roi_max_type; 80 94 81 95 begin … … 95 109 when CONFIG => 96 110 config_started <= '1'; 97 -- config config manager 98 config_start_cm <= '1'; 99 if (config_started_cm = '1') then 100 state_generate <= CONFIG1; 111 if (new_config = '0') then 112 config_started <= '0'; 113 -- config config manager 114 config_start_cm <= '1'; 115 if (config_started_cm = '1') then 116 config_start_cm <= '0'; 117 state_generate <= CONFIG1; 118 end if; 101 119 end if; 102 120 when CONFIG1 => 103 121 if (config_ready_cm = '1') then 104 config_started <= '0';105 config_start_cm <= '0';106 122 config_start_mm <= '1'; 107 123 end if; 108 124 if (config_started_mm = '1') then 125 config_start_mm <= '0'; 109 126 state_generate <= CONFIG2; 110 127 end if; 111 128 when CONFIG2 => 112 129 if (config_ready_mm = '1') then 113 config_start_mm <= '0';114 130 config_start_spi <= '1'; 115 131 end if; 116 132 if (config_started_spi = '1') then 133 config_start_spi <= '0'; 117 134 state_generate <= CONFIG3; 118 135 end if; 119 136 when CONFIG3 => 120 137 if (config_ready_spi = '1') then 121 config_start_spi <= '0'; 138 state_generate <= CONFIG4; 139 -- state_generate <= WRITE_DATA_IDLE; 140 end if; 141 -- configure DRS 142 when CONFIG4 => 143 drs_channel_id <= DRS_WRITE_SHIFT_REG; 144 drs_srin_data <= "10101010"; 145 drs_srin_write_8b <= '1'; 146 if (drs_srin_write_ack = '1') then 147 drs_srin_write_8b <= '0'; 148 state_generate <= CONFIG5; 149 end if; 150 when CONFIG5 => 151 if (drs_srin_write_ready = '1') then 152 roi_max_int <= roi_max; 122 153 state_generate <= WRITE_DATA_IDLE; 123 154 end if; 155 -- end configure DRS 124 156 125 157 when WRITE_DATA_IDLE => … … 127 159 state_generate <= CONFIG; 128 160 end if; 129 if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then 161 -- if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then 162 if (ram_write_ea = '1' and trigger_flag = '1') then 130 163 -- stop drs, dwrite low 131 164 drs_dwrite <= '0'; … … 248 281 when WRITE_EXTERNAL_TRIGGER => -- external trigger ID 249 282 addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH); 250 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); 283 -- data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); 284 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); 251 285 state_generate <= WRITE_INTERNAL_TRIGGER; 252 286 when WRITE_INTERNAL_TRIGGER => -- internal trigger ID … … 263 297 state_generate <= WRITE_DATA_END_WAIT; 264 298 when WRITE_DATA_END_WAIT => 265 state_generate <= WRITE_DATA_STOP; 299 -- -- 300 if (ram_write_ready_ack = '1') then 301 state_generate <= WRITE_DATA_STOP; 302 -- -- 303 ram_write_ready <= '0'; 304 -- -- 305 end if; 306 -- -- 266 307 when WRITE_DATA_STOP => 267 drs_dwrite <= '1'; 268 data_cntr <= 0; 269 addr_cntr <= 0; 270 channel_id <= 0; 271 ram_write_ready <= '0'; 272 state_generate <= WRITE_DATA_IDLE; 273 308 -- -- 309 if (ram_write_ready_ack = '0') then 310 -- -- 311 drs_dwrite <= '1'; 312 data_cntr <= 0; 313 addr_cntr <= 0; 314 channel_id <= 0; 315 state_generate <= WRITE_DATA_IDLE; 316 -- -- 317 end if; 318 -- -- 274 319 when others => 275 320 null; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf
r9912 r10073 25 25 NET RS485_C_DE LOC = C5 | IOSTANDARD=LVCMOS33; #ok 26 26 NET RS485_C_RE LOC = C6 | IOSTANDARD=LVCMOS33; #ok 27 #NET RS485_C_DO LOC = C7 | IOSTANDARD=LVCMOS33; #ok28 #NET RS485_C_DI LOC = C8 | IOSTANDARD=LVCMOS33; #ok27 NET RS485_C_DO LOC = C7 | IOSTANDARD=LVCMOS33; #ok 28 NET RS485_C_DI LOC = C8 | IOSTANDARD=LVCMOS33; #ok 29 29 30 30 NET RS485_E_DE LOC = D20 | IOSTANDARD=LVCMOS33; #ok 31 31 NET RS485_E_RE LOC = D21 | IOSTANDARD=LVCMOS33; #ok 32 #NET RS485_E_DO LOC = D22 | IOSTANDARD=LVCMOS33; #ok33 #NET RS485_E_DI LOC = D23 | IOSTANDARD=LVCMOS33; #ok32 NET RS485_E_DO LOC = D22 | IOSTANDARD=LVCMOS33; #ok 33 NET RS485_E_DI LOC = D23 | IOSTANDARD=LVCMOS33; #ok 34 34 35 35 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r9912 r10073 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 0:49:29 30.08.20105 -- at - 17:00:27 03.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 23 23 D3_SROUT : IN std_logic; 24 24 D_PLLLCK : IN std_logic_vector (3 DOWNTO 0); 25 RS485_C_DI : IN std_logic; 26 RS485_E_DI : IN std_logic; 27 RS485_E_DO : IN std_logic; 25 28 TRG : IN STD_LOGIC; 26 29 W_INT : IN std_logic; … … 44 47 OE_ADC : OUT STD_LOGIC; 45 48 RS485_C_DE : OUT std_logic; 49 RS485_C_DO : OUT std_logic; 46 50 RS485_C_RE : OUT std_logic; 47 51 RS485_E_DE : OUT std_logic; 48 52 RS485_E_RE : OUT std_logic; 49 53 RSRLOAD : OUT std_logic := '0'; 50 SRIN : OUT std_logic ;54 SRIN : OUT std_logic := '0'; 51 55 S_CLK : OUT std_logic; 52 56 T0_CS : OUT std_logic; … … 73 77 -- Created: 74 78 -- by - dneise.UNKNOWN (E5B-LABOR6) 75 -- at - 1 0:49:29 30.08.201079 -- at - 17:00:27 03.01.2011 76 80 -- 77 81 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 152 156 RSRLOAD : OUT std_logic := '0'; 153 157 SRCLK : OUT std_logic := '0'; 158 SRIN_out : OUT std_logic := '0'; 154 159 adc_clk_en : OUT std_logic := '0'; 155 160 adc_oeb : OUT std_logic := '1'; … … 220 225 -- MISC 6 221 226 TRG_V <= '0'; 222 RS485_C_RE <= ' 1';227 RS485_C_RE <= '0'; 223 228 RS485_C_DE <= '0'; 224 RS485_E_RE <= '1'; 229 RS485_C_DO <= RS485_C_DI; 230 231 RS485_E_RE <= '0'; 225 232 RS485_E_DE <= '0'; 233 --RS485_E_DO <= RS485_E_DI; 226 234 227 235 -- DENABLE <= '0'; -- domino wave stopped 228 236 -- DENABLE <= '1'; -- domino wave running 229 237 230 SRIN <= '1';238 231 239 EE_CS <= '1'; 232 240 -- LEDs are low active … … 305 313 RSRLOAD => RSRLOAD, 306 314 SRCLK => SRCLK, 315 SRIN_out => SRIN, 307 316 adc_clk_en => adc_clk_en, 308 317 adc_oeb => OE_ADC, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r9912 r10073 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 0:49:27 30.08.20105 -- at - 17:00:23 03.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 44 44 RSRLOAD : OUT std_logic := '0'; 45 45 SRCLK : OUT std_logic := '0'; 46 SRIN_out : OUT std_logic := '0'; 46 47 adc_clk_en : OUT std_logic := '0'; 47 48 adc_oeb : OUT std_logic := '1'; … … 76 77 -- Created: 77 78 -- by - dneise.UNKNOWN (E5B-LABOR6) 78 -- at - 1 0:49:28 30.08.201079 -- at - 17:00:24 03.01.2011 79 80 -- 80 81 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 113 114 SIGNAL config_ready_cm : std_logic; 114 115 SIGNAL config_ready_spi : std_logic; 116 -- -- 117 SIGNAL config_rw_ack : std_logic := '0'; 118 -- -- 119 SIGNAL config_rw_ready : std_logic := '0'; 115 120 SIGNAL config_start : std_logic := '0'; 116 121 SIGNAL config_start_cm : std_logic; … … 130 135 SIGNAL drs_read_s_cell_ready : std_logic; 131 136 SIGNAL drs_s_cell_array : drs_s_cell_array_type; 137 SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0'); 132 138 SIGNAL dwrite : std_logic := '1'; 133 139 SIGNAL dwrite_enable : std_logic := '1'; … … 142 148 SIGNAL ram_write_ea : std_logic; 143 149 SIGNAL ram_write_ready : std_logic := '0'; 150 -- -- 151 SIGNAL ram_write_ready_ack : std_logic := '0'; 144 152 SIGNAL roi_array : roi_array_type; 145 153 SIGNAL roi_max : roi_max_type; 146 SIGNAL s_trigger : std_logic := '0';154 SIGNAL s_trigger : std_logic; 147 155 SIGNAL sclk1 : std_logic; 148 156 SIGNAL sclk_enable : std_logic; … … 150 158 SIGNAL sensor_ready : std_logic; 151 159 SIGNAL srclk_enable : std_logic := '0'; 160 SIGNAL srin_write_ack : std_logic := '0'; 161 SIGNAL srin_write_ready : std_logic := '0'; 162 SIGNAL start_srin_write_8b : std_logic; 152 163 SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0); 164 SIGNAL trigger_out : std_logic; 153 165 SIGNAL wiz_ack : std_logic; 154 166 SIGNAL wiz_busy : std_logic; … … 207 219 config_data_valid : OUT std_logic ; 208 220 config_ready : OUT std_logic ; 221 -- -- 222 config_rw_ack : OUT std_logic := '0'; 223 -- -- 224 config_rw_ready : OUT std_logic := '0'; 209 225 config_started : OUT std_logic := '0'; 210 226 dac_array : OUT dac_array_type ; 211 drs_address : OUT std_logic_vector (3 DOWNTO 0);212 drs_address_mode : OUT std_logic ;213 227 roi_array : OUT roi_array_type ; 214 228 config_data : INOUT std_logic_vector (15 DOWNTO 0) … … 231 245 ); 232 246 PORT ( 247 -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 233 248 clk : IN std_logic ; 234 249 data_out : OUT std_logic_vector (63 DOWNTO 0); … … 238 253 ram_write_ea : IN std_logic ; 239 254 ram_write_ready : OUT std_logic := '0'; 255 -- -- 256 ram_write_ready_ack : IN std_logic ; 257 -- -- 240 258 config_start_mm : OUT std_logic := '0'; 259 -- -- 241 260 config_start_cm : OUT std_logic := '0'; 261 -- -- 242 262 config_start_spi : OUT std_logic := '0'; 243 263 config_ready_mm : IN std_logic ; … … 257 277 trigger_id : IN std_logic_vector (47 DOWNTO 0); 258 278 trigger : IN std_logic ; 259 s_trigger : IN std_logic;279 -- s_trigger : in std_logic; 260 280 new_config : IN std_logic ; 261 281 config_started : OUT std_logic := '0'; … … 268 288 drs_clk_en : OUT std_logic := '0'; 269 289 drs_read_s_cell : OUT std_logic := '0'; 290 drs_srin_write_8b : OUT std_logic := '0'; 291 drs_srin_write_ack : IN std_logic ; 292 drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 293 drs_srin_write_ready : IN std_logic ; 270 294 drs_read_s_cell_ready : IN std_logic ; 271 295 drs_s_cell_array : IN drs_s_cell_array_type … … 279 303 SROUT_in_2 : IN std_logic; 280 304 SROUT_in_3 : IN std_logic; 305 srin_data : IN std_logic_vector (7 DOWNTO 0); 281 306 start_endless_mode : IN std_logic; 282 307 start_read_stop_pos_mode : IN std_logic; 308 start_srin_write_8b : IN std_logic; 283 309 RSRLOAD : OUT std_logic := '0'; 284 310 SRCLK : OUT std_logic := '0'; 311 SRIN_out : OUT std_logic := '0'; 312 srin_write_ack : OUT std_logic := '0'; 313 srin_write_ready : OUT std_logic := '0'; 285 314 stop_pos : OUT drs_s_cell_array_type; 286 315 stop_pos_valid : OUT std_logic := '0' … … 296 325 config_start : IN std_logic ; 297 326 ram_write_ready : IN std_logic ; 327 -- -- 328 ram_write_ready_ack : OUT std_logic := '0'; 329 -- -- 298 330 roi_array : IN roi_array_type ; 299 331 ram_write_ea : OUT std_logic := '0'; … … 367 399 config_wr_en : OUT std_logic := '0'; 368 400 config_rd_en : OUT std_logic := '0'; 401 -- -- 402 config_rw_ack : IN std_logic ; 403 -- -- 404 config_rw_ready : IN std_logic ; 405 -- -- 369 406 config_busy : IN std_logic ; 370 407 denable : OUT std_logic := '0'; -- default domino wave off … … 429 466 END CASE; 430 467 END PROCESS u_0combo_proc; 468 469 -- ModuleWare code(v1.9) for instance 'U_9' of 'or' 470 trigger_out <= s_trigger OR trigger; 431 471 432 472 -- Instance port mappings. … … 468 508 config_data_valid => config_data_valid, 469 509 config_ready => config_ready_cm, 510 config_rw_ack => config_rw_ack, 511 config_rw_ready => config_rw_ready, 470 512 config_started => config_started_cu, 471 513 dac_array => dac_array, 472 drs_address => drs_address,473 drs_address_mode => drs_address_mode,474 514 roi_array => roi_array, 475 515 config_data => config_data … … 497 537 ram_write_ea => ram_write_ea, 498 538 ram_write_ready => ram_write_ready, 539 ram_write_ready_ack => ram_write_ready_ack, 499 540 config_start_mm => config_start, 500 541 config_start_cm => config_start_cm, … … 515 556 crate_id => crate_id, 516 557 trigger_id => trigger_id, 517 trigger => trigger, 518 s_trigger => s_trigger, 558 trigger => trigger_out, 519 559 new_config => new_config, 520 560 config_started => config_started, … … 527 567 drs_clk_en => drs_clk_en, 528 568 drs_read_s_cell => drs_read_s_cell, 569 drs_srin_write_8b => start_srin_write_8b, 570 drs_srin_write_ack => srin_write_ack, 571 drs_srin_data => drs_srin_data, 572 drs_srin_write_ready => srin_write_ready, 529 573 drs_read_s_cell_ready => drs_read_s_cell_ready, 530 574 drs_s_cell_array => drs_s_cell_array … … 541 585 stop_pos => drs_s_cell_array, 542 586 stop_pos_valid => drs_read_s_cell_ready, 587 start_srin_write_8b => start_srin_write_8b, 588 srin_write_ready => srin_write_ready, 589 srin_write_ack => srin_write_ack, 590 srin_data => drs_srin_data, 591 SRIN_out => SRIN_out, 543 592 RSRLOAD => RSRLOAD, 544 593 SRCLK => SRCLK1 … … 553 602 config_start => config_start, 554 603 ram_write_ready => ram_write_ready, 604 ram_write_ready_ack => ram_write_ready_ack, 555 605 roi_array => roi_array, 556 606 ram_write_ea => ram_write_ea, … … 587 637 PORT MAP ( 588 638 trigger_id => trigger_id, 589 trigger => trigger ,639 trigger => trigger_out, 590 640 clk => CLK_25_PS_internal 591 641 ); … … 621 671 config_wr_en => config_wr_en, 622 672 config_rd_en => config_rd_en, 673 config_rw_ack => config_rw_ack, 674 config_rw_ready => config_rw_ready, 623 675 config_busy => config_busy, 624 676 denable => denable, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd
r9912 r10073 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 09:42:04 30.07.20105 -- at - 14:00:24 01.10.2010 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 38 38 -- Created: 39 39 -- by - dneise.UNKNOWN (E5B-LABOR6) 40 -- at - 09:42:04 30.07.201040 -- at - 14:00:25 01.10.2010 41 41 -- 42 42 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
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