Changeset 10176
- Timestamp:
- 02/24/11 14:58:17 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 6 edited
-
data_generator.vhd (modified) (9 diffs)
-
fad_board_struct.vhd (modified) (2 diffs)
-
fad_definitions.vhd (modified) (2 diffs)
-
fad_main_struct.vhd (modified) (12 diffs)
-
memory_manager_beha.vhd (modified) (2 diffs)
-
w5300_modul.vhd (modified) (6 diffs)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10174 r10176 32 32 ram_write_ea : in std_logic; 33 33 ram_write_ready : out std_logic := '0'; 34 35 34 ram_write_ready_ack : IN std_logic; 36 37 35 config_start_mm : out std_logic := '0'; 38 36 config_start_cm : out std_logic := '0'; … … 49 47 sensor_ready : in std_logic; 50 48 dac_array : in dac_array_type; 51 49 50 mode : in std_logic := '0'; -- 0: config mode | 1: run mode 51 idling : out std_logic; 52 52 53 -- EVT HEADER - part 1 53 54 package_length : in std_logic_vector (15 downto 0); … … 109 110 110 111 type state_generate_type is ( 111 CONFIG_CHAIN_START, -- WRITE_DATA_IDLE branches into this state, if needed.112 CONFIG_CHAIN_START, -- IDLE branches into this state, if needed. 112 113 CONFIG_MEMORY_MANAGER, 113 114 CONFIG_SPI_INTERFACE, … … 118 119 WAIT_FOR_DRS_CONFIG_READY, 119 120 120 WRITE_DATA_IDLE,121 IDLE, 121 122 WRITE_HEADER, WRITE_FTM_INFO, WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER, WRITE_BOARD_ID, 122 123 WRITE_DNA, WRITE_TIMER, WRITE_TEMPERATURES, … … 138 139 signal start_config_chain_sr : std_logic_vector(1 downto 0); 139 140 140 signal state_generate : state_generate_type := CONFIG ;141 signal state_generate : state_generate_type := CONFIG_CHAIN_START; 141 142 signal start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); 142 143 … … 155 156 signal sig_drs_readout_started : std_logic := '0'; 156 157 158 signal sig_idling : std_logic := '1'; 159 157 160 begin 158 161 drs_readout_started <= sig_drs_readout_started; 159 162 idling <= sig_idling; 160 163 generate_data : process (clk) 161 164 begin … … 164 167 if (start_config_chain_sr = "01") then 165 168 start_config_chain_flag <= '1'; 166 config_chain_done = '0';169 config_chain_done <= '0'; 167 170 end if; 168 171 trigger_sr <= trigger_sr(0) & trigger; --synching in of asynchrounous trigger signal. … … 227 230 drs_channel_id <= DRS_ADDR_IDLE; -- to make sure not to write accidentally into DRS shift registers 228 231 roi_max_int <= roi_max; 229 config_chain_done = '1';230 state_generate <= WRITE_DATA_IDLE;232 config_chain_done <= '1'; 233 state_generate <= IDLE; 231 234 end if; 232 235 -- end configure DRS 233 236 237 when IDLE => 238 if (mode = '0') then -- do not accept any triggers ! stay in idle, or do a configuration. 239 sig_idling <= '1'; 240 if (start_config_chain_flag = '1') then 241 sig_idling <= '0'; 242 start_config_chain_flag <= '0'; 243 state_generate <= CONFIG_CHAIN_START; 244 else 245 state_generate <= IDLE; 246 end if; 247 else --mode = '1' -- check if trigger arrived. 248 sig_idling<= '0'; 249 if (ram_write_ea = '1' and trigger_sr = "01") then 250 sig_drs_readout_started <= '1'; -- is set to '0' in next state ... just a pulse. 251 start_read_drs_stop_cell <= '1'; 252 adc_output_enable_inverted <= '0'; 253 -- at this moment the ADC ist beeing clocked. 254 -- this is not the start of the readout. 255 -- the DRS needs to be clocked as well. 256 adc_clk_en <= '1'; 257 start_addr <= ram_start_addr; 258 state_generate <= WRITE_HEADER; 259 end if; 260 end if; 234 261 235 when WRITE_DATA_IDLE =>236 if (start_config_chain_flag = '1') then237 start_config_chain_flag = '0';238 state_generate <= CONFIG_CHAIN_START;239 end if;240 if (ram_write_ea = '1' and trigger_sr = "01") then241 sig_drs_readout_started <= '1'; -- is set to '0' in next state ... just a pulse.242 start_read_drs_stop_cell <= '1';243 adc_output_enable_inverted <= '0';244 -- at this moment the ADC ist beeing clocked.245 -- this is not the start of the readout.246 -- the DRS needs to be clocked as well.247 adc_clk_en <= '1';248 start_addr <= ram_start_addr;249 state_generate <= WRITE_HEADER;250 end if;251 262 when WRITE_HEADER => 252 sig_drs_readout_started <= '0'; -- is set to '1' in state WRITE_DATA_IDLE263 sig_drs_readout_started <= '0'; -- is set to '1' in state IDLE 253 264 dataRAM_write_ea_o <= "1"; 254 265 data_out <= X"000" & pll_lock & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01"; … … 434 445 channel_id <= 0; 435 446 state_generate <= WRITE_DATA_STOP1; 436 447 end if; 437 448 when WRITE_DATA_STOP1 => 438 449 if (drs_readout_ready_ack = '1') then 439 450 drs_readout_ready <= '0'; 440 state_generate <= WRITE_DATA_IDLE;451 state_generate <= IDLE; 441 452 end if; 442 453 when others => -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10172 r10176 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 4:09:41 23.02.20115 -- at - 15:55:14 24.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 76 76 -- Created: 77 77 -- by - dneise.UNKNOWN (E5B-LABOR6) 78 -- at - 1 4:09:41 23.02.201178 -- at - 15:55:15 24.02.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10173 r10176 130 130 constant DEFAULT_DRSADDR_MODE : std_logic := '0'; 131 131 132 132 -- config RAM addresses 133 constant BADDR_ROI : std_logic_vector := X"00"; -- Baseaddress ROI-Values 134 constant BADDR_DAC : std_logic_vector := X"24"; -- Baseaddress DAC-Values 133 135 134 136 -- Commands 135 constant BADDR_ROI : std_logic_vector := X"00"; -- Baseaddress ROI-Values136 137 constant CMD_WRITE : std_logic_vector := X"05"; 137 138 constant CMD_DENABLE : std_logic_vector := X"06"; … … 154 155 constant CMD_START : std_logic_vector := X"22"; -- set data generator in RUN-mnode 155 156 constant CMD_STOP : std_logic_vector := X"23"; -- set data generator in STOP-mode 156 constant BADDR_DAC : std_logic_vector := X"24"; -- Baseaddress DAC-Values157 157 constant CMC_MODE_COMMAND : std_logic_vector := X"30"; 158 158 constant CMD_TRIGGER : std_logic_vector := X"A0"; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10172 r10176 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 4:08:52 23.02.20115 -- at - 15:55:13 24.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 72 72 -- Created: 73 73 -- by - dneise.UNKNOWN (E5B-LABOR6) 74 -- at - 1 4:08:53 23.02.201174 -- at - 15:55:14 24.02.2011 75 75 -- 76 76 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 97 97 98 98 -- Internal signal declarations 99 SIGNAL CLK_25 : std_logic;100 SIGNAL DCM_PS_status : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');99 SIGNAL CLK_25 : std_logic; 100 SIGNAL DCM_PS_status : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 101 101 -- 102 102 … … 104 104 -- during EVT header wrinting, this field is left out ... and only written into event header, 105 105 -- when the DRS chip were read out already. 106 SIGNAL FTM_RS485_ready : std_logic;107 SIGNAL SRCLK1 : std_logic := '0';108 SIGNAL adc_data_array_int : adc_data_array_type;109 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0);110 SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);111 SIGNAL c_trigger_enable : std_logic := '0';112 SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0);113 SIGNAL config_addr : std_logic_vector(7 DOWNTO 0);114 SIGNAL config_busy : std_logic;115 SIGNAL config_data : std_logic_vector(15 DOWNTO 0);116 SIGNAL config_data_valid : std_logic;117 SIGNAL config_rd_en : std_logic;118 SIGNAL config_ready : std_logic;119 SIGNAL config_ready_cm : std_logic;120 SIGNAL config_ready_spi : std_logic;106 SIGNAL FTM_RS485_ready : std_logic; 107 SIGNAL SRCLK1 : std_logic := '0'; 108 SIGNAL adc_data_array_int : adc_data_array_type; 109 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); 110 SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); 111 SIGNAL c_trigger_enable : std_logic := '0'; 112 SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0); 113 SIGNAL config_addr : std_logic_vector(7 DOWNTO 0); 114 SIGNAL config_busy : std_logic; 115 SIGNAL config_data : std_logic_vector(15 DOWNTO 0); 116 SIGNAL config_data_valid : std_logic; 117 SIGNAL config_rd_en : std_logic; 118 SIGNAL config_ready : std_logic; 119 SIGNAL config_ready_cm : std_logic; 120 SIGNAL config_ready_spi : std_logic; 121 121 -- -- 122 SIGNAL config_rw_ack : std_logic := '0';122 SIGNAL config_rw_ack : std_logic := '0'; 123 123 -- -- 124 SIGNAL config_rw_ready : std_logic := '0'; 125 SIGNAL config_start : std_logic := '0'; 126 SIGNAL config_start_cm : std_logic; 127 SIGNAL config_start_spi : std_logic := '0'; 128 SIGNAL config_started : std_logic; 129 SIGNAL config_started_cu : std_logic := '0'; 130 SIGNAL config_started_mm : std_logic; 131 SIGNAL config_started_spi : std_logic := '0'; 132 SIGNAL config_wr_en : std_logic; 133 SIGNAL crc : std_logic_vector(7 DOWNTO 0); 134 SIGNAL dac_array : dac_array_type; 135 SIGNAL data_out : std_logic_vector(63 DOWNTO 0); 136 SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off 137 SIGNAL denable_prim : std_logic := '0'; -- default domino wave off 138 SIGNAL din1 : std_logic := '0'; -- default domino wave off 139 SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0'); 140 SIGNAL dout : std_logic; 141 SIGNAL dout1 : std_logic; 142 SIGNAL drs_clk_en : std_logic := '0'; 143 SIGNAL drs_read_s_cell : std_logic := '0'; 144 SIGNAL drs_read_s_cell_ready : std_logic; 124 SIGNAL config_rw_ready : std_logic := '0'; 125 SIGNAL config_start : std_logic := '0'; 126 SIGNAL config_start_cm : std_logic; 127 SIGNAL config_start_spi : std_logic := '0'; 128 SIGNAL config_started : std_logic; 129 SIGNAL config_started_cu : std_logic := '0'; 130 SIGNAL config_started_mm : std_logic; 131 SIGNAL config_started_spi : std_logic := '0'; 132 SIGNAL config_wr_en : std_logic; 133 SIGNAL crc : std_logic_vector(7 DOWNTO 0); 134 SIGNAL dac_array : dac_array_type; 135 SIGNAL data_generator_run_mode : std_logic := '0'; -- default triggers are NOT accepted 136 SIGNAL data_out : std_logic_vector(63 DOWNTO 0); 137 SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off 138 SIGNAL denable_prim : std_logic := '0'; -- default domino wave off 139 SIGNAL din1 : std_logic := '0'; -- default domino wave off 140 SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0'); 141 SIGNAL dout : std_logic; 142 SIGNAL dout1 : std_logic; 143 SIGNAL drs_clk_en : std_logic := '0'; 144 SIGNAL drs_read_s_cell : std_logic := '0'; 145 SIGNAL drs_read_s_cell_ready : std_logic; 145 146 -- -- 146 147 -- drs_dwrite : out std_logic := '1'; 147 SIGNAL drs_readout_ready : std_logic := '0';148 SIGNAL drs_readout_ready_ack : std_logic;149 SIGNAL drs_readout_started : std_logic;150 SIGNAL drs_s_cell_array : drs_s_cell_array_type;151 SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0');152 SIGNAL dwrite : std_logic := '1';153 SIGNAL dwrite_enable : std_logic := '1';154 SIGNAL enable_i : std_logic;155 SIGNAL new_config : std_logic := '0';156 SIGNAL package_length : std_logic_vector(15 DOWNTO 0);157 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards158 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once159 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift160 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0);161 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0);162 SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);163 SIGNAL ram_write_ea : std_logic;164 SIGNAL ram_write_ready : std_logic := '0';148 SIGNAL drs_readout_ready : std_logic := '0'; 149 SIGNAL drs_readout_ready_ack : std_logic; 150 SIGNAL drs_readout_started : std_logic; 151 SIGNAL drs_s_cell_array : drs_s_cell_array_type; 152 SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0'); 153 SIGNAL dwrite : std_logic := '1'; 154 SIGNAL dwrite_enable : std_logic := '1'; 155 SIGNAL enable_i : std_logic; 156 SIGNAL new_config : std_logic := '0'; 157 SIGNAL package_length : std_logic_vector(15 DOWNTO 0); 158 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards 159 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once 160 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift 161 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); 162 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); 163 SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); 164 SIGNAL ram_write_ea : std_logic; 165 SIGNAL ram_write_ready : std_logic := '0'; 165 166 -- -- 166 SIGNAL ram_write_ready_ack : std_logic := '0';167 SIGNAL ready : STD_LOGIC := '0';168 SIGNAL reset_synch_i : std_logic;169 SIGNAL roi_array : roi_array_type;170 SIGNAL roi_max : roi_max_type;171 SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte172 SIGNAL s_trigger : std_logic;173 SIGNAL s_trigger_0 : std_logic;174 SIGNAL sclk1 : std_logic;175 SIGNAL sclk_enable : std_logic;176 SIGNAL sensor_array : sensor_array_type;177 SIGNAL sensor_ready : std_logic;178 SIGNAL socks_connected : std_logic;179 SIGNAL socks_waiting : std_logic;180 SIGNAL srclk_enable : std_logic := '0';181 SIGNAL srin_write_ack : std_logic := '0';182 SIGNAL srin_write_ready : std_logic := '0';183 SIGNAL start_srin_write_8b : std_logic;184 SIGNAL time : std_logic_vector(31 DOWNTO 0);185 SIGNAL trigger1 : std_logic;186 SIGNAL trigger_enable : std_logic;187 SIGNAL trigger_id : std_logic_vector(31 DOWNTO 0);188 SIGNAL trigger_out : std_logic;189 SIGNAL trigger_type1 : std_logic_vector(7 DOWNTO 0);190 SIGNAL trigger_type2 : std_logic_vector(7 DOWNTO 0);191 SIGNAL wiz_ack : std_logic;192 SIGNAL wiz_busy : std_logic;193 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0');194 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0');195 SIGNAL wiz_write_ea : std_logic := '0';196 SIGNAL wiz_write_end : std_logic := '0';197 SIGNAL wiz_write_header : std_logic := '0';198 SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0');199 SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0";167 SIGNAL ram_write_ready_ack : std_logic := '0'; 168 SIGNAL ready : STD_LOGIC := '0'; 169 SIGNAL reset_synch_i : std_logic; 170 SIGNAL roi_array : roi_array_type; 171 SIGNAL roi_max : roi_max_type; 172 SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte 173 SIGNAL s_trigger : std_logic; 174 SIGNAL s_trigger_0 : std_logic; 175 SIGNAL sclk1 : std_logic; 176 SIGNAL sclk_enable : std_logic; 177 SIGNAL sensor_array : sensor_array_type; 178 SIGNAL sensor_ready : std_logic; 179 SIGNAL socks_connected : std_logic; 180 SIGNAL socks_waiting : std_logic; 181 SIGNAL srclk_enable : std_logic := '0'; 182 SIGNAL srin_write_ack : std_logic := '0'; 183 SIGNAL srin_write_ready : std_logic := '0'; 184 SIGNAL start_srin_write_8b : std_logic; 185 SIGNAL time : std_logic_vector(31 DOWNTO 0); 186 SIGNAL trigger1 : std_logic; 187 SIGNAL trigger_enable : std_logic; 188 SIGNAL trigger_id : std_logic_vector(31 DOWNTO 0); 189 SIGNAL trigger_out : std_logic; 190 SIGNAL trigger_type1 : std_logic_vector(7 DOWNTO 0); 191 SIGNAL trigger_type2 : std_logic_vector(7 DOWNTO 0); 192 SIGNAL wiz_ack : std_logic; 193 SIGNAL wiz_busy : std_logic; 194 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); 195 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); 196 SIGNAL wiz_write_ea : std_logic := '0'; 197 SIGNAL wiz_write_end : std_logic := '0'; 198 SIGNAL wiz_write_header : std_logic := '0'; 199 SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0'); 200 SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0"; 200 201 201 202 -- Implicit buffer signal declarations … … 296 297 ); 297 298 PORT ( 298 -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 299 clk : IN std_logic ; 300 data_out : OUT std_logic_vector (63 DOWNTO 0); 301 addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 302 write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0"; 303 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 304 ram_write_ea : IN std_logic ; 305 ram_write_ready : OUT std_logic := '0'; 306 -- -- 307 ram_write_ready_ack : IN std_logic ; 308 -- -- 309 config_start_mm : OUT std_logic := '0'; 310 -- -- 311 config_start_cm : OUT std_logic := '0'; 312 -- -- 313 config_start_spi : OUT std_logic := '0'; 314 config_ready_mm : IN std_logic ; 315 config_ready_cm : IN std_logic ; 316 config_ready_spi : IN std_logic ; 317 config_started_mm : IN std_logic ; 318 config_started_cm : IN std_logic ; 319 config_started_spi : IN std_logic ; 320 roi_array : IN roi_array_type ; 321 roi_max : IN roi_max_type ; 322 sensor_array : IN sensor_array_type ; 323 sensor_ready : IN std_logic ; 324 dac_array : IN dac_array_type ; 299 clk : IN std_logic ; -- CLK_25. 300 data_out : OUT std_logic_vector (63 DOWNTO 0); 301 addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 302 dataRAM_write_ea_o : OUT std_logic_vector (0 DOWNTO 0) := "0"; 303 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 304 ram_write_ea : IN std_logic ; 305 ram_write_ready : OUT std_logic := '0'; 306 ram_write_ready_ack : IN std_logic ; 307 config_start_mm : OUT std_logic := '0'; 308 config_start_cm : OUT std_logic := '0'; 309 config_start_spi : OUT std_logic := '0'; 310 config_ready_mm : IN std_logic ; 311 config_ready_cm : IN std_logic ; 312 config_ready_spi : IN std_logic ; 313 config_started_mm : IN std_logic ; 314 config_started_cm : IN std_logic ; 315 config_started_spi : IN std_logic ; 316 roi_array : IN roi_array_type ; 317 roi_max : IN roi_max_type ; 318 sensor_array : IN sensor_array_type ; 319 sensor_ready : IN std_logic ; 320 dac_array : IN dac_array_type ; 321 mode : IN std_logic := '0'; -- 0: config mode | 1: run mode 322 idling : OUT std_logic ; 325 323 -- EVT HEADER - part 1 326 package_length : IN std_logic_vector (15 DOWNTO 0); 327 pll_lock : IN std_logic_vector ( 3 DOWNTO 0); 328 -- 329 324 package_length : IN std_logic_vector (15 DOWNTO 0); 325 pll_lock : IN std_logic_vector ( 3 DOWNTO 0); 330 326 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... 331 327 -- during EVT header wrinting, this field is left out ... and only written into event header, 332 328 -- when the DRS chip were read out already. 333 FTM_RS485_ready : IN std_logic ; 334 FTM_trigger_info : IN std_logic_vector (55 DOWNTO 0); --7 byte 335 -- 336 329 FTM_RS485_ready : IN std_logic ; 330 FTM_trigger_info : IN std_logic_vector (55 DOWNTO 0); --7 byte 337 331 -- EVT HEADER - part 3 338 fad_event_counter : IN std_logic_vector (31 DOWNTO 0); 339 refclk_counter : IN std_logic_vector (11 DOWNTO 0); 340 refclk_too_high : IN std_logic ; 341 refclk_too_low : IN std_logic ; 342 -- 343 332 fad_event_counter : IN std_logic_vector (31 DOWNTO 0); 333 refclk_counter : IN std_logic_vector (11 DOWNTO 0); 334 refclk_too_high : IN std_logic ; 335 refclk_too_low : IN std_logic ; 344 336 -- EVT HEADER - part 4 345 board_id : IN std_logic_vector (3 DOWNTO 0); 346 crate_id : IN std_logic_vector (1 DOWNTO 0); 347 DCM_PS_status : IN std_logic_vector (7 DOWNTO 0); 348 TRG_GEN_div : IN std_logic_vector (15 DOWNTO 0); 349 -- 350 337 board_id : IN std_logic_vector (3 DOWNTO 0); 338 crate_id : IN std_logic_vector (1 DOWNTO 0); 339 DCM_PS_status : IN std_logic_vector (7 DOWNTO 0); 340 TRG_GEN_div : IN std_logic_vector (15 DOWNTO 0); 351 341 -- EVT HEADER - part 5 352 dna : IN std_logic_vector (63 DOWNTO 0); 353 -- 354 342 dna : IN std_logic_vector (63 DOWNTO 0); 355 343 -- EVT HEADER - part 6 356 timer_value : IN std_logic_vector (31 DOWNTO 0); -- time in units of 100us 357 -- 358 trigger : IN std_logic ; 359 -- s_trigger : in std_logic; 360 new_config : IN std_logic ; 361 config_started : OUT std_logic := '0'; 362 adc_data_array : IN adc_data_array_type ; 363 adc_oeb : OUT std_logic := '1'; 364 adc_clk_en : OUT std_logic := '0'; 365 adc_otr : IN std_logic_vector (3 DOWNTO 0); 366 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 367 -- -- 368 -- drs_dwrite : out std_logic := '1'; 369 drs_readout_ready : OUT std_logic := '0'; 370 drs_readout_ready_ack : IN std_logic ; 371 -- -- 372 drs_clk_en : OUT std_logic := '0'; 373 -- -- 374 drs_read_s_cell : OUT std_logic := '0'; 375 drs_srin_write_8b : OUT std_logic := '0'; 376 drs_srin_write_ack : IN std_logic ; 377 drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 378 drs_srin_write_ready : IN std_logic ; 379 drs_read_s_cell_ready : IN std_logic ; 380 drs_s_cell_array : IN drs_s_cell_array_type ; 381 drs_readout_started : OUT std_logic := '0' 344 timer_value : IN std_logic_vector (31 DOWNTO 0); -- time in units of 100us 345 trigger : IN std_logic ; 346 start_config_chain : IN std_logic ; -- here W5300_MODUL can start the whole config chain 347 config_chain_done : OUT std_logic ; 348 adc_data_array : IN adc_data_array_type ; 349 adc_output_enable_inverted : OUT std_logic := '1'; 350 adc_clk_en : OUT std_logic := '0'; 351 adc_otr : IN std_logic_vector (3 DOWNTO 0); 352 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 353 --drs_dwrite : out std_logic := '1'; 354 drs_readout_ready : OUT std_logic := '0'; 355 drs_readout_ready_ack : IN std_logic ; 356 drs_clk_en : OUT std_logic := '0'; 357 start_read_drs_stop_cell : OUT std_logic := '0'; 358 drs_srin_write_8b : OUT std_logic := '0'; 359 drs_srin_write_ack : IN std_logic ; 360 drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 361 drs_srin_write_ready : IN std_logic ; 362 drs_read_s_cell_ready : IN std_logic ; 363 drs_s_cell_array : IN drs_s_cell_array_type ; 364 drs_readout_started : OUT std_logic := '0' 382 365 ); 383 366 END COMPONENT; … … 452 435 wiz_busy : IN std_logic ; 453 436 wiz_ack : IN std_logic ; 437 buffer_ram_empty : OUT std_logic ; 454 438 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') 455 439 ); … … 507 491 ); 508 492 PORT ( 509 clk : IN std_logic ;510 wiz_reset : OUT std_logic := '1';511 addr : OUT std_logic_vector (9 DOWNTO 0);512 data : INOUT std_logic_vector (15 DOWNTO 0);513 cs : OUT std_logic := '1';514 wr : OUT std_logic := '1';515 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');516 rd : OUT std_logic := '1';517 int : IN std_logic ;518 write_length : IN std_logic_vector (16 DOWNTO 0);519 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);520 ram_data : IN std_logic_vector (15 DOWNTO 0);521 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);522 data_valid : IN std_logic ;523 data_valid_ack : OUT std_logic := '0';524 busy : OUT std_logic := '1';525 write_header_flag : IN std_logic ;526 write_end_flag : IN std_logic ;527 fifo_channels : IN std_logic_vector (3 DOWNTO 0);493 clk : IN std_logic ; 494 wiz_reset : OUT std_logic := '1'; 495 addr : OUT std_logic_vector (9 DOWNTO 0); 496 data : INOUT std_logic_vector (15 DOWNTO 0); 497 cs : OUT std_logic := '1'; 498 wr : OUT std_logic := '1'; 499 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 500 rd : OUT std_logic := '1'; 501 int : IN std_logic ; 502 write_length : IN std_logic_vector (16 DOWNTO 0); 503 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 504 ram_data : IN std_logic_vector (15 DOWNTO 0); 505 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 506 data_valid : IN std_logic ; 507 data_valid_ack : OUT std_logic := '0'; 508 busy : OUT std_logic := '1'; 509 write_header_flag : IN std_logic ; 510 write_end_flag : IN std_logic ; 511 fifo_channels : IN std_logic_vector (3 DOWNTO 0); 528 512 -- softtrigger: 529 s_trigger : OUT std_logic := '0';530 c_trigger_enable : OUT std_logic := '0';531 c_trigger_mult : OUT std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(100 ,16); --subject TO changes513 s_trigger : OUT std_logic := '0'; 514 c_trigger_enable : OUT std_logic := '0'; 515 c_trigger_mult : OUT std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(100 ,16); --subject TO changes 532 516 -- FAD configuration signals: 533 517 ------------------------------------------------------------------------------ 534 518 -- start entire configuration chain 535 new_config : OUT std_logic := '0';536 config_ started: IN std_logic ;519 new_config : OUT std_logic := '0'; 520 config_chain_done : IN std_logic ; 537 521 -- read/write configRAM 538 config_addr : OUT std_logic_vector (7 DOWNTO 0);539 config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z');540 config_wr_en : OUT std_logic := '0';541 config_rd_en : OUT std_logic := '0';542 config_rw_ack : IN std_logic ;543 config_rw_ready : IN std_logic ;544 config_busy : IN std_logic ;522 config_addr : OUT std_logic_vector (7 DOWNTO 0); 523 config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 524 config_wr_en : OUT std_logic := '0'; 525 config_rd_en : OUT std_logic := '0'; 526 config_rw_ack : IN std_logic ; 527 config_rw_ready : IN std_logic ; 528 config_busy : IN std_logic ; 545 529 ------------------------------------------------------------------------------ 546 530 547 531 -- MAC/IP calculation signals: 548 532 ------------------------------------------------------------------------------ 549 MAC_jumper : IN std_logic_vector (1 DOWNTO 0);550 BoardID : IN std_logic_vector (3 DOWNTO 0);551 CrateID : IN std_logic_vector (1 DOWNTO 0);533 MAC_jumper : IN std_logic_vector (1 DOWNTO 0); 534 BoardID : IN std_logic_vector (3 DOWNTO 0); 535 CrateID : IN std_logic_vector (1 DOWNTO 0); 552 536 ------------------------------------------------------------------------------ 553 537 554 538 -- user controllable enable signals 555 539 ------------------------------------------------------------------------------ 556 trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted 557 denable : OUT std_logic := '0'; -- default domino wave off 558 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. 559 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. 560 srclk_enable : OUT std_logic := '1'; -- default SRCLK on. 540 trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted 541 data_generator_run_mode : OUT std_logic := '0'; -- default triggers are NOT accepted 542 denable : OUT std_logic := '0'; -- default domino wave off 543 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. 544 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. 545 srclk_enable : OUT std_logic := '1'; -- default SRCLK on. 561 546 ------------------------------------------------------------------------------ 562 547 … … 564 549 -- these signals control the behavior of the digital clock manager (DCM) 565 550 ------------------------------------------------------------------------------ 566 ps_direction : OUT std_logic := '1'; -- default phase shift upwards567 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once568 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift551 ps_direction : OUT std_logic := '1'; -- default phase shift upwards 552 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once 553 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift 569 554 ------------------------------------------------------------------------------ 570 555 … … 572 557 -- one of the three LEDs is used for com-status info 573 558 ------------------------------------------------------------------------------ 574 socks_waiting : OUT std_logic ;575 socks_connected : OUT std_logic559 socks_waiting : OUT std_logic ; 560 socks_connected : OUT std_logic 576 561 ------------------------------------------------------------------------------ 577 562 ); … … 722 707 ) 723 708 PORT MAP ( 724 clk => CLK_25, 725 data_out => data_out, 726 addr_out => addr_out, 727 write_ea => write_ea, 728 ram_start_addr => ram_start_addr, 729 ram_write_ea => ram_write_ea, 730 ram_write_ready => ram_write_ready, 731 ram_write_ready_ack => ram_write_ready_ack, 732 config_start_mm => config_start, 733 config_start_cm => config_start_cm, 734 config_start_spi => config_start_spi, 735 config_ready_mm => config_ready, 736 config_ready_cm => config_ready_cm, 737 config_ready_spi => config_ready_spi, 738 config_started_mm => config_started_mm, 739 config_started_cm => config_started_cu, 740 config_started_spi => config_started_spi, 741 roi_array => roi_array, 742 roi_max => roi_max, 743 sensor_array => sensor_array, 744 sensor_ready => sensor_ready, 745 dac_array => dac_array, 746 package_length => package_length, 747 pll_lock => plllock_in, 748 FTM_RS485_ready => FTM_RS485_ready, 749 FTM_trigger_info => rs465_data, 750 fad_event_counter => trigger_id, 751 refclk_counter => counter_result_internal, 752 refclk_too_high => alarm_refclk_too_high_internal, 753 refclk_too_low => alarm_refclk_too_low_internal, 754 board_id => board_id, 755 crate_id => crate_id, 756 DCM_PS_status => DCM_PS_status, 757 TRG_GEN_div => c_trigger_mult, 758 dna => dna, 759 timer_value => time, 760 trigger => trigger_out, 761 new_config => new_config, 762 config_started => config_started, 763 adc_data_array => adc_data_array_int, 764 adc_oeb => adc_oeb, 765 adc_clk_en => adc_clk_en, 766 adc_otr => adc_otr, 767 drs_channel_id => drs_channel_id, 768 drs_readout_ready => drs_readout_ready, 769 drs_readout_ready_ack => drs_readout_ready_ack, 770 drs_clk_en => drs_clk_en, 771 drs_read_s_cell => drs_read_s_cell, 772 drs_srin_write_8b => start_srin_write_8b, 773 drs_srin_write_ack => srin_write_ack, 774 drs_srin_data => drs_srin_data, 775 drs_srin_write_ready => srin_write_ready, 776 drs_read_s_cell_ready => drs_read_s_cell_ready, 777 drs_s_cell_array => drs_s_cell_array, 778 drs_readout_started => drs_readout_started 709 clk => CLK_25, 710 data_out => data_out, 711 addr_out => addr_out, 712 dataRAM_write_ea_o => write_ea, 713 ram_start_addr => ram_start_addr, 714 ram_write_ea => ram_write_ea, 715 ram_write_ready => ram_write_ready, 716 ram_write_ready_ack => ram_write_ready_ack, 717 config_start_mm => config_start, 718 config_start_cm => config_start_cm, 719 config_start_spi => config_start_spi, 720 config_ready_mm => config_ready, 721 config_ready_cm => config_ready_cm, 722 config_ready_spi => config_ready_spi, 723 config_started_mm => config_started_mm, 724 config_started_cm => config_started_cu, 725 config_started_spi => config_started_spi, 726 roi_array => roi_array, 727 roi_max => roi_max, 728 sensor_array => sensor_array, 729 sensor_ready => sensor_ready, 730 dac_array => dac_array, 731 mode => OPEN, 732 idling => OPEN, 733 package_length => package_length, 734 pll_lock => plllock_in, 735 FTM_RS485_ready => FTM_RS485_ready, 736 FTM_trigger_info => rs465_data, 737 fad_event_counter => trigger_id, 738 refclk_counter => counter_result_internal, 739 refclk_too_high => alarm_refclk_too_high_internal, 740 refclk_too_low => alarm_refclk_too_low_internal, 741 board_id => board_id, 742 crate_id => crate_id, 743 DCM_PS_status => DCM_PS_status, 744 TRG_GEN_div => c_trigger_mult, 745 dna => dna, 746 timer_value => time, 747 trigger => trigger_out, 748 start_config_chain => new_config, 749 config_chain_done => config_started, 750 adc_data_array => adc_data_array_int, 751 adc_output_enable_inverted => adc_oeb, 752 adc_clk_en => adc_clk_en, 753 adc_otr => adc_otr, 754 drs_channel_id => drs_channel_id, 755 drs_readout_ready => drs_readout_ready, 756 drs_readout_ready_ack => drs_readout_ready_ack, 757 drs_clk_en => drs_clk_en, 758 start_read_drs_stop_cell => drs_read_s_cell, 759 drs_srin_write_8b => start_srin_write_8b, 760 drs_srin_write_ack => srin_write_ack, 761 drs_srin_data => drs_srin_data, 762 drs_srin_write_ready => srin_write_ready, 763 drs_read_s_cell_ready => drs_read_s_cell_ready, 764 drs_s_cell_array => drs_s_cell_array, 765 drs_readout_started => drs_readout_started 779 766 ); 780 767 U_0 : dna_gen … … 843 830 wiz_busy => wiz_busy, 844 831 wiz_ack => wiz_ack, 832 buffer_ram_empty => OPEN, 845 833 ram_start_addr => ram_start_addr 846 834 ); … … 888 876 drs_readout_ready_ack => drs_readout_ready_ack 889 877 ); 890 I_main_ethernet: w5300_modul878 w5300_modul_instance : w5300_modul 891 879 GENERIC MAP ( 892 880 RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2 893 881 ) 894 882 PORT MAP ( 895 clk => CLK_50_internal, 896 wiz_reset => wiz_reset, 897 addr => wiz_addr, 898 data => wiz_data, 899 cs => wiz_cs, 900 wr => wiz_wr, 901 led => led, 902 rd => wiz_rd, 903 int => wiz_int, 904 write_length => wiz_write_length, 905 ram_start_addr => wiz_ram_start_addr, 906 ram_data => ram_data, 907 ram_addr => ram_addr, 908 data_valid => wiz_write_ea, 909 data_valid_ack => wiz_ack, 910 busy => wiz_busy, 911 write_header_flag => wiz_write_header, 912 write_end_flag => wiz_write_end, 913 fifo_channels => wiz_number_of_channels, 914 s_trigger => s_trigger_0, 915 c_trigger_enable => c_trigger_enable, 916 c_trigger_mult => c_trigger_mult, 917 new_config => new_config, 918 config_started => config_started, 919 config_addr => config_addr, 920 config_data => config_data, 921 config_wr_en => config_wr_en, 922 config_rd_en => config_rd_en, 923 config_rw_ack => config_rw_ack, 924 config_rw_ready => config_rw_ready, 925 config_busy => config_busy, 926 MAC_jumper => D_T_in, 927 BoardID => board_id, 928 CrateID => crate_id, 929 trigger_enable => trigger_enable, 930 denable => denable_prim, 931 dwrite_enable => dwrite_enable, 932 sclk_enable => sclk_enable, 933 srclk_enable => srclk_enable, 934 ps_direction => ps_direction, 935 ps_do_phase_shift => ps_do_phase_shift, 936 ps_reset => ps_reset, 937 socks_waiting => socks_waiting, 938 socks_connected => socks_connected 883 clk => CLK_50_internal, 884 wiz_reset => wiz_reset, 885 addr => wiz_addr, 886 data => wiz_data, 887 cs => wiz_cs, 888 wr => wiz_wr, 889 led => led, 890 rd => wiz_rd, 891 int => wiz_int, 892 write_length => wiz_write_length, 893 ram_start_addr => wiz_ram_start_addr, 894 ram_data => ram_data, 895 ram_addr => ram_addr, 896 data_valid => wiz_write_ea, 897 data_valid_ack => wiz_ack, 898 busy => wiz_busy, 899 write_header_flag => wiz_write_header, 900 write_end_flag => wiz_write_end, 901 fifo_channels => wiz_number_of_channels, 902 s_trigger => s_trigger_0, 903 c_trigger_enable => c_trigger_enable, 904 c_trigger_mult => c_trigger_mult, 905 new_config => new_config, 906 config_chain_done => config_started, 907 config_addr => config_addr, 908 config_data => config_data, 909 config_wr_en => config_wr_en, 910 config_rd_en => config_rd_en, 911 config_rw_ack => config_rw_ack, 912 config_rw_ready => config_rw_ready, 913 config_busy => config_busy, 914 MAC_jumper => D_T_in, 915 BoardID => board_id, 916 CrateID => crate_id, 917 trigger_enable => trigger_enable, 918 data_generator_run_mode => data_generator_run_mode, 919 denable => denable_prim, 920 dwrite_enable => dwrite_enable, 921 sclk_enable => sclk_enable, 922 srclk_enable => srclk_enable, 923 ps_direction => ps_direction, 924 ps_do_phase_shift => ps_do_phase_shift, 925 ps_reset => ps_reset, 926 socks_waiting => socks_waiting, 927 socks_connected => socks_connected 939 928 ); 940 929 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd
r10174 r10176 28 28 29 29 ENTITY memory_manager IS 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 30 generic( 31 RAM_ADDR_WIDTH_64B : integer := 12; 32 RAM_ADDR_WIDTH_16B : integer := 14 33 ); 34 PORT( 35 clk : IN std_logic; 36 config_start : IN std_logic; 37 ram_write_ready : IN std_logic; 38 -- -- 39 ram_write_ready_ack : OUT std_logic := '0'; 40 -- -- 41 roi_array : IN roi_array_type; 42 ram_write_ea : OUT std_logic := '0'; 43 config_ready, config_started : OUT std_logic := '0'; 44 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); 45 package_length : OUT std_logic_vector (15 downto 0) := (others => '0'); 46 wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0'); 47 wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0'); 48 wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0'); 49 wiz_write_ea : OUT std_logic := '0'; 50 wiz_write_header : OUT std_logic := '0'; 51 wiz_write_end : OUT std_logic := '0'; 52 wiz_busy : IN std_logic; 53 53 wiz_ack : IN std_logic; 54 buffer_ram_empty : out std_logic;55 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') 56 54 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0'); 55 buffer_ram_empty : out std_logic 56 ); 57 57 58 58 -- Declarations … … 105 105 106 106 -- led <= conv_std_logic_vector (events_in_ram, 4) & "00" & wiz_ack & wiz_busy; 107 buffer_ram_empty <= ' 0' when events_in_ram=0 else '1';107 buffer_ram_empty <= '1' when events_in_ram = 0 else '0'; 108 108 109 109 mm : process (clk) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10174 r10176 40 40 new_config : OUT std_logic := '0'; 41 41 config_chain_done : IN std_logic; 42 config_started : in std_logic; 42 43 43 -- read/write configRAM 44 44 config_addr : out std_logic_vector (7 downto 0); … … 88 88 architecture Behavioral of w5300_modul is 89 89 90 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, 91 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 92 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA); 90 type state_init_type is ( 91 INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, 92 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 93 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, 94 CONFIG, WAIT_FOR_CONFIG_DONE, 95 MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA 96 ); 93 97 type state_write_type is ( 94 98 WR_START, 95 99 WR_GET_EVT_ID_WAIT1, WR_GET_EVT_ID1, WR_GET_EVT_ID_WAIT2, WR_GET_EVT_ID2, 96 100 WR_MOD7_STARTED, WR_WAIT_FOR_MOD7, 97 WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04, 98 101 WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04, 99 102 WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, 100 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3); 103 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3 104 ); 101 105 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); 102 106 type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); 103 type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END); 107 type state_read_data_type is ( 108 RD_1, 109 RD_2, 110 RD_3, 111 RD_4, 112 RD_5, 113 RD_6, 114 READ_COMMAND_DATA_SECTION, 115 PUT_COMMAND_DATA_SECTION, 116 NEW_CONT_TRIGGER_MULT_FACTOR_READ, 117 NEW_CONT_TRIGGER_MULT_FACTOR_PUT, 118 RD_WAIT, 119 RD_WAIT1, 120 RD_END 121 ); 104 122 105 123 signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; … … 140 158 141 159 signal rx_packets_cnt : std_logic_vector (15 downto 0); 142 signal next_packet_data : std_logic := '0';143 160 signal new_config_flag : std_logic := '0'; 144 161 … … 192 209 signal mod7_valid : std_logic; 193 210 signal mod7_result : std_logic_vector(2 downto 0); 194 195 signal set_new_CONT_TRIGGER_MULT_FACTOR : std_logic := '0';196 211 197 212 COMPONENT mod7 … … 577 592 578 593 when ESTABLISH => 579 580 594 socks_waiting <= '1'; 595 socks_connected <= '0'; 581 596 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; 582 597 state_init <= READ_REG; 583 598 next_state <= EST1; 584 599 when EST1 => 585 -- led <= data_read (7 downto 0);586 -- led <= X"00";587 600 case data_read (7 downto 0) is 588 601 when X"17" => -- established 589 590 591 592 593 594 595 596 602 if (socket_cnt = 7) then 603 socket_cnt <= "000"; 604 busy <= '0'; 605 state_init <= MAIN; 606 else 607 socket_cnt <= socket_cnt + 1; 608 state_init <= ESTABLISH; 609 end if; 597 610 when others => 598 611 state_init <= ESTABLISH; … … 608 621 end if; 609 622 610 611 -- MAIN "loop"--------------------------612 623 ---------------------------------------------------------------------------------- 624 -- MAIN "loop" ------------------------------------------------------------------- 625 ---------------------------------------------------------------------------------- 613 626 614 627 when MAIN => 615 socks_waiting <= '0'; 616 socks_connected <= '1'; 617 618 ps_do_phase_shift <= '0'; 619 ps_reset <= '0'; 620 if (trigger_stop = '1') then 621 s_trigger <= '0'; 622 end if; 623 data_valid_ack <= '0'; 624 state_init <= MAIN1; 625 --data_valid_int <= data_valid; 628 socks_waiting <= '0'; 629 socks_connected <= '1'; 630 ps_do_phase_shift <= '0'; 631 ps_reset <= '0'; 632 if (trigger_stop = '1') then 633 s_trigger <= '0'; 634 end if; 635 data_valid_ack <= '0'; 636 state_init <= MAIN1; 637 --data_valid_int <= data_valid; 626 638 when MAIN1 => 627 if (chk_recv_cntr = 1000) then 628 chk_recv_cntr <= 0; 629 state_read_data <= RD_1; 630 state_init <= READ_DATA; 631 busy <= '1'; 632 else 633 chk_recv_cntr <= chk_recv_cntr + 1; 634 state_init <= MAIN2; 635 end if; 636 when MAIN2 => 637 busy <= '0'; 638 --if (data_valid = '1') then 639 if (data_valid_sr = "01" or data_valid_sr = "11") then 640 --data_valid_int <= '0'; 641 busy <= '1'; 642 local_write_length <= write_length; 643 local_ram_start_addr <= ram_start_addr; 644 local_ram_addr <= (others => '0'); 645 local_write_header_flag <= write_header_flag; 646 local_write_end_flag <= write_end_flag; 647 local_fifo_channels <= fifo_channels; 648 -- data_valid_ack <= '1'; 649 -- next_state <= MAIN; 650 -- state_init <= WRITE_DATA; 651 state_init <= MAIN3; 652 else 653 state_init <= MAIN1; 654 end if; 655 when MAIN3 => 656 -- led <= local_ram_start_addr (7 downto 0); 657 639 if (chk_recv_cntr = 1000) then 640 chk_recv_cntr <= 0; 641 state_read_data <= RD_1; 642 state_init <= READ_DATA; 643 busy <= '1'; 644 else 645 chk_recv_cntr <= chk_recv_cntr + 1; 646 state_init <= MAIN2; 647 end if; 648 when MAIN2 => 649 busy <= '0'; 650 --if (data_valid = '1') then 651 if (data_valid_sr = "01" or data_valid_sr = "11") then 652 --data_valid_int <= '0'; 653 busy <= '1'; 654 local_write_length <= write_length; 655 local_ram_start_addr <= ram_start_addr; 656 local_ram_addr <= (others => '0'); 657 local_write_header_flag <= write_header_flag; 658 local_write_end_flag <= write_end_flag; 659 local_fifo_channels <= fifo_channels; 660 -- data_valid_ack <= '1'; 661 -- next_state <= MAIN; 662 -- state_init <= WRITE_DATA; 663 state_init <= MAIN3; 664 else 665 state_init <= MAIN1; 666 end if; 667 when MAIN3 => 658 668 -- needed for the check: if there is enough space in W5300 FIFO 659 669 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2) 660 661 data_valid_ack <= '1'; 662 next_state <= MAIN; 663 state_init <= WRITE_DATA; 664 665 ----------------------------------------- 666 -- END OF MAIN ------------------ 667 ----------------------------------------- 668 669 670 data_valid_ack <= '1'; 671 next_state <= MAIN; 672 state_init <= WRITE_DATA; 673 674 ---------------------------------------------------------------------------------- 675 -- END OF MAIN ----------------------------------------------------------- 676 ---------------------------------------------------------------------------------- 670 677 671 678 -- read data from socket 0 672 when READ_DATA => 673 case state_read_data is 674 when RD_1 => 675 par_addr <= W5300_S0_RX_RSR; 676 state_init <= READ_REG; 677 next_state <= READ_DATA; 678 state_read_data <= RD_2; 679 when RD_2 => 680 socket_rx_received (31 downto 16) <= data_read; 681 par_addr <= W5300_S0_RX_RSR + X"2"; 682 state_init <= READ_REG; 683 next_state <= READ_DATA; 684 state_read_data <= RD_3; 685 when RD_3 => 686 socket_rx_received (15 downto 0) <= data_read; 687 state_read_data <= RD_4; 688 when RD_4 => 689 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then 690 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2 691 state_read_data <= RD_5; 692 else 693 busy <= '0'; 694 state_init <= MAIN; 695 end if; 696 when RD_5 => 697 if (rx_packets_cnt > 0) then 698 rx_packets_cnt <= rx_packets_cnt - '1'; 699 par_addr <= W5300_S0_RX_FIFOR; 700 state_init <= READ_REG; 701 next_state <= READ_DATA; 702 state_read_data <= RD_6; 703 else 704 state_read_data <= RD_END; 705 end if; 706 when RD_6 => 707 -- led <= data_read (15 downto 8); 708 -- read command 709 if (next_packet_data = '0') then 710 case data_read (15 downto 8) is 711 712 when CMD_START => 713 data_generator_run_mode <= '1'; 714 state_read_data <= RD_5; 715 when CMD_STOP => 716 data_generator_run_mode <= '0'; 717 state_read_data <= RD_5; 718 719 when CMD_MODE_ALL_SOCKETS => -- all data will be send via socket 1..7 720 socket_send_mode <= '1'; 721 state_read_data <= RD_5; 722 723 when CMC_MODE_COMMAND => -- all data will be send via socket 0 724 socket_send_mode <= '0'; 725 state_read_data <= RD_5; 726 727 when CMD_TRIGGER => 728 trigger_stop <= '1'; 729 s_trigger <= '1'; 730 state_read_data <= RD_5; 731 when CMD_DWRITE_RUN => 732 dwrite_enable <= '1'; 733 state_read_data <= RD_5; 734 when CMD_DWRITE_STOP => 735 dwrite_enable <= '0'; 736 state_read_data <= RD_5; 737 when CMD_SCLK_ON => 738 sclk_enable <= '1'; 739 state_read_data <= RD_5; 740 when CMD_SCLK_OFF => 741 sclk_enable <= '0'; 742 state_read_data <= RD_5; 743 when CMD_DENABLE => 744 denable <= '1'; 745 state_read_data <= RD_5; 746 when CMD_DDISABLE => 747 denable <= '0'; 748 state_read_data <= RD_5; 749 when CMD_TRIGGER_C => 750 c_trigger_enable <= '1'; 751 --trigger_stop <= '0'; 752 --s_trigger <= '1'; 753 state_read_data <= RD_5; 754 when CMD_TRIGGER_S => 755 c_trigger_enable <= '0'; 756 --trigger_stop <= '1'; 757 state_read_data <= RD_5; 758 when CMD_SET_TRIGGER_MULT => 759 set_new_CONT_TRIGGER_MULT_FACTOR <= '1'; 760 next_packet_data <= '1'; 761 state_read_data <= RD_5; 762 763 -- phase shift commands here: 764 when CMD_PS_DO => 765 ps_do_phase_shift <= '1'; 766 state_read_data <= RD_5; 767 when CMD_PS_DIRINC => 768 ps_direction <= '1'; 769 state_read_data <= RD_5; 770 when CMD_PS_RESET => 771 ps_reset <= '1'; 772 state_read_data <= RD_5; 773 774 when CMD_SRCLK_ON => 775 srclk_enable <= '1'; 776 state_read_data <= RD_5; 777 when CMD_SRCLK_OFF => 778 srclk_enable <= '0'; 779 state_read_data <= RD_5; 780 781 when CMD_TRIGGERS_ON => 782 trigger_enable <= '1'; 783 state_read_data <= RD_5; 784 when CMD_TRIGGERS_OFF => 785 trigger_enable <= '0'; 786 state_read_data <= RD_5; 787 788 789 when CMD_PS_DIRDEC => 790 ps_direction <= '0'; 791 state_read_data <= RD_5; 792 when CMD_WRITE => 793 config_addr <= data_read (7 downto 0); 794 next_packet_data <= '1'; 795 state_read_data <= RD_5; 796 when others => 797 state_read_data <= RD_5; 798 end case; 679 when READ_DATA => 680 case state_read_data is 681 when RD_1 => 682 par_addr <= W5300_S0_RX_RSR; 683 state_init <= READ_REG; 684 next_state <= READ_DATA; 685 state_read_data <= RD_2; 686 when RD_2 => 687 socket_rx_received (31 downto 16) <= data_read; 688 par_addr <= W5300_S0_RX_RSR + X"2"; 689 state_init <= READ_REG; 690 next_state <= READ_DATA; 691 state_read_data <= RD_3; 692 when RD_3 => 693 socket_rx_received (15 downto 0) <= data_read; 694 state_read_data <= RD_4; 695 when RD_4 => 696 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then 697 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2 698 state_read_data <= RD_5; 699 else 700 busy <= '0'; 701 state_init <= MAIN; 702 end if; 703 when RD_5 => 704 if (rx_packets_cnt > 0) then 705 rx_packets_cnt <= rx_packets_cnt - '1'; 706 par_addr <= W5300_S0_RX_FIFOR; 707 state_init <= READ_REG; 708 next_state <= READ_DATA; 709 state_read_data <= RD_6; 710 else 711 state_read_data <= RD_END; 712 end if; 713 714 when RD_6 => 715 -- The next 16bit word is assumed to contain a 'command' so it is 716 -- beeing parsed in this state 717 case data_read (15 downto 8) is 718 when CMD_START => 719 data_generator_run_mode <= '1'; 720 state_read_data <= RD_5; 721 when CMD_STOP => 722 data_generator_run_mode <= '0'; 723 state_read_data <= RD_5; 724 when CMD_MODE_ALL_SOCKETS => -- all data will be send via socket 1..7 725 socket_send_mode <= '1'; 726 state_read_data <= RD_5; 727 when CMC_MODE_COMMAND => -- all data will be send via socket 0 728 socket_send_mode <= '0'; 729 state_read_data <= RD_5; 730 when CMD_TRIGGER => 731 trigger_stop <= '1'; 732 s_trigger <= '1'; 733 state_read_data <= RD_5; 734 when CMD_DWRITE_RUN => 735 dwrite_enable <= '1'; 736 state_read_data <= RD_5; 737 when CMD_DWRITE_STOP => 738 dwrite_enable <= '0'; 739 state_read_data <= RD_5; 740 when CMD_SCLK_ON => 741 sclk_enable <= '1'; 742 state_read_data <= RD_5; 743 when CMD_SCLK_OFF => 744 sclk_enable <= '0'; 745 state_read_data <= RD_5; 746 when CMD_DENABLE => 747 denable <= '1'; 748 state_read_data <= RD_5; 749 when CMD_DDISABLE => 750 denable <= '0'; 751 state_read_data <= RD_5; 752 when CMD_TRIGGER_C => 753 c_trigger_enable <= '1'; 754 state_read_data <= RD_5; 755 when CMD_TRIGGER_S => 756 c_trigger_enable <= '0'; 757 state_read_data <= RD_5; 758 when CMD_SET_TRIGGER_MULT => 759 state_read_data <= NEW_CONT_TRIGGER_MULT_FACTOR_READ; 760 -- phase shift commands here: 761 when CMD_PS_DO => 762 ps_do_phase_shift <= '1'; 763 state_read_data <= RD_5; 764 when CMD_PS_DIRINC => 765 ps_direction <= '1'; 766 state_read_data <= RD_5; 767 when CMD_PS_RESET => 768 ps_reset <= '1'; 769 state_read_data <= RD_5; 770 when CMD_SRCLK_ON => 771 srclk_enable <= '1'; 772 state_read_data <= RD_5; 773 when CMD_SRCLK_OFF => 774 srclk_enable <= '0'; 775 state_read_data <= RD_5; 776 when CMD_TRIGGERS_ON => 777 trigger_enable <= '1'; 778 state_read_data <= RD_5; 779 when CMD_TRIGGERS_OFF => 780 trigger_enable <= '0'; 781 state_read_data <= RD_5; 782 when CMD_PS_DIRDEC => 783 ps_direction <= '0'; 784 state_read_data <= RD_5; 785 when CMD_WRITE => 786 config_addr <= data_read (7 downto 0); 787 state_read_data <= READ_COMMAND_DATA_SECTION; 788 when others => 789 state_read_data <= RD_5; 790 end case; 799 791 -- read data 800 else 801 if ( set_new_CONT_TRIGGER_MULT_FACTOR = '1' ) then 802 set_new_CONT_TRIGGER_MULT_FACTOR <= '0'; 803 c_trigger_mult <= data_read; 804 state_read_data <= RD_5; 805 else 806 if (config_busy = '0') then 807 config_data <= data_read; 808 config_wr_en <= '1'; 809 new_config_flag <= '1'; 810 next_packet_data <= '0'; 811 state_read_data <= RD_WAIT; 812 end if; 813 end if; 814 end if; 792 793 -- these states are beeing precessed, if the 'command' was a 'write command' 794 -- so it is assumed, that some data in config RAM changed, and we need full (re)config 795 when READ_COMMAND_DATA_SECTION => 796 if (rx_packets_cnt > 0) then 797 rx_packets_cnt <= rx_packets_cnt - '1'; 798 par_addr <= W5300_S0_RX_FIFOR; 799 state_init <= READ_REG; 800 next_state <= READ_DATA; 801 state_read_data <= PUT_COMMAND_DATA_SECTION; 802 else 803 state_read_data <= RD_END; 804 end if; 805 806 when PUT_COMMAND_DATA_SECTION => 807 if (config_busy = '0') then 808 config_data <= data_read; 809 config_wr_en <= '1'; 810 new_config_flag <= '1'; 811 state_read_data <= RD_WAIT; 812 end if; 813 814 -- these states are beeing precessed, if the 'command' was a 'set new continouus trigger prescaler multiplication factor'-command 815 -- so the next 16bit word is just put out at the apropriate output. 816 when NEW_CONT_TRIGGER_MULT_FACTOR_READ => 817 if (rx_packets_cnt > 0) then 818 rx_packets_cnt <= rx_packets_cnt - '1'; 819 par_addr <= W5300_S0_RX_FIFOR; 820 state_init <= READ_REG; 821 next_state <= READ_DATA; 822 state_read_data <= NEW_CONT_TRIGGER_MULT_FACTOR_PUT; 823 else 824 state_read_data <= RD_END; 825 end if; 826 when NEW_CONT_TRIGGER_MULT_FACTOR_PUT => 827 c_trigger_mult <= data_read; 828 state_read_data <= RD_5; 829 830 815 831 when RD_WAIT => 816 832 if (config_rw_ack = '1') then
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