Changeset 10180 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Timestamp:
- 02/25/11 15:56:47 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 5 edited
-
data_generator.vhd (modified) (1 diff)
-
fad_board_struct.vhd (modified) (8 diffs)
-
fad_main_struct.vhd (modified) (26 diffs)
-
memory_manager_beha.vhd (modified) (2 diffs)
-
w5300_modul.vhd (modified) (8 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10176 r10180 48 48 dac_array : in dac_array_type; 49 49 50 mode : in std_logic := '0'; -- 0: config mode | 1: run mode50 mode : in std_logic; -- 0: config mode | 1: run mode 51 51 idling : out std_logic; 52 52 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10176 r10180 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 5:55:14 24.02.20115 -- at - 16:24:40 25.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 57 57 S_CLK : OUT std_logic; 58 58 TCS : OUT std_logic_vector (3 DOWNTO 0); 59 TRG_V : OUT std_logic ;59 TRG_V : OUT std_logic := '0'; 60 60 W_A : OUT std_logic_vector (9 DOWNTO 0); 61 61 W_CS : OUT std_logic := '1'; … … 76 76 -- Created: 77 77 -- by - dneise.UNKNOWN (E5B-LABOR6) 78 -- at - 1 5:55:15 24.02.201178 -- at - 16:24:40 25.02.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 96 96 97 97 -- Internal signal declarations 98 SIGNAL CLK_25_PS : std_logic; 99 SIGNAL CLK_25_PS1 : std_logic; 98 SIGNAL ADC_CLK : std_logic; 100 99 SIGNAL CLK_50 : std_logic; 101 100 SIGNAL SRCLK : std_logic := '0'; 102 SIGNAL adc_clk_en : std_logic := '0';103 101 SIGNAL adc_data_array : adc_data_array_type; 104 102 SIGNAL alarm_refclk_too_high : std_logic := '0'; … … 116 114 ); 117 115 PORT ( 118 CLK : IN std_logic ; 119 D_T_in : IN std_logic_vector (1 DOWNTO 0); 120 SROUT_in_0 : IN std_logic ; 121 SROUT_in_1 : IN std_logic ; 122 SROUT_in_2 : IN std_logic ; 123 SROUT_in_3 : IN std_logic ; 124 adc_data_array : IN adc_data_array_type ; 125 adc_otr_array : IN std_logic_vector (3 DOWNTO 0); 126 board_id : IN std_logic_vector (3 DOWNTO 0); 127 crate_id : IN std_logic_vector (1 DOWNTO 0); 128 drs_refclk_in : IN std_logic ; -- used TO check if DRS REFCLK exsists, if not DENABLE inhibit 129 plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked 130 trigger : IN std_logic ; 131 wiz_int : IN std_logic ; 132 CLK_25_PS : OUT std_logic ; 133 CLK_50 : OUT std_logic ; 134 RSRLOAD : OUT std_logic := '0'; 135 SRCLK : OUT std_logic := '0'; 136 SRIN_out : OUT std_logic := '0'; 137 adc_clk_en : OUT std_logic := '0'; 138 adc_oeb : OUT std_logic := '1'; 139 additional_flasher_out : OUT std_logic ; 140 alarm_refclk_too_high : OUT std_logic ; 141 alarm_refclk_too_low : OUT std_logic ; 142 amber : OUT std_logic ; 143 counter_result : OUT std_logic_vector (11 DOWNTO 0); 144 dac_cs : OUT std_logic ; 145 denable : OUT std_logic := '0'; -- default domino wave off 146 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 147 drs_dwrite : OUT std_logic := '1'; 148 green : OUT std_logic ; 149 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 150 mosi : OUT std_logic := '0'; 151 red : OUT std_logic ; 152 sclk : OUT std_logic ; 153 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 154 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 155 wiz_cs : OUT std_logic := '1'; 156 wiz_rd : OUT std_logic := '1'; 157 wiz_reset : OUT std_logic := '1'; 158 wiz_wr : OUT std_logic := '1'; 159 sio : INOUT std_logic ; 160 wiz_data : INOUT std_logic_vector (15 DOWNTO 0) 116 CLK : IN std_logic ; 117 D_T_in : IN std_logic_vector (1 DOWNTO 0); 118 SROUT_in_0 : IN std_logic ; 119 SROUT_in_1 : IN std_logic ; 120 SROUT_in_2 : IN std_logic ; 121 SROUT_in_3 : IN std_logic ; 122 adc_data_array : IN adc_data_array_type ; 123 adc_otr_array : IN std_logic_vector (3 DOWNTO 0); 124 board_id : IN std_logic_vector (3 DOWNTO 0); 125 crate_id : IN std_logic_vector (1 DOWNTO 0); 126 drs_refclk_in : IN std_logic ; -- used TO check if DRS REFCLK exsists, if not DENABLE inhibit 127 plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked 128 trigger : IN std_logic ; 129 wiz_int : IN std_logic ; 130 ADC_CLK : OUT std_logic ; 131 CLK_25_PS : OUT std_logic ; 132 CLK_50 : OUT std_logic ; 133 RSRLOAD : OUT std_logic := '0'; 134 SRCLK : OUT std_logic := '0'; 135 SRIN_out : OUT std_logic := '0'; 136 adc_oeb : OUT std_logic := '1'; 137 alarm_refclk_too_high : OUT std_logic ; 138 alarm_refclk_too_low : OUT std_logic ; 139 amber : OUT std_logic ; 140 counter_result : OUT std_logic_vector (11 DOWNTO 0); 141 dac_cs : OUT std_logic ; 142 denable : OUT std_logic := '0'; -- default domino wave off 143 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 144 drs_dwrite : OUT std_logic := '1'; 145 green : OUT std_logic ; 146 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 147 mosi : OUT std_logic := '0'; 148 red : OUT std_logic ; 149 sclk : OUT std_logic ; 150 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 151 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 152 wiz_cs : OUT std_logic := '1'; 153 wiz_rd : OUT std_logic := '1'; 154 wiz_reset : OUT std_logic := '1'; 155 wiz_wr : OUT std_logic := '1'; 156 sio : INOUT std_logic ; 157 wiz_data : INOUT std_logic_vector (15 DOWNTO 0) 161 158 ); 162 159 END COMPONENT; … … 174 171 175 172 -- HDL Embedded Text Block 2 ADC_CLK 176 A_CLK <= (CLK_25_PS, CLK_25_PS, CLK_25_PS, CLK_25_PS); 173 A_CLK <= ( 174 ADC_CLK, 175 ADC_CLK, 176 ADC_CLK, 177 ADC_CLK 178 ); 177 179 178 180 -- HDL Embedded Text Block 3 ADC_DATA … … 222 224 223 225 224 -- ModuleWare code(v1.9) for instance 'I0' of ' and'225 CLK_25_PS <= adc_clk_en AND CLK_25_PS1;226 -- ModuleWare code(v1.9) for instance 'I0' of 'gnd' 227 TRG_V <= '0'; 226 228 227 229 -- Instance port mappings. … … 231 233 ) 232 234 PORT MAP ( 233 CLK => X_50M, 234 D_T_in => D_T_in, 235 SROUT_in_0 => D0_SROUT, 236 SROUT_in_1 => D1_SROUT, 237 SROUT_in_2 => D2_SROUT, 238 SROUT_in_3 => D3_SROUT, 239 adc_data_array => adc_data_array, 240 adc_otr_array => A_OTR, 241 board_id => board_id, 242 crate_id => crate_id, 243 drs_refclk_in => REFCLK, 244 plllock_in => D_PLLLCK, 245 trigger => TRG, 246 wiz_int => W_INT, 247 CLK_25_PS => CLK_25_PS1, 248 CLK_50 => CLK_50, 249 RSRLOAD => RSRLOAD, 250 SRCLK => SRCLK, 251 SRIN_out => SRIN, 252 adc_clk_en => adc_clk_en, 253 adc_oeb => OE_ADC, 254 additional_flasher_out => TRG_V, 255 alarm_refclk_too_high => alarm_refclk_too_high, 256 alarm_refclk_too_low => alarm_refclk_too_low, 257 amber => AMBER_LED, 258 counter_result => counter_result, 259 dac_cs => DAC_CS, 260 denable => DENABLE, 261 drs_channel_id => D_A, 262 drs_dwrite => DWRITE, 263 green => RED_LED, 264 led => led, 265 mosi => MOSI, 266 red => GREEN_LED, 267 sclk => S_CLK, 268 sensor_cs => TCS, 269 wiz_addr => W_A, 270 wiz_cs => W_CS, 271 wiz_rd => W_RD, 272 wiz_reset => W_RES, 273 wiz_wr => W_WR, 274 sio => MISO, 275 wiz_data => W_D 235 CLK => X_50M, 236 D_T_in => D_T_in, 237 SROUT_in_0 => D0_SROUT, 238 SROUT_in_1 => D1_SROUT, 239 SROUT_in_2 => D2_SROUT, 240 SROUT_in_3 => D3_SROUT, 241 adc_data_array => adc_data_array, 242 adc_otr_array => A_OTR, 243 board_id => board_id, 244 crate_id => crate_id, 245 drs_refclk_in => REFCLK, 246 plllock_in => D_PLLLCK, 247 trigger => TRG, 248 wiz_int => W_INT, 249 ADC_CLK => ADC_CLK, 250 CLK_25_PS => OPEN, 251 CLK_50 => CLK_50, 252 RSRLOAD => RSRLOAD, 253 SRCLK => SRCLK, 254 SRIN_out => SRIN, 255 adc_oeb => OE_ADC, 256 alarm_refclk_too_high => alarm_refclk_too_high, 257 alarm_refclk_too_low => alarm_refclk_too_low, 258 amber => AMBER_LED, 259 counter_result => counter_result, 260 dac_cs => DAC_CS, 261 denable => DENABLE, 262 drs_channel_id => D_A, 263 drs_dwrite => DWRITE, 264 green => RED_LED, 265 led => led, 266 mosi => MOSI, 267 red => GREEN_LED, 268 sclk => S_CLK, 269 sensor_cs => TCS, 270 wiz_addr => W_A, 271 wiz_cs => W_CS, 272 wiz_rd => W_RD, 273 wiz_reset => W_RES, 274 wiz_wr => W_WR, 275 sio => MISO, 276 wiz_data => W_D 276 277 ); 277 278 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10176 r10180 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 5:55:13 24.02.20115 -- at - 16:10:13 25.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 18 18 ); 19 19 PORT( 20 CLK : IN std_logic; 21 D_T_in : IN std_logic_vector (1 DOWNTO 0); 22 SROUT_in_0 : IN std_logic; 23 SROUT_in_1 : IN std_logic; 24 SROUT_in_2 : IN std_logic; 25 SROUT_in_3 : IN std_logic; 26 adc_data_array : IN adc_data_array_type; 27 adc_otr_array : IN std_logic_vector (3 DOWNTO 0); 28 board_id : IN std_logic_vector (3 DOWNTO 0); 29 crate_id : IN std_logic_vector (1 DOWNTO 0); 30 drs_refclk_in : IN std_logic; -- used to check if DRS REFCLK exsists, if not DENABLE inhibit 31 plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked 32 trigger : IN std_logic; 33 wiz_int : IN std_logic; 34 CLK_25_PS : OUT std_logic; 35 CLK_50 : OUT std_logic; 36 RSRLOAD : OUT std_logic := '0'; 37 SRCLK : OUT std_logic := '0'; 38 SRIN_out : OUT std_logic := '0'; 39 adc_clk_en : OUT std_logic := '0'; 40 adc_oeb : OUT std_logic := '1'; 41 additional_flasher_out : OUT std_logic; 42 alarm_refclk_too_high : OUT std_logic; 43 alarm_refclk_too_low : OUT std_logic; 44 amber : OUT std_logic; 45 counter_result : OUT std_logic_vector (11 DOWNTO 0); 46 dac_cs : OUT std_logic; 47 denable : OUT std_logic := '0'; -- default domino wave off 48 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 49 drs_dwrite : OUT std_logic := '1'; 50 green : OUT std_logic; 51 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 52 mosi : OUT std_logic := '0'; 53 red : OUT std_logic; 54 sclk : OUT std_logic; 55 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 56 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 57 wiz_cs : OUT std_logic := '1'; 58 wiz_rd : OUT std_logic := '1'; 59 wiz_reset : OUT std_logic := '1'; 60 wiz_wr : OUT std_logic := '1'; 61 sio : INOUT std_logic; 62 wiz_data : INOUT std_logic_vector (15 DOWNTO 0) 20 CLK : IN std_logic; 21 D_T_in : IN std_logic_vector (1 DOWNTO 0); 22 SROUT_in_0 : IN std_logic; 23 SROUT_in_1 : IN std_logic; 24 SROUT_in_2 : IN std_logic; 25 SROUT_in_3 : IN std_logic; 26 adc_data_array : IN adc_data_array_type; 27 adc_otr_array : IN std_logic_vector (3 DOWNTO 0); 28 board_id : IN std_logic_vector (3 DOWNTO 0); 29 crate_id : IN std_logic_vector (1 DOWNTO 0); 30 drs_refclk_in : IN std_logic; -- used to check if DRS REFCLK exsists, if not DENABLE inhibit 31 plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked 32 trigger : IN std_logic; 33 wiz_int : IN std_logic; 34 ADC_CLK : OUT std_logic; 35 CLK_25_PS : OUT std_logic; 36 CLK_50 : OUT std_logic; 37 RSRLOAD : OUT std_logic := '0'; 38 SRCLK : OUT std_logic := '0'; 39 SRIN_out : OUT std_logic := '0'; 40 adc_oeb : OUT std_logic := '1'; 41 alarm_refclk_too_high : OUT std_logic; 42 alarm_refclk_too_low : OUT std_logic; 43 amber : OUT std_logic; 44 counter_result : OUT std_logic_vector (11 DOWNTO 0); 45 dac_cs : OUT std_logic; 46 denable : OUT std_logic := '0'; -- default domino wave off 47 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 48 drs_dwrite : OUT std_logic := '1'; 49 green : OUT std_logic; 50 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 51 mosi : OUT std_logic := '0'; 52 red : OUT std_logic; 53 sclk : OUT std_logic; 54 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 55 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 56 wiz_cs : OUT std_logic := '1'; 57 wiz_rd : OUT std_logic := '1'; 58 wiz_reset : OUT std_logic := '1'; 59 wiz_wr : OUT std_logic := '1'; 60 sio : INOUT std_logic; 61 wiz_data : INOUT std_logic_vector (15 DOWNTO 0) 63 62 ); 64 63 … … 72 71 -- Created: 73 72 -- by - dneise.UNKNOWN (E5B-LABOR6) 74 -- at - 1 5:55:14 24.02.201173 -- at - 16:10:14 25.02.2011 75 74 -- 76 75 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 106 105 SIGNAL FTM_RS485_ready : std_logic; 107 106 SIGNAL SRCLK1 : std_logic := '0'; 107 SIGNAL adc_clk_en : std_logic; 108 108 SIGNAL adc_data_array_int : adc_data_array_type; 109 109 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); … … 135 135 SIGNAL data_generator_run_mode : std_logic := '0'; -- default triggers are NOT accepted 136 136 SIGNAL data_out : std_logic_vector(63 DOWNTO 0); 137 SIGNAL data_ram_empty : std_logic; 137 138 SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off 138 139 SIGNAL denable_prim : std_logic := '0'; -- default domino wave off … … 319 320 sensor_ready : IN std_logic ; 320 321 dac_array : IN dac_array_type ; 321 mode : IN std_logic := '0';-- 0: config mode | 1: run mode322 mode : IN std_logic ; -- 0: config mode | 1: run mode 322 323 idling : OUT std_logic ; 323 324 -- EVT HEADER - part 1 … … 435 436 wiz_busy : IN std_logic ; 436 437 wiz_ack : IN std_logic ; 437 buffer_ram_empty : OUT std_logic;438 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')438 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0'); 439 data_ram_empty : OUT std_logic 439 440 ); 440 441 END COMPONENT; … … 513 514 s_trigger : OUT std_logic := '0'; 514 515 c_trigger_enable : OUT std_logic := '0'; 515 c_trigger_mult : OUT std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector( 100 ,16); --subject TO changes516 c_trigger_mult : OUT std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(0 ,16); --subject TO changes 516 517 -- FAD configuration signals: 517 518 ------------------------------------------------------------------------------ … … 519 520 new_config : OUT std_logic := '0'; 520 521 config_chain_done : IN std_logic ; 522 data_generator_run_mode : OUT std_logic ; -- default triggers will be accepted 523 data_ram_empty : IN std_logic ; 521 524 -- read/write configRAM 522 525 config_addr : OUT std_logic_vector (7 DOWNTO 0); … … 538 541 -- user controllable enable signals 539 542 ------------------------------------------------------------------------------ 540 trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted 541 data_generator_run_mode : OUT std_logic := '0'; -- default triggers are NOT accepted 542 denable : OUT std_logic := '0'; -- default domino wave off 543 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. 544 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. 545 srclk_enable : OUT std_logic := '1'; -- default SRCLK on. 543 trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted 544 denable : OUT std_logic := '0'; -- default domino wave off 545 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. 546 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. 547 srclk_enable : OUT std_logic := '1'; -- default SRCLK on. 546 548 ------------------------------------------------------------------------------ 547 549 … … 549 551 -- these signals control the behavior of the digital clock manager (DCM) 550 552 ------------------------------------------------------------------------------ 551 ps_direction : OUT std_logic := '1'; 552 ps_do_phase_shift : OUT std_logic := '0'; 553 ps_reset : OUT std_logic := '0'; 553 ps_direction : OUT std_logic := '1'; -- default phase shift upwards 554 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once 555 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift 554 556 ------------------------------------------------------------------------------ 555 557 … … 593 595 594 596 595 -- ModuleWare code(v1.9) for instance 'I5' of 'and'596 drs_dwrite <= dwrite AND dwrite_enable;597 598 597 -- ModuleWare code(v1.9) for instance 'I6' of 'and' 599 598 SRCLK <= SRCLK1 AND srclk_enable; 600 599 601 -- ModuleWare code(v1.9) for instance 'U_1' of 'and' 600 -- ModuleWare code(v1.9) for instance 'and_1' of 'and' 601 ADC_CLK <= adc_clk_en AND CLK_25_PS_internal; 602 603 -- ModuleWare code(v1.9) for instance 'and_2' of 'and' 604 denable <= denable_prim AND din1; 605 606 -- ModuleWare code(v1.9) for instance 'and_3' of 'and' 602 607 sclk <= sclk_enable AND sclk1; 603 608 604 -- ModuleWare code(v1.9) for instance 'U_5' of 'and' 605 denable <= denable_prim AND din1; 606 607 -- ModuleWare code(v1.9) for instance 'U_11' of 'and' 609 -- ModuleWare code(v1.9) for instance 'and_4' of 'and' 608 610 dout1 <= dout AND trigger_enable; 611 612 -- ModuleWare code(v1.9) for instance 'and_5' of 'and' 613 drs_dwrite <= dwrite AND dwrite_enable; 609 614 610 615 -- ModuleWare code(v1.9) for instance 'U_15' of 'gnd' 611 616 reset_synch_i <= '0'; 612 617 613 -- ModuleWare code(v1.9) for instance ' U_7' of 'inv'618 -- ModuleWare code(v1.9) for instance 'inverter_1' of 'inv' 614 619 din1 <= NOT(denable_inhibit); 615 620 616 -- ModuleWare code(v1.9) for instance 'U_6' of 'or' 621 -- ModuleWare code(v1.9) for instance 'or_1' of 'or' 622 s_trigger <= s_trigger_0 OR trigger1; 623 624 -- ModuleWare code(v1.9) for instance 'or_2' of 'or' 617 625 denable_inhibit <= alarm_refclk_too_low_internal 618 626 OR alarm_refclk_too_high_internal; 619 627 620 -- ModuleWare code(v1.9) for instance ' U_9' of 'or'628 -- ModuleWare code(v1.9) for instance 'or_5' of 'or' 621 629 dout <= s_trigger OR trigger; 622 623 -- ModuleWare code(v1.9) for instance 'U_13' of 'or'624 s_trigger <= s_trigger_0 OR trigger1;625 630 626 631 -- ModuleWare code(v1.9) for instance 'U_14' of 'vdd' … … 636 641 alarm_refclk_too_low => alarm_refclk_too_low_internal 637 642 ); 638 U_16: RS485_receiver_fake643 RS485_receiver_fake_instance : RS485_receiver_fake 639 644 PORT MAP ( 640 645 trigger_no => trigger_id, … … 653 658 adc_otr => adc_otr 654 659 ); 655 U_2: clock_generator_var_ps660 clock_generator_instance : clock_generator_var_ps 656 661 PORT MAP ( 657 662 CLK => CLK, … … 664 669 offset => DCM_PS_status 665 670 ); 666 U_3: continous_pulser671 continous_pulser_instance : continous_pulser 667 672 GENERIC MAP ( 668 673 MINIMAL_TRIGGER_WAIT_TIME => 250000, … … 692 697 config_data => config_data 693 698 ); 694 U_4: dataRAM_64b_16b_width14_5699 dataRAM_instance : dataRAM_64b_16b_width14_5 695 700 PORT MAP ( 696 701 clka => CLK_25, … … 729 734 sensor_ready => sensor_ready, 730 735 dac_array => dac_array, 731 mode => OPEN,736 mode => data_generator_run_mode, 732 737 idling => OPEN, 733 738 package_length => package_length, … … 765 770 drs_readout_started => drs_readout_started 766 771 ); 767 U_0: dna_gen772 dna_gen_instance : dna_gen 768 773 PORT MAP ( 769 774 clk => CLK_25, … … 790 795 SRCLK => SRCLK1 791 796 ); 792 U_10: led_controller797 led_controller_instance : led_controller 793 798 GENERIC MAP ( 794 799 HEARTBEAT_PWM_DIVIDER => 50000, -- 10kHz @ 50 MHz … … 801 806 amber => amber, 802 807 red => red, 803 additional_flasher_out => additional_flasher_out,808 additional_flasher_out => OPEN, 804 809 trigger => drs_readout_started, 805 810 socks_waiting => socks_waiting, … … 830 835 wiz_busy => wiz_busy, 831 836 wiz_ack => wiz_ack, 832 buffer_ram_empty => OPEN,833 ram_start_addr => ram_start_addr837 ram_start_addr => ram_start_addr, 838 data_ram_empty => data_ram_empty 834 839 ); 835 840 I_main_SPI_interface : spi_interface … … 848 853 miso => sio 849 854 ); 850 U_8: timer855 timer_instance : timer 851 856 GENERIC MAP ( 852 857 TIMER_WIDTH => 32, … … 861 866 enable_i => enable_i 862 867 ); 863 I_main_ext_trigger: trigger_counter868 trigger_counter_instance : trigger_counter 864 869 PORT MAP ( 865 870 trigger_id => trigger_id, … … 867 872 clk => CLK_25_PS_internal 868 873 ); 869 U_12: trigger_manager874 trigger_manager_instance : trigger_manager 870 875 PORT MAP ( 871 876 clk => CLK_25, … … 905 910 new_config => new_config, 906 911 config_chain_done => config_started, 912 data_generator_run_mode => data_generator_run_mode, 913 data_ram_empty => data_ram_empty, 907 914 config_addr => config_addr, 908 915 config_data => config_data, … … 916 923 CrateID => crate_id, 917 924 trigger_enable => trigger_enable, 918 data_generator_run_mode => data_generator_run_mode,919 925 denable => denable_prim, 920 926 dwrite_enable => dwrite_enable, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd
r10176 r10180 53 53 wiz_ack : IN std_logic; 54 54 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0'); 55 buffer_ram_empty : out std_logic55 data_ram_empty : out std_logic 56 56 ); 57 57 … … 105 105 106 106 -- led <= conv_std_logic_vector (events_in_ram, 4) & "00" & wiz_ack & wiz_busy; 107 buffer_ram_empty <= '1' when events_in_ram = 0 else '0';107 data_ram_empty <= '1' when events_in_ram = 0 else '0'; 108 108 109 109 mm : process (clk) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10176 r10180 33 33 s_trigger : OUT std_logic := '0'; 34 34 c_trigger_enable: out std_logic := '0'; 35 c_trigger_mult: out std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector( 100 ,16); --subject to changes35 c_trigger_mult: out std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(0 ,16); --subject to changes 36 36 37 37 -- FAD configuration signals: … … 40 40 new_config : OUT std_logic := '0'; 41 41 config_chain_done : IN std_logic; 42 42 data_generator_run_mode : out std_logic; -- default triggers will be accepted 43 data_ram_empty : IN std_logic; 43 44 -- read/write configRAM 44 45 config_addr : out std_logic_vector (7 downto 0); … … 60 61 ------------------------------------------------------------------------------ 61 62 trigger_enable : out std_logic := '0'; -- default triggers are NOT accepted 62 data_generator_run_mode : out std_logic := '0'; -- default triggers are NOT accepted63 63 64 denable : out std_logic := '0'; -- default domino wave off 64 65 dwrite_enable : out std_logic := '0'; -- default DWRITE low. … … 92 93 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 93 94 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, 94 CONFIG, WAIT_FOR_ CONFIG_DONE,95 CONFIG, WAIT_FOR_DATA_RAM_EMPTY, WAIT_FOR_CONFIG_DONE, 95 96 MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA 96 97 ); … … 198 199 --signal error_cnt : std_logic_vector (7 downto 0) := (others => '0'); 199 200 --signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0'); 200 201 201 signal DG_run_mode_temp_storage_signal : std_logic; 202 signal data_generator_run_mode_signal : std_logic := '1'; -- default triggers will be accepted 202 203 -- signals for different socket modes: DN 04.01.11 203 204 signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending … … 240 241 RST_TIME <= X"00120"; 241 242 --synthesis translate_on 242 243 244 -- concurrent statemnets 245 data_generator_run_mode <= data_generator_run_mode_signal; 243 246 244 247 w5300_proc : process (clk) … … 613 616 614 617 when CONFIG => 615 new_config <= '1'; 616 state_init <= WAIT_FOR_CONFIG_DONE; 618 DG_run_mode_temp_storage_signal <= data_generator_run_mode_signal; --save current value of DG run mode signal. 619 data_generator_run_mode_signal <= '0'; --switch DG to config-mode --> no triggers are accepted 620 state_init <= WAIT_FOR_DATA_RAM_EMPTY; 621 when WAIT_FOR_DATA_RAM_EMPTY => 622 if (data_ram_empty = '1') then 623 new_config <= '1'; 624 state_init <= WAIT_FOR_CONFIG_DONE; 625 end if; 617 626 when WAIT_FOR_CONFIG_DONE => 618 627 new_config <= '0'; 619 628 if (config_chain_done ='1') then 620 629 state_init <= MAIN; 630 data_generator_run_mode_signal <= DG_run_mode_temp_storage_signal; -- restore former value of DG run mode signal 621 631 end if; 622 632 … … 717 727 case data_read (15 downto 8) is 718 728 when CMD_START => 719 data_generator_run_mode <= '1';729 data_generator_run_mode_signal <= '1'; 720 730 state_read_data <= RD_5; 721 731 when CMD_STOP => 722 data_generator_run_mode <= '0';732 data_generator_run_mode_signal <= '0'; 723 733 state_read_data <= RD_5; 724 734 when CMD_MODE_ALL_SOCKETS => -- all data will be send via socket 1..7
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