Changeset 10225 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Timestamp:
- 03/04/11 10:16:36 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 3 added
- 16 edited
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REFCLK_counter_behavior.vhd (modified) (2 diffs)
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RS485_receiver_fake_beha.vhd (modified) (1 diff)
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clock_generator_struct.vhd (modified) (2 diffs)
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clock_generator_var_ps_struct.vhd (modified) (5 diffs)
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data_generator.vhd (modified) (12 diffs)
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dna_gen.vhd (modified) (1 diff)
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fad_board_struct.vhd (modified) (2 diffs)
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fad_definitions.vhd (modified) (6 diffs, 1 prop)
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fad_main_struct.vhd (modified) (35 diffs)
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led_controller_bahavior.vhd (modified) (4 diffs)
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memory_manager_beha.vhd (modified) (4 diffs)
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phase_shifter.vhd (modified) (2 diffs)
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spi_distributor_beha.vhd (modified) (6 diffs)
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spi_interface_struct.vhd (modified) (8 diffs)
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string_to_int_pkg.vhd (added)
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text_util_pkg.vhd (added)
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transcript (added)
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trigger_counter_beha.vhd (modified) (3 diffs)
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w5300_modul.vhd (modified) (27 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/REFCLK_counter_behavior.vhd
r10149 r10225 41 41 42 42 signal gate : std_logic := '0'; 43 signal time : integer range 0 to TIMER_MAX-1; --2ms clock43 signal time_sig : integer range 0 to TIMER_MAX-1; --2ms clock 44 44 45 45 signal counter : integer range 0 to 4095 :=0 ; 46 46 BEGIN 47 47 48 -- synchronize REFCLK in49 48 process (clk) 50 49 begin 51 if rising_edge(clk) then 52 -- Schieberegister 53 refclk_in_sr <= refclk_in_sr(0) & refclk_in; 54 end if; 55 end process; 56 57 process ( refclk_in_sr(1)) 58 59 begin 60 if rising_edge( refclk_in_sr(1) ) then 61 gate_sr <= gate_sr(0) & gate; 62 case gate_sr is 63 when "00" => 64 when "01" => --rising edge 65 counter <= 0; 66 when "10" => 67 counter_result <= std_logic_vector( to_unsigned(counter,12) ); 68 if (counter < FREQ_LOWER_LIMIT ) then 69 alarm_refclk_too_low <= '1'; 70 else 71 alarm_refclk_too_low <= '0'; 72 end if; 73 if (counter > FREQ_UPPER_LIMIT ) then 74 alarm_refclk_too_high <= '1'; 75 else 76 alarm_refclk_too_high <= '0'; 77 end if; 78 when "11" => 79 counter <= counter +1; 80 WHEN OTHERS => 81 82 end case; 83 end if; 84 end process; 50 if rising_edge( clk ) then 51 refclk_in_sr <= refclk_in_sr(0) & refclk_in; -- synchronize REFCLK in 52 gate_sr <= gate_sr(0) & gate; 53 case gate_sr is 54 when "00" => 55 when "01" => --rising edge 56 counter <= 0; 57 when "10" => 58 counter_result <= std_logic_vector( to_unsigned(counter,12) ); 59 if (counter < FREQ_LOWER_LIMIT ) then 60 alarm_refclk_too_low <= '1'; 61 else 62 alarm_refclk_too_low <= '0'; 63 end if; 64 if (counter > FREQ_UPPER_LIMIT ) then 65 alarm_refclk_too_high <= '1'; 66 else 67 alarm_refclk_too_high <= '0'; 68 end if; 69 when "11" => 70 if (refclk_in_sr = "01") then 71 counter <= counter +1; 72 end if; 73 WHEN OTHERS => 74 end case; 75 end if; 76 end process; 85 77 86 78 -- timer proc; generates 1ms gate … … 89 81 begin 90 82 if rising_edge(clk) then 91 if (time < TIMER_MAX-1) then92 time <= time+ 1;83 if (time_sig < TIMER_MAX-1) then 84 time_sig <= time_sig + 1; 93 85 else 94 time <= 0;86 time_sig <= 0; 95 87 end if; 96 88 97 if (time = 0) then89 if (time_sig = 0) then 98 90 gate <= '1'; 99 91 end if; 100 if (time = (TIMER_MAX/2)-1) then92 if (time_sig = (TIMER_MAX/2)-1) then 101 93 gate <= '0'; 102 94 end if; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/RS485_receiver_fake_beha.vhd
r10172 r10225 28 28 BEGIN 29 29 rs485_ready <= '1'; 30 rs465_data <= trigger_no & trigger_type1 & trigger_type2 & crc;30 rs465_data <= crc & trigger_type2 & trigger_type1 & trigger_no; 31 31 32 32 END ARCHITECTURE beha; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_struct.vhd
r9912 r10225 2 2 -- 3 3 -- Created: 4 -- by - d neise.UNKNOWN (E5B-LABOR6)5 -- at - 1 3:21:39 24.08.20104 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 16:36:52 02.03.2011 6 6 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 8 8 -- 9 9 LIBRARY ieee; … … 27 27 -- 28 28 -- Created: 29 -- by - d neise.UNKNOWN (E5B-LABOR6)30 -- at - 1 3:21:40 24.08.201029 -- by - daqct3.UNKNOWN (IHP110) 30 -- at - 16:36:52 02.03.2011 31 31 -- 32 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)32 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 33 33 -- 34 34 LIBRARY ieee; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd
r10155 r10225 2 2 -- 3 3 -- Created: 4 -- by - d neise.UNKNOWN (E5B-LABOR6)5 -- at - 1 3:26:27 14.02.20114 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 17:35:41 03.03.2011 6 6 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 8 8 -- 9 9 LIBRARY ieee; … … 13 13 ENTITY clock_generator_var_ps IS 14 14 PORT( 15 CLK : IN std_logic; 16 RST_IN : IN std_logic; 17 direction : IN std_logic; 18 do_shift : IN std_logic; 19 CLK_25 : OUT std_logic; 20 CLK_25_PS : OUT std_logic; 21 CLK_50 : OUT std_logic; 22 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') 15 CLK : IN std_logic; 16 RST_IN : IN std_logic; 17 direction : IN std_logic; 18 do_shift : IN std_logic; 19 CLK_25 : OUT std_logic; 20 CLK_25_PS : OUT std_logic; 21 CLK_50 : OUT std_logic; 22 locked_status_o : OUT std_logic; 23 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 24 ready_status_o : OUT std_logic 23 25 ); 24 26 … … 31 33 -- 32 34 -- Created: 33 -- by - d neise.UNKNOWN (E5B-LABOR6)34 -- at - 1 3:26:27 14.02.201135 -- by - daqct3.UNKNOWN (IHP110) 36 -- at - 17:35:41 03.03.2011 35 37 -- 36 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)38 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 37 39 -- 38 40 LIBRARY ieee; … … 93 95 COMPONENT phase_shifter 94 96 PORT ( 95 CLK : IN std_logic ;96 rst : OUT std_logic := '0'; --asynch in of DCM97 CLK : IN std_logic ; 98 rst : OUT std_logic := '0'; --asynch in of DCM 97 99 -- interface to: clock_generator_variable_PS_struct.vhd 98 PSCLK : OUT std_logic ;99 PSEN : OUT std_logic := '0';100 PSINCDEC : OUT std_logic := '1'; -- default is 'incrementing'101 PSDONE : IN std_logic ; -- will pulse once, if phase shifting was done.102 LOCKED : IN std_logic ; -- when is this going high?100 PSCLK : OUT std_logic ; 101 PSEN : OUT std_logic := '0'; 102 PSINCDEC : OUT std_logic := '1'; -- default is 'incrementing' 103 PSDONE : IN std_logic ; -- will pulse once, if phase shifting was done. 104 LOCKED : IN std_logic ; -- when is this going high? 103 105 -- interface to: w5300_modul.vhd 104 shift_phase : IN std_logic ;105 direction : IN std_logic ; -- corresponds TO 'PSINCDEC'106 reset_DCM : IN std_logic ; -- asynch in: orders us, TO reset the DCM106 shift_phase : IN std_logic ; 107 direction : IN std_logic ; -- corresponds TO 'PSINCDEC' 108 reset_DCM : IN std_logic ; -- asynch in: orders us, TO reset the DCM 107 109 -- status: 108 shifting : OUT std_logic := '0'; 109 ready : OUT std_logic := '0'; 110 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') 110 shifting : OUT std_logic := '0'; 111 ready : OUT std_logic := '0'; 112 locked_status_o : OUT std_logic ; 113 ready_status_o : OUT std_logic ; 114 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') 111 115 ); 112 116 END COMPONENT; … … 149 153 U_4 : phase_shifter 150 154 PORT MAP ( 151 CLK => CLK0_OUT, 152 rst => rst, 153 PSCLK => PSCLK_IN, 154 PSEN => PSEN_IN, 155 PSINCDEC => PSINCDEC_IN, 156 PSDONE => PSDONE_OUT, 157 LOCKED => LOCKED_OUT, 158 shift_phase => do_shift, 159 direction => direction, 160 reset_DCM => RST_IN, 161 shifting => OPEN, 162 ready => OPEN, 163 offset => offset 155 CLK => CLK0_OUT, 156 rst => rst, 157 PSCLK => PSCLK_IN, 158 PSEN => PSEN_IN, 159 PSINCDEC => PSINCDEC_IN, 160 PSDONE => PSDONE_OUT, 161 LOCKED => LOCKED_OUT, 162 shift_phase => do_shift, 163 direction => direction, 164 reset_DCM => RST_IN, 165 shifting => OPEN, 166 ready => OPEN, 167 locked_status_o => locked_status_o, 168 ready_status_o => ready_status_o, 169 offset => offset 164 170 ); 165 171 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10180 r10225 33 33 ram_write_ready : out std_logic := '0'; 34 34 ram_write_ready_ack : IN std_logic; 35 config_start_mm : out std_logic := '0'; 36 config_start_cm : out std_logic := '0'; 37 config_start_spi : out std_logic := '0'; 38 config_ready_mm : in std_logic; 39 config_ready_cm : in std_logic; 40 config_ready_spi : in std_logic; 41 config_started_mm : in std_logic; 42 config_started_cm : in std_logic; 43 config_started_spi : in std_logic; 35 44 36 roi_array : in roi_array_type; 45 37 roi_max : in roi_max_type; … … 48 40 dac_array : in dac_array_type; 49 41 50 mode : in std_logic; -- 0: config mode | 1: run mode51 idling : out std_logic;42 config_start : in std_logic; 43 config_done : out std_logic := '0'; 52 44 53 45 -- EVT HEADER - part 1 54 46 package_length : in std_logic_vector (15 downto 0); 55 47 pll_lock : in std_logic_vector ( 3 downto 0); 48 dwrite_enable_in : in std_logic; 49 denable_enable_in : in std_logic; 56 50 57 51 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... … … 71 65 crate_id : in std_logic_vector (1 downto 0); 72 66 DCM_PS_status : in std_logic_vector (7 downto 0); 67 DCM_locked_status : in std_logic; 68 DCM_ready_status : in std_logic; 69 SPI_SCLK_enable_status : in std_logic; 73 70 TRG_GEN_div : in std_logic_vector (15 downto 0); 74 71 … … 80 77 81 78 trigger : in std_logic; 82 start_config_chain : in std_logic; -- here W5300_MODUL can start the whole config chain83 config_chain_done : out std_logic;84 79 85 80 adc_data_array : in adc_data_array_type; … … 110 105 111 106 type state_generate_type is ( 112 CONFIG_CHAIN_START, -- IDLE branches into this state, if needed. 113 CONFIG_MEMORY_MANAGER, 114 CONFIG_SPI_INTERFACE, 115 WAIT_FOR_CONFIG_SPI_INTERFACE, 107 CONFIG, -- IDLE branches into this state, if needed. 116 108 CONFIG_DRS_01, -- these four states configure the DRS shift registers, 117 109 CONFIG_DRS_02, -- the make great use of the drs_pulser entity. … … 134 126 135 127 -- configuration stuff: 136 -- this flag is set, when ever a rising edge on ' start_config_chain' is detected.137 -- this flag is cleared only, when a configuration chainwas successfully processed138 signal start_config_chain_flag : std_logic;139 signal start_config_chain_sr : std_logic_vector(1 downto 0); 140 141 signal state_generate : state_generate_type := CONFIG _CHAIN_START;128 -- this flag is set, when ever a rising edge on 'config_start' is detected. 129 -- this flag is cleared only, when a configuration was successfully processed 130 signal config_start_sig : std_logic := '0'; 131 132 133 signal state_generate : state_generate_type := CONFIG; 142 134 signal start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); 143 135 … … 153 145 -- internal signal: to be sampled once and used instead of inputs! 154 146 signal roi_max_int : roi_max_type; 155 147 signal package_length_sig : std_logic_vector (15 downto 0); 156 148 signal sig_drs_readout_started : std_logic := '0'; 157 149 158 signal sig_idling : std_logic := '1'; 150 151 152 -- self configuration signals: 153 signal internal_roi_array : roi_array_type; 154 signal internal_roi_max : roi_max_type; 159 155 160 156 begin 161 157 drs_readout_started <= sig_drs_readout_started; 162 idling <= sig_idling;163 158 generate_data : process (clk) 164 159 begin 165 160 if rising_edge (clk) then 166 start_config_chain_sr <= start_config_chain_sr(0) & start_config_chain; 167 if ( start_config_chain_sr = "01") then168 start_config_chain_flag <= '1';169 config_ chain_done <= '0';161 162 if (config_start = '1') then 163 config_start_sig <= '1'; 164 config_done <= '0'; 170 165 end if; 171 166 trigger_sr <= trigger_sr(0) & trigger; --synching in of asynchrounous trigger signal. … … 174 169 case state_generate is 175 170 176 when CONFIG_CHAIN_START => -- CONFIG_CONTROL_MANAGER 177 config_start_cm <= '1'; 178 if (config_started_cm = '1') then 179 config_start_cm <= '0'; 180 state_generate <= CONFIG_MEMORY_MANAGER; 181 end if; 182 when CONFIG_MEMORY_MANAGER => -- CONFIG_MEMORY_MANAGER 183 if (config_ready_cm = '1') then 184 config_start_mm <= '1'; 185 end if; 186 if (config_started_mm = '1') then 187 config_start_mm <= '0'; 188 state_generate <= CONFIG_SPI_INTERFACE; 189 end if; 190 when CONFIG_SPI_INTERFACE => -- CONFIG_SPI_INTERFACE 191 if (config_ready_mm = '1') then 192 config_start_spi <= '1'; 193 end if; 194 if (config_started_spi = '1') then 195 config_start_spi <= '0'; 196 state_generate <= WAIT_FOR_CONFIG_SPI_INTERFACE; 197 end if; 198 when WAIT_FOR_CONFIG_SPI_INTERFACE => 199 if (config_ready_spi = '1') then 200 state_generate <= CONFIG_DRS_01; 201 end if; 171 172 when CONFIG => 173 internal_roi_array <= roi_array; 174 package_length_sig <= package_length; 175 internal_roi_max <= roi_max; 176 state_generate <= CONFIG_DRS_01; 202 177 -- configure DRS 203 178 -- all this might be done in the drs_pulser entity … … 223 198 end if; 224 199 225 -- last state of CONFIG CHAIN:200 -- last state of CONFIG: 226 201 -- here the input roi_max is sampled 227 202 -- all other interesting input signals should be sampled here as well! 228 when WAIT_FOR_DRS_CONFIG_READY => -- END OF CONFIG CHAIN203 when WAIT_FOR_DRS_CONFIG_READY => -- END OF CONFIG 229 204 if (drs_srin_write_ready = '1') then 230 205 drs_channel_id <= DRS_ADDR_IDLE; -- to make sure not to write accidentally into DRS shift registers 231 roi_max_int <= roi_max;232 config_ chain_done <= '1';206 roi_max_int <= internal_roi_max; 207 config_done <= '1'; 233 208 state_generate <= IDLE; 234 209 end if; 235 210 -- end configure DRS 211 236 212 237 213 when IDLE => 238 if (mode = '0') then -- do not accept any triggers ! stay in idle, or do a configuration. 239 sig_idling <= '1'; 240 if (start_config_chain_flag = '1') then 241 sig_idling <= '0'; 242 start_config_chain_flag <= '0'; 243 state_generate <= CONFIG_CHAIN_START; 244 else 245 state_generate <= IDLE; 246 end if; 247 else --mode = '1' -- check if trigger arrived. 248 sig_idling<= '0'; 249 if (ram_write_ea = '1' and trigger_sr = "01") then 250 sig_drs_readout_started <= '1'; -- is set to '0' in next state ... just a pulse. 251 start_read_drs_stop_cell <= '1'; 252 adc_output_enable_inverted <= '0'; 253 -- at this moment the ADC ist beeing clocked. 254 -- this is not the start of the readout. 255 -- the DRS needs to be clocked as well. 256 adc_clk_en <= '1'; 257 start_addr <= ram_start_addr; 258 state_generate <= WRITE_HEADER; 259 end if; 260 end if; 214 state_generate <= IDLE; 215 216 if (config_start_sig = '1') then 217 config_start_sig <= '0'; 218 state_generate <= CONFIG; 219 end if; 220 221 if (ram_write_ea = '1' and trigger_sr = "01") then 222 sig_drs_readout_started <= '1'; -- is set to '0' in next state ... just a pulse. 223 start_read_drs_stop_cell <= '1'; 224 adc_output_enable_inverted <= '0'; 225 -- at this moment the ADC ist beeing clocked. 226 -- this is not the start of the readout. 227 -- the DRS needs to be clocked as well. 228 adc_clk_en <= '1'; 229 start_addr <= ram_start_addr; 230 state_generate <= WRITE_HEADER; 231 end if; 232 261 233 262 234 when WRITE_HEADER => 263 235 sig_drs_readout_started <= '0'; -- is set to '1' in state IDLE 264 236 dataRAM_write_ea_o <= "1"; 265 data_out <= X"000" & pll_lock & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01"; 237 data_out <= 238 -- the first word contains a lot of single status bits. 239 pll_lock & -- 4 bits 240 denable_enable_in & -- 1 bit 241 dwrite_enable_in & -- 1 bit 242 refclk_too_high & -- 1 bit 243 refclk_too_low & -- 1 bit 244 DCM_locked_status & -- 1 bit 245 DCM_ready_status & -- 1 bit 246 SPI_SCLK_enable_status &-- 1 bit 247 conv_std_logic_vector(0,5) & 248 PACKAGE_VERSION & PACKAGE_SUB_VERSION & 249 package_length_sig & 250 X"FB01"; 266 251 addr_cntr <= addr_cntr + 1; 267 252 state_generate <= WRITE_FTM_INFO; … … 275 260 276 261 when WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER => 277 data_out <= X"0000" & 278 refclk_too_high & refclk_too_low & "00" & refclk_counter & 262 data_out <= 263 "0000" & refclk_counter & 264 X"0000" & 279 265 fad_event_counter(15 downto 0) & 280 266 fad_event_counter(31 downto 16) ; … … 285 271 data_out <= TRG_GEN_div & -- this is a kind of prescaler for the continouus trigger generator 286 272 X"0000" & -- this might be the number of soft triggers beeing generated in a 'burst' not implemented yet 287 X"00" & DCM_PS_status & "000000" &-- number of steps, the phase shifter was shifted...288 crate_id & "1000" & board_id; -- position of the board inside the camera273 X"00" & DCM_PS_status & -- number of steps, the phase shifter was shifted... 274 "000000" & crate_id & "0000" & board_id; -- position of the board inside the camera 289 275 addr_cntr <= addr_cntr + 1; 290 276 state_generate <= WRITE_DNA; 291 277 292 278 when WRITE_DNA => 293 data_out <= X"00" & dna(55 downto 0); 279 data_out <= 280 dna(55 downto 48) & dna(63 downto 56) & 281 dna(39 downto 32) & dna(47 downto 40) & 282 dna(23 downto 16) & dna(31 downto 24) & 283 dna(7 downto 0) & dna(15 downto 8); 294 284 addr_cntr <= addr_cntr + 1; 295 285 state_generate <= WRITE_TIMER; 296 286 297 287 when WRITE_TIMER => 298 data_out <= X"0000" & X"0000" & timer_value; -- 2times 16bit reserved for additional status info 288 data_out <= 289 X"0000" & -- 2times 16bit reserved for additional status info 290 X"0000" & 291 timer_value(15 downto 0) & 292 timer_value(31 downto 16); 299 293 addr_cntr <= addr_cntr + 1; 300 294 state_generate <= WRITE_TEMPERATURES; … … 370 364 371 365 when WRITE_ROI => -- write ROI 372 data_out <= "00000" & conv_std_logic_vector ( roi_array((3) * 9 + channel_id), 11) &373 "00000" & conv_std_logic_vector ( roi_array((2) * 9 + channel_id), 11) &374 "00000" & conv_std_logic_vector ( roi_array((1) * 9 + channel_id), 11) &375 "00000" & conv_std_logic_vector ( roi_array((0) * 9 + channel_id), 11);366 data_out <= "00000" & conv_std_logic_vector (internal_roi_array((3) * 9 + channel_id), 11) & 367 "00000" & conv_std_logic_vector (internal_roi_array((2) * 9 + channel_id), 11) & 368 "00000" & conv_std_logic_vector (internal_roi_array((1) * 9 + channel_id), 11) & 369 "00000" & conv_std_logic_vector (internal_roi_array((0) * 9 + channel_id), 11); 376 370 addr_cntr <= addr_cntr + 1; 377 371 state_generate <= WRITE_FILLING; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/dna_gen.vhd
r10170 r10225 66 66 begin 67 67 if Falling_edge(clk) then 68 if (start_sig = '0') then 69 68 if (start_sig = '0') then -- do it only once. 69 start_sig <= '1'; 70 70 end if; 71 71 case FTU_dna_gen_State is -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10180 r10225 2 2 -- 3 3 -- Created: 4 -- by - d neise.UNKNOWN (E5B-LABOR6)5 -- at - 16:24:40 25.02.20116 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 08:30:59 04.03.2011 6 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 8 8 -- 9 9 LIBRARY ieee; … … 75 75 -- 76 76 -- Created: 77 -- by - d neise.UNKNOWN (E5B-LABOR6)78 -- at - 16:24:40 25.02.201179 -- 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)77 -- by - daqct3.UNKNOWN (IHP110) 78 -- at - 08:30:59 04.03.2011 79 -- 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 81 81 -- 82 82 LIBRARY ieee; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
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r10176 r10225 9 9 use IEEE.STD_LOGIC_ARITH.ALL; 10 10 use IEEE.STD_LOGIC_UNSIGNED.ALL; 11 use std.textio.all; 12 use work.txt_util.all; 11 13 -- use IEEE.NUMERIC_STD.ALL; 12 14 … … 51 53 constant CAM_MAC_prefix : mac_type := (X"FAC7", X"0FAD", X"0000"); 52 54 -- Network Settings End 53 55 --constant SUBVERSION_LONGSTRING : string := "$Rev$:: $"; 56 --constant SUBVERSION_STRING : string := SUBVERSION_LONGSTRING(7 to 25); -- cut off starting "$Rev$:: " and trailing "$" 57 --constant SUBVERSION_NUMBER : std_logic_vector (15 downto 0) := conv_std_logic_vector(str_to_int(SUBVERSION_STRING),16); 54 58 constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01"; 55 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"0 2";59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"03"; 56 60 constant PACKAGE_HEADER_LENGTH : integer := 36; 57 61 constant PACKAGE_HEADER_ZEROS : integer := 0; … … 60 64 constant CHANNEL_HEADER_SIZE : integer := 4; 61 65 constant NUMBER_OF_DRS : integer := 4; 66 constant POSITION_OF_ROI_IN_CHANNEL_HEADER : integer := 3; 62 67 63 68 constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset … … 122 127 -- 12, 181, 100, 102, 101, 102, 0, 101, 108); 123 128 -- constant DEFAULT_ROI : roi_array_type := (others => 100); 124 constant DEFAULT_ROI : roi_array_type := (others => 210);129 constant DEFAULT_ROI : roi_array_type := (others => 1024); 125 130 126 131 constant DEFAULT_DAC : dac_array_type := (20972, 34079, 20526, 0, 28836, 28836, 28836, 28836); … … 133 138 constant BADDR_ROI : std_logic_vector := X"00"; -- Baseaddress ROI-Values 134 139 constant BADDR_DAC : std_logic_vector := X"24"; -- Baseaddress DAC-Values 140 141 135 142 136 143 -- Commands … … 152 159 constant CMD_TRIGGERS_OFF : std_logic_vector := X"19"; 153 160 constant CMD_TRIGGER_S : std_logic_vector := X"20"; 154 constant CMD_SET_TRIGGER_MULT : std_logic_vector := X"21"; 161 155 162 constant CMD_START : std_logic_vector := X"22"; -- set data generator in RUN-mnode 156 163 constant CMD_STOP : std_logic_vector := X"23"; -- set data generator in STOP-mode 157 constant CMC_MODE_COMMAND : std_logic_vector := X"30"; 164 constant CMD_MODE_COMMAND : std_logic_vector := X"30"; 165 constant CMD_MODE_ALL_SOCKETS : std_logic_vector := X"31"; 158 166 constant CMD_TRIGGER : std_logic_vector := X"A0"; 159 167 constant CMD_TRIGGER_C : std_logic_vector := X"B0"; 160 constant CMD_MODE_ALL_SOCKETS : std_logic_vector := X"C0"; 168 161 169 162 170 -- DRS Registers -
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10180 r10225 2 2 -- 3 3 -- Created: 4 -- by - d neise.UNKNOWN (E5B-LABOR6)5 -- at - 16:10:13 25.02.20114 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 08:30:56 04.03.2011 6 6 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 8 8 -- 9 9 LIBRARY ieee; … … 70 70 -- 71 71 -- Created: 72 -- by - d neise.UNKNOWN (E5B-LABOR6)73 -- at - 16:10:14 25.02.201172 -- by - daqct3.UNKNOWN (IHP110) 73 -- at - 08:30:58 04.03.2011 74 74 -- 75 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)75 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 76 76 -- 77 77 library ieee; … … 87 87 USE IEEE.NUMERIC_STD.all; 88 88 USE IEEE.std_logic_signed.all; 89 USE UNISIM.VComponents.all;90 89 91 90 LIBRARY FACT_FAD_lib; … … 96 95 97 96 -- Internal signal declarations 98 SIGNAL CLK_25 : std_logic; 99 SIGNAL DCM_PS_status : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 97 SIGNAL CLK_25 : std_logic; 98 SIGNAL DCM_PS_status : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 99 SIGNAL DCM_locked_status : std_logic; 100 SIGNAL DCM_ready_status : std_logic; 100 101 -- 101 102 … … 103 104 -- during EVT header wrinting, this field is left out ... and only written into event header, 104 105 -- when the DRS chip were read out already. 105 SIGNAL FTM_RS485_ready : std_logic; 106 SIGNAL SRCLK1 : std_logic := '0'; 107 SIGNAL adc_clk_en : std_logic; 108 SIGNAL adc_data_array_int : adc_data_array_type; 109 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); 110 SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); 111 SIGNAL c_trigger_enable : std_logic := '0'; 112 SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0); 113 SIGNAL config_addr : std_logic_vector(7 DOWNTO 0); 114 SIGNAL config_busy : std_logic; 115 SIGNAL config_data : std_logic_vector(15 DOWNTO 0); 116 SIGNAL config_data_valid : std_logic; 117 SIGNAL config_rd_en : std_logic; 118 SIGNAL config_ready : std_logic; 119 SIGNAL config_ready_cm : std_logic; 120 SIGNAL config_ready_spi : std_logic; 121 -- -- 122 SIGNAL config_rw_ack : std_logic := '0'; 123 -- -- 124 SIGNAL config_rw_ready : std_logic := '0'; 125 SIGNAL config_start : std_logic := '0'; 126 SIGNAL config_start_cm : std_logic; 127 SIGNAL config_start_spi : std_logic := '0'; 128 SIGNAL config_started : std_logic; 129 SIGNAL config_started_cu : std_logic := '0'; 130 SIGNAL config_started_mm : std_logic; 131 SIGNAL config_started_spi : std_logic := '0'; 132 SIGNAL config_wr_en : std_logic; 133 SIGNAL crc : std_logic_vector(7 DOWNTO 0); 134 SIGNAL dac_array : dac_array_type; 135 SIGNAL data_generator_run_mode : std_logic := '0'; -- default triggers are NOT accepted 136 SIGNAL data_out : std_logic_vector(63 DOWNTO 0); 137 SIGNAL data_ram_empty : std_logic; 138 SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off 139 SIGNAL denable_prim : std_logic := '0'; -- default domino wave off 140 SIGNAL din1 : std_logic := '0'; -- default domino wave off 141 SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0'); 142 SIGNAL dout : std_logic; 143 SIGNAL dout1 : std_logic; 144 SIGNAL drs_clk_en : std_logic := '0'; 145 SIGNAL drs_read_s_cell : std_logic := '0'; 146 SIGNAL drs_read_s_cell_ready : std_logic; 106 SIGNAL FTM_RS485_ready : std_logic; 107 SIGNAL I_really_want_dwrite : STD_LOGIC; 108 SIGNAL SRCLK1 : std_logic := '0'; 109 SIGNAL adc_clk_en : std_logic; 110 SIGNAL adc_data_array_int : adc_data_array_type; 111 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); 112 SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); 113 SIGNAL c_trigger_enable : std_logic := '0'; 114 SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0); 115 SIGNAL cont_trigger : std_logic; 116 SIGNAL crc : std_logic_vector(7 DOWNTO 0); 117 SIGNAL current_dac_array : dac_array_type := ( others => 0); 118 SIGNAL dac_setting : dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd 119 SIGNAL data_generator_config_start : std_logic := '0'; 120 SIGNAL data_generator_config_valid : std_logic; 121 SIGNAL data_out : std_logic_vector(63 DOWNTO 0); 122 SIGNAL data_ram_empty : std_logic; 123 SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off 124 SIGNAL denable_prim : std_logic := '0'; -- default domino wave off 125 SIGNAL denable_sig : std_logic := '0'; -- default domino wave off 126 SIGNAL din1 : std_logic := '0'; -- default domino wave off 127 SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0'); 128 SIGNAL dout : STD_LOGIC; 129 SIGNAL dout0 : STD_LOGIC; 130 SIGNAL dout1 : STD_LOGIC; 131 SIGNAL dout2 : STD_LOGIC; 132 SIGNAL dout3 : STD_LOGIC; 133 SIGNAL dout4 : STD_LOGIC; 134 SIGNAL drs_clk_en : std_logic := '0'; 135 SIGNAL drs_read_s_cell : std_logic := '0'; 136 SIGNAL drs_read_s_cell_ready : std_logic; 147 137 -- -- 148 138 -- drs_dwrite : out std_logic := '1'; 149 SIGNAL drs_readout_ready : std_logic := '0'; 150 SIGNAL drs_readout_ready_ack : std_logic; 151 SIGNAL drs_readout_started : std_logic; 152 SIGNAL drs_s_cell_array : drs_s_cell_array_type; 153 SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0'); 154 SIGNAL dwrite : std_logic := '1'; 155 SIGNAL dwrite_enable : std_logic := '1'; 156 SIGNAL enable_i : std_logic; 157 SIGNAL new_config : std_logic := '0'; 158 SIGNAL package_length : std_logic_vector(15 DOWNTO 0); 159 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards 160 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once 161 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift 162 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); 163 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); 164 SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); 165 SIGNAL ram_write_ea : std_logic; 166 SIGNAL ram_write_ready : std_logic := '0'; 139 SIGNAL drs_readout_ready : std_logic := '0'; 140 SIGNAL drs_readout_ready_ack : std_logic; 141 SIGNAL drs_readout_started : std_logic; 142 SIGNAL drs_s_cell_array : drs_s_cell_array_type; 143 SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0'); 144 SIGNAL dwrite_enable_w5300 : std_logic := '1'; 145 SIGNAL dwrite_global_enable : std_logic := '1'; 146 SIGNAL dwrite_trigger_manager : std_logic := '1'; 147 SIGNAL enable_i : std_logic; 148 SIGNAL enabled_trigger_or_s_trigger : std_logic; 149 SIGNAL memory_manager_config_start : std_logic := '0'; 150 SIGNAL memory_manager_config_valid : std_logic; 151 SIGNAL package_length : std_logic_vector(15 DOWNTO 0); 152 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards 153 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once 154 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift 155 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); 156 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); 157 SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); 158 SIGNAL ram_write_ea : std_logic; 159 SIGNAL ram_write_ready : std_logic := '0'; 167 160 -- -- 168 SIGNAL ram_write_ready_ack : std_logic := '0'; 169 SIGNAL ready : STD_LOGIC := '0'; 170 SIGNAL reset_synch_i : std_logic; 171 SIGNAL roi_array : roi_array_type; 172 SIGNAL roi_max : roi_max_type; 173 SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte 174 SIGNAL s_trigger : std_logic; 175 SIGNAL s_trigger_0 : std_logic; 176 SIGNAL sclk1 : std_logic; 177 SIGNAL sclk_enable : std_logic; 178 SIGNAL sensor_array : sensor_array_type; 179 SIGNAL sensor_ready : std_logic; 180 SIGNAL socks_connected : std_logic; 181 SIGNAL socks_waiting : std_logic; 182 SIGNAL srclk_enable : std_logic := '0'; 183 SIGNAL srin_write_ack : std_logic := '0'; 184 SIGNAL srin_write_ready : std_logic := '0'; 185 SIGNAL start_srin_write_8b : std_logic; 186 SIGNAL time : std_logic_vector(31 DOWNTO 0); 187 SIGNAL trigger1 : std_logic; 188 SIGNAL trigger_enable : std_logic; 189 SIGNAL trigger_id : std_logic_vector(31 DOWNTO 0); 190 SIGNAL trigger_out : std_logic; 191 SIGNAL trigger_type1 : std_logic_vector(7 DOWNTO 0); 192 SIGNAL trigger_type2 : std_logic_vector(7 DOWNTO 0); 193 SIGNAL wiz_ack : std_logic; 194 SIGNAL wiz_busy : std_logic; 195 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); 196 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); 197 SIGNAL wiz_write_ea : std_logic := '0'; 198 SIGNAL wiz_write_end : std_logic := '0'; 199 SIGNAL wiz_write_header : std_logic := '0'; 200 SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0'); 201 SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0"; 161 SIGNAL ram_write_ready_ack : std_logic := '0'; 162 SIGNAL ready : STD_LOGIC := '0'; 163 SIGNAL reset : std_logic; 164 SIGNAL reset_synch_i : std_logic; 165 SIGNAL roi_max : roi_max_type; 166 SIGNAL roi_setting : roi_array_type; 167 SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte 168 SIGNAL s_trigger : std_logic; 169 SIGNAL s_trigger_or_cont_trigger : std_logic; 170 SIGNAL sclk_enable : std_logic; 171 SIGNAL sensor_array : sensor_array_type; 172 SIGNAL sensor_ready : std_logic; 173 SIGNAL socks_connected : std_logic; 174 SIGNAL socks_waiting : std_logic; 175 SIGNAL spi_interface_config_start : std_logic := '0'; 176 SIGNAL spi_interface_config_valid : std_logic; 177 SIGNAL srclk_enable : std_logic := '0'; 178 SIGNAL srin_write_ack : std_logic := '0'; 179 SIGNAL srin_write_ready : std_logic := '0'; 180 SIGNAL start_srin_write_8b : std_logic; 181 SIGNAL time : std_logic_vector(31 DOWNTO 0); 182 SIGNAL trigger_enable : std_logic; 183 SIGNAL trigger_id : std_logic_vector(31 DOWNTO 0); 184 SIGNAL trigger_or_s_trigger : std_logic; 185 SIGNAL trigger_out : std_logic; 186 SIGNAL trigger_type1 : std_logic_vector(7 DOWNTO 0); 187 SIGNAL trigger_type2 : std_logic_vector(7 DOWNTO 0); 188 SIGNAL wiz_ack : std_logic; 189 SIGNAL wiz_busy : std_logic; 190 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); 191 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); 192 SIGNAL wiz_write_ea : std_logic := '0'; 193 SIGNAL wiz_write_end : std_logic := '0'; 194 SIGNAL wiz_write_header : std_logic := '0'; 195 SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0'); 196 SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0"; 202 197 203 198 -- Implicit buffer signal declarations … … 209 204 210 205 206 -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'split' 207 SIGNAL mw_U_0temp_din : std_logic_vector(3 DOWNTO 0); 208 211 209 -- Component Declarations 212 210 COMPONENT REFCLK_counter … … 240 238 COMPONENT clock_generator_var_ps 241 239 PORT ( 242 CLK : IN std_logic ; 243 RST_IN : IN std_logic ; 244 direction : IN std_logic ; 245 do_shift : IN std_logic ; 246 CLK_25 : OUT std_logic ; 247 CLK_25_PS : OUT std_logic ; 248 CLK_50 : OUT std_logic ; 249 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') 240 CLK : IN std_logic ; 241 RST_IN : IN std_logic ; 242 direction : IN std_logic ; 243 do_shift : IN std_logic ; 244 CLK_25 : OUT std_logic ; 245 CLK_25_PS : OUT std_logic ; 246 CLK_50 : OUT std_logic ; 247 locked_status_o : OUT std_logic ; 248 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 249 ready_status_o : OUT std_logic 250 250 ); 251 251 END COMPONENT; … … 260 260 multiplier : IN std_logic_vector (15 DOWNTO 0); 261 261 trigger : OUT std_logic 262 );263 END COMPONENT;264 COMPONENT control_unit265 PORT (266 clk : IN STD_LOGIC ;267 config_addr : IN std_logic_vector (7 DOWNTO 0);268 config_rd_en : IN std_logic ;269 config_start : IN std_logic ;270 config_wr_en : IN std_logic ;271 config_busy : OUT std_logic ;272 config_data_valid : OUT std_logic ;273 config_ready : OUT std_logic ;274 -- --275 config_rw_ack : OUT std_logic := '0';276 -- --277 config_rw_ready : OUT std_logic := '0';278 config_started : OUT std_logic := '0';279 dac_array : OUT dac_array_type ;280 roi_array : OUT roi_array_type ;281 config_data : INOUT std_logic_vector (15 DOWNTO 0)282 262 ); 283 263 END COMPONENT; … … 306 286 ram_write_ready : OUT std_logic := '0'; 307 287 ram_write_ready_ack : IN std_logic ; 308 config_start_mm : OUT std_logic := '0';309 config_start_cm : OUT std_logic := '0';310 config_start_spi : OUT std_logic := '0';311 config_ready_mm : IN std_logic ;312 config_ready_cm : IN std_logic ;313 config_ready_spi : IN std_logic ;314 config_started_mm : IN std_logic ;315 config_started_cm : IN std_logic ;316 config_started_spi : IN std_logic ;317 288 roi_array : IN roi_array_type ; 318 289 roi_max : IN roi_max_type ; … … 320 291 sensor_ready : IN std_logic ; 321 292 dac_array : IN dac_array_type ; 322 mode : IN std_logic ; -- 0: config mode | 1: run mode323 idling : OUT std_logic;293 config_start : IN std_logic ; 294 config_done : OUT std_logic := '0'; 324 295 -- EVT HEADER - part 1 325 296 package_length : IN std_logic_vector (15 DOWNTO 0); 326 297 pll_lock : IN std_logic_vector ( 3 DOWNTO 0); 298 dwrite_enable_in : IN std_logic ; 299 denable_enable_in : IN std_logic ; 327 300 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... 328 301 -- during EVT header wrinting, this field is left out ... and only written into event header, … … 339 312 crate_id : IN std_logic_vector (1 DOWNTO 0); 340 313 DCM_PS_status : IN std_logic_vector (7 DOWNTO 0); 314 DCM_locked_status : IN std_logic ; 315 DCM_ready_status : IN std_logic ; 316 SPI_SCLK_enable_status : IN std_logic ; 341 317 TRG_GEN_div : IN std_logic_vector (15 DOWNTO 0); 342 318 -- EVT HEADER - part 5 … … 345 321 timer_value : IN std_logic_vector (31 DOWNTO 0); -- time in units of 100us 346 322 trigger : IN std_logic ; 347 start_config_chain : IN std_logic ; -- here W5300_MODUL can start the whole config chain348 config_chain_done : OUT std_logic ;349 323 adc_data_array : IN adc_data_array_type ; 350 324 adc_output_enable_inverted : OUT std_logic := '1'; … … 368 342 COMPONENT dna_gen 369 343 PORT ( 370 clk : IN STD_LOGIC 344 clk : IN STD_LOGIC; 371 345 dna : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) := (others => '0'); 372 346 ready : OUT STD_LOGIC := '0' … … 396 370 GENERIC ( 397 371 HEARTBEAT_PWM_DIVIDER : integer := 500; 398 MAX_DELAY : integer := 100; --not used anymore at all :-(399 372 WAITING_DIVIDER : integer := 500000000 400 373 ); 401 374 PORT ( 402 375 CLK : IN std_logic; 376 refclk_too_high : IN std_logic; 377 refclk_too_low : IN std_logic; 403 378 socks_connected : IN std_logic; 404 379 socks_waiting : IN std_logic; … … 424 399 roi_array : IN roi_array_type ; 425 400 ram_write_ea : OUT std_logic := '0'; 426 config_ready : OUT std_logic := '0'; 427 config_started : OUT std_logic := '0'; 401 config_ready : OUT std_logic := '1'; 428 402 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); 429 403 package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); … … 442 416 COMPONENT spi_interface 443 417 PORT ( 444 clk_50MHz : IN std_logic ; 445 config_start : IN std_logic ; 446 dac_array : IN dac_array_type ; 447 config_ready : OUT std_logic ; 448 config_started : OUT std_logic := '0'; 449 dac_cs : OUT std_logic ; 450 mosi : OUT std_logic := '0'; 451 sclk : OUT std_logic ; 452 sensor_array : OUT sensor_array_type ; 453 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 454 sensor_ready : OUT std_logic ; 455 miso : INOUT std_logic 418 clk_50MHz : IN std_logic ; 419 config_start : IN std_logic ; 420 dac_array : IN dac_array_type ; 421 sclk_enable_i : IN std_logic ; 422 config_ready : OUT std_logic ; 423 current_dac_array : OUT dac_array_type := ( others => 0); 424 dac_cs : OUT std_logic ; 425 mosi : OUT std_logic := '0'; 426 sclk : OUT std_logic ; 427 sensor_array : OUT sensor_array_type ; 428 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 429 sensor_ready : OUT std_logic ; 430 miso : INOUT std_logic 456 431 ); 457 432 END COMPONENT; … … 474 449 trigger_id : OUT std_logic_vector (31 DOWNTO 0); 475 450 trigger : IN std_logic ; 451 reset : IN std_logic ; 476 452 clk : IN std_logic 477 453 ); … … 492 468 ); 493 469 PORT ( 494 clk : IN std_logic ;495 wiz_reset : OUT std_logic := '1';496 addr : OUT std_logic_vector (9 DOWNTO 0);497 data : INOUT std_logic_vector (15 DOWNTO 0);498 cs : OUT std_logic := '1';499 wr : OUT std_logic := '1';500 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');501 rd : OUT std_logic := '1';502 int : IN std_logic ;503 write_length : IN std_logic_vector (16 DOWNTO 0);504 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);505 ram_data : IN std_logic_vector (15 DOWNTO 0);506 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);507 data_valid : IN std_logic ;508 data_valid_ack : OUT std_logic := '0';509 busy : OUT std_logic := '1';510 write_header_flag : IN std_logic ;511 write_end_flag : IN std_logic ;512 fifo_channels : IN std_logic_vector (3 DOWNTO 0);470 clk : IN std_logic ; 471 wiz_reset : OUT std_logic := '1'; 472 addr : OUT std_logic_vector (9 DOWNTO 0); 473 data : INOUT std_logic_vector (15 DOWNTO 0); 474 cs : OUT std_logic := '1'; 475 wr : OUT std_logic := '1'; 476 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 477 rd : OUT std_logic := '1'; 478 int : IN std_logic ; 479 write_length : IN std_logic_vector (16 DOWNTO 0); 480 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 481 ram_data : IN std_logic_vector (15 DOWNTO 0); 482 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 483 data_valid : IN std_logic ; 484 data_valid_ack : OUT std_logic := '0'; 485 busy : OUT std_logic := '1'; 486 write_header_flag : IN std_logic ; 487 write_end_flag : IN std_logic ; 488 fifo_channels : IN std_logic_vector (3 DOWNTO 0); 513 489 -- softtrigger: 514 s_trigger : OUT std_logic := '0';515 c_trigger_enable : OUT std_logic := '0';516 c_trigger_mult : OUT std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(0 ,16); --subject TO changes490 s_trigger : OUT std_logic := '0'; 491 c_trigger_enable : OUT std_logic := '0'; 492 c_trigger_mult : OUT std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(0 ,16); --subject TO changes 517 493 -- FAD configuration signals: 518 494 ------------------------------------------------------------------------------ 519 -- start entire configuration chain 520 new_config : OUT std_logic := '0'; 521 config_chain_done : IN std_logic ; 522 data_generator_run_mode : OUT std_logic ; -- default triggers will be accepted 523 data_ram_empty : IN std_logic ; 524 -- read/write configRAM 525 config_addr : OUT std_logic_vector (7 DOWNTO 0); 526 config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 527 config_wr_en : OUT std_logic := '0'; 528 config_rd_en : OUT std_logic := '0'; 529 config_rw_ack : IN std_logic ; 530 config_rw_ready : IN std_logic ; 531 config_busy : IN std_logic ; 495 memory_manager_config_start_o : OUT std_logic := '0'; 496 memory_manager_config_valid_i : IN std_logic ; 497 spi_interface_config_start_o : OUT std_logic := '0'; 498 spi_interface_config_valid_i : IN std_logic ; 499 data_generator_config_start_o : OUT std_logic := '0'; 500 data_generator_config_valid_i : IN std_logic ; 501 dac_setting : OUT dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd 502 roi_setting : OUT roi_array_type := DEFAULT_ROI; --<<-- default defined in fad_definitions.vhd 503 data_ram_empty : IN std_logic ; 532 504 ------------------------------------------------------------------------------ 533 505 534 506 -- MAC/IP calculation signals: 535 507 ------------------------------------------------------------------------------ 536 MAC_jumper : IN std_logic_vector (1 DOWNTO 0);537 BoardID : IN std_logic_vector (3 DOWNTO 0);538 CrateID : IN std_logic_vector (1 DOWNTO 0);508 MAC_jumper : IN std_logic_vector (1 DOWNTO 0); 509 BoardID : IN std_logic_vector (3 DOWNTO 0); 510 CrateID : IN std_logic_vector (1 DOWNTO 0); 539 511 ------------------------------------------------------------------------------ 540 512 541 513 -- user controllable enable signals 542 514 ------------------------------------------------------------------------------ 543 trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted544 denable : OUT std_logic := '0'; -- default domino wave off545 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low.546 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH.547 srclk_enable : OUT std_logic := '1'; -- default SRCLK on.515 trigger_enable : OUT std_logic ; 516 denable : OUT std_logic := '0'; -- default domino wave on. ... in case if REFCLK error ... REFCLK counter will override. 517 dwrite_enable : OUT std_logic := '1'; -- default DWRITE low. 518 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. 519 srclk_enable : OUT std_logic := '1'; -- default SRCLK on. 548 520 ------------------------------------------------------------------------------ 549 521 … … 551 523 -- these signals control the behavior of the digital clock manager (DCM) 552 524 ------------------------------------------------------------------------------ 553 ps_direction : OUT std_logic := '1'; -- default phase shift upwards 554 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once 555 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift 525 ps_direction : OUT std_logic := '1'; -- default phase shift upwards 526 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once 527 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift 528 ps_ready : IN std_logic ; 556 529 ------------------------------------------------------------------------------ 557 530 … … 559 532 -- one of the three LEDs is used for com-status info 560 533 ------------------------------------------------------------------------------ 561 socks_waiting : OUT std_logic ;562 socks_connected : OUT std_logic534 socks_waiting : OUT std_logic ; 535 socks_connected : OUT std_logic 563 536 ------------------------------------------------------------------------------ 564 537 ); … … 572 545 FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps; 573 546 FOR ALL : continous_pulser USE ENTITY FACT_FAD_lib.continous_pulser; 574 FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit;575 547 FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5; 576 548 FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator; … … 598 570 SRCLK <= SRCLK1 AND srclk_enable; 599 571 572 -- ModuleWare code(v1.9) for instance 'U_1' of 'and' 573 dout <= dout0 AND dout1 AND dout2 AND dout3; 574 575 -- ModuleWare code(v1.9) for instance 'U_4' of 'and' 576 dwrite_global_enable <= dwrite_enable_w5300 AND dout4; 577 600 578 -- ModuleWare code(v1.9) for instance 'and_1' of 'and' 601 579 ADC_CLK <= adc_clk_en AND CLK_25_PS_internal; 602 580 603 581 -- ModuleWare code(v1.9) for instance 'and_2' of 'and' 604 denable <= denable_prim AND din1; 605 606 -- ModuleWare code(v1.9) for instance 'and_3' of 'and' 607 sclk <= sclk_enable AND sclk1; 582 denable_sig <= denable_prim AND din1; 608 583 609 584 -- ModuleWare code(v1.9) for instance 'and_4' of 'and' 610 dout1 <= dout AND trigger_enable; 585 enabled_trigger_or_s_trigger <= trigger_or_s_trigger 586 AND trigger_enable; 611 587 612 588 -- ModuleWare code(v1.9) for instance 'and_5' of 'and' 613 drs_dwrite <= dwrite AND dwrite_enable; 589 drs_dwrite <= dwrite_trigger_manager AND dwrite_global_enable; 590 591 -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment' 592 denable <= denable_sig; 593 594 -- ModuleWare code(v1.9) for instance 'U_6' of 'gnd' 595 reset <= '0'; 614 596 615 597 -- ModuleWare code(v1.9) for instance 'U_15' of 'gnd' … … 619 601 din1 <= NOT(denable_inhibit); 620 602 603 -- ModuleWare code(v1.9) for instance 'U_2' of 'or' 604 dout4 <= dout OR I_really_want_dwrite; 605 621 606 -- ModuleWare code(v1.9) for instance 'or_1' of 'or' 622 s_trigger <= s_trigger_0 OR trigger1;607 s_trigger_or_cont_trigger <= s_trigger OR cont_trigger; 623 608 624 609 -- ModuleWare code(v1.9) for instance 'or_2' of 'or' … … 627 612 628 613 -- ModuleWare code(v1.9) for instance 'or_5' of 'or' 629 dout <= s_trigger OR trigger; 614 trigger_or_s_trigger <= s_trigger_or_cont_trigger OR trigger; 615 616 -- ModuleWare code(v1.9) for instance 'U_0' of 'split' 617 mw_U_0temp_din <= plllock_in; 618 u_0combo_proc: PROCESS (mw_U_0temp_din) 619 VARIABLE temp_din: std_logic_vector(3 DOWNTO 0); 620 BEGIN 621 temp_din := mw_U_0temp_din(3 DOWNTO 0); 622 dout0 <= temp_din(0); 623 dout1 <= temp_din(1); 624 dout2 <= temp_din(2); 625 dout3 <= temp_din(3); 626 END PROCESS u_0combo_proc; 627 628 -- ModuleWare code(v1.9) for instance 'U_3' of 'vdd' 629 I_really_want_dwrite <= '1'; 630 630 631 631 -- ModuleWare code(v1.9) for instance 'U_14' of 'vdd' … … 660 660 clock_generator_instance : clock_generator_var_ps 661 661 PORT MAP ( 662 CLK => CLK, 663 RST_IN => ps_reset, 664 direction => ps_direction, 665 do_shift => ps_do_phase_shift, 666 CLK_25 => CLK_25, 667 CLK_25_PS => CLK_25_PS_internal, 668 CLK_50 => CLK_50_internal, 669 offset => DCM_PS_status 662 CLK => CLK, 663 RST_IN => ps_reset, 664 direction => ps_direction, 665 do_shift => ps_do_phase_shift, 666 CLK_25 => CLK_25, 667 CLK_25_PS => CLK_25_PS_internal, 668 CLK_50 => CLK_50_internal, 669 locked_status_o => DCM_locked_status, 670 offset => DCM_PS_status, 671 ready_status_o => DCM_ready_status 670 672 ); 671 673 continous_pulser_instance : continous_pulser … … 678 680 enable => c_trigger_enable, 679 681 multiplier => c_trigger_mult, 680 trigger => trigger1 681 ); 682 I_main_control_unit : control_unit 683 PORT MAP ( 684 clk => CLK_50_internal, 685 config_addr => config_addr, 686 config_rd_en => config_rd_en, 687 config_start => config_start_cm, 688 config_wr_en => config_wr_en, 689 config_busy => config_busy, 690 config_data_valid => config_data_valid, 691 config_ready => config_ready_cm, 692 config_rw_ack => config_rw_ack, 693 config_rw_ready => config_rw_ready, 694 config_started => config_started_cu, 695 dac_array => dac_array, 696 roi_array => roi_array, 697 config_data => config_data 682 trigger => cont_trigger 698 683 ); 699 684 dataRAM_instance : dataRAM_64b_16b_width14_5 … … 720 705 ram_write_ready => ram_write_ready, 721 706 ram_write_ready_ack => ram_write_ready_ack, 722 config_start_mm => config_start, 723 config_start_cm => config_start_cm, 724 config_start_spi => config_start_spi, 725 config_ready_mm => config_ready, 726 config_ready_cm => config_ready_cm, 727 config_ready_spi => config_ready_spi, 728 config_started_mm => config_started_mm, 729 config_started_cm => config_started_cu, 730 config_started_spi => config_started_spi, 731 roi_array => roi_array, 707 roi_array => roi_setting, 732 708 roi_max => roi_max, 733 709 sensor_array => sensor_array, 734 710 sensor_ready => sensor_ready, 735 dac_array => dac_array,736 mode => data_generator_run_mode,737 idling => OPEN,711 dac_array => current_dac_array, 712 config_start => data_generator_config_start, 713 config_done => data_generator_config_valid, 738 714 package_length => package_length, 739 715 pll_lock => plllock_in, 716 dwrite_enable_in => dwrite_enable_w5300, 717 denable_enable_in => denable_sig, 740 718 FTM_RS485_ready => FTM_RS485_ready, 741 719 FTM_trigger_info => rs465_data, … … 747 725 crate_id => crate_id, 748 726 DCM_PS_status => DCM_PS_status, 727 DCM_locked_status => DCM_locked_status, 728 DCM_ready_status => DCM_ready_status, 729 SPI_SCLK_enable_status => sclk_enable, 749 730 TRG_GEN_div => c_trigger_mult, 750 731 dna => dna, 751 732 timer_value => time, 752 733 trigger => trigger_out, 753 start_config_chain => new_config,754 config_chain_done => config_started,755 734 adc_data_array => adc_data_array_int, 756 735 adc_output_enable_inverted => adc_oeb, … … 797 776 led_controller_instance : led_controller 798 777 GENERIC MAP ( 799 HEARTBEAT_PWM_DIVIDER => 50000, -- 10kHz @ 50 MHz 800 MAX_DELAY => 100, 801 WAITING_DIVIDER => 50000000 -- 1Hz @ 50 MHz 778 HEARTBEAT_PWM_DIVIDER => 50000, 779 WAITING_DIVIDER => 50000000 802 780 ) 803 781 PORT MAP ( … … 808 786 additional_flasher_out => OPEN, 809 787 trigger => drs_readout_started, 788 refclk_too_high => alarm_refclk_too_high_internal, 789 refclk_too_low => alarm_refclk_too_low_internal, 810 790 socks_waiting => socks_waiting, 811 791 socks_connected => socks_connected … … 818 798 PORT MAP ( 819 799 clk => CLK_25, 820 config_start => config_start,800 config_start => memory_manager_config_start, 821 801 ram_write_ready => ram_write_ready, 822 802 ram_write_ready_ack => ram_write_ready_ack, 823 roi_array => roi_ array,803 roi_array => roi_setting, 824 804 ram_write_ea => ram_write_ea, 825 config_ready => config_ready, 826 config_started => config_started_mm, 805 config_ready => memory_manager_config_valid, 827 806 roi_max => roi_max, 828 807 package_length => package_length, … … 840 819 I_main_SPI_interface : spi_interface 841 820 PORT MAP ( 842 clk_50MHz => CLK_50_internal, 843 config_start => config_start_spi, 844 dac_array => dac_array, 845 config_ready => config_ready_spi, 846 config_started => config_started_spi, 847 dac_cs => dac_cs, 848 mosi => mosi, 849 sclk => sclk1, 850 sensor_array => sensor_array, 851 sensor_cs => sensor_cs, 852 sensor_ready => sensor_ready, 853 miso => sio 821 clk_50MHz => CLK_50_internal, 822 config_start => spi_interface_config_start, 823 dac_array => dac_setting, 824 sclk_enable_i => sclk_enable, 825 config_ready => spi_interface_config_valid, 826 current_dac_array => current_dac_array, 827 dac_cs => dac_cs, 828 mosi => mosi, 829 sclk => sclk, 830 sensor_array => sensor_array, 831 sensor_cs => sensor_cs, 832 sensor_ready => sensor_ready, 833 miso => sio 854 834 ); 855 835 timer_instance : timer … … 870 850 trigger_id => trigger_id, 871 851 trigger => trigger_out, 852 reset => reset, 872 853 clk => CLK_25_PS_internal 873 854 ); … … 875 856 PORT MAP ( 876 857 clk => CLK_25, 877 trigger_in => dout1,858 trigger_in => enabled_trigger_or_s_trigger, 878 859 trigger_out => trigger_out, 879 drs_write => dwrite ,860 drs_write => dwrite_trigger_manager, 880 861 drs_readout_ready => drs_readout_ready, 881 862 drs_readout_ready_ack => drs_readout_ready_ack … … 886 867 ) 887 868 PORT MAP ( 888 clk => CLK_50_internal, 889 wiz_reset => wiz_reset, 890 addr => wiz_addr, 891 data => wiz_data, 892 cs => wiz_cs, 893 wr => wiz_wr, 894 led => led, 895 rd => wiz_rd, 896 int => wiz_int, 897 write_length => wiz_write_length, 898 ram_start_addr => wiz_ram_start_addr, 899 ram_data => ram_data, 900 ram_addr => ram_addr, 901 data_valid => wiz_write_ea, 902 data_valid_ack => wiz_ack, 903 busy => wiz_busy, 904 write_header_flag => wiz_write_header, 905 write_end_flag => wiz_write_end, 906 fifo_channels => wiz_number_of_channels, 907 s_trigger => s_trigger_0, 908 c_trigger_enable => c_trigger_enable, 909 c_trigger_mult => c_trigger_mult, 910 new_config => new_config, 911 config_chain_done => config_started, 912 data_generator_run_mode => data_generator_run_mode, 913 data_ram_empty => data_ram_empty, 914 config_addr => config_addr, 915 config_data => config_data, 916 config_wr_en => config_wr_en, 917 config_rd_en => config_rd_en, 918 config_rw_ack => config_rw_ack, 919 config_rw_ready => config_rw_ready, 920 config_busy => config_busy, 921 MAC_jumper => D_T_in, 922 BoardID => board_id, 923 CrateID => crate_id, 924 trigger_enable => trigger_enable, 925 denable => denable_prim, 926 dwrite_enable => dwrite_enable, 927 sclk_enable => sclk_enable, 928 srclk_enable => srclk_enable, 929 ps_direction => ps_direction, 930 ps_do_phase_shift => ps_do_phase_shift, 931 ps_reset => ps_reset, 932 socks_waiting => socks_waiting, 933 socks_connected => socks_connected 869 clk => CLK_50_internal, 870 wiz_reset => wiz_reset, 871 addr => wiz_addr, 872 data => wiz_data, 873 cs => wiz_cs, 874 wr => wiz_wr, 875 led => led, 876 rd => wiz_rd, 877 int => wiz_int, 878 write_length => wiz_write_length, 879 ram_start_addr => wiz_ram_start_addr, 880 ram_data => ram_data, 881 ram_addr => ram_addr, 882 data_valid => wiz_write_ea, 883 data_valid_ack => wiz_ack, 884 busy => wiz_busy, 885 write_header_flag => wiz_write_header, 886 write_end_flag => wiz_write_end, 887 fifo_channels => wiz_number_of_channels, 888 s_trigger => s_trigger, 889 c_trigger_enable => c_trigger_enable, 890 c_trigger_mult => c_trigger_mult, 891 memory_manager_config_start_o => memory_manager_config_start, 892 memory_manager_config_valid_i => memory_manager_config_valid, 893 spi_interface_config_start_o => spi_interface_config_start, 894 spi_interface_config_valid_i => spi_interface_config_valid, 895 data_generator_config_start_o => data_generator_config_start, 896 data_generator_config_valid_i => data_generator_config_valid, 897 dac_setting => dac_setting, 898 roi_setting => roi_setting, 899 data_ram_empty => data_ram_empty, 900 MAC_jumper => D_T_in, 901 BoardID => board_id, 902 CrateID => crate_id, 903 trigger_enable => trigger_enable, 904 denable => denable_prim, 905 dwrite_enable => dwrite_enable_w5300, 906 sclk_enable => sclk_enable, 907 srclk_enable => srclk_enable, 908 ps_direction => ps_direction, 909 ps_do_phase_shift => ps_do_phase_shift, 910 ps_reset => ps_reset, 911 ps_ready => DCM_ready_status, 912 socks_waiting => socks_waiting, 913 socks_connected => socks_connected 934 914 ); 935 915 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/led_controller_bahavior.vhd
r10121 r10225 22 22 GENERIC( 23 23 HEARTBEAT_PWM_DIVIDER : integer := 500; 24 MAX_DELAY : integer := 100; --not used anymore at all :-(25 24 WAITING_DIVIDER : integer := 500000000 26 25 ); … … 38 37 trigger : IN std_logic; -- when trigger is received green should toggle 39 38 39 refclk_too_high : in std_logic; 40 refclk_too_low : in std_logic; 41 40 42 socks_waiting : IN std_logic; 41 43 socks_connected: IN std_logic 42 44 45 43 46 --heartbeat_en : IN std_logic 44 47 ); … … 56 59 signal red_loc : std_logic := '0'; --default off 57 60 signal flasher : std_logic; 61 62 signal heartbeat_counter: integer range 0 to HEARTBEAT_PWM_DIVIDER - 1 := 0; 63 constant ontime_update : integer := 100; 64 signal ontime_update_counter : integer range 0 to ontime_update - 1 := 0; 65 signal on_time: integer range 0 to HEARTBEAT_PWM_DIVIDER - 1 := 0; 66 constant ontime_divider : integer range 0 to HEARTBEAT_PWM_DIVIDER - 1 := 1; 67 signal delta_ontime : integer range 0 to HEARTBEAT_PWM_DIVIDER - 1 := 1; 68 signal DIR : std_logic := '0'; 58 69 59 70 BEGIN … … 119 130 -- can be switched off with heartbeat_en high 120 131 heartbeat : process (CLK) 121 variable Z: integer range 0 to HEARTBEAT_PWM_DIVIDER - 1 := 0; 122 variable ON_TIME: integer range 0 to HEARTBEAT_PWM_DIVIDER - 1 := 0; 123 variable DELAY: integer range 0 to MAX_DELAY - 1 := 0; 124 variable DIR : std_logic := '1'; 132 133 134 125 135 126 136 begin 127 137 if rising_edge(CLK) then 128 if ( Z< HEARTBEAT_PWM_DIVIDER - 1) then129 Z := Z+ 1;138 if (heartbeat_counter < HEARTBEAT_PWM_DIVIDER - 1) then 139 heartbeat_counter <= heartbeat_counter + 1; 130 140 else 131 Z := 0; 132 if (DELAY < MAX_DELAY - 1) then 133 DELAY := DELAY + 1; 134 else 135 DELAY := 0; 136 end if; 141 heartbeat_counter <= 0; 137 142 end if; 138 143 144 -- calculate the change in on_time 145 -- if the change is too small... then change at least by 1. 146 if ( on_time / (2*ontime_divider) = 0) then 147 delta_ontime <= 1; 148 else 149 delta_ontime <= on_time / (2*ontime_divider); 150 end if; 151 if (heartbeat_counter = 0) then 152 if (ontime_update_counter < ontime_update - 1) then 153 ontime_update_counter <= ontime_update_counter + 1; 154 else 155 ontime_update_counter <= 0; 156 157 -- set new on_time 158 if (DIR = '0') then -- increase on_time 159 if (on_time + delta_ontime < HEARTBEAT_PWM_DIVIDER - 1) then 160 on_time <= on_time + delta_ontime; 161 else 162 on_time <= HEARTBEAT_PWM_DIVIDER - 1; 163 DIR <= '1'; 164 end if; 165 else -- DIR is '1' -- count down 166 if (on_time - delta_ontime > 0) then 167 on_time <= on_time - delta_ontime; 168 else 169 on_time <= 0; 170 DIR <= '0'; 171 end if; 172 end if; 173 174 end if; 175 end if; 176 177 139 178 140 if (Z = 0) then 141 if (DIR = '0') then -- count up 142 if (ON_TIME < HEARTBEAT_PWM_DIVIDER - 11) then 143 ON_TIME := ON_TIME + 10; 144 else 145 DIR := '1'; 146 end if; 147 else -- DIR is '1' -- count down 148 if (ON_TIME > 10) then 149 ON_TIME := ON_TIME - 10; 150 else 151 DIR := '0'; 152 end if; 153 end if; 154 end if; 155 156 if (Z = 0) then 179 if (heartbeat_counter = 0) then 157 180 red_loc <= '1'; 158 181 end if; 159 if ( Z = ON_TIME) then182 if (heartbeat_counter = on_time) then 160 183 red_loc <= '0'; 161 184 end if; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd
r10180 r10225 41 41 roi_array : IN roi_array_type; 42 42 ram_write_ea : OUT std_logic := '0'; 43 config_ready , config_started : OUT std_logic := '0';43 config_ready : OUT std_logic := '1'; 44 44 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); 45 45 package_length : OUT std_logic_vector (15 downto 0) := (others => '0'); … … 114 114 when MM_CONFIG => 115 115 if (config_start = '1') then 116 config_ started <= '1';116 config_ready <= '0'; 117 117 roi_max_array <= (others => 0); 118 118 channel_size <= (others => 0); … … 209 209 ram_start_addr <= (others => '0'); 210 210 ram_write_ea <= '1'; 211 config_started <= '0';212 211 config_ready <= '1'; 213 212 package_length <= conv_std_logic_vector (event_size, 16); … … 224 223 state_mm <= MM_MAIN1; 225 224 if (config_start = '1') then 226 config_ready <= '0';225 --config_ready <= '0'; 227 226 if (events_in_ram = 0) then 228 227 state_mm <= MM_CONFIG; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd
r10155 r10225 36 36 ready : OUT std_logic := '0'; 37 37 38 locked_status_o : OUT std_logic; 39 ready_status_o : OUT std_logic; 38 40 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') 39 41 … … 91 93 ready <= ready_int; 92 94 PSCLK <= CLK; 93 offset <= LOCKED & ready_int & std_logic_vector(to_signed(offset_int,6)); 95 offset <= std_logic_vector(to_signed(offset_int,8)); 96 locked_status_o <= LOCKED; 97 ready_status_o <= ready_int; 94 98 95 99 -- MAIN FSM -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_distributor_beha.vhd
r9912 r10225 28 28 clk : IN std_logic; -- 50MHz 29 29 config_start : IN std_logic; 30 config_ready , config_started : OUT std_logic := '0';30 config_ready : OUT std_logic := '1'; 31 31 sensor_valid : OUT std_logic := '0'; 32 32 dac_array : IN dac_array_type; 33 current_dac_array : OUT dac_array_type := ( others => 0); 33 34 sensor_array : OUT sensor_array_type; 34 35 dac_config_start : OUT std_logic := '0'; 35 36 dac_config_ready : IN std_logic; 37 sclk_enable_override : OUT std_logic := '0'; 36 38 sensor_read_start : OUT std_logic := '0'; 37 39 sensor_read_valid : IN std_logic; … … 53 55 signal dac_id_cnt : integer range 0 to 7 := 0; 54 56 57 signal internal_dac_array : dac_array_type; 58 signal sclk_enable_override_sig : std_logic := '0'; 55 59 56 60 BEGIN 61 sclk_enable_override <= sclk_enable_override_sig; 57 62 58 63 spi_distribute_proc: process (clk) 59 64 begin 65 60 66 61 67 if rising_edge(clk) then … … 67 73 spi_distr_state <= READ_SENSOR; 68 74 when IDLE => 75 sclk_enable_override_sig <= '0'; 69 76 if (int_sensor_valid = '1') then 70 77 sensor_array <= int_sensor_array; … … 74 81 -- start DAC configuration 75 82 if (config_start = '1' AND int_sensor_valid = '1') then 76 config_started <= '1';77 83 config_ready <= '0'; 84 sclk_enable_override_sig <= '1'; 78 85 dac_config_start <= '1'; 79 86 dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); 80 87 data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); 88 internal_dac_array <= dac_array; 81 89 spi_distr_state <= CONFIG_DAC; 82 90 -- start temperature sensor reading … … 111 119 dac_config_start <= '1'; 112 120 dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); 113 data <= conv_std_logic_vector( dac_array(dac_id_cnt),data'length);121 data <= conv_std_logic_vector(internal_dac_array(dac_id_cnt),data'length); 114 122 if (dac_config_ready = '1') then 115 123 dac_config_start <= '0'; … … 120 128 else 121 129 dac_id_cnt <= 0; 122 config_started <= '0';123 130 config_ready <= '1'; 131 current_dac_array <= internal_dac_array; 124 132 spi_distr_state <= IDLE; 125 133 end if; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd
r10155 r10225 2 2 -- 3 3 -- Created: 4 -- by - d neise.UNKNOWN (E5B-LABOR6)5 -- at - 1 3:10:37 12.02.20114 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 16:52:21 02.03.2011 6 6 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 8 8 -- 9 9 LIBRARY ieee; … … 15 15 ENTITY spi_interface IS 16 16 PORT( 17 clk_50MHz : IN std_logic; 18 config_start : IN std_logic; 19 dac_array : IN dac_array_type; 20 config_ready : OUT std_logic; 21 config_started : OUT std_logic := '0'; 22 dac_cs : OUT std_logic; 23 mosi : OUT std_logic := '0'; 24 sclk : OUT std_logic; 25 sensor_array : OUT sensor_array_type; 26 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 27 sensor_ready : OUT std_logic; 28 miso : INOUT std_logic 17 clk_50MHz : IN std_logic; 18 config_start : IN std_logic; 19 dac_array : IN dac_array_type; 20 sclk_enable_i : IN std_logic; 21 config_ready : OUT std_logic; 22 current_dac_array : OUT dac_array_type := ( others => 0); 23 dac_cs : OUT std_logic; 24 mosi : OUT std_logic := '0'; 25 sclk : OUT std_logic; 26 sensor_array : OUT sensor_array_type; 27 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 28 sensor_ready : OUT std_logic; 29 miso : INOUT std_logic 29 30 ); 30 31 … … 37 38 -- 38 39 -- Created: 39 -- by - d neise.UNKNOWN (E5B-LABOR6)40 -- at - 1 3:10:37 12.02.201140 -- by - daqct3.UNKNOWN (IHP110) 41 -- at - 16:52:21 02.03.2011 41 42 -- 42 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)43 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 43 44 -- 44 45 LIBRARY ieee; … … 57 58 58 59 -- Internal signal declarations 59 SIGNAL T_sensor_start : std_logic; 60 SIGNAL dac_config_ready : std_logic; 61 SIGNAL dac_config_start : std_logic; 62 SIGNAL dac_id : std_logic_vector(2 DOWNTO 0); 63 SIGNAL data : std_logic_vector(15 DOWNTO 0); 64 SIGNAL sensor_id : std_logic_vector(1 DOWNTO 0); 65 SIGNAL sensor_start : std_logic; 66 SIGNAL sensor_valid : std_logic; 60 SIGNAL T_sensor_start : std_logic; 61 SIGNAL clk_2Mhz : std_logic := '0'; 62 SIGNAL dac_config_ready : std_logic; 63 SIGNAL dac_config_start : std_logic; 64 SIGNAL dac_id : std_logic_vector(2 DOWNTO 0); 65 SIGNAL data : std_logic_vector(15 DOWNTO 0); 66 SIGNAL sclk_enable_override : std_logic := '0'; 67 SIGNAL sclk_enable_sig : std_logic := '0'; 68 SIGNAL sensor_id : std_logic_vector(1 DOWNTO 0); 69 SIGNAL sensor_start : std_logic; 70 SIGNAL sensor_valid : std_logic; 67 71 68 72 -- Implicit buffer signal declarations … … 101 105 ); 102 106 PORT ( 103 clk : IN std_logic; 104 config_start : IN std_logic; 105 dac_array : IN dac_array_type; 106 dac_config_ready : IN std_logic; 107 sensor_read_valid : IN std_logic; 108 config_ready : OUT std_logic := '0'; 109 config_started : OUT std_logic := '0'; 110 dac_config_start : OUT std_logic := '0'; 111 dac_id : OUT std_logic_vector (2 DOWNTO 0) := (others => '0'); 112 sensor_array : OUT sensor_array_type; 113 sensor_id : OUT std_logic_vector (1 DOWNTO 0) := (others => '0'); 114 sensor_read_start : OUT std_logic := '0'; 115 sensor_valid : OUT std_logic := '0'; 116 data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z') 107 clk : IN std_logic; 108 config_start : IN std_logic; 109 dac_array : IN dac_array_type; 110 dac_config_ready : IN std_logic; 111 sensor_read_valid : IN std_logic; 112 config_ready : OUT std_logic := '0'; 113 current_dac_array : OUT dac_array_type := ( others => 0); 114 dac_config_start : OUT std_logic := '0'; 115 dac_id : OUT std_logic_vector (2 DOWNTO 0) := (others => '0'); 116 sclk_enable_override : OUT std_logic := '0'; 117 sensor_array : OUT sensor_array_type; 118 sensor_id : OUT std_logic_vector (1 DOWNTO 0) := (others => '0'); 119 sensor_read_start : OUT std_logic := '0'; 120 sensor_valid : OUT std_logic := '0'; 121 data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z') 117 122 ); 118 123 END COMPONENT; … … 128 133 BEGIN 129 134 135 -- ModuleWare code(v1.9) for instance 'I0' of 'and' 136 sclk_internal <= clk_2Mhz AND sclk_enable_sig; 137 138 -- ModuleWare code(v1.9) for instance 'I2' of 'or' 139 sclk_enable_sig <= sclk_enable_i OR sclk_enable_override; 140 130 141 -- Instance port mappings. 131 142 I1 : clk_divider … … 135 146 PORT MAP ( 136 147 clk => clk_50MHz, 137 sclk => sclk_internal148 sclk => clk_2Mhz 138 149 ); 139 150 Measure_Temperature_Timer : clk_divider … … 165 176 ) 166 177 PORT MAP ( 167 clk => sclk_internal, 168 config_start => config_start, 169 config_ready => config_ready, 170 config_started => config_started, 171 sensor_valid => sensor_ready, 172 dac_array => dac_array, 173 sensor_array => sensor_array, 174 dac_config_start => dac_config_start, 175 dac_config_ready => dac_config_ready, 176 sensor_read_start => sensor_start, 177 sensor_read_valid => sensor_valid, 178 dac_id => dac_id, 179 sensor_id => sensor_id, 180 data => data 178 clk => sclk_internal, 179 config_start => config_start, 180 config_ready => config_ready, 181 sensor_valid => sensor_ready, 182 dac_array => dac_array, 183 current_dac_array => current_dac_array, 184 sensor_array => sensor_array, 185 dac_config_start => dac_config_start, 186 dac_config_ready => dac_config_ready, 187 sclk_enable_override => sclk_enable_override, 188 sensor_read_start => sensor_start, 189 sensor_read_valid => sensor_valid, 190 dac_id => dac_id, 191 sensor_id => sensor_id, 192 data => data 181 193 ); 182 194 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/trigger_counter_beha.vhd
r10155 r10225 18 18 trigger_id : out std_logic_vector(31 downto 0); 19 19 trigger : in std_logic; 20 reset : in std_logic; 20 21 clk : in std_logic 21 22 ); … … 25 26 architecture beha of trigger_counter is 26 27 28 signal trigger_sr : std_logic_vector (1 downto 0) := "00"; 29 signal reset_sr : std_logic_vector (1 downto 0) := "00"; 27 30 signal temp_id : integer := 0; 28 31 … … 34 37 begin 35 38 if rising_edge(clk) then 36 if (trigger = '1') then 39 reset_sr <= reset_sr(0) & reset; 40 trigger_sr <= trigger_sr(0) & trigger; 41 if (trigger_sr = "01") then 37 42 temp_id <= temp_id + 1; 43 end if; 44 if (reset_sr = "01") then 45 temp_id <= 0; 38 46 end if; 39 47 end if; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10180 r10225 37 37 -- FAD configuration signals: 38 38 ------------------------------------------------------------------------------ 39 -- start entire configuration chain 40 new_config : OUT std_logic := '0'; 41 config_chain_done : IN std_logic; 42 data_generator_run_mode : out std_logic; -- default triggers will be accepted 43 data_ram_empty : IN std_logic; 44 -- read/write configRAM 45 config_addr : out std_logic_vector (7 downto 0); 46 config_data : inout std_logic_vector (15 downto 0) := (others => 'Z'); 47 config_wr_en : out std_logic := '0'; 48 config_rd_en : out std_logic := '0'; 49 config_rw_ack, config_rw_ready : in std_logic; 50 config_busy : in std_logic; 39 memory_manager_config_start_o : out std_logic := '0'; 40 memory_manager_config_valid_i : in std_logic; 41 42 spi_interface_config_start_o : out std_logic := '0'; 43 spi_interface_config_valid_i : in std_logic; 44 45 data_generator_config_start_o : out std_logic := '0'; 46 data_generator_config_valid_i : in std_logic; 47 48 dac_setting : out dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd 49 roi_setting : out roi_array_type := DEFAULT_ROI; --<<-- default defined in fad_definitions.vhd 50 51 data_ram_empty : IN std_logic; 52 51 53 ------------------------------------------------------------------------------ 52 54 … … 60 62 -- user controllable enable signals 61 63 ------------------------------------------------------------------------------ 62 trigger_enable : out std_logic := '0'; -- default triggers are NOT accepted64 trigger_enable : out std_logic; 63 65 64 denable : out std_logic := '0'; -- default domino wave o ff65 dwrite_enable : out std_logic := ' 0'; -- default DWRITE low.66 denable : out std_logic := '0'; -- default domino wave on. ... in case if REFCLK error ... REFCLK counter will override. 67 dwrite_enable : out std_logic := '1'; -- default DWRITE low. 66 68 sclk_enable : out std_logic := '1'; -- default DWRITE HIGH. 67 69 srclk_enable : out std_logic := '1'; -- default SRCLK on. … … 74 76 ps_do_phase_shift : out std_logic := '0'; --pulse this to phase shift once 75 77 ps_reset : out std_logic := '0'; -- pulse this to reset the variable phase shift 78 ps_ready : in std_logic; 76 79 ------------------------------------------------------------------------------ 77 80 … … 82 85 socks_connected: out std_logic 83 86 ------------------------------------------------------------------------------ 84 87 88 85 89 86 90 ); … … 93 97 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 94 98 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, 95 CONFIG, WAIT_FOR_DATA_RAM_EMPTY, WAIT_FOR_CONFIG_DONE, 99 100 CONFIG, 101 WAIT_FOR_OLLI, 102 WAIT_FOR_DATA_RAM_EMPTY, 103 CONFIG_MEMORY_MANAGER, WAIT_FOR_CONFIG_MEMORY_MANAGER, 104 CONFIG_DATA_GENERATOR, WAIT_FOR_CONFIG_DATA_GENERATOR, 105 CONFIG_DAC_ONLY, WAIT_FOR_CONFIG_DAC_ONLY, 106 96 107 MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA 97 108 ); … … 115 126 READ_COMMAND_DATA_SECTION, 116 127 PUT_COMMAND_DATA_SECTION, 117 NEW_CONT_TRIGGER_MULT_FACTOR_READ,118 NEW_CONT_TRIGGER_MULT_FACTOR_PUT,119 RD_WAIT,120 RD_WAIT1,121 128 RD_END 122 129 ); … … 148 155 signal data_end : integer := 0; 149 156 150 signal socket_tx_free : std_logic_vector ( 31downto 0) := (others => '0');157 signal socket_tx_free : std_logic_vector (16 downto 0) := (others => '0'); 151 158 signal write_length_bytes : std_logic_vector (16 downto 0); 152 159 153 signal socket_rx_received : std_logic_vector ( 31downto 0) := (others => '0');160 signal socket_rx_received : std_logic_vector (16 downto 0) := (others => '0'); 154 161 signal chk_recv_cntr : integer range 0 to 10000 := 0; 155 162 … … 159 166 160 167 signal rx_packets_cnt : std_logic_vector (15 downto 0); 161 signal new_config_flag : std_logic := '0'; 162 163 signal trigger_stop : std_logic := '1'; 168 169 signal update_of_rois : std_logic := '1'; 170 signal update_of_lessimportant : std_logic := '1'; 171 172 173 signal trigger_enable_sig : std_logic := '0'; 174 signal trigger_enable_storage_sig : std_logic; 164 175 165 176 signal local_write_length : std_logic_vector (16 DOWNTO 0); … … 170 181 signal local_fifo_channels : std_logic_vector (3 downto 0); 171 182 172 173 183 signal data_ram_empty_sr : std_logic_vector (3 downto 0) := "0000"; 184 185 signal config_addr : integer range 0 to 44; 186 type config_data_type is array (0 to 44) of std_logic_vector(15 downto 0); 187 signal config_setting : config_data_type := ( 188 -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs TESTING ONLY 189 -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs TESTING ONLY 190 -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs TESTING ONLY 191 -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs TESTING ONLY 192 193 194 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs 195 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs 196 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs 197 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs 198 X"61A8", X"0000", X"0000", X"0000", X"7080", X"7080", X"7080", X"7080", --<<-- DACs 199 X"0000" 200 ); 174 201 175 202 -- signals used for MAC/IP calculation: … … 211 238 signal mod7_result : std_logic_vector(2 downto 0); 212 239 240 241 213 242 COMPONENT mod7 214 243 PORT ( … … 243 272 244 273 -- concurrent statemnets 245 data_generator_run_mode <= data_generator_run_mode_signal; 274 275 -- output config settings as DAC and ROI arrays. 276 277 278 roi_mapping : for i in 0 to 35 generate 279 roi_setting(i) <= conv_integer(config_setting(i)) when (conv_integer(config_setting(i)) < 1025) else 1024; 280 end generate roi_mapping; 281 dac_mapping : for i in 0 to 7 generate 282 dac_setting(i) <= conv_integer(config_setting(i+36)); 283 end generate dac_mapping; 284 c_trigger_mult <= config_setting(44); 285 286 trigger_enable <= trigger_enable_sig; 246 287 247 288 w5300_proc : process (clk) … … 249 290 if rising_edge (clk) then 250 291 -- synch asynchronous input in: 292 data_ram_empty_sr <= data_ram_empty_sr(2 downto 0) & data_ram_empty; 251 293 w5300_interrupt_sr <= w5300_interrupt_sr(1) & int; 252 294 data_valid_sr <= data_valid_sr(1) & data_valid; … … 257 299 -- When sockets receive disconnection request. 258 300 259 if (w5300_interrupt_sr = " 01") and (interrupt_ignore = '0') then301 if (w5300_interrupt_sr = "10") and (interrupt_ignore = '0') then 260 302 case state_interrupt_1 is 261 303 when IR1_01 => … … 390 432 -- this should never happen!!!!! 391 433 -- impossible to find this out, if in cam 392 state_init <= INIT; 434 gateway_loc <= ETHZ_GATEWAY; 435 netmask_loc <= ETHZ_NETMASK; 436 mac_loc <= MAC_FAD2; 437 ip_loc <= IP_ETHZ_FAD2; 438 --state_init <= INIT; 393 439 else -- everything is fine 394 440 -- IP & MAC are calculated from BID & CID … … 614 660 state_init <= ESTABLISH; 615 661 end case; 662 663 when CONFIG => 664 trigger_enable_storage_sig <= trigger_enable_sig; -- store last value of this signal. 665 trigger_enable_sig <= '0'; --no triggers must occur, while configurating. 666 state_init <= WAIT_FOR_OLLI; -- now wait until the last event was send down.. 616 667 617 when CONFIG => 618 DG_run_mode_temp_storage_signal <= data_generator_run_mode_signal; --save current value of DG run mode signal. 619 data_generator_run_mode_signal <= '0'; --switch DG to config-mode --> no triggers are accepted 668 when WAIT_FOR_OLLI => 620 669 state_init <= WAIT_FOR_DATA_RAM_EMPTY; 670 671 621 672 when WAIT_FOR_DATA_RAM_EMPTY => 622 if (data_ram_empty = '1') then 623 new_config <= '1'; 624 state_init <= WAIT_FOR_CONFIG_DONE; 673 if (data_ram_empty_sr(3) = '1') then 674 state_init <= CONFIG_MEMORY_MANAGER; 625 675 end if; 626 when WAIT_FOR_CONFIG_DONE => 627 new_config <= '0'; 628 if (config_chain_done ='1') then 676 677 when CONFIG_MEMORY_MANAGER => 678 memory_manager_config_start_o <= '1'; 679 if (memory_manager_config_valid_i = '0') then 680 state_init <= WAIT_FOR_CONFIG_MEMORY_MANAGER; 681 end if; 682 683 when WAIT_FOR_CONFIG_MEMORY_MANAGER => 684 memory_manager_config_start_o <= '0'; 685 if (memory_manager_config_valid_i = '1') then 686 state_init <= CONFIG_DATA_GENERATOR; 687 end if; 688 689 when CONFIG_DATA_GENERATOR => 690 data_generator_config_start_o <= '1'; 691 if (data_generator_config_valid_i = '0') then 692 state_init <= WAIT_FOR_CONFIG_DATA_GENERATOR; 693 end if; 694 when WAIT_FOR_CONFIG_DATA_GENERATOR => 695 data_generator_config_start_o <= '0'; 696 if (data_generator_config_valid_i = '1') then 697 trigger_enable_sig <= trigger_enable_storage_sig; --restore value of this signal to the value it had before CONFIG 629 698 state_init <= MAIN; 630 data_generator_run_mode_signal <= DG_run_mode_temp_storage_signal; -- restore former value of DG run mode signal631 699 end if; 632 700 701 702 when CONFIG_DAC_ONLY => 703 spi_interface_config_start_o <= '1'; 704 if (spi_interface_config_valid_i ='0') then 705 state_init <= WAIT_FOR_CONFIG_DAC_ONLY; 706 end if; 707 708 when WAIT_FOR_CONFIG_DAC_ONLY => 709 spi_interface_config_start_o <= '0'; 710 if (spi_interface_config_valid_i ='1') then 711 state_init <= MAIN; 712 end if; 713 633 714 ---------------------------------------------------------------------------------- 634 715 -- MAIN "loop" ------------------------------------------------------------------- … … 636 717 637 718 when MAIN => 638 socks_waiting <= '0'; 639 socks_connected <= '1'; 640 ps_do_phase_shift <= '0'; 641 ps_reset <= '0'; 642 if (trigger_stop = '1') then 643 s_trigger <= '0'; 719 720 721 if (update_of_rois = '1') then 722 update_of_rois <= '0'; 723 state_init <= CONFIG; 724 elsif (update_of_lessimportant = '1') then 725 update_of_lessimportant <= '0'; 726 state_init <= CONFIG_DAC_ONLY; 727 elsif ( update_of_rois='0' and update_of_lessimportant='0' ) then 728 socks_waiting <= '0'; 729 socks_connected <= '1'; 730 ps_do_phase_shift <= '0'; 731 ps_reset <= '0'; 732 data_valid_ack <= '0'; 733 state_init <= MAIN1; 734 --data_valid_int <= data_valid; 644 735 end if; 645 data_valid_ack <= '0'; 646 state_init <= MAIN1; 647 --data_valid_int <= data_valid; 736 648 737 when MAIN1 => 649 738 if (chk_recv_cntr = 1000) then … … 695 784 state_read_data <= RD_2; 696 785 when RD_2 => 697 socket_rx_received ( 31 downto 16) <= data_read;786 socket_rx_received (16) <= data_read(0); 698 787 par_addr <= W5300_S0_RX_RSR + X"2"; 699 788 state_init <= READ_REG; … … 712 801 end if; 713 802 when RD_5 => 803 s_trigger <= '0'; 804 ps_do_phase_shift <= '0'; 714 805 if (rx_packets_cnt > 0) then 715 806 rx_packets_cnt <= rx_packets_cnt - '1'; … … 727 818 case data_read (15 downto 8) is 728 819 when CMD_START => 729 data_generator_run_mode_signal <= '1';820 730 821 state_read_data <= RD_5; 731 822 when CMD_STOP => 732 data_generator_run_mode_signal <= '0';823 733 824 state_read_data <= RD_5; 734 825 when CMD_MODE_ALL_SOCKETS => -- all data will be send via socket 1..7 735 826 socket_send_mode <= '1'; 736 827 state_read_data <= RD_5; 737 when CM C_MODE_COMMAND => -- all data will be send via socket 0828 when CMD_MODE_COMMAND => -- all data will be send via socket 0 738 829 socket_send_mode <= '0'; 739 830 state_read_data <= RD_5; 740 831 when CMD_TRIGGER => 741 trigger_stop <= '1';742 832 s_trigger <= '1'; 743 833 state_read_data <= RD_5; … … 766 856 c_trigger_enable <= '0'; 767 857 state_read_data <= RD_5; 768 when CMD_SET_TRIGGER_MULT => 769 state_read_data <= NEW_CONT_TRIGGER_MULT_FACTOR_READ; 858 770 859 -- phase shift commands here: 771 860 when CMD_PS_DO => … … 785 874 state_read_data <= RD_5; 786 875 when CMD_TRIGGERS_ON => 787 trigger_enable <= '1';876 trigger_enable_sig <= '1'; 788 877 state_read_data <= RD_5; 789 878 when CMD_TRIGGERS_OFF => 790 trigger_enable <= '0';879 trigger_enable_sig <= '0'; 791 880 state_read_data <= RD_5; 792 881 when CMD_PS_DIRDEC => … … 794 883 state_read_data <= RD_5; 795 884 when CMD_WRITE => 796 config_addr <= data_read (7 downto 0);885 config_addr <= conv_integer(data_read (7 downto 0)); 797 886 state_read_data <= READ_COMMAND_DATA_SECTION; 798 887 when others => … … 815 904 816 905 when PUT_COMMAND_DATA_SECTION => 817 if (config_busy = '0') then818 config_data <= data_read;819 config_wr_en<= '1';820 new_config_flag <= '1';821 state_read_data <= RD_WAIT;906 config_setting(config_addr) <= data_read; 907 if (config_addr < 36) then 908 update_of_rois <= '1'; 909 else 910 update_of_lessimportant <= '1'; 822 911 end if; 823 824 -- these states are beeing precessed, if the 'command' was a 'set new continouus trigger prescaler multiplication factor'-command825 -- so the next 16bit word is just put out at the apropriate output.826 when NEW_CONT_TRIGGER_MULT_FACTOR_READ =>827 if (rx_packets_cnt > 0) then828 rx_packets_cnt <= rx_packets_cnt - '1';829 par_addr <= W5300_S0_RX_FIFOR;830 state_init <= READ_REG;831 next_state <= READ_DATA;832 state_read_data <= NEW_CONT_TRIGGER_MULT_FACTOR_PUT;833 else834 state_read_data <= RD_END;835 end if;836 when NEW_CONT_TRIGGER_MULT_FACTOR_PUT =>837 c_trigger_mult <= data_read;838 912 state_read_data <= RD_5; 839 840 841 when RD_WAIT => 842 if (config_rw_ack = '1') then 843 state_read_data <= RD_WAIT1; 844 end if; 845 when RD_WAIT1 => 846 if (config_rw_ready = '1') then 847 config_data <= (others => 'Z'); 848 config_wr_en <= '0'; 849 state_read_data <= RD_5; 850 end if; 851 when RD_END => 852 par_addr <= W5300_S0_CR; 913 914 915 when RD_END => 916 par_addr <= W5300_S0_CR; 853 917 par_data <= X"0040"; -- RECV 854 918 state_init <= WRITE_REG; 855 if (new_config_flag = '1') then 856 new_config_flag <= '0'; 857 next_state <= CONFIG; 858 else 859 next_state <= MAIN; 860 end if; 919 next_state <= MAIN; 920 861 921 862 922 end case; -- state_data_read … … 885 945 when WR_GET_EVT_ID2 => 886 946 event_number(15 downto 0) <= ram_data; 887 if (mod7_valid = '1') then888 mod7_start <= '1';947 mod7_start <= '1'; 948 if (mod7_valid = '0') then 889 949 state_write <= WR_MOD7_STARTED; 890 950 else … … 919 979 state_write <= WR_CHECK_FOR_FIFO_SPACE_02; 920 980 when WR_CHECK_FOR_FIFO_SPACE_02 => 921 socket_tx_free ( 31 downto 16) <= data_read;981 socket_tx_free (16) <= data_read(0); 922 982 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; 923 983 state_init <= READ_REG; … … 968 1028 ---- Start... 969 1029 when WR_ADC => 970 971 972 973 974 975 data_end <= 3;976 1030 adc_data_addr <= local_ram_start_addr + local_ram_addr; 1031 drs_cnt <= 0; 1032 channel_cnt <= 1; 1033 data_cnt <= 0; 1034 roi_max <= (others => '0'); 1035 data_end <= POSITION_OF_ROI_IN_CHANNEL_HEADER; 1036 state_write <= WR_ADC1; 977 1037 978 1038 ---- Write Channel 979 1039 when WR_ADC1 => 980 981 if (data_cnt = 3) then982 data_end <= conv_integer (ram_data) + 3;983 984 985 986 987 988 1040 -- read ROI and set end of Channel-Data 1041 if (data_cnt = POSITION_OF_ROI_IN_CHANNEL_HEADER) then 1042 data_end <= conv_integer (ram_data) + CHANNEL_HEADER_SIZE; 1043 if (ram_data > roi_max) then 1044 roi_max <= ram_data (10 downto 0); 1045 end if; 1046 end if; 1047 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4); 1048 state_write <= WR_ADC2; 989 1049 when WR_ADC2 => 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 data_end <= 3;1003 1004 1005 1006 1007 1008 1009 1010 1011 data_end <= 3;1012 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 -- End Write ADC-Data1050 if (data_cnt < data_end) then 1051 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1052 ram_access <= '1'; 1053 state_init <= WRITE_REG; 1054 next_state <= WRITE_DATA; 1055 data_cnt <= data_cnt + 1; 1056 state_write <= WR_ADC1; 1057 else 1058 -- Next DRS 1059 if (drs_cnt < 3) then 1060 drs_cnt <= drs_cnt + 1; 1061 data_cnt <= 0; 1062 data_end <= POSITION_OF_ROI_IN_CHANNEL_HEADER; 1063 state_write <= WR_ADC1; 1064 else 1065 -- Next Channel 1066 if (channel_cnt < local_fifo_channels) then 1067 channel_cnt <= channel_cnt + 1; 1068 roi_max <= (others => '0'); 1069 drs_cnt <= 0; 1070 data_cnt <= 0; 1071 data_end <= POSITION_OF_ROI_IN_CHANNEL_HEADER; 1072 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4); 1073 state_write <= WR_ADC1; 1074 else 1075 -- Ready 1076 if (local_write_end_flag = '1') then 1077 state_write <= WR_ENDFLAG; 1078 else 1079 state_write <= WR_05; 1080 end if; 1081 end if; 1082 end if; 1083 end if; 1084 -- End Write ADC-Data 1025 1085 1026 1086 -- Write End Package Flag 1027 1087 when WR_ENDFLAG => 1028 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);1088 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4); 1029 1089 state_write <= WR_ENDFLAG1; 1030 1090 when WR_ENDFLAG1 => … … 1035 1095 state_write <= WR_ENDFLAG2; 1036 1096 when WR_ENDFLAG2 => 1037 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1;1097 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4) + 1; 1038 1098 state_write <= WR_ENDFLAG3; 1039 1099 when WR_ENDFLAG3 =>
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