Changeset 10879


Ignore:
Timestamp:
May 27, 2011, 5:28:59 PM (9 years ago)
Author:
weitzel
Message:
FTM: new light pulser interface, new timing constraint in .ucf file 
Location:
firmware/FTM
Files:
8 edited

Legend:

Unmodified
Added
Removed
  • firmware/FTM/FTM_central_control.vhd

    r10803 r10879  
    6565    config_started_cc    : in  std_logic;
    6666    config_ready_cc      : in  std_logic;
     67    config_start_lp      : out std_logic := '0';
     68    config_started_lp    : in  std_logic;
     69    config_ready_lp      : in  std_logic;
    6770    config_trigger       : out  std_logic := '0';
    6871    config_trigger_done  : in  std_logic;
     
    110113                                   CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01,
    111114                                   CP_CONFIG_CC, CP_CONFIG_CC_01,
     115                                   CP_CONFIG_LP, CP_CONFIG_LP_01,
    112116                                   CP_CONFIG_FTU, CP_CONFIG_FTU_01,
    113117                                   CP_CONFIG_SCALER, CP_CONFIG_SCALER_01,
     
    194198          cc_state_test <= X"06";
    195199          if (config_ready_cc = '1') then
     200            state_central_proc <= CP_CONFIG_LP;
     201            --state_central_proc <= CP_CONFIG_FTU;
     202          end if;
     203
     204        when CP_CONFIG_LP =>
     205          current_cc_state <= FTM_STATE_CFG;
     206          cc_state_test <= X"1C";
     207          config_start_lp <= '1';
     208          if (config_started_lp = '1') then
     209            config_start_lp <= '0';
     210            state_central_proc <= CP_CONFIG_LP_01;
     211          end if;
     212         
     213        when CP_CONFIG_LP_01 =>
     214          current_cc_state <= FTM_STATE_CFG;
     215          cc_state_test <= X"1D";
     216          if (config_ready_lp = '1') then
    196217            state_central_proc <= CP_CONFIG_FTU;
    197218          end if;
  • firmware/FTM/FTM_top.vhd

    r10779 r10879  
    212212    -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
    213213    -------------------------------------------------------------------------------
    214     -- RES_p      : out STD_LOGIC;   --  RES+   Reset
    215     -- RES_n      : out STD_LOGIC;   -- RES-  IO-Bank 0
     214    RES_p      : out STD_LOGIC;   -- RES+  Reset
     215    RES_n      : out STD_LOGIC;   -- RES-  IO-Bank 0
    216216
    217217    TRG_p      : out STD_LOGIC;   -- TRG+  Trigger
     
    230230    -- to connector J13
    231231    -- for light pulsar in the mirror dish
    232     -- Cal_0_p    : out STD_LOGIC; 
    233     -- Cal_0_n    : out STD_LOGIC;
    234     -- Cal_1_p    : out STD_LOGIC;
    235     -- Cal_1_n    : out STD_LOGIC;
    236     -- Cal_2_p    : out STD_LOGIC;
    237     -- Cal_2_n    : out STD_LOGIC;
    238     -- Cal_3_p    : out STD_LOGIC;
    239     -- Cal_3_n    : out STD_LOGIC;
     232    Cal_0_p    : out STD_LOGIC; 
     233    Cal_0_n    : out STD_LOGIC;
     234    Cal_1_p    : out STD_LOGIC;
     235    Cal_1_n    : out STD_LOGIC;
     236    Cal_2_p    : out STD_LOGIC;
     237    Cal_2_n    : out STD_LOGIC;
     238    Cal_3_p    : out STD_LOGIC;
     239    Cal_3_n    : out STD_LOGIC;
    240240
    241241    -- to connector J12
    242242    -- for light pulsar inside shutter
    243     -- Cal_4_p    : out STD_LOGIC;
    244     -- Cal_4_n    : out STD_LOGIC;
    245     -- Cal_5_p    : out STD_LOGIC;
    246     -- Cal_5_n    : out STD_LOGIC;
    247     -- Cal_6_p    : out STD_LOGIC;
    248     -- Cal_6_n    : out STD_LOGIC;
    249     -- Cal_7_p    : out STD_LOGIC;
    250     -- Cal_7_n    : out STD_LOGIC 
     243    Cal_4_p    : out STD_LOGIC;
     244    Cal_4_n    : out STD_LOGIC;
     245    Cal_5_p    : out STD_LOGIC;
     246    Cal_5_n    : out STD_LOGIC;
     247    Cal_6_p    : out STD_LOGIC;
     248    Cal_6_n    : out STD_LOGIC;
     249    Cal_7_p    : out STD_LOGIC;
     250    Cal_7_n    : out STD_LOGIC; 
    251251
    252252
     
    347347  signal trigger_counter_valid_sig  : std_logic;
    348348 
    349   signal config_start_cc_sig   : std_logic := '0';
     349  signal config_start_cc_sig   : std_logic;  -- initialized in central control
    350350  signal config_started_cc_sig : std_logic := '0';
    351351  signal config_ready_cc_sig   : std_logic := '0';
    352352
     353  signal config_start_lp_sig   : std_logic;  -- initialized in central control
     354  signal config_started_lp_sig : std_logic;  -- initialized in light pulser interface
     355  signal config_ready_lp_sig   : std_logic;  -- initialized in light pulser interface
     356 
    353357  signal config_trigger_sig : std_logic;
    354358  signal config_trigger_done_sig : std_logic;
     
    412416  signal crate_res3_sig : std_logic;  -- initialized in FTM_central_control
    413417
     418  signal LP1_pulse_sig : std_logic := '0';
     419  signal LP2_pulse_sig : std_logic := '0';
     420 
    414421--  component FTM_clk_gen
    415422--    port(
     
    557564      config_started_cc    : in  std_logic;
    558565      config_ready_cc      : in  std_logic;
     566      config_start_lp      : out std_logic := '0';
     567      config_started_lp    : in  std_logic;
     568      config_ready_lp      : in  std_logic;
    559569      config_trigger       : out std_logic;
    560570      config_trigger_done  : in  std_logic;
     
    785795  end component;
    786796
     797  component Lightpulser_interface_Basic is
     798    port(
     799      clk_50    : IN  STD_LOGIC;
     800      --clk_250   : IN  STD_LOGIC;
     801      Cal_0_p   : out STD_LOGIC := '0';
     802      Cal_0_n   : out STD_LOGIC := '1';
     803      Cal_1_p   : out STD_LOGIC := '0';
     804      Cal_1_n   : out STD_LOGIC := '1';
     805      Cal_2_p   : out STD_LOGIC := '0';
     806      Cal_2_n   : out STD_LOGIC := '1';
     807      Cal_3_p   : out STD_LOGIC := '0';
     808      Cal_3_n   : out STD_LOGIC := '1';
     809      Cal_4_p    : out STD_LOGIC := '0';
     810      Cal_4_n    : out STD_LOGIC := '1';
     811      Cal_5_p    : out STD_LOGIC := '0';
     812      Cal_5_n    : out STD_LOGIC := '1';
     813      Cal_6_p    : out STD_LOGIC := '0';
     814      Cal_6_n    : out STD_LOGIC := '1';
     815      Cal_7_p    : out STD_LOGIC := '0';
     816      Cal_7_n    : out STD_LOGIC := '1'; 
     817      LP1_ampl       : in std_logic_vector (15 downto 0);
     818      LP2_ampl       : in std_logic_vector (15 downto 0);
     819      --LP1_delay      : in std_logic_vector (15 downto 0);
     820      --LP2_delay      : in std_logic_vector (15 downto 0);
     821      LP1_pulse      : in std_logic;
     822      LP2_pulse      : in std_logic;
     823      start_config   : in std_logic;
     824      config_started : out std_logic := '0';
     825      config_done    : out std_logic := '0'
     826    );
     827  end component;
    787828 
    788829begin
     
    832873    );
    833874 
    834    --differential output buffer for trigger signal
    835    OBUFDS_LVDS_33_TRG : OBUFDS_LVDS_33
    836      port map(
    837        O  => TRG_p,
    838        OB => TRG_n,
    839        I  => trigger_signal_sig
    840      );
    841 
    842    --differential output buffer for trigger signal
    843    OBUFDS_LVDS_33_TIM : OBUFDS_LVDS_33
    844      port map(
    845        O  => TIM_Run_p,
    846        OB => TIM_Run_n,
    847        I  => TIM_signal_sig
    848      );
    849    
     875  --differential output buffer for trigger signal
     876  OBUFDS_LVDS_33_TRG : OBUFDS_LVDS_33
     877    port map(
     878      O  => TRG_p,
     879      OB => TRG_n,
     880      I  => trigger_signal_sig
     881    );
     882
     883  --differential output buffer for TIM signal
     884  OBUFDS_LVDS_33_TIM : OBUFDS_LVDS_33
     885    port map(
     886      O  => TIM_Run_p,
     887      OB => TIM_Run_n,
     888      I  => TIM_signal_sig
     889    );
     890
     891  --differential output buffer for fast reset signal
     892  OBUFDS_LVDS_33_RES : OBUFDS_LVDS_33
     893    port map(
     894      O  => RES_p,
     895      OB => RES_n,
     896      I  => '0'
     897    );
     898 
    850899   Inst_trigger_manager : trigger_manager
    851900     port map(
     
    895944      trigger_active      => trigger_active_sig,  --phys triggers are enabled/active
    896945      config_done         => config_trigger_done_sig,
    897       LP1_pulse           => open,  --send start signal to light pulser 1
    898       LP2_pulse           => open,  --send start signal to light pulser 2
     946      LP1_pulse           => LP1_pulse_sig,  --send start signal to light pulser 1
     947      LP2_pulse           => LP2_pulse_sig,  --send start signal to light pulser 2
    899948      --trigger and time marker output signals to FADs
    900949      trigger_signal      => trigger_signal_sig,
     
    9581007      config_started_cc    => config_started_cc_sig,
    9591008      config_ready_cc      => config_ready_cc_sig,
     1009      config_start_lp      => config_start_lp_sig,
     1010      config_started_lp    => config_started_lp_sig,
     1011      config_ready_lp      => config_ready_lp_sig,
    9601012      config_trigger       => config_trigger_sig,
    9611013      config_trigger_done  => config_trigger_done_sig,
     
    11991251      counter_reading     => on_time_counter_sig
    12001252    );
     1253
     1254  Inst_Lightpulser_interface_Basic : Lightpulser_interface_Basic
     1255    port map (
     1256      clk_50         => clk_50M_sig,
     1257      --clk_250        => clk_250M_sig,
     1258      Cal_0_p        => Cal_0_p,
     1259      Cal_0_n        => Cal_0_n,
     1260      Cal_1_p        => Cal_1_p,
     1261      Cal_1_n        => Cal_1_n,
     1262      Cal_2_p        => Cal_2_p,
     1263      Cal_2_n        => Cal_2_n,
     1264      Cal_3_p        => Cal_3_p,
     1265      Cal_3_n        => Cal_3_n,
     1266      Cal_4_p        => Cal_4_p,
     1267      Cal_4_n        => Cal_4_n,
     1268      Cal_5_p        => Cal_5_p,
     1269      Cal_5_n        => Cal_5_n,
     1270      Cal_6_p        => Cal_6_p,
     1271      Cal_6_n        => Cal_6_n,
     1272      Cal_7_p        => Cal_7_p,
     1273      Cal_7_n        => Cal_7_n,
     1274      LP1_ampl       => lp1_amplitude_sig,
     1275      LP2_ampl       => lp2_amplitude_sig,
     1276      --LP1_delay      => lp1_delay_sig,
     1277      --LP2_delay      => lp2_delay_sig,
     1278      LP1_pulse      => LP1_pulse_sig,
     1279      LP2_pulse      => LP2_pulse_sig,
     1280      start_config   => config_start_lp_sig,
     1281      config_started => config_started_lp_sig,
     1282      config_done    => config_ready_lp_sig
     1283    );
    12011284 
    12021285  LED_red <= led_sig(3 downto 0);
  • firmware/FTM/FTM_top_tb.vhd

    r10740 r10879  
    208208      -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
    209209      -------------------------------------------------------------------------------
    210 --      RES_p      : out STD_LOGIC;   --  RES+   Reset
    211 --      RES_n      : out STD_LOGIC;   --  RES-
     210      RES_p      : out STD_LOGIC;   --  RES+   Reset
     211      RES_n      : out STD_LOGIC;   --  RES-
    212212
    213213      TRG_p      : out STD_LOGIC;   -- TRG+  Trigger
     
    216216      TIM_Run_p  : out STD_LOGIC;   -- TIM_Run+  Time Marker
    217217      TIM_Run_n  : out STD_LOGIC;   -- TIM_Run-
    218 --      TIM_Sel    : out STD_LOGIC;   -- Time Marker selector
     218      TIM_Sel    : out STD_LOGIC;   -- Time Marker selector
    219219                                                   
    220220      -- CLD_FPGA   : in STD_LOGIC;    -- DRS-Clock feedback into FPGA
     
    225225      -- to connector J13
    226226      -- for light pulsar in the mirror dish
    227 --      Cal_0_p    : out STD_LOGIC; 
    228 --      Cal_0_n    : out STD_LOGIC;
    229 --      Cal_1_p    : out STD_LOGIC;
    230 --      Cal_1_n    : out STD_LOGIC;
    231 --      Cal_2_p    : out STD_LOGIC;
    232 --      Cal_2_n    : out STD_LOGIC;
    233 --      Cal_3_p    : out STD_LOGIC;
    234 --      Cal_3_n    : out STD_LOGIC;
     227      Cal_0_p    : out STD_LOGIC; 
     228      Cal_0_n    : out STD_LOGIC;
     229      Cal_1_p    : out STD_LOGIC;
     230      Cal_1_n    : out STD_LOGIC;
     231      Cal_2_p    : out STD_LOGIC;
     232      Cal_2_n    : out STD_LOGIC;
     233      Cal_3_p    : out STD_LOGIC;
     234      Cal_3_n    : out STD_LOGIC;
    235235
    236236      -- to connector J12
    237237      -- for light pulsar inside shutter
    238 --      Cal_4_p    : out STD_LOGIC;
    239 --      Cal_4_n    : out STD_LOGIC;
    240 --      Cal_5_p    : out STD_LOGIC;
    241 --      Cal_5_n    : out STD_LOGIC;
    242 --      Cal_6_p    : out STD_LOGIC;
    243 --      Cal_6_n    : out STD_LOGIC;
    244 --      Cal_7_p    : out STD_LOGIC;
    245 --      Cal_7_n    : out STD_LOGIC 
     238      Cal_4_p    : out STD_LOGIC;
     239      Cal_4_n    : out STD_LOGIC;
     240      Cal_5_p    : out STD_LOGIC;
     241      Cal_5_n    : out STD_LOGIC;
     242      Cal_6_p    : out STD_LOGIC;
     243      Cal_6_n    : out STD_LOGIC;
     244      Cal_7_p    : out STD_LOGIC;
     245      Cal_7_n    : out STD_LOGIC; 
    246246
    247247
     
    414414      Busy2         => Busy2_sig,
    415415      Busy3         => Busy3_sig,
    416 --      RES_p         => RES_p_sig,
    417 --      RES_n         => RES_n_sig,
     416      RES_p         => RES_p_sig,
     417      RES_n         => RES_n_sig,
    418418      TRG_p         => TRG_p_sig,
    419419      TRG_n         => TRG_n_sig,
    420420      TIM_Run_p     => TIM_Run_p_sig,
    421421      TIM_Run_n     => TIM_Run_n_sig,
    422 --      TIM_Sel       => TIM_Sel_sig,
    423 --      Cal_0_p       => Cal_0_p_sig, 
    424 --      Cal_0_n       => Cal_0_n_sig,
    425 --      Cal_1_p       => Cal_1_p_sig,
    426 --      Cal_1_n       => Cal_1_n_sig,
    427 --      Cal_2_p       => Cal_2_p_sig,
    428 --      Cal_2_n       => Cal_2_n_sig,
    429 --      Cal_3_p       => Cal_3_p_sig,
    430 --      Cal_3_n       => Cal_3_n_sig,
    431 --      Cal_4_p       => Cal_4_p_sig,
    432 --      Cal_4_n       => Cal_4_n_sig,
    433 --      Cal_5_p       => Cal_5_p_sig,
    434 --      Cal_5_n       => Cal_5_n_sig,
    435 --      Cal_6_p       => Cal_6_p_sig,
    436 --      Cal_6_n       => Cal_6_n_sig,
    437 --      Cal_7_p       => Cal_7_p_sig,
    438 --      Cal_7_n       => Cal_7_n_sig,
     422      TIM_Sel       => TIM_Sel_sig,
     423      Cal_0_p       => Cal_0_p_sig, 
     424      Cal_0_n       => Cal_0_n_sig,
     425      Cal_1_p       => Cal_1_p_sig,
     426      Cal_1_n       => Cal_1_n_sig,
     427      Cal_2_p       => Cal_2_p_sig,
     428      Cal_2_n       => Cal_2_n_sig,
     429      Cal_3_p       => Cal_3_p_sig,
     430      Cal_3_n       => Cal_3_n_sig,
     431      Cal_4_p       => Cal_4_p_sig,
     432      Cal_4_n       => Cal_4_n_sig,
     433      Cal_5_p       => Cal_5_p_sig,
     434      Cal_5_n       => Cal_5_n_sig,
     435      Cal_6_p       => Cal_6_p_sig,
     436      Cal_6_n       => Cal_6_n_sig,
     437      Cal_7_p       => Cal_7_p_sig,
     438      Cal_7_n       => Cal_7_n_sig,
    439439      TP            => TP_sig
    440440    );
  • firmware/FTM/Lightpulser_interface/Basic_Version/FM_pulse_generator_Basic.vhd

    r10855 r10879  
    1111--               by Patrick Vogler
    1212--               "Lightpulser Basic Version"
     13--
     14-- modified:     May 27 2011
     15--               by Patrick Vogler, Quirin Weitzel
     16--               -> clean up
     17
    1318
    1419LIBRARY ieee;
     
    2429ENTITY FM_pulse_generator_Basic IS
    2530   GENERIC(
    26       pulse_length : integer := FLD_PULSE_LENGTH   -- 48ns                                                               
     31      pulse_length : integer := FLD_PULSE_LENGTH_BASIC   -- 60ns                                                               
    2732         );
    2833   PORT(
     
    5257                      Z := Z + 1;
    5358                  else
    54                       Z := - FLD_MIN_FREQ_DIV;
     59                      Z := - FLD_MIN_FREQ_DIV_BASIC;
    5560                      Y := 0;
    5661                  end if;                 
    5762        end if;   
    5863
    59       if (Y < FLD_PULSE_LENGTH_BASIC) then
     64      if (Y < pulse_length) then
    6065        Y := Y + 1;
    6166        FM_out <= '1';
  • firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic.vhd

    r10855 r10879  
    55-- Create Date:    24 February 2010
    66-- Design Name:   
    7 -- Module Name:    FTM Lightpulser interface
     7-- Module Name:    FTM Lightpulser interface Basic
    88-- Project Name:
    99-- Target Devices:
     
    2828--               "Lightpulser Basic Version"
    2929--
     30-- modified:     May 27 2011
     31--               by Patrick Vogler, Quirin Weitzel
     32--               -> clean up
     33--
    3034----------------------------------------------------------------------------------
    3135
     
    4549
    4650
    47 
    48 entity Lightpulser_interface is
     51entity Lightpulser_interface_Basic is
    4952  port(
    5053   
     
    99102   
    100103  );
    101 end Lightpulser_interface;
    102 
    103 
    104 architecture Behavioral of Lightpulser_interface is
    105 
     104end Lightpulser_interface_Basic;
     105
     106
     107architecture Behavioral of Lightpulser_interface_Basic is
    106108
    107109
    108110component FM_pulse_generator_Basic is
    109    port(
    110       clk            : in  std_logic;    -- 50 MHz
    111       pulse_freq     : in  std_logic_vector (5 downto 0);
    112       FM_out         : out std_logic  := '0'
    113          );
     111  port(
     112    clk            : in  std_logic;    -- 50 MHz
     113    pulse_freq     : in  std_logic_vector (5 downto 0);
     114    FM_out         : out std_logic  := '0'
     115  );
    114116end component;
    115117
    116118
    117   component single_LP_Basic is
     119component single_LP_Basic is
    118120  port( 
    119    clk_50         : in  STD_LOGIC;       
    120    LP_Pulse_out    : out STD_LOGIC;                                                 
    121    LP_pulse_in     : in std_logic 
    122    );
     121    clk_50         : in  STD_LOGIC;       
     122    LP_Pulse_out   : out STD_LOGIC;                                                 
     123    LP_pulse_in    : in std_logic 
     124  );
    123125end component;
    124126
    125127
    126 
    127 
    128   -- LP1: mirror dish
    129   signal Cal_0_1 : STD_LOGIC := '0'; 
     128-- LP1: mirror dish
     129signal Cal_0_1 : STD_LOGIC := '0'; 
    130130--  signal Cal_1_1 : STD_LOGIC;
    131131
    132   -- LP2: shutter
    133   signal Cal_0_2 : STD_LOGIC := '0';
     132-- LP2: shutter
     133signal Cal_0_2 : STD_LOGIC := '0';
    134134--  signal Cal_1_2 : STD_LOGIC;
    135135
    136  -- PWM for amplitude stabilization
    137   signal PWM_sig_1 : std_logic := '0';  -- LP1: mirror dish
    138   signal PWM_sig_2 : std_logic := '0';  -- LP2: shutter
    139 
    140   -- control data latch
    141   signal LP1_ampl_sig   :  std_logic_vector (15 downto 0) := (others => '0');
    142   signal LP2_ampl_sig   :  std_logic_vector (15 downto 0) := (others => '0');
     136-- PWM for amplitude stabilization
     137signal PWM_sig_1 : std_logic := '0';  -- LP1: mirror dish
     138signal PWM_sig_2 : std_logic := '0';  -- LP2: shutter
     139
     140-- control data latch
     141signal LP1_ampl_sig   :  std_logic_vector (15 downto 0) := (others => '0');
     142signal LP2_ampl_sig   :  std_logic_vector (15 downto 0) := (others => '0');
    143143 
    144144
    145   type type_latch_state is (IDLE, COPY, CONFIGURED);   
    146   signal latch_state       : type_latch_state  := IDLE;   
    147  
    148 
    149 
    150 
     145type type_latch_state is (IDLE, COPY, CONFIGURED);   
     146signal latch_state : type_latch_state  := IDLE;   
     147 
    151148
    152149begin
    153150 
    154151
    155 -- input latch
    156 input_latch : process (clk_50)
     152  -- input latch
     153  input_latch : process (clk_50)
    157154  begin
    158155    if rising_edge(clk_50) then
     
    180177       end case;           
    181178    end if; 
    182 end process input_latch;
     179  end process input_latch;
    183180                 
    184 
    185181 
    186182  Inst_LP1_mirror_dish:single_LP_Basic
    187183    port map (
    188         clk_50        => clk_50,   
    189         LP_Pulse_out  => Cal_0_1,                                     
    190         LP_pulse_in   => LP1_pulse               
    191               );
    192 
    193  
    194     Inst_LP2_shutter:single_LP_Basic
     184      clk_50        => clk_50,   
     185      LP_Pulse_out  => Cal_0_1,                                     
     186      LP_pulse_in   => LP1_pulse               
     187      );
     188
     189 
     190  Inst_LP2_shutter:single_LP_Basic
    195191    port map (
    196         clk_50        => clk_50,   
    197         LP_Pulse_out  => Cal_0_2,                                     
    198         LP_pulse_in   => LP2_pulse               
    199           );
    200 
    201 Inst_LP1_FM_pulse_generator:FM_pulse_generator_Basic    -- LP1: mirror dish
    202    port map(
     192      clk_50        => clk_50,   
     193      LP_Pulse_out  => Cal_0_2,                                     
     194      LP_pulse_in   => LP2_pulse               
     195    );
     196
     197  Inst_LP1_FM_pulse_generator:FM_pulse_generator_Basic    -- LP1: mirror dish
     198    port map(
    203199      clk            => clk_50, 
    204200      pulse_freq     => LP1_ampl_sig(5 downto 0),
    205201      FM_out         => PWM_sig_1   
    206          );
    207 
    208 
    209 Inst_LP2_FM_pulse_generator:FM_pulse_generator_Basic    -- LP2: shutter
    210    port map(
     202    );
     203
     204
     205  Inst_LP2_FM_pulse_generator:FM_pulse_generator_Basic    -- LP2: shutter
     206    port map(
    211207      clk            => clk_50, 
    212208      pulse_freq     => LP2_ampl_sig(5 downto 0),
    213209      FM_out         => PWM_sig_2   
    214          );
    215 
    216 
    217 -- Light Pulser 1 (in the mirror dish): differential output buffers
     210    );
     211
     212
     213  -- Light Pulser 1 (in the mirror dish): differential output buffers
    218214
    219215  OBUFDS_inst_Cal_0 : OBUFDS
    220    generic map (
    221       IOSTANDARD => "DEFAULT")
    222    port map  (  O  => Cal_0_p ,     -- Diff_p output (connect directly to top-level port)
    223       OB =>  Cal_0_n ,   -- Diff_n output (connect directly to top-level port)
    224       I  =>  Cal_0_1     -- Buffer input
    225    );
    226 
    227      OBUFDS_inst_Cal_1 : OBUFDS
    228    generic map (
    229       IOSTANDARD => "DEFAULT")
    230    port map  (  O  => Cal_1_p ,     -- Diff_p output (connect directly to top-level port)
    231       OB =>  Cal_1_n ,   -- Diff_n output (connect directly to top-level port)
    232       I  =>  PWM_sig_1   -- Buffer input
    233    );
    234 
    235      OBUFDS_inst_Cal_2 : OBUFDS
    236    generic map (
    237       IOSTANDARD => "DEFAULT")
    238    port map  (  O  => Cal_2_p ,     -- Diff_p output (connect directly to top-level port)
    239       OB =>  Cal_2_n ,   -- Diff_n output (connect directly to top-level port)
    240       I  =>  LP1_ampl_sig(14)       -- Buffer input
    241    );
    242 
    243      OBUFDS_inst_Cal_3 : OBUFDS
    244    generic map (
    245       IOSTANDARD => "DEFAULT")
    246    port map (   O  => Cal_3_p ,     -- Diff_p output (connect directly to top-level port)
    247       OB =>  Cal_3_n ,   -- Diff_n output (connect directly to top-level port)
    248       I  =>  LP1_ampl_sig(15)      -- Buffer input
    249    );     
     216    generic map (
     217      IOSTANDARD => "DEFAULT")
     218    port map (  O  => Cal_0_p ,    -- Diff_p output (connect directly to top-level port)
     219                OB =>  Cal_0_n ,   -- Diff_n output (connect directly to top-level port)
     220                I  =>  Cal_0_1     -- Buffer input
     221                );
     222
     223  OBUFDS_inst_Cal_1 : OBUFDS
     224    generic map (
     225      IOSTANDARD => "DEFAULT")
     226    port map  (  O  => Cal_1_p ,    -- Diff_p output (connect directly to top-level port)
     227                 OB =>  Cal_1_n ,   -- Diff_n output (connect directly to top-level port)
     228                 I  =>  PWM_sig_1   -- Buffer input
     229                 );
     230
     231  OBUFDS_inst_Cal_2 : OBUFDS
     232    generic map (
     233      IOSTANDARD => "DEFAULT")
     234    port map  (  O  => Cal_2_p ,     -- Diff_p output (connect directly to top-level port)
     235                 OB =>  Cal_2_n ,    -- Diff_n output (connect directly to top-level port)
     236                 I  =>  LP1_ampl_sig(14)       -- Buffer input
     237                 );
     238
     239  OBUFDS_inst_Cal_3 : OBUFDS
     240    generic map (
     241      IOSTANDARD => "DEFAULT")
     242    port map (   O  => Cal_3_p ,     -- Diff_p output (connect directly to top-level port)
     243                 OB =>  Cal_3_n ,    -- Diff_n output (connect directly to top-level port)
     244                 I  =>  LP1_ampl_sig(15)      -- Buffer input
     245                 );     
    250246
    251247
    252248     
    253 --  Light Pulser 2 (in the shutter): differential output buffers
     249  --  Light Pulser 2 (in the shutter): differential output buffers
    254250     
    255  OBUFDS_inst_Cal_4 : OBUFDS
    256    generic map (
    257       IOSTANDARD => "DEFAULT")
    258    port map (   O  => Cal_4_p ,     -- Diff_p output (connect directly to top-level port)
    259       OB =>  Cal_4_n ,   -- Diff_n output (connect directly to top-level port)
    260       I  =>  Cal_0_2      -- Buffer input
    261    );
    262 
    263      OBUFDS_inst_Cal_5 : OBUFDS
    264    generic map (
    265       IOSTANDARD => "DEFAULT")
    266    port map  (  O  => Cal_5_p ,     -- Diff_p output (connect directly to top-level port)
    267       OB =>  Cal_5_n ,   -- Diff_n output (connect directly to top-level port)
    268       I  =>  PWM_sig_2        -- Buffer input
    269    );
    270 
    271      OBUFDS_inst_Cal_6 : OBUFDS
    272    generic map (
    273       IOSTANDARD => "DEFAULT")
    274    port map  (  O  => Cal_6_p ,     -- Diff_p output (connect directly to top-level port)
    275       OB =>  Cal_6_n ,   -- Diff_n output (connect directly to top-level port)
    276       I  =>  LP2_ampl_sig(14)
    277     );             
    278 
    279      OBUFDS_inst_Cal_7 : OBUFDS
    280    generic map (
    281       IOSTANDARD => "DEFAULT")
    282    port map  (  O  => Cal_7_p ,     -- Diff_p output (connect directly to top-level port)
    283       OB =>  Cal_7_n ,   -- Diff_n output (connect directly to top-level port)
    284       I  =>  LP2_ampl_sig(15)   -- Buffer input
    285    );     
     251  OBUFDS_inst_Cal_4 : OBUFDS
     252    generic map (
     253      IOSTANDARD => "DEFAULT")
     254    port map (   O  => Cal_4_p ,    -- Diff_p output (connect directly to top-level port)
     255                 OB =>  Cal_4_n ,   -- Diff_n output (connect directly to top-level port)
     256                 I  =>  Cal_0_2     -- Buffer input
     257                 );
     258
     259  OBUFDS_inst_Cal_5 : OBUFDS
     260    generic map (
     261      IOSTANDARD => "DEFAULT")
     262    port map  (  O  => Cal_5_p ,    -- Diff_p output (connect directly to top-level port)
     263                 OB =>  Cal_5_n ,   -- Diff_n output (connect directly to top-level port)
     264                 I  =>  PWM_sig_2   -- Buffer input
     265                 );
     266
     267  OBUFDS_inst_Cal_6 : OBUFDS
     268    generic map (
     269      IOSTANDARD => "DEFAULT")
     270    port map  (  O  => Cal_6_p ,     -- Diff_p output (connect directly to top-level port)
     271                 OB =>  Cal_6_n ,    -- Diff_n output (connect directly to top-level port)
     272                 I  =>  LP2_ampl_sig(14)
     273                 );             
     274
     275  OBUFDS_inst_Cal_7 : OBUFDS
     276    generic map (
     277      IOSTANDARD => "DEFAULT")
     278    port map  (  O  => Cal_7_p ,     -- Diff_p output (connect directly to top-level port)
     279                 OB =>  Cal_7_n ,    -- Diff_n output (connect directly to top-level port)
     280                 I  =>  LP2_ampl_sig(15)   -- Buffer input
     281                 );     
    286282   
    287283
    288284end Behavioral;
    289 
    290 
  • firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basic.vhd

    r10855 r10879  
    2828-- modified:     May 27 2011
    2929--               by Patrick Vogler
     30--
     31-- modified:     May 27 2011
     32--               by Patrick Vogler, Quirin Weitzel
     33--               -> clean up
    3034----------------------------------------------------------------------------------
    3135----------------------------------------------------------------------------------
  • firmware/FTM/ftm_board.ucf

    r10740 r10879  
    1111########################################################
    1212
    13 
    1413#Clock
    1514#######################################################
    16 NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47
    17 
     15NET clk LOC = Y14 |IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47
    1816
    1917# Ethernet Interface
     
    2220#######################################################
    2321# data bus
    24 NET W_D<0>  LOC  = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300       
    25 NET W_D<1>  LOC  = L22 | IOSTANDARD=LVCMOS33; #
    26 NET W_D<2>  LOC  = K23 | IOSTANDARD=LVCMOS33; #
    27 NET W_D<3>  LOC  = K25 | IOSTANDARD=LVCMOS33; #
    28 NET W_D<4>  LOC  = K26 | IOSTANDARD=LVCMOS33; #
    29 NET W_D<5>  LOC  = J22 | IOSTANDARD=LVCMOS33; #
    30 NET W_D<6>  LOC  = J23 | IOSTANDARD=LVCMOS33; #         
    31 NET W_D<7>  LOC  = G23 | IOSTANDARD=LVCMOS33; #
    32 NET W_D<8>  LOC  = G24 | IOSTANDARD=LVCMOS33; #
    33 NET W_D<9>  LOC  = F24 | IOSTANDARD=LVCMOS33; #
    34 NET W_D<10> LOC  = F25 | IOSTANDARD=LVCMOS33; #
    35 NET W_D<11> LOC  = E24 | IOSTANDARD=LVCMOS33; #
    36 NET W_D<12> LOC  = E26 | IOSTANDARD=LVCMOS33; #
    37 NET W_D<13> LOC  = D24 | IOSTANDARD=LVCMOS33; #
    38 NET W_D<14> LOC  = D26 | IOSTANDARD=LVCMOS33; #
    39 NET W_D<15> LOC  = D25 | IOSTANDARD=LVCMOS33; #
    40 
     22NET W_D<0>  LOC  = M22 |IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300
     23NET W_D<1>  LOC  = L22 |IOSTANDARD=LVCMOS33; #
     24NET W_D<2>  LOC  = K23 |IOSTANDARD=LVCMOS33; #
     25NET W_D<3>  LOC  = K25 |IOSTANDARD=LVCMOS33; #
     26NET W_D<4>  LOC  = K26 |IOSTANDARD=LVCMOS33; #
     27NET W_D<5>  LOC  = J22 |IOSTANDARD=LVCMOS33; #
     28NET W_D<6>  LOC  = J23 |IOSTANDARD=LVCMOS33; # 
     29NET W_D<7>  LOC  = G23 |IOSTANDARD=LVCMOS33; #
     30NET W_D<8>  LOC  = G24 |IOSTANDARD=LVCMOS33; #
     31NET W_D<9>  LOC  = F24 |IOSTANDARD=LVCMOS33; #
     32NET W_D<10> LOC  = F25 |IOSTANDARD=LVCMOS33; #
     33NET W_D<11> LOC  = E24 |IOSTANDARD=LVCMOS33; #
     34NET W_D<12> LOC  = E26 |IOSTANDARD=LVCMOS33; #
     35NET W_D<13> LOC  = D24 |IOSTANDARD=LVCMOS33; #
     36NET W_D<14> LOC  = D26 |IOSTANDARD=LVCMOS33; #
     37NET W_D<15> LOC  = D25 |IOSTANDARD=LVCMOS33; #
    4138# W5300 address bus
    42 NET W_A<0> LOC  = U18  | IOSTANDARD=LVCMOS33; # there is no real net W_A0 because
    43 NET W_A<1> LOC  = AA25 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode
    44 NET W_A<2> LOC  = AA24 | IOSTANDARD=LVCMOS33; # (see W5300 datasheet)
    45 NET W_A<3> LOC  = AA23 | IOSTANDARD=LVCMOS33; # -> W_A<0> assigned to unconnected pin
    46 NET W_A<4> LOC  = Y25  | IOSTANDARD=LVCMOS33; #
    47 NET W_A<5> LOC  = Y24  | IOSTANDARD=LVCMOS33; #
    48 NET W_A<6> LOC  = Y23  | IOSTANDARD=LVCMOS33; #
    49 NET W_A<7> LOC  = W23  | IOSTANDARD=LVCMOS33; #
    50 NET W_A<8> LOC  = V25  | IOSTANDARD=LVCMOS33; #
    51 NET W_A<9> LOC  = V24  | IOSTANDARD=LVCMOS33; #
    52 
     39NET W_A<0> LOC  = U18  |IOSTANDARD=LVCMOS33; # there is no real net W_A0 because
     40NET W_A<1> LOC  = AA25 |IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode
     41NET W_A<2> LOC  = AA24 |IOSTANDARD=LVCMOS33; #  (see W5300 datasheet)
     42NET W_A<3> LOC  = AA23 |IOSTANDARD=LVCMOS33; # -> W_A<0> assigned to unconnected pin
     43NET W_A<4> LOC  = Y25  |IOSTANDARD=LVCMOS33; #
     44NET W_A<5> LOC  = Y24  |IOSTANDARD=LVCMOS33; #
     45NET W_A<6> LOC  = Y23  |IOSTANDARD=LVCMOS33; #
     46NET W_A<7> LOC  = W23  |IOSTANDARD=LVCMOS33; #
     47NET W_A<8> LOC  = V25  |IOSTANDARD=LVCMOS33; #
     48NET W_A<9> LOC  = V24  |IOSTANDARD=LVCMOS33; #
    5349# W5300 control signals
    5450# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
    5551# W_CS is also routed to testpoint JP7
    56 NET W_CS    LOC  = T20  | IOSTANDARD=LVCMOS33; # W5300 chip select
    57 NET W_INT   LOC  = U22  | IOSTANDARD=LVCMOS33; # interrupt
    58 NET W_RD    LOC  = R20  | IOSTANDARD=LVCMOS33; # read
    59 NET W_WR    LOC  = P22  | IOSTANDARD=LVCMOS33; # write
    60 NET W_RES   LOC  = U23  | IOSTANDARD=LVCMOS33; # reset W5300 chip
    61 
     52NET W_CS    LOC  = T20  |IOSTANDARD=LVCMOS33; # W5300 chip select
     53NET W_INT   LOC  = U22  |IOSTANDARD=LVCMOS33; # interrupt
     54NET W_RD    LOC  = R20  |IOSTANDARD=LVCMOS33; # read
     55NET W_WR    LOC  = P22  |IOSTANDARD=LVCMOS33; # write
     56NET W_RES   LOC  = U23  |IOSTANDARD=LVCMOS33; # reset W5300 chip
    6257# W5300 buffer ready indicator
    6358# NET W_BRDY<0>   LOC  = AB26  | IOSTANDARD=LVCMOS33; #
     
    6560# NET W_BRDY<2>   LOC  = AC25  | IOSTANDARD=LVCMOS33; #
    6661# NET W_BRDY<3>   LOC  = AD26  | IOSTANDARD=LVCMOS33; #
    67 
    6862# W5300 associated testpoints
    6963# NET W_T<0>   LOC  = N21  | IOSTANDARD=LVCMOS33; #
     
    7266# NET W_T<3>   LOC  = R19  | IOSTANDARD=LVCMOS33; #
    7367
    74 
    7568# SPI Interface
    7669# connection to the EEPROM U36 (AL25L016M) and the temperature
     
    7972#######################################################
    8073# NET S_CLK  LOC  = U20  | IOSTANDARD=LVCMOS33;  # SPI clock
    81 
    8274# EEPROM
    8375# NET MOSI   LOC  = AA22 | IOSTANDARD=LVCMOS33;    # master out slave in
    8476# NET MISO   LOC  = V22  | IOSTANDARD=LVCMOS33;    # master in slave out
    8577# NET EE_CS  LOC  = G22  | IOSTANDARD=LVCMOS33;    # master out slave in
    86 
    8778# temperature sensors
    8879# NET SIO       LOC  = F22  | IOSTANDARD=LVCMOS33;  # serial IO
     
    9283# NET TS_CS<3>  LOC  = C26  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select3
    9384
    94 
    9585# Trigger primitives inputs
    9686# on IO-Bank 2
     
    9888# crate 0
    9989# crate A
    100 NET Trig_Prim_A<0>  LOC  = AC6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>       
    101 NET Trig_Prim_A<1>  LOC  = AD6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>
    102 NET Trig_Prim_A<2>  LOC  = AF3  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>
    103 NET Trig_Prim_A<3>  LOC  = AE4  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>
    104 NET Trig_Prim_A<4>  LOC  = AE6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>
    105 NET Trig_Prim_A<5>  LOC  = AE7  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>
    106 NET Trig_Prim_A<6>  LOC  = AE8  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>
    107 NET Trig_Prim_A<7>  LOC  = AC8  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>
    108 NET Trig_Prim_A<8>  LOC  = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>
    109 NET Trig_Prim_A<9>  LOC  = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>
    110 
     90NET Trig_Prim_A<0>  LOC  = AC6  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>
     91NET Trig_Prim_A<1>  LOC  = AD6  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>
     92NET Trig_Prim_A<2>  LOC  = AF3  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>
     93NET Trig_Prim_A<3>  LOC  = AE4  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>
     94NET Trig_Prim_A<4>  LOC  = AE6  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>
     95NET Trig_Prim_A<5>  LOC  = AE7  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>
     96NET Trig_Prim_A<6>  LOC  = AE8  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>
     97NET Trig_Prim_A<7>  LOC  = AC8  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>
     98NET Trig_Prim_A<8>  LOC  = AC11 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>
     99NET Trig_Prim_A<9>  LOC  = AD11 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>
    111100# crate 1
    112101# crate B
    113 NET Trig_Prim_B<0>  LOC  = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>       
    114 NET Trig_Prim_B<1>  LOC  = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>
    115 NET Trig_Prim_B<2>  LOC  = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>
    116 NET Trig_Prim_B<3>  LOC  = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>
    117 NET Trig_Prim_B<4>  LOC  = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>
    118 NET Trig_Prim_B<5>  LOC  = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>
    119 NET Trig_Prim_B<6>  LOC  = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>
    120 NET Trig_Prim_B<7>  LOC  = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>
    121 NET Trig_Prim_B<8>  LOC  = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>
    122 NET Trig_Prim_B<9>  LOC  = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>
    123 
     102NET Trig_Prim_B<0>  LOC  = AB16 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>
     103NET Trig_Prim_B<1>  LOC  = AC15 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>
     104NET Trig_Prim_B<2>  LOC  = AC16 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>
     105NET Trig_Prim_B<3>  LOC  = AE17 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>
     106NET Trig_Prim_B<4>  LOC  = AD19 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>
     107NET Trig_Prim_B<5>  LOC  = AE19 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>
     108NET Trig_Prim_B<6>  LOC  = AE20 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>
     109NET Trig_Prim_B<7>  LOC  = AF20 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>
     110NET Trig_Prim_B<8>  LOC  = AD21 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>
     111NET Trig_Prim_B<9>  LOC  = AE23 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>
    124112# crate 2
    125113# crate C
    126 NET Trig_Prim_C<0>  LOC  = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>       
    127 NET Trig_Prim_C<1>  LOC  = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>
    128 NET Trig_Prim_C<2>  LOC  = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>
    129 NET Trig_Prim_C<3>  LOC  = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>
    130 NET Trig_Prim_C<4>  LOC  = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>
    131 NET Trig_Prim_C<5>  LOC  = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>
    132 NET Trig_Prim_C<6>  LOC  = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>
    133 NET Trig_Prim_C<7>  LOC  = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>
    134 NET Trig_Prim_C<8>  LOC  = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>
    135 NET Trig_Prim_C<9>  LOC  = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>
    136 
     114NET Trig_Prim_C<0>  LOC  = AF23 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>
     115NET Trig_Prim_C<1>  LOC  = AC21 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>
     116NET Trig_Prim_C<2>  LOC  = AE21 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>
     117NET Trig_Prim_C<3>  LOC  = AD20 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>
     118NET Trig_Prim_C<4>  LOC  = AC20 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>
     119NET Trig_Prim_C<5>  LOC  = AF19 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>
     120NET Trig_Prim_C<6>  LOC  = AC19 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>
     121NET Trig_Prim_C<7>  LOC  = AD17 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>
     122NET Trig_Prim_C<8>  LOC  = AD14 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>
     123NET Trig_Prim_C<9>  LOC  = AC14 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>
    137124# crate 3
    138125# crate D
    139 NET Trig_Prim_D<0>  LOC  = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>       
    140 NET Trig_Prim_D<1>  LOC  = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>
    141 NET Trig_Prim_D<2>  LOC  = AC9  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>
    142 NET Trig_Prim_D<3>  LOC  = AB9  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>
    143 NET Trig_Prim_D<4>  LOC  = AB7  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>
    144 NET Trig_Prim_D<5>  LOC  = AF8  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>
    145 NET Trig_Prim_D<6>  LOC  = AF4  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>
    146 NET Trig_Prim_D<7>  LOC  = AF5  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>
    147 NET Trig_Prim_D<8>  LOC  = AD7  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>
    148 NET Trig_Prim_D<9>  LOC  = AE3  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>
    149 
     126NET Trig_Prim_D<0>  LOC  = AB12 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>
     127NET Trig_Prim_D<1>  LOC  = AC12 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>
     128NET Trig_Prim_D<2>  LOC  = AC9  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>
     129NET Trig_Prim_D<3>  LOC  = AB9  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>
     130NET Trig_Prim_D<4>  LOC  = AB7  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>
     131NET Trig_Prim_D<5>  LOC  = AF8  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>
     132NET Trig_Prim_D<6>  LOC  = AF4  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>
     133NET Trig_Prim_D<7>  LOC  = AF5  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>
     134NET Trig_Prim_D<8>  LOC  = AD7  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>
     135NET Trig_Prim_D<9>  LOC  = AE3  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>
    150136
    151137# NIM inputs
    152138#######################################################
    153139# on IO-Bank 3
    154 NET ext_Trig<1>  LOC  = B1  | IOSTANDARD=LVCMOS33; #   
    155 NET ext_Trig<2>  LOC  = B2  | IOSTANDARD=LVCMOS33; #
    156 NET Veto         LOC  = E4  | IOSTANDARD=LVCMOS33; #
     140NET ext_Trig<1>  LOC  = B1  |IOSTANDARD=LVCMOS33; #     
     141NET ext_Trig<2>  LOC  = B2  |IOSTANDARD=LVCMOS33; #
     142NET Veto         LOC  = E4  |IOSTANDARD=LVCMOS33; #
    157143# NET NIM_In<0>    LOC  = D3  | IOSTANDARD=LVCMOS33; #
    158144# NET NIM_In<1>    LOC  = F4  | IOSTANDARD=LVCMOS33; #
    159145# NET NIM_In<2>    LOC  = E3  | IOSTANDARD=LVCMOS33; #
    160 
    161146# on IO-Bank 0
    162147# input pin with global clock buffer available
    163148# NET NIM_In3_GCLK  LOC  = K14  | IOSTANDARD=LVCMOS33;
    164149
    165 
    166150# LEDs
    167151# on IO-Banks 0 and 3
    168152#######################################################
    169153# red
    170 NET LED_red<0>  LOC  = D6  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
    171 NET LED_red<1>  LOC  = A4  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
    172 NET LED_red<2>  LOC  = E1  | IOSTANDARD=LVCMOS33; # IO-Bank 3   
    173 NET LED_red<3>  LOC  = J5  | IOSTANDARD=LVCMOS33; # IO-Bank 3   
    174 
     154NET LED_red<0>  LOC  = D6  |IOSTANDARD=LVCMOS33; # IO-Bank 0   
     155NET LED_red<1>  LOC  = A4  |IOSTANDARD=LVCMOS33; # IO-Bank 0   
     156NET LED_red<2>  LOC  = E1  |IOSTANDARD=LVCMOS33; # IO-Bank 3   
     157NET LED_red<3>  LOC  = J5  |IOSTANDARD=LVCMOS33; # IO-Bank 3   
    175158# yellow
    176 NET LED_ye<0>   LOC  = C5  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
    177 NET LED_ye<1>   LOC  = B3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
    178 
     159NET LED_ye<0>   LOC  = C5  |IOSTANDARD=LVCMOS33; # IO-Bank 0   
     160NET LED_ye<1>   LOC  = B3  |IOSTANDARD=LVCMOS33; # IO-Bank 0
    179161# green
    180 NET LED_gn<0>   LOC  = B4  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
    181 NET LED_gn<1>   LOC  = A3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
    182 
     162NET LED_gn<0>   LOC  = B4  |IOSTANDARD=LVCMOS33; # IO-Bank 0   
     163NET LED_gn<1>   LOC  = A3  |IOSTANDARD=LVCMOS33; # IO-Bank 0
    183164
    184165# Clock conditioner LMK03000
    185166# on IO-Bank 3
    186167#######################################################
    187 NET CLK_Clk_Cond    LOC  = G4  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    188 NET LE_Clk_Cond     LOC  = F2  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    189 NET LD_Clk_Cond     LOC  = J4  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    190 NET DATA_Clk_Cond   LOC  = F3  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    191 NET SYNC_Clk_Cond   LOC  = H2  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    192 
     168NET CLK_Clk_Cond    LOC  = G4  |IOSTANDARD=LVCMOS33; # IO-Bank 3
     169NET LE_Clk_Cond     LOC  = F2  |IOSTANDARD=LVCMOS33; # IO-Bank 3
     170NET LD_Clk_Cond     LOC  = J4  |IOSTANDARD=LVCMOS33; # IO-Bank 3
     171NET DATA_Clk_Cond   LOC  = F3  |IOSTANDARD=LVCMOS33; # IO-Bank 3
     172NET SYNC_Clk_Cond   LOC  = H2  |IOSTANDARD=LVCMOS33; # IO-Bank 3
    193173
    194174# various RS-485 Interfaces
     
    196176#######################################################
    197177# Bus 1: FTU slow control
    198 NET Bus1_Tx_En   LOC  = H1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    199 NET Bus1_Rx_En   LOC  = G3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    200 
     178NET Bus1_Tx_En   LOC  = H1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     179NET Bus1_Rx_En   LOC  = G3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    201180# crate 0
    202 NET Bus1_RxD_0   LOC  = K3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    203 NET Bus1_TxD_0   LOC  = L3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    204 
     181NET Bus1_RxD_0   LOC  = K3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     182NET Bus1_TxD_0   LOC  = L3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    205183# crate 1
    206 NET Bus1_RxD_1   LOC  = M2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    207 NET Bus1_TxD_1   LOC  = N4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    208 
     184NET Bus1_RxD_1   LOC  = M2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     185NET Bus1_TxD_1   LOC  = N4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    209186# crate 2
    210 NET Bus1_RxD_2   LOC  = P3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    211 NET Bus1_TxD_2   LOC  = P4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    212 
     187NET Bus1_RxD_2   LOC  = P3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     188NET Bus1_TxD_2   LOC  = P4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    213189# crate 3
    214 NET Bus1_RxD_3   LOC  = T4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    215 NET Bus1_TxD_3   LOC  = T3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    216 
     190NET Bus1_RxD_3   LOC  = T4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     191NET Bus1_TxD_3   LOC  = T3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    217192
    218193# Bus 2: Trigger-ID to FAD boards
    219 NET Bus2_Tx_En   LOC  = K2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    220 NET Bus2_Rx_En   LOC  = K4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    221 
     194NET Bus2_Tx_En   LOC  = K2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     195NET Bus2_Rx_En   LOC  = K4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    222196# crate 0
    223 NET Bus2_RxD_0   LOC  = L4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    224 NET Bus2_TxD_0   LOC  = M3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    225 
     197NET Bus2_RxD_0   LOC  = L4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     198NET Bus2_TxD_0   LOC  = M3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    226199# crate 1
    227 NET Bus2_RxD_1   LOC  = N2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    228 NET Bus2_TxD_1   LOC  = N1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    229 
     200NET Bus2_RxD_1   LOC  = N2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     201NET Bus2_TxD_1   LOC  = N1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    230202# crate 2
    231 NET Bus2_RxD_2   LOC  = R2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    232 NET Bus2_TxD_2   LOC  = R1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    233 
     203NET Bus2_RxD_2   LOC  = R2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     204NET Bus2_TxD_2   LOC  = R1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    234205# crate 3
    235 NET Bus2_RxD_3   LOC  = U4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    236 NET Bus2_TxD_3   LOC  = U2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    237 
     206NET Bus2_RxD_3   LOC  = U4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     207NET Bus2_TxD_3   LOC  = U2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    238208
    239209# auxiliary access
     
    242212# NET Aux_Rx_En    LOC  = W4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable
    243213# NET Aux_Tx_En    LOC  = V1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary Trigger-ID
    244 
    245214# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
    246215# NET TrID_Rx_D    LOC  = U6  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    247216# NET TrID_Tx_D    LOC  = T7  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    248217
    249 
    250218# Crate-Resets
    251219# on IO-Bank 3
    252220#######################################################
    253 NET Crate_Res0    LOC  = M1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    254 NET Crate_Res1    LOC  = P1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    255 NET Crate_Res2    LOC  = R3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    256 NET Crate_Res3    LOC  = V2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    257 
     221NET Crate_Res0    LOC  = M1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     222NET Crate_Res1    LOC  = P1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     223NET Crate_Res2    LOC  = R3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     224NET Crate_Res3    LOC  = V2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    258225
    259226# Busy signals from the FAD boards
    260227# on IO-Bank 3
    261228#######################################################
    262 NET Busy0    LOC  = M4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    263 NET Busy1    LOC  = P2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    264 NET Busy2    LOC  = R4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    265 NET Busy3    LOC  = U1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    266 
     229NET Busy0    LOC  = M4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     230NET Busy1    LOC  = P2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     231NET Busy2    LOC  = R4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     232NET Busy3    LOC  = U1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    267233
    268234# NIM outputs
     
    276242# NET Cal_NIM2_p   LOC  = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  Cal_NIM2+
    277243# NET Cal_NIM2_n   LOC  = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  Cal_NIM2-
    278 
    279244# auxiliarry / spare NIM outputs
    280245# NET NIM_Out0_p  LOC  = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; #  NIM_Out0+
     
    283248# NET NIM_Out1_n  LOC  = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1-
    284249
    285 
    286250# fast control signal outputs
    287251# LVDS output at the FPGA followed by LVDS to NIM
    288252# conversion stage
    289253#######################################################
    290 # NET RES_p       LOC  = D16  | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset
    291 # NET RES_n       LOC  = C15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0
    292 
    293 NET TRG_p       LOC  = B15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger
    294 NET TRG_n       LOC  = A15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0
    295 
    296 NET TIM_Run_p   LOC  = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker
    297 NET TIM_Run_n   LOC  = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2
    298 
    299 NET TIM_Sel     LOC  = AD22 | IOSTANDARD=LVCMOS33;  # Time Marker selector IO-Bank 2
    300 
     254NET RES_p       LOC  = D16  |IOSTANDARD=LVDS_33; # RES+ Reset
     255NET RES_n       LOC  = C15  |IOSTANDARD=LVDS_33; # RES- IO-Bank 0
     256NET TRG_p       LOC  = B15  |IOSTANDARD=LVDS_33; # TRG+ Trigger
     257NET TRG_n       LOC  = A15  |IOSTANDARD=LVDS_33; # TRG- IO-Bank 0
     258NET TIM_Run_p   LOC  = AF25 |IOSTANDARD=LVDS_33; # TIM_Run+ Time Marker
     259NET TIM_Run_n   LOC  = AE25 |IOSTANDARD=LVDS_33; # TIM_Run- on IO-Bank2
     260NET TIM_Sel     LOC  = AD22 |IOSTANDARD=LVCMOS33;  # Time Marker selector IO-Bank 2
    301261# NET CLD_FPGA    LOC  = AA14 | IOSTANDARD=LVCMOS33;  # DRS-Clock feedback into FPGA
    302 
    303262
    304263# LVDS calibration outputs
     
    306265#######################################################
    307266# to connector J13
    308 # NET Cal_0_p   LOC  = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+
    309 # NET Cal_0_n   LOC  = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0-
    310 # NET Cal_1_p   LOC  = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+
    311 # NET Cal_1_n   LOC  = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1-
    312 # NET Cal_2_p   LOC  = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+
    313 # NET Cal_2_n   LOC  = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2-
    314 # NET Cal_3_p   LOC  = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+
    315 # NET Cal_3_n   LOC  = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3-
    316 
     267NET Cal_0_p   LOC  = D22 | IOSTANDARD=LVDS_33; # Cal_0+
     268NET Cal_0_n   LOC  = C22 | IOSTANDARD=LVDS_33; # Cal_0-
     269NET Cal_1_p   LOC  = D23 | IOSTANDARD=LVDS_33; # Cal_1+
     270NET Cal_1_n   LOC  = C23 | IOSTANDARD=LVDS_33; # Cal_1-
     271NET Cal_2_p   LOC  = B23 | IOSTANDARD=LVDS_33; # Cal_2+
     272NET Cal_2_n   LOC  = A22 | IOSTANDARD=LVDS_33; # Cal_2-
     273NET Cal_3_p   LOC  = C21 | IOSTANDARD=LVDS_33; # Cal_3+
     274NET Cal_3_n   LOC  = B21 | IOSTANDARD=LVDS_33; # Cal_3-
    317275# to connector J12
    318 # NET Cal_4_p   LOC  = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+   
    319 # NET Cal_4_n   LOC  = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4-   
    320 # NET Cal_5_p   LOC  = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+   
    321 # NET Cal_5_n   LOC  = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5-   
    322 # NET Cal_6_p   LOC  = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+   
    323 # NET Cal_6_n   LOC  = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6-   
    324 # NET Cal_7_p   LOC  = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+   
    325 # NET Cal_7_n   LOC  = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7-   
    326 
     276NET Cal_4_p   LOC  = E21 | IOSTANDARD=LVDS_33; # Cal_4+   
     277NET Cal_4_n   LOC  = D21 | IOSTANDARD=LVDS_33; # Cal_4-   
     278NET Cal_5_p   LOC  = D20 | IOSTANDARD=LVDS_33; # Cal_5+   
     279NET Cal_5_n   LOC  = C20 | IOSTANDARD=LVDS_33; # Cal_5-   
     280NET Cal_6_p   LOC  = B20 | IOSTANDARD=LVDS_33; # Cal_6+   
     281NET Cal_6_n   LOC  = A20 | IOSTANDARD=LVDS_33; # Cal_6-   
     282NET Cal_7_p   LOC  = B19 | IOSTANDARD=LVDS_33; # Cal_7+   
     283NET Cal_7_n   LOC  = A19 | IOSTANDARD=LVDS_33; # Cal_7-   
    327284
    328285# Testpoints
     
    330287# Connector T7
    331288# IO-Bank 0
    332 NET TP<0> LOC  = B14 | IOSTANDARD=LVCMOS33;  #
    333 NET TP<1> LOC  = A14 | IOSTANDARD=LVCMOS33;  #
    334 NET TP<2> LOC  = C13 | IOSTANDARD=LVCMOS33;  #
    335 NET TP<3> LOC  = B13 | IOSTANDARD=LVCMOS33;  #
    336 
     289NET TP<0> LOC  = B14 |IOSTANDARD=LVCMOS33;  #
     290NET TP<1> LOC  = A14 |IOSTANDARD=LVCMOS33;  #
     291NET TP<2> LOC  = C13 |IOSTANDARD=LVCMOS33;  #
     292NET TP<3> LOC  = B13 |IOSTANDARD=LVCMOS33;  #
    337293# Connector T10
    338294# IO-Bank 0
    339 NET TP<4> LOC  = D13 | IOSTANDARD=LVCMOS33;  #
    340 NET TP<5> LOC  = C12 | IOSTANDARD=LVCMOS33;  #
    341 NET TP<6> LOC  = B12 | IOSTANDARD=LVCMOS33;  #
    342 NET TP<7> LOC  = A12 | IOSTANDARD=LVCMOS33;  #
    343 
     295NET TP<4> LOC  = D13 |IOSTANDARD=LVCMOS33;  #
     296NET TP<5> LOC  = C12 |IOSTANDARD=LVCMOS33;  #
     297NET TP<6> LOC  = B12 |IOSTANDARD=LVCMOS33;  #
     298NET TP<7> LOC  = A12 |IOSTANDARD=LVCMOS33;  #
    344299# on Connector T12
    345300# IO-Bank 0
    346 NET TP<8> LOC  = D11 | IOSTANDARD=LVCMOS33;  #
    347 NET TP<9> LOC  = C11 | IOSTANDARD=LVCMOS33;  #
    348 
     301NET TP<8> LOC  = D11 |IOSTANDARD=LVCMOS33;  #
     302NET TP<9> LOC  = C11 |IOSTANDARD=LVCMOS33;  #
    349303# on Connector T14
    350304# IO-Bank 0
    351 NET TP<10> LOC  = D10 | IOSTANDARD=LVCMOS33;  #
    352 NET TP<11> LOC  = C10 | IOSTANDARD=LVCMOS33;  #
    353 NET TP<12> LOC  = A10 | IOSTANDARD=LVCMOS33;  #
    354 NET TP<13> LOC  = B10 | IOSTANDARD=LVCMOS33;  #
    355 
     305NET TP<10> LOC  = D10 |IOSTANDARD=LVCMOS33;  #
     306NET TP<11> LOC  = C10 |IOSTANDARD=LVCMOS33;  #
     307NET TP<12> LOC  = A10 |IOSTANDARD=LVCMOS33;  #
     308NET TP<13> LOC  = B10 |IOSTANDARD=LVCMOS33;  #
    356309# on Connector T16
    357310# IO-Bank 0
    358 NET TP<14> LOC  = A9 | IOSTANDARD=LVCMOS33;  #
    359 NET TP<15> LOC  = B9 | IOSTANDARD=LVCMOS33;  #
    360 NET TP<16> LOC  = A8 | IOSTANDARD=LVCMOS33;  #
    361 NET TP<17> LOC  = B8 | IOSTANDARD=LVCMOS33;  #
    362 
     311NET TP<14> LOC  = A9 |IOSTANDARD=LVCMOS33;  #
     312NET TP<15> LOC  = B9 |IOSTANDARD=LVCMOS33;  #
     313NET TP<16> LOC  = A8 |IOSTANDARD=LVCMOS33;  #
     314NET TP<17> LOC  = B8 |IOSTANDARD=LVCMOS33;  #
    363315# on Connector T8
    364316# IO-Bank 0
    365 NET TP<18> LOC  = C8 | IOSTANDARD=LVCMOS33;  #
    366 NET TP<19> LOC  = D8 | IOSTANDARD=LVCMOS33;  #
    367 NET TP<20> LOC  = C6 | IOSTANDARD=LVCMOS33;  #
    368 NET TP<21> LOC  = B6 | IOSTANDARD=LVCMOS33;  #
    369 
     317NET TP<18> LOC  = C8 |IOSTANDARD=LVCMOS33;  #
     318NET TP<19> LOC  = D8 |IOSTANDARD=LVCMOS33;  #
     319NET TP<20> LOC  = C6 |IOSTANDARD=LVCMOS33;  #
     320NET TP<21> LOC  = B6 |IOSTANDARD=LVCMOS33;  #
    370321# on Connector T9
    371322# IO-Bank 0
    372 NET TP<22> LOC  = C7 | IOSTANDARD=LVCMOS33;  #
    373 NET TP<23> LOC  = B7 | IOSTANDARD=LVCMOS33;  #
    374 
     323NET TP<22> LOC  = C7 |IOSTANDARD=LVCMOS33;  #
     324NET TP<23> LOC  = B7 |IOSTANDARD=LVCMOS33;  #
    375325# on Connector T11
    376326# IO-Bank 3
    377 NET TP<24> LOC  = Y1  | IOSTANDARD=LVCMOS33;  #
    378 NET TP<25> LOC  = AA3 | IOSTANDARD=LVCMOS33;  #
    379 NET TP<26> LOC  = AA2 | IOSTANDARD=LVCMOS33;  #
    380 NET TP<27> LOC  = AC1 | IOSTANDARD=LVCMOS33;  #
    381 
     327NET TP<24> LOC  = Y1  |IOSTANDARD=LVCMOS33;  #
     328NET TP<25> LOC  = AA3 |IOSTANDARD=LVCMOS33;  #
     329NET TP<26> LOC  = AA2 |IOSTANDARD=LVCMOS33;  #
     330NET TP<27> LOC  = AC1 |IOSTANDARD=LVCMOS33;  #
    382331# on Connector T13
    383332# IO-Bank 3
    384 NET TP<28> LOC  = AB1 | IOSTANDARD=LVCMOS33;  #
    385 NET TP<29> LOC  = AC3 | IOSTANDARD=LVCMOS33;  #
    386 NET TP<30> LOC  = AC2 | IOSTANDARD=LVCMOS33;  #
    387 NET TP<31> LOC  = AD2 | IOSTANDARD=LVCMOS33;  #
    388 
     333NET TP<28> LOC  = AB1 |IOSTANDARD=LVCMOS33;  #
     334NET TP<29> LOC  = AC3 |IOSTANDARD=LVCMOS33;  #
     335NET TP<30> LOC  = AC2 |IOSTANDARD=LVCMOS33;  #
     336NET TP<31> LOC  = AD2 |IOSTANDARD=LVCMOS33;  #
    389337# on Connector T15
    390 NET TP<32> LOC  = AD1 | IOSTANDARD=LVCMOS33;  # IO-Bank 3
     338NET TP<32> LOC  = AD1 |IOSTANDARD=LVCMOS33;  # IO-Bank 3
    391339# NET TP_in<33> LOC  = AE2 | IOSTANDARD=LVCMOS33;  # input only
    392340# NET TP_in<34> LOC  = AE1 | IOSTANDARD=LVCMOS33;  # input only
    393 
    394341
    395342# Board ID - inputs
     
    405352# NET brd_id<6> LOC  = H24 | IOSTANDARD=LVCMOS33; #
    406353# NET brd_id<7> LOC  = Y26 | IOSTANDARD=LVCMOS33; #
     354
     355NET "clk" TNM_NET = clk;
     356TIMESPEC TS_clk = PERIOD "clk" 25 ns HIGH 50%;
  • firmware/FTM/ftm_definitions.vhd

    r10857 r10879  
    342342      X"0000", -- SD_ADDR_lp_pt_ratio...    -- ratio between LP1, LP2 and pedestal triggers
    343343      --X"0001", -- SD_ADDR_lp_pt_ratio...    -- ratio between LP1, LP2 and pedestal triggers
    344       X"0004", -- SD_ADDR_lp1_amplitude     -- light pulser 1 amplitude
    345       X"0005", -- SD_ADDR_lp2_amplitude     -- light pulser 2 amplitude
    346       X"0006", -- SD_ADDR_lp1_delay         -- light pulser 1 delay
    347       X"0007", -- SD_ADDR_lp2_delay         -- light pulser 2 delay
     344      X"8020", -- SD_ADDR_lp1_amplitude     -- light pulser 1 amplitude
     345      X"4001", -- SD_ADDR_lp2_amplitude     -- light pulser 2 amplitude
     346      X"0000", -- SD_ADDR_lp1_delay         -- light pulser 1 delay
     347      X"0000", -- SD_ADDR_lp2_delay         -- light pulser 2 delay
    348348      X"0001", -- SD_ADDR_coin_n_p          -- majority coincidence n (for physics)
    349349      X"001E", -- SD_ADDR_coin_n_c          -- majority coincidence n (for calibration)
     
    399399  -- constant low_PLC : integer := 16;   -- minimal pulse duration in units of 4 ns
    400400  -- constant width_PLC : integer := 6;  -- counter width pulse duration
    401   constant FLD_PULSE_LENGTH       : integer := 12;       
    402   constant FLD_MIN_FREQ_DIV       : integer := 25;     
    403   constant FLD_FD_MULT            : integer := 50;       
    404   constant FLD_FD_MAX_RANGE       : integer := 64;
    405 
    406 
     401  -- constant FLD_PULSE_LENGTH       : integer := 12;       
     402  -- constant FLD_MIN_FREQ_DIV       : integer := 25;     
     403  -- constant FLD_FD_MULT            : integer := 50;       
     404  -- constant FLD_FD_MAX_RANGE       : integer := 64;
    407405
    408406  -- --------------------------------------------------------------------------------------
     
    414412  constant FLD_FD_MAX_RANGE_BASIC       : integer := 64;
    415413
    416 
    417  
    418  
    419414  -- Timing counter
    420415  constant TC_WIDTH         : integer := 48;
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