Changeset 10914 for firmware

Timestamp:

06/06/11 16:25:42 (13 years ago)

Author:

neise

Message:

 

Location:

firmware/FAD/FACT_FAD_20MHz_VAR_PS

Files:

• FACT_FAD.hdp (modified) (1 diff)
• FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd (modified) (1 diff)
• FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd (modified) (3 diffs)
• FACT_FAD_TB_lib/hdl/fad_main_tb_w5300_2_struct.vhd (added)
• FACT_FAD_TB_lib/hdl/w5300_interface_tb_struct.vhd (added)
• FACT_FAD_TB_lib/hdl/w5300_interface_tester_beha.vhd (added)
• FACT_FAD_TB_lib/hdl/w5300_modul2_tb_struct.vhd (added)
• FACT_FAD_TB_lib/hdl/w5300_modul2_tester_beha.vhd (added)
• FACT_FAD_TB_lib/hds/.cache.dat (modified) ( previous)
• FACT_FAD_TB_lib/hds/_fad_main_tb_w5300_2._epf (added)
• FACT_FAD_TB_lib/hds/_w5300_interface_tb._epf (added)
• FACT_FAD_TB_lib/hds/_w5300_interface_tester._epf (added)
• FACT_FAD_TB_lib/hds/_w5300_modul2_tb._epf (added)
• FACT_FAD_TB_lib/hds/_w5300_modul2_tester._epf (added)
• FACT_FAD_TB_lib/hds/clock_generator/symbol.sb (modified) (18 diffs)
• FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd (modified) (31 diffs)
• FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak (modified) (317 diffs)
• FACT_FAD_TB_lib/hds/w5300_interface_tb (added)
• FACT_FAD_TB_lib/hds/w5300_interface_tb/struct.bd (added)
• FACT_FAD_TB_lib/hds/w5300_interface_tb/struct.bd.bak (added)
• FACT_FAD_TB_lib/hds/w5300_interface_tb/symbol.sb (added)
• FACT_FAD_TB_lib/hds/w5300_interface_tb/symbol.sb.bak (added)
• FACT_FAD_TB_lib/hds/w5300_interface_tester (added)
• FACT_FAD_TB_lib/hds/w5300_interface_tester/interface (added)
• FACT_FAD_TB_lib/hds/w5300_modul2_tb (added)
• FACT_FAD_TB_lib/hds/w5300_modul2_tb/struct.bd (added)
• FACT_FAD_TB_lib/hds/w5300_modul2_tb/struct.bd.bak (added)
• FACT_FAD_TB_lib/hds/w5300_modul2_tb/symbol.sb (added)
• FACT_FAD_TB_lib/hds/w5300_modul2_tb/symbol.sb.bak (added)
• FACT_FAD_TB_lib/hds/w5300_modul2_tester (added)
• FACT_FAD_TB_lib/hds/w5300_modul2_tester/interface (added)
• FACT_FAD_lib/hds/.cache.dat (modified) ( previous)

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp

@@ -8 +8 @@
 simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
 unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
-unisim = D:\unisim\unisim
-XilinxCoreLib = D:\unisim\xilinxcorelib
+unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
+XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
 [QuestaSim]
 secureip = D:/unisim/secureip

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd

@@ -26 +26 @@
 ENTITY clock_generator IS
    GENERIC( 
-      clock_period : time := 20 ns;
+      clock_period : time := 50 ns;
       reset_time   : time := 50 ns
    );

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd

@@ -2 +2 @@
 --
 -- Created:
---          by - daqct3.UNKNOWN (IHP110)
---          at - 22:55:01 26.05.2011
---
--- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--          by - dneise.UNKNOWN (E5B-LABOR6)
+--          at - 13:22:05 01.06.2011
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
 --
 LIBRARY ieee;
@@ -20 +20 @@
 --
 -- Created:
---          by - daqct3.UNKNOWN (IHP110)
---          at - 22:55:01 26.05.2011
---
--- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--          by - dneise.UNKNOWN (E5B-LABOR6)
+--          at - 13:22:05 01.06.2011
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
 --
 LIBRARY ieee;
@@ -177 +177 @@
    COMPONENT clock_generator
    GENERIC (
-      clock_period : time := 20 ns;
+      clock_period : time := 50 ns;
       reset_time   : time := 50 ns
    );

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/clock_generator/symbol.sb

@@ -265 +265 @@
 name "clock_period"
 type "time"
-value "20 ns"
-)
-uid 156,0
+value "50 ns"
+)
+uid 183,0
 )
 *44 (LogGeneric
@@ -275 +275 @@
 value "50 ns"
 )
-uid 158,0
+uid 185,0
 )
 ]
@@ -331 +331 @@
 pos 0
 dimension 20
-uid 157,0
+uid 184,0
 )
 *51 (MRCItem
@@ -337 +337 @@
 pos 1
 dimension 20
-uid 159,0
+uid 186,0
 )
 ]
@@ -410 +410 @@
 (vvPair
 variable "HDLDir"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb.user"
 )
 (vvPair
 variable "SourceDir"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
 )
 (vvPair
@@ -438 +438 @@
 (vvPair
 variable "config"
-value "%(unit)_config"
+value "%(unit)_%(view)_config"
 )
 (vvPair
 variable "d"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\clock_generator"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\clock_generator"
 )
 (vvPair
 variable "d_logical"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\clock_generator"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\clock_generator"
 )
 (vvPair
 variable "date"
-value "23.06.2010"
+value "01.06.2011"
 )
 (vvPair
@@ -462 +462 @@
 (vvPair
 variable "dd"
-value "23"
+value "01"
 )
 (vvPair
@@ -490 +490 @@
 (vvPair
 variable "host"
-value "EEPC8"
+value "E5B-LABOR6"
 )
 (vvPair
@@ -501 +501 @@
 )
 (vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
 variable "mm"
 value "06"
@@ -518 +538 @@
 (vvPair
 variable "p"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb"
 )
 (vvPair
 variable "p_logical"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb"
 )
 (vvPair
@@ -546 +566 @@
 (vvPair
 variable "task_ModelSimPath"
-value "$HDS_HOME/../Modeltech/win32"
+value "C:\\modeltech_6.6a\\win32"
 )
 (vvPair
@@ -554 +574 @@
 (vvPair
 variable "task_PrecisionRTLPath"
-value "$HDS_HOME/../Precision/Mgc_home/bin"
+value "<TBD>"
 )
 (vvPair
@@ -578 +598 @@
 (vvPair
 variable "time"
-value "10:52:12"
+value "12:57:51"
 )
 (vvPair
@@ -586 +606 @@
 (vvPair
 variable "user"
-value "Benjamin Krumm"
+value "dneise"
 )
 (vvPair
@@ -598 +618 @@
 (vvPair
 variable "year"
-value "2010"
+value "2011"
 )
 (vvPair
 variable "yy"
-value "10"
+value "11"
 )
 ]
@@ -787 +807 @@
 st "Generic Declarations
 
-clock_period time 20 ns  
+clock_period time 50 ns  
 reset_time   time 50 ns  
 "
@@ -798 +818 @@
 name "clock_period"
 type "time"
-value "20 ns"
+value "50 ns"
 )
 (GiElement
@@ -1448 +1468 @@
 )
 )
-lastUid 159,0
+lastUid 186,0
 activeModelName "Symbol:CDM"
 )

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd

@@ -159 +159 @@
 )
 version "29.1"
-appVersion "2009.1 (Build 12)"
+appVersion "2009.2 (Build 10)"
 noEmbeddedEditors 1
 model (BlockDiag
@@ -166 +166 @@
 (vvPair
 variable "HDLDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"
 )
 (vvPair
 variable "SourceDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
 )
 (vvPair
@@ -198 +198 @@
 (vvPair
 variable "d"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
 )
 (vvPair
 variable "d_logical"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
 )
 (vvPair
 variable "date"
-value "25.05.2011"
+value "01.06.2011"
 )
 (vvPair
@@ -218 +218 @@
 (vvPair
 variable "dd"
-value "25"
+value "01"
 )
 (vvPair
@@ -246 +246 @@
 (vvPair
 variable "host"
-value "IHP110"
+value "E5B-LABOR6"
 )
 (vvPair
@@ -278 +278 @@
 (vvPair
 variable "mm"
-value "05"
+value "06"
 )
 (vvPair
@@ -286 +286 @@
 (vvPair
 variable "month"
-value "Mai"
+value "Jun"
 )
 (vvPair
 variable "month_long"
-value "Mai"
+value "Juni"
 )
 (vvPair
 variable "p"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
 )
 (vvPair
 variable "p_logical"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
 )
 (vvPair
@@ -322 +322 @@
 (vvPair
 variable "task_ModelSimPath"
-value "D:\\modeltech_6.5e\\win32"
+value "C:\\modeltech_6.6a\\win32"
 )
 (vvPair
@@ -354 +354 @@
 (vvPair
 variable "time"
-value "17:24:50"
+value "13:20:42"
 )
 (vvPair
@@ -362 +362 @@
 (vvPair
 variable "user"
-value "daqct3"
+value "dneise"
 )
 (vvPair
 variable "version"
-value "2009.1 (Build 12)"
+value "2009.2 (Build 10)"
 )
 (vvPair
@@ -406 +406 @@
 bg "0,0,32768"
 )
-xt "109200,97000,120000,98000"
+xt "109200,97000,118700,98000"
 st "
 by %user on %dd %month %year
@@ -437 +437 @@
 bg "0,0,32768"
 )
-xt "126200,93000,129500,94000"
+xt "126200,93000,129200,94000"
 st "
 Project:
@@ -468 +468 @@
 bg "0,0,32768"
 )
-xt "109200,95000,120100,96000"
+xt "109200,95000,119200,96000"
 st "
 <enter diagram title here>
@@ -499 +499 @@
 bg "0,0,32768"
 )
-xt "105200,95000,107500,96000"
+xt "105200,95000,107300,96000"
 st "
 Title:
@@ -530 +530 @@
 bg "0,0,32768"
 )
-xt "126200,94200,136000,95200"
+xt "126200,94200,135400,95200"
 st "
 <enter comments here>
@@ -560 +560 @@
 bg "0,0,32768"
 )
-xt "130200,93000,134900,94000"
+xt "130200,93000,134700,94000"
 st "
 %project_name
@@ -590 +590 @@
 fg "32768,0,0"
 )
-xt "112450,93000,118550,95000"
+xt "112700,93000,118300,95000"
 st "
 TU Dortmund 
@@ -623 +623 @@
 bg "0,0,32768"
 )
-xt "105200,96000,107500,97000"
+xt "105200,96000,107300,97000"
 st "
 Path:
@@ -654 +654 @@
 bg "0,0,32768"
 )
-xt "105200,97000,108300,98000"
+xt "105200,97000,107900,98000"
 st "
 Edited:
@@ -685 +685 @@
 bg "0,0,32768"
 )
-xt "109200,96000,125800,97000"
+xt "109200,96000,123400,97000"
 st "
 %library/%unit/%view
@@ -3432 +3432 @@
 va (VaSet
 )
-xt "50200,45200,58200,49200"
+xt "50200,45200,60200,48200"
 st "
 -- eb_ID 1: hard-wired IDs
@@ -3806 +3806 @@
 va (VaSet
 )
-xt "50200,57200,60900,67200"
+xt "50200,57200,62100,66200"
 st "
 -- eb_adc 2: ADC routing
@@ -4449 +4449 @@
 va (VaSet
 )
-xt "27200,72200,40200,77200"
+xt "27200,72200,39400,77200"
 st "
 
@@ -7443 +7443 @@
 va (VaSet
 )
-xt "-87000,1000,-70900,11000"
+xt "-87000,1000,-72500,11000"
 st "LIBRARY ieee;
 USE ieee.std_logic_1164.all;
@@ -7487 +7487 @@
 isHidden 1
 )
-xt "20000,2000,28200,4000"
+xt "20000,2000,27500,4000"
 st "`resetall
 `timescale 1ns/10ps"
@@ -7531 +7531 @@
 associable 1
 )
-windowSize "0,20,1681,1050"
-viewArea "69200,38600,161306,94544"
+windowSize "0,0,1281,1024"
+viewArea "53418,13863,168802,105975"
 cachedDiagramExtent "-92000,0,146000,98000"
 pageSetupInfo (PageSetupInfo
@@ -7545 +7545 @@
 hasePageBreakOrigin 1
 pageBreakOrigin "-146000,0"
-lastUid 2951,0
+lastUid 3294,0
 defaultCommentText (CommentText
 shape (Rectangle
@@ -7560 +7560 @@
 fg "0,0,32768"
 )
-xt "200,200,2400,1200"
+xt "200,200,2000,1200"
 st "
 Text
@@ -7978 +7978 @@
 va (VaSet
 )
-xt "200,200,2400,1200"
+xt "200,200,2000,1200"
 st "
 Text
@@ -8316 +8316 @@
 va (VaSet
 )
-xt "0,-1100,12900,-100"
+xt "0,-1100,12600,-100"
 st "g0: FOR i IN 0 TO n GENERATE"
 tm "FrameTitleTextMgr"
@@ -8376 +8376 @@
 va (VaSet
 )
-xt "0,-1100,7700,-100"
+xt "0,-1100,7400,-100"
 st "b0: BLOCK (guard)"
 tm "FrameTitleTextMgr"

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak

@@ -137 +137 @@
 uid 2336,0
 )
+(Instance
+name "I0"
+duLibraryName "FACT_FAD_lib"
+duName "FAD_main_with_w53002"
+elements [
+(GiElement
+name "RAMADDRWIDTH64b"
+type "integer"
+value "15"
+)
+]
+mwi 0
+uid 3285,0
+)
 ]
 embeddedInstances [
@@ -159 +173 @@
 )
 version "29.1"
-appVersion "2009.1 (Build 12)"
+appVersion "2009.2 (Build 10)"
 noEmbeddedEditors 1
 model (BlockDiag
@@ -166 +180 @@
 (vvPair
 variable "HDLDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"
 )
 (vvPair
 variable "SourceDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
 )
 (vvPair
@@ -198 +212 @@
 (vvPair
 variable "d"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
 )
 (vvPair
 variable "d_logical"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
 )
 (vvPair
 variable "date"
-value "23.05.2011"
+value "01.06.2011"
 )
 (vvPair
 variable "day"
-value "Mo"
+value "Mi"
 )
 (vvPair
 variable "day_long"
-value "Montag"
+value "Mittwoch"
 )
 (vvPair
 variable "dd"
-value "23"
+value "01"
 )
 (vvPair
@@ -246 +260 @@
 (vvPair
 variable "host"
-value "IHP110"
+value "E5B-LABOR6"
 )
 (vvPair
@@ -278 +292 @@
 (vvPair
 variable "mm"
-value "05"
+value "06"
 )
 (vvPair
@@ -286 +300 @@
 (vvPair
 variable "month"
-value "Mai"
+value "Jun"
 )
 (vvPair
 variable "month_long"
-value "Mai"
+value "Juni"
 )
 (vvPair
 variable "p"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
 )
 (vvPair
 variable "p_logical"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
 )
 (vvPair
@@ -322 +336 @@
 (vvPair
 variable "task_ModelSimPath"
-value "D:\\modeltech_6.5e\\win32"
+value "C:\\modeltech_6.6a\\win32"
 )
 (vvPair
@@ -354 +368 @@
 (vvPair
 variable "time"
-value "18:19:57"
+value "13:20:01"
 )
 (vvPair
@@ -362 +376 @@
 (vvPair
 variable "user"
-value "daqct3"
+value "dneise"
 )
 (vvPair
 variable "version"
-value "2009.1 (Build 12)"
+value "2009.2 (Build 10)"
 )
 (vvPair
@@ -406 +420 @@
 bg "0,0,32768"
 )
-xt "109200,97000,120300,98000"
+xt "109200,97000,118900,98000"
 st "
 by %user on %dd %month %year
@@ -437 +451 @@
 bg "0,0,32768"
 )
-xt "126200,93000,129500,94000"
+xt "126200,93000,129200,94000"
 st "
 Project:
@@ -468 +482 @@
 bg "0,0,32768"
 )
-xt "109200,95000,120100,96000"
+xt "109200,95000,119200,96000"
 st "
 <enter diagram title here>
@@ -499 +513 @@
 bg "0,0,32768"
 )
-xt "105200,95000,107500,96000"
+xt "105200,95000,107300,96000"
 st "
 Title:
@@ -530 +544 @@
 bg "0,0,32768"
 )
-xt "126200,94200,136000,95200"
+xt "126200,94200,135400,95200"
 st "
 <enter comments here>
@@ -560 +574 @@
 bg "0,0,32768"
 )
-xt "130200,93000,134900,94000"
+xt "130200,93000,134700,94000"
 st "
 %project_name
@@ -590 +604 @@
 fg "32768,0,0"
 )
-xt "112450,93000,118550,95000"
+xt "112700,93000,118300,95000"
 st "
 TU Dortmund 
@@ -623 +637 @@
 bg "0,0,32768"
 )
-xt "105200,96000,107500,97000"
+xt "105200,96000,107300,97000"
 st "
 Path:
@@ -654 +668 @@
 bg "0,0,32768"
 )
-xt "105200,97000,108300,98000"
+xt "105200,97000,107900,98000"
 st "
 Edited:
@@ -685 +699 @@
 bg "0,0,32768"
 )
-xt "109200,96000,125800,97000"
+xt "109200,96000,123400,97000"
 st "
 %library/%unit/%view
@@ -745 +759 @@
 n "wiz_reset"
 t "std_logic"
-o 49
+o 50
 suid 2,0
 i "'1'"
@@ -964 +978 @@
 t "std_logic_vector"
 b "(9 DOWNTO 0)"
-o 46
+o 47
 suid 26,0
 )
@@ -1001 +1015 @@
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
-o 52
+o 53
 suid 27,0
 )
@@ -1037 +1051 @@
 n "wiz_cs"
 t "std_logic"
-o 47
+o 48
 suid 28,0
 i "'1'"
@@ -1074 +1088 @@
 n "wiz_wr"
 t "std_logic"
-o 50
+o 51
 suid 29,0
 i "'1'"
@@ -1111 +1125 @@
 n "wiz_rd"
 t "std_logic"
-o 48
+o 49
 suid 30,0
 i "'1'"
@@ -1677 +1691 @@
 preAdd 0
 posAdd 0
-o 51
+o 52
 suid 63,0
 )
@@ -2550 +2564 @@
 n "trigger_veto"
 t "std_logic"
-o 44
+o 45
 suid 98,0
 i "'1'"
@@ -2590 +2604 @@
 eolc "-- state is encoded here ... useful for debugging."
 posAdd 0
-o 45
+o 46
 suid 103,0
+)
+)
+)
+*65 (CptPort
+uid 2924,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2925,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "109000,89625,109750,90375"
+)
+tg (CPTG
+uid 2926,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2927,0
+va (VaSet
+)
+xt "96100,89500,108000,90500"
+st "socket_tx_free_out : (16:0)"
+ju 2
+blo "108000,90300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "socket_tx_free_out"
+t "std_logic_vector"
+b "(16 DOWNTO 0)"
+eolc "-- 17bit value .. that's true"
+posAdd 0
+o 44
+suid 109,0
 )
 )
@@ -2604 +2657 @@
 lineWidth 2
 )
-xt "81000,19000,109000,90000"
+xt "81000,19000,109000,91000"
 )
 oxt "15000,-8000,43000,46000"
@@ -2612 +2665 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*65 (Text
+*66 (Text
 uid 236,0
 va (VaSet
@@ -2622 +2675 @@
 tm "BdLibraryNameMgr"
 )
-*66 (Text
+*67 (Text
 uid 237,0
 va (VaSet
@@ -2632 +2685 @@
 tm "CptNameMgr"
 )
-*67 (Text
+*68 (Text
 uid 238,0
 va (VaSet
@@ -2674 +2727 @@
 fg "49152,49152,49152"
 )
-xt "81250,88250,82750,89750"
+xt "81250,89250,82750,90750"
 iconName "BlockDiagram.png"
 iconMaskName "BlockDiagram.msk"
@@ -2684 +2737 @@
 archFileType "UNKNOWN"
 )
-*68 (SaComponent
+*69 (SaComponent
 uid 274,0
 optionalChildren [
-*69 (CptPort
+*70 (CptPort
 uid 266,0
 ps "OnEdgeStrategy"
@@ -2723 +2776 @@
 )
 )
-*70 (CptPort
+*71 (CptPort
 uid 270,0
 ps "OnEdgeStrategy"
@@ -2776 +2829 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*71 (Text
+*72 (Text
 uid 277,0
 va (VaSet
@@ -2786 +2839 @@
 tm "BdLibraryNameMgr"
 )
-*72 (Text
+*73 (Text
 uid 278,0
 va (VaSet
@@ -2796 +2849 @@
 tm "CptNameMgr"
 )
-*73 (Text
+*74 (Text
 uid 279,0
 va (VaSet
@@ -2855 +2908 @@
 archFileType "UNKNOWN"
 )
-*74 (Net
+*75 (Net
 uid 284,0
 decl (Decl
@@ -2871 +2924 @@
 )
 xt "-90000,46200,-68000,47000"
-st "SIGNAL clk                   : STD_LOGIC
-"
-)
-)
-*75 (Net
+st "SIGNAL clk                   : STD_LOGIC"
+)
+)
+*76 (Net
 uid 316,0
 decl (Decl
@@ -2889 +2941 @@
 font "Courier New,8,0"
 )
-xt "-90000,63000,-58500,63800"
-st "SIGNAL wiz_addr              : std_logic_vector(9 DOWNTO 0)
-"
-)
-)
-*76 (Net
+xt "-90000,63800,-58500,64600"
+st "SIGNAL wiz_addr              : std_logic_vector(9 DOWNTO 0)"
+)
+)
+*77 (Net
 uid 322,0
 decl (Decl
@@ -2908 +2959 @@
 font "Courier New,8,0"
 )
-xt "-90000,64600,-58000,65400"
-st "SIGNAL wiz_data              : std_logic_vector(15 DOWNTO 0)
-"
-)
-)
-*77 (Net
+xt "-90000,65400,-58000,66200"
+st "SIGNAL wiz_data              : std_logic_vector(15 DOWNTO 0)"
+)
+)
+*78 (Net
 uid 328,0
 decl (Decl
@@ -2927 +2977 @@
 font "Courier New,8,0"
 )
-xt "-90000,66200,-55000,67000"
-st "SIGNAL wiz_rd                : std_logic                    := '1'
-"
-)
-)
-*78 (Net
+xt "-90000,67000,-55000,67800"
+st "SIGNAL wiz_rd                : std_logic                    := '1'"
+)
+)
+*79 (Net
 uid 334,0
 decl (Decl
@@ -2946 +2995 @@
 font "Courier New,8,0"
 )
-xt "-90000,67800,-55000,68600"
-st "SIGNAL wiz_wr                : std_logic                    := '1'
-"
-)
-)
-*79 (SaComponent
+xt "-90000,68600,-55000,69400"
+st "SIGNAL wiz_wr                : std_logic                    := '1'"
+)
+)
+*80 (SaComponent
 uid 362,0
 optionalChildren [
-*80 (CptPort
+*81 (CptPort
 uid 350,0
 ps "OnEdgeStrategy"
@@ -2990 +3038 @@
 )
 )
-*81 (CptPort
+*82 (CptPort
 uid 354,0
 ps "OnEdgeStrategy"
@@ -3027 +3075 @@
 )
 )
-*82 (CptPort
+*83 (CptPort
 uid 358,0
 ps "OnEdgeStrategy"
@@ -3081 +3129 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*83 (Text
+*84 (Text
 uid 365,0
 va (VaSet
@@ -3091 +3139 @@
 tm "BdLibraryNameMgr"
 )
-*84 (Text
+*85 (Text
 uid 366,0
 va (VaSet
@@ -3101 +3149 @@
 tm "CptNameMgr"
 )
-*85 (Text
+*86 (Text
 uid 367,0
 va (VaSet
@@ -3155 +3203 @@
 archFileType "UNKNOWN"
 )
-*86 (Net
+*87 (Net
 uid 372,0
 decl (Decl
@@ -3170 +3218 @@
 )
 xt "-90000,59000,-58500,59800"
-st "SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0)
-"
-)
-)
-*87 (Net
+st "SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0)"
+)
+)
+*88 (Net
 uid 378,0
 decl (Decl
@@ -3188 +3235 @@
 )
 xt "-90000,58200,-68000,59000"
-st "SIGNAL sclk                  : std_logic
-"
-)
-)
-*88 (Net
+st "SIGNAL sclk                  : std_logic"
+)
+)
+*89 (Net
 uid 384,0
 decl (Decl
@@ -3208 +3254 @@
 )
 xt "-90000,59800,-68000,60600"
-st "SIGNAL sio                   : std_logic
-"
-)
-)
-*89 (SaComponent
+st "SIGNAL sio                   : std_logic"
+)
+)
+*90 (SaComponent
 uid 414,0
 optionalChildren [
-*90 (CptPort
+*91 (CptPort
 uid 410,0
 ps "OnEdgeStrategy"
@@ -3270 +3315 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*91 (Text
+*92 (Text
 uid 417,0
 va (VaSet
@@ -3280 +3325 @@
 tm "BdLibraryNameMgr"
 )
-*92 (Text
+*93 (Text
 uid 418,0
 va (VaSet
@@ -3290 +3335 @@
 tm "CptNameMgr"
 )
-*93 (Text
+*94 (Text
 uid 419,0
 va (VaSet
@@ -3350 +3395 @@
 archFileType "UNKNOWN"
 )
-*94 (Net
+*95 (Net
 uid 424,0
 decl (Decl
@@ -3365 +3410 @@
 font "Courier New,8,0"
 )
-xt "-90000,60600,-68000,61400"
-st "SIGNAL trigger               : std_logic
-"
-)
-)
-*95 (HdlText
+xt "-90000,61400,-68000,62200"
+st "SIGNAL trigger               : std_logic"
+)
+)
+*96 (HdlText
 uid 430,0
 optionalChildren [
-*96 (EmbeddedText
+*97 (EmbeddedText
 uid 436,0
 commentText (CommentText
@@ -3393 +3437 @@
 va (VaSet
 )
-xt "50200,45200,58200,49200"
+xt "50200,45200,60200,48200"
 st "
 -- eb_ID 1: hard-wired IDs
@@ -3424 +3468 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*97 (Text
+*98 (Text
 uid 433,0
 va (VaSet
@@ -3434 +3478 @@
 tm "HdlTextNameMgr"
 )
-*98 (Text
+*99 (Text
 uid 434,0
 va (VaSet
@@ -3460 +3504 @@
 viewiconposition 0
 )
-*99 (Net
+*100 (Net
 uid 440,0
 decl (Decl
@@ -3477 +3521 @@
 )
 xt "-90000,45400,-58500,46200"
-st "SIGNAL board_id              : std_logic_vector(3 downto 0)
-"
-)
-)
-*100 (Net
+st "SIGNAL board_id              : std_logic_vector(3 downto 0)"
+)
+)
+*101 (Net
 uid 448,0
 decl (Decl
@@ -3496 +3539 @@
 )
 xt "-90000,47800,-58500,48600"
-st "SIGNAL crate_id              : std_logic_vector(1 downto 0)
-"
-)
-)
-*101 (SaComponent
+st "SIGNAL crate_id              : std_logic_vector(1 downto 0)"
+)
+)
+*102 (SaComponent
 uid 508,0
 optionalChildren [
-*102 (CptPort
+*103 (CptPort
 uid 489,0
 ps "OnEdgeStrategy"
@@ -3539 +3581 @@
 )
 )
-*103 (CptPort
+*104 (CptPort
 uid 493,0
 ps "OnEdgeStrategy"
@@ -3578 +3620 @@
 )
 )
-*104 (CptPort
+*105 (CptPort
 uid 497,0
 ps "OnEdgeStrategy"
@@ -3616 +3658 @@
 )
 )
-*105 (CptPort
+*106 (CptPort
 uid 501,0
 ps "OnEdgeStrategy"
@@ -3670 +3712 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*106 (Text
+*107 (Text
 uid 511,0
 va (VaSet
@@ -3680 +3722 @@
 tm "BdLibraryNameMgr"
 )
-*107 (Text
+*108 (Text
 uid 512,0
 va (VaSet
@@ -3690 +3732 @@
 tm "CptNameMgr"
 )
-*108 (Text
+*109 (Text
 uid 513,0
 va (VaSet
@@ -3744 +3786 @@
 archFileType "UNKNOWN"
 )
-*109 (HdlText
+*110 (HdlText
 uid 518,0
 optionalChildren [
-*110 (EmbeddedText
+*111 (EmbeddedText
 uid 524,0
 commentText (CommentText
@@ -3767 +3809 @@
 va (VaSet
 )
-xt "50200,57200,60900,67200"
+xt "50200,57200,62100,66200"
 st "
 -- eb_adc 2: ADC routing
@@ -3804 +3846 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*111 (Text
+*112 (Text
 uid 521,0
 va (VaSet
@@ -3814 +3856 @@
 tm "HdlTextNameMgr"
 )
-*112 (Text
+*113 (Text
 uid 522,0
 va (VaSet
@@ -3840 +3882 @@
 viewiconposition 0
 )
-*113 (Net
+*114 (Net
 uid 528,0
 decl (Decl
@@ -3855 +3897 @@
 )
 xt "-90000,42200,-58500,43000"
-st "SIGNAL adc_otr_array         : std_logic_vector(3 DOWNTO 0)
-"
-)
-)
-*114 (Net
+st "SIGNAL adc_otr_array         : std_logic_vector(3 DOWNTO 0)"
+)
+)
+*115 (Net
 uid 536,0
 decl (Decl
@@ -3873 +3914 @@
 )
 xt "-90000,39800,-63000,40600"
-st "SIGNAL adc_data_array        : adc_data_array_type
-"
-)
-)
-*115 (Net
+st "SIGNAL adc_data_array        : adc_data_array_type"
+)
+)
+*116 (Net
 uid 544,0
 decl (Decl
@@ -3893 +3933 @@
 )
 xt "-90000,40600,-68000,41400"
-st "SIGNAL adc_oeb               : std_logic
-"
-)
-)
-*116 (Net
+st "SIGNAL adc_oeb               : std_logic"
+)
+)
+*117 (Net
 uid 560,0
 decl (Decl
@@ -3913 +3952 @@
 )
 xt "-90000,41400,-68000,42200"
-st "SIGNAL adc_otr               : STD_LOGIC
-"
-)
-)
-*117 (Net
+st "SIGNAL adc_otr               : STD_LOGIC"
+)
+)
+*118 (Net
 uid 568,0
 decl (Decl
@@ -3934 +3972 @@
 )
 xt "-90000,39000,-58000,39800"
-st "SIGNAL adc_data              : std_logic_vector(11 DOWNTO 0)
-"
-)
-)
-*118 (Net
+st "SIGNAL adc_data              : std_logic_vector(11 DOWNTO 0)"
+)
+)
+*119 (Net
 uid 767,0
 decl (Decl
@@ -3952 +3989 @@
 font "Courier New,8,0"
 )
-xt "-90000,67000,-55000,67800"
-st "SIGNAL wiz_reset             : std_logic                    := '1'
-"
-)
-)
-*119 (Net
+xt "-90000,67800,-55000,68600"
+st "SIGNAL wiz_reset             : std_logic                    := '1'"
+)
+)
+*120 (Net
 uid 775,0
 decl (Decl
@@ -3974 +4010 @@
 )
 xt "-90000,54200,-49000,55000"
-st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')
-"
-)
-)
-*120 (Net
+st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
+)
+)
+*121 (Net
 uid 783,0
 decl (Decl
@@ -3992 +4027 @@
 font "Courier New,8,0"
 )
-xt "-90000,63800,-55000,64600"
-st "SIGNAL wiz_cs                : std_logic                    := '1'
-"
-)
-)
-*121 (Net
+xt "-90000,64600,-55000,65400"
+st "SIGNAL wiz_cs                : std_logic                    := '1'"
+)
+)
+*122 (Net
 uid 791,0
 decl (Decl
@@ -4010 +4044 @@
 font "Courier New,8,0"
 )
-xt "-90000,65400,-68000,66200"
-st "SIGNAL wiz_int               : std_logic
-"
-)
-)
-*122 (Net
+xt "-90000,66200,-68000,67000"
+st "SIGNAL wiz_int               : std_logic"
+)
+)
+*123 (Net
 uid 799,0
 decl (Decl
@@ -4029 +4062 @@
 )
 xt "-90000,48600,-68000,49400"
-st "SIGNAL dac_cs                : std_logic
-"
-)
-)
-*123 (Net
+st "SIGNAL dac_cs                : std_logic"
+)
+)
+*124 (Net
 uid 807,0
 decl (Decl
@@ -4048 +4080 @@
 )
 xt "-90000,55800,-55000,56600"
-st "SIGNAL mosi                  : std_logic                    := '0'
-"
-)
-)
-*124 (Net
+st "SIGNAL mosi                  : std_logic                    := '0'"
+)
+)
+*125 (Net
 uid 815,0
 decl (Decl
@@ -4069 +4100 @@
 )
 xt "-90000,51000,-41500,51800"
-st "SIGNAL denable               : std_logic                    := '0' -- default domino wave off
-"
-)
-)
-*125 (Net
+st "SIGNAL denable               : std_logic                    := '0' -- default domino wave off"
+)
+)
+*126 (Net
 uid 823,0
 decl (Decl
@@ -4087 +4117 @@
 )
 xt "-90000,25400,-68000,26200"
-st "SIGNAL CLK_25_PS             : std_logic
-"
-)
-)
-*126 (Net
+st "SIGNAL CLK_25_PS             : std_logic"
+)
+)
+*127 (Net
 uid 831,0
 decl (Decl
@@ -4105 +4134 @@
 )
 xt "-90000,26200,-68000,27000"
-st "SIGNAL CLK_50                : std_logic
-"
-)
-)
-*127 (Net
+st "SIGNAL CLK_50                : std_logic"
+)
+)
+*128 (Net
 uid 839,0
 decl (Decl
@@ -4125 +4153 @@
 )
 xt "-90000,51800,-49000,52600"
-st "SIGNAL drs_channel_id        : std_logic_vector(3 downto 0) := (others => '0')
-"
-)
-)
-*128 (Net
+st "SIGNAL drs_channel_id        : std_logic_vector(3 downto 0) := (others => '0')"
+)
+)
+*129 (Net
 uid 847,0
 decl (Decl
@@ -4144 +4171 @@
 )
 xt "-90000,52600,-55000,53400"
-st "SIGNAL drs_dwrite            : std_logic                    := '1'
-"
-)
-)
-*129 (Net
+st "SIGNAL drs_dwrite            : std_logic                    := '1'"
+)
+)
+*130 (Net
 uid 855,0
 decl (Decl
@@ -4163 +4189 @@
 )
 xt "-90000,33400,-55000,34200"
-st "SIGNAL RSRLOAD               : std_logic                    := '0'
-"
-)
-)
-*130 (Net
+st "SIGNAL RSRLOAD               : std_logic                    := '0'"
+)
+)
+*131 (Net
 uid 863,0
 decl (Decl
@@ -4182 +4207 @@
 )
 xt "-90000,34200,-55000,35000"
-st "SIGNAL SRCLK                 : std_logic                    := '0'
-"
-)
-)
-*131 (Net
+st "SIGNAL SRCLK                 : std_logic                    := '0'"
+)
+)
+*132 (Net
 uid 871,0
 decl (Decl
@@ -4200 +4224 @@
 )
 xt "-90000,35800,-68000,36600"
-st "SIGNAL SROUT_in_0            : std_logic
-"
-)
-)
-*132 (Net
+st "SIGNAL SROUT_in_0            : std_logic"
+)
+)
+*133 (Net
 uid 879,0
 decl (Decl
@@ -4218 +4241 @@
 )
 xt "-90000,36600,-68000,37400"
-st "SIGNAL SROUT_in_1            : std_logic
-"
-)
-)
-*133 (Net
+st "SIGNAL SROUT_in_1            : std_logic"
+)
+)
+*134 (Net
 uid 887,0
 decl (Decl
@@ -4236 +4258 @@
 )
 xt "-90000,37400,-68000,38200"
-st "SIGNAL SROUT_in_2            : std_logic
-"
-)
-)
-*134 (Net
+st "SIGNAL SROUT_in_2            : std_logic"
+)
+)
+*135 (Net
 uid 895,0
 decl (Decl
@@ -4254 +4275 @@
 )
 xt "-90000,38200,-68000,39000"
-st "SIGNAL SROUT_in_3            : std_logic
-"
-)
-)
-*135 (Net
+st "SIGNAL SROUT_in_3            : std_logic"
+)
+)
+*136 (Net
 uid 1435,0
 decl (Decl
@@ -4273 +4293 @@
 )
 xt "-90000,35000,-55000,35800"
-st "SIGNAL SRIN_out              : std_logic                    := '0'
-"
-)
-)
-*136 (Net
+st "SIGNAL SRIN_out              : std_logic                    := '0'"
+)
+)
+*137 (Net
 uid 1443,0
 decl (Decl
@@ -4291 +4310 @@
 )
 xt "-90000,44600,-68000,45400"
-st "SIGNAL amber                 : std_logic
-"
-)
-)
-*137 (Net
+st "SIGNAL amber                 : std_logic"
+)
+)
+*138 (Net
 uid 1451,0
 decl (Decl
@@ -4309 +4327 @@
 )
 xt "-90000,57400,-68000,58200"
-st "SIGNAL red                   : std_logic
-"
-)
-)
-*138 (Net
+st "SIGNAL red                   : std_logic"
+)
+)
+*139 (Net
 uid 1459,0
 decl (Decl
@@ -4327 +4344 @@
 )
 xt "-90000,53400,-68000,54200"
-st "SIGNAL green                 : std_logic
-"
-)
-)
-*139 (Net
+st "SIGNAL green                 : std_logic"
+)
+)
+*140 (Net
 uid 1467,0
 decl (Decl
@@ -4346 +4362 @@
 )
 xt "-90000,47000,-58000,47800"
-st "SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0)
-"
-)
-)
-*140 (Net
+st "SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0)"
+)
+)
+*141 (Net
 uid 1475,0
 decl (Decl
@@ -4365 +4380 @@
 )
 xt "-90000,43800,-68000,44600"
-st "SIGNAL alarm_refclk_too_low  : std_logic
-"
-)
-)
-*141 (Net
+st "SIGNAL alarm_refclk_too_low  : std_logic"
+)
+)
+*142 (Net
 uid 1483,0
 decl (Decl
@@ -4383 +4397 @@
 )
 xt "-90000,43000,-68000,43800"
-st "SIGNAL alarm_refclk_too_high : std_logic
-"
-)
-)
-*142 (HdlText
+st "SIGNAL alarm_refclk_too_high : std_logic"
+)
+)
+*143 (HdlText
 uid 1491,0
 optionalChildren [
-*143 (EmbeddedText
+*144 (EmbeddedText
 uid 1497,0
 commentText (CommentText
@@ -4410 +4423 @@
 va (VaSet
 )
-xt "27200,72200,40200,77200"
+xt "27200,72200,39400,77200"
 st "
 
@@ -4445 +4458 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*144 (Text
+*145 (Text
 uid 1494,0
 va (VaSet
@@ -4455 +4468 @@
 tm "HdlTextNameMgr"
 )
-*145 (Text
+*146 (Text
 uid 1495,0
 va (VaSet
@@ -4481 +4494 @@
 viewiconposition 0
 )
-*146 (Net
+*147 (Net
 uid 1501,0
 decl (Decl
@@ -4496 +4509 @@
 )
 xt "-90000,28600,-58500,29400"
-st "SIGNAL D_T_in                : std_logic_vector(1 DOWNTO 0)
-"
-)
-)
-*147 (SaComponent
+st "SIGNAL D_T_in                : std_logic_vector(1 DOWNTO 0)"
+)
+)
+*148 (SaComponent
 uid 1509,0
 optionalChildren [
-*148 (CptPort
+*149 (CptPort
 uid 1519,0
 ps "OnEdgeStrategy"
@@ -4539 +4551 @@
 )
 )
-*149 (CptPort
+*150 (CptPort
 uid 1523,0
 ps "OnEdgeStrategy"
@@ -4592 +4604 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*150 (Text
+*151 (Text
 uid 1512,0
 va (VaSet
@@ -4602 +4614 @@
 tm "BdLibraryNameMgr"
 )
-*151 (Text
+*152 (Text
 uid 1513,0
 va (VaSet
@@ -4612 +4624 @@
 tm "CptNameMgr"
 )
-*152 (Text
+*153 (Text
 uid 1514,0
 va (VaSet
@@ -4671 +4683 @@
 archFileType "UNKNOWN"
 )
-*153 (Net
+*154 (Net
 uid 1559,0
 decl (Decl
@@ -4687 +4699 @@
 )
 xt "-90000,56600,-29000,57400"
-st "SIGNAL plllock_in            : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked
-"
-)
-)
-*154 (Net
+st "SIGNAL plllock_in            : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked"
+)
+)
+*155 (Net
 uid 1682,0
 lang 2
@@ -4706 +4717 @@
 )
 xt "-90000,24600,-68000,25400"
-st "SIGNAL ADC_CLK               : std_logic
-"
-)
-)
-*155 (Net
+st "SIGNAL ADC_CLK               : std_logic"
+)
+)
+*156 (Net
 uid 2001,0
 decl (Decl
@@ -4725 +4735 @@
 )
 xt "-90000,32600,-55000,33400"
-st "SIGNAL REF_CLK               : STD_LOGIC                    := '0'
-"
-)
-)
-*156 (SaComponent
+st "SIGNAL REF_CLK               : STD_LOGIC                    := '0'"
+)
+)
+*157 (SaComponent
 uid 2336,0
 optionalChildren [
-*157 (CptPort
+*158 (CptPort
 uid 2315,0
 ps "OnEdgeStrategy"
@@ -4769 +4778 @@
 )
 )
-*158 (CptPort
+*159 (CptPort
 uid 2319,0
 ps "OnEdgeStrategy"
@@ -4807 +4816 @@
 )
 )
-*159 (CptPort
+*160 (CptPort
 uid 2323,0
 ps "OnEdgeStrategy"
@@ -4843 +4852 @@
 )
 )
-*160 (CptPort
+*161 (CptPort
 uid 2327,0
 ps "OnEdgeStrategy"
@@ -4879 +4888 @@
 )
 )
-*161 (CptPort
+*162 (CptPort
 uid 2331,0
 ps "OnEdgeStrategy"
@@ -4915 +4924 @@
 )
 )
-*162 (CptPort
+*163 (CptPort
 uid 2548,0
 ps "OnEdgeStrategy"
@@ -4966 +4975 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*163 (Text
+*164 (Text
 uid 2339,0
 va (VaSet
@@ -4976 +4985 @@
 tm "BdLibraryNameMgr"
 )
-*164 (Text
+*165 (Text
 uid 2340,0
 va (VaSet
@@ -4986 +4995 @@
 tm "CptNameMgr"
 )
-*165 (Text
+*166 (Text
 uid 2341,0
 va (VaSet
@@ -5033 +5042 @@
 archFileType "UNKNOWN"
 )
-*166 (Net
+*167 (Net
 uid 2705,0
 decl (Decl
@@ -5047 +5056 @@
 )
 xt "-90000,49400,-68000,50200"
-st "SIGNAL debug_data_ram_empty  : std_logic
-"
-)
-)
-*167 (Net
+st "SIGNAL debug_data_ram_empty  : std_logic"
+)
+)
+*168 (Net
 uid 2713,0
 decl (Decl
@@ -5065 +5073 @@
 )
 xt "-90000,50200,-68000,51000"
-st "SIGNAL debug_data_valid      : std_logic
-"
-)
-)
-*168 (Net
+st "SIGNAL debug_data_valid      : std_logic"
+)
+)
+*169 (Net
 uid 2721,0
 decl (Decl
@@ -5087 +5094 @@
 xt "-90000,27000,-58500,28600"
 st "-- for debugging
-SIGNAL DG_state              : std_logic_vector(7 downto 0)
-"
-)
-)
-*169 (Net
+SIGNAL DG_state              : std_logic_vector(7 downto 0)"
+)
+)
+*170 (Net
 uid 2729,0
 decl (Decl
@@ -5105 +5111 @@
 )
 xt "-90000,30200,-68000,31000"
-st "SIGNAL FTM_RS485_rx_en       : std_logic
-"
-)
-)
-*170 (Net
+st "SIGNAL FTM_RS485_rx_en       : std_logic"
+)
+)
+*171 (Net
 uid 2737,0
 decl (Decl
@@ -5123 +5128 @@
 )
 xt "-90000,31000,-68000,31800"
-st "SIGNAL FTM_RS485_tx_d        : std_logic
-"
-)
-)
-*171 (Net
+st "SIGNAL FTM_RS485_tx_d        : std_logic"
+)
+)
+*172 (Net
 uid 2745,0
 decl (Decl
@@ -5141 +5145 @@
 )
 xt "-90000,31800,-68000,32600"
-st "SIGNAL FTM_RS485_tx_en       : std_logic
-"
-)
-)
-*172 (Net
+st "SIGNAL FTM_RS485_tx_en       : std_logic"
+)
+)
+*173 (Net
 uid 2753,0
 lang 2
@@ -5163 +5166 @@
 )
 xt "-90000,55000,-33000,55800"
-st "SIGNAL mem_manager_state     : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging.
-"
-)
-)
-*173 (Net
+st "SIGNAL mem_manager_state     : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging."
+)
+)
+*174 (Net
 uid 2761,0
 decl (Decl
@@ -5181 +5183 @@
 font "Courier New,8,0"
 )
-xt "-90000,61400,-55000,62200"
-st "SIGNAL trigger_veto          : std_logic                    := '1'
-"
-)
-)
-*174 (Net
+xt "-90000,62200,-55000,63000"
+st "SIGNAL trigger_veto          : std_logic                    := '1'"
+)
+)
+*175 (Net
 uid 2769,0
 decl (Decl
@@ -5202 +5203 @@
 font "Courier New,8,0"
 )
-xt "-90000,62200,-33000,63000"
-st "SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging.
-"
-)
-)
-*175 (Net
+xt "-90000,63000,-33000,63800"
+st "SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging."
+)
+)
+*176 (Net
 uid 2777,0
 decl (Decl
@@ -5221 +5221 @@
 )
 xt "-90000,29400,-68000,30200"
-st "SIGNAL FTM_RS485_rx_d        : std_logic
+st "SIGNAL FTM_RS485_rx_d        : std_logic"
+)
+)
+*177 (Net
+uid 2942,0
+decl (Decl
+n "socket_tx_free_out"
+t "std_logic_vector"
+b "(16 DOWNTO 0)"
+eolc "-- 17bit value .. that's true"
+posAdd 0
+o 55
+suid 64,0
+)
+declText (MLText
+uid 2943,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "-90000,60600,-43000,61400"
+st "SIGNAL socket_tx_free_out    : std_logic_vector(16 DOWNTO 0) -- 17bit value .. that's true"
+)
+)
+*178 (SaComponent
+uid 3285,0
+optionalChildren [
+*179 (CptPort
+uid 3073,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3074,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,19625,168750,20375"
+)
+tg (CPTG
+uid 3075,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3076,0
+va (VaSet
+)
+xt "163400,19500,167000,20500"
+st "wiz_reset"
+ju 2
+blo "167000,20300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wiz_reset"
+t "std_logic"
+o 50
+suid 2,0
+i "'1'"
+)
+)
+)
+*180 (CptPort
+uid 3077,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3078,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,65625,168750,66375"
+)
+tg (CPTG
+uid 3079,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3080,0
+va (VaSet
+)
+xt "163000,65500,167000,66500"
+st "led : (7:0)"
+ju 2
+blo "167000,66300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "led"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+posAdd 0
+o 38
+suid 7,0
+i "(OTHERS => '0')"
+)
+)
+)
+*181 (CptPort
+uid 3081,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3082,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,27625,140000,28375"
+)
+tg (CPTG
+uid 3083,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3084,0
+va (VaSet
+)
+xt "141000,27500,143800,28500"
+st "trigger"
+blo "141000,28300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "trigger"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 14
+suid 18,0
+)
+)
+)
+*182 (CptPort
+uid 3085,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3086,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,38625,140000,39375"
+)
+tg (CPTG
+uid 3087,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3088,0
+va (VaSet
+)
+xt "141000,38500,144200,39500"
+st "adc_oeb"
+blo "141000,39300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "adc_oeb"
+t "std_logic"
+o 26
+suid 21,0
+i "'1'"
+)
+)
+)
+*183 (CptPort
+uid 3089,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3090,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,29625,140000,30375"
+)
+tg (CPTG
+uid 3091,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3092,0
+va (VaSet
+)
+xt "141000,29500,146900,30500"
+st "board_id : (3:0)"
+blo "141000,30300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "board_id"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 10
+suid 24,0
+)
+)
+)
+*184 (CptPort
+uid 3093,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3094,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,30625,140000,31375"
+)
+tg (CPTG
+uid 3095,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3096,0
+va (VaSet
+)
+xt "141000,30500,146700,31500"
+st "crate_id : (1:0)"
+blo "141000,31300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "crate_id"
+t "std_logic_vector"
+b "(1 DOWNTO 0)"
+o 11
+suid 25,0
+)
+)
+)
+*185 (CptPort
+uid 3097,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3098,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,16625,168750,17375"
+)
+tg (CPTG
+uid 3099,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3100,0
+va (VaSet
+)
+xt "161000,16500,167000,17500"
+st "wiz_addr : (9:0)"
+ju 2
+blo "167000,17300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wiz_addr"
+t "std_logic_vector"
+b "(9 DOWNTO 0)"
+o 47
+suid 26,0
+)
+)
+)
+*186 (CptPort
+uid 3101,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 3102,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,17625,168750,18375"
+)
+tg (CPTG
+uid 3103,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3104,0
+va (VaSet
+)
+xt "160700,17500,167000,18500"
+st "wiz_data : (15:0)"
+ju 2
+blo "167000,18300"
+)
+)
+thePort (LogicalPort
+m 2
+decl (Decl
+n "wiz_data"
+t "std_logic_vector"
+b "(15 DOWNTO 0)"
+o 53
+suid 27,0
+)
+)
+)
+*187 (CptPort
+uid 3105,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3106,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,23625,168750,24375"
+)
+tg (CPTG
+uid 3107,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3108,0
+va (VaSet
+)
+xt "164300,23500,167000,24500"
+st "wiz_cs"
+ju 2
+blo "167000,24300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wiz_cs"
+t "std_logic"
+o 48
+suid 28,0
+i "'1'"
+)
+)
+)
+*188 (CptPort
+uid 3109,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3110,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,21625,168750,22375"
+)
+tg (CPTG
+uid 3111,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3112,0
+va (VaSet
+)
+xt "164300,21500,167000,22500"
+st "wiz_wr"
+ju 2
+blo "167000,22300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wiz_wr"
+t "std_logic"
+o 51
+suid 29,0
+i "'1'"
+)
+)
+)
+*189 (CptPort
+uid 3113,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3114,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,20625,168750,21375"
+)
+tg (CPTG
+uid 3115,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3116,0
+va (VaSet
+)
+xt "164400,20500,167000,21500"
+st "wiz_rd"
+ju 2
+blo "167000,21300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wiz_rd"
+t "std_logic"
+o 49
+suid 30,0
+i "'1'"
+)
+)
+)
+*190 (CptPort
+uid 3117,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3118,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,22625,168750,23375"
+)
+tg (CPTG
+uid 3119,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3120,0
+va (VaSet
+)
+xt "164300,22500,167000,23500"
+st "wiz_int"
+ju 2
+blo "167000,23300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "wiz_int"
+t "std_logic"
+o 15
+suid 31,0
+)
+)
+)
+*191 (CptPort
+uid 3121,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3122,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,18625,140000,19375"
+)
+tg (CPTG
+uid 3123,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3124,0
+va (VaSet
+)
+xt "141000,18500,145500,19500"
+st "CLK_25_PS"
+blo "141000,19300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "CLK_25_PS"
+t "std_logic"
+o 17
+suid 35,0
+)
+)
+)
+*192 (CptPort
+uid 3125,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3126,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,17625,140000,18375"
+)
+tg (CPTG
+uid 3127,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3128,0
+va (VaSet
+)
+xt "141000,17500,144100,18500"
+st "CLK_50"
+blo "141000,18300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "CLK_50"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 18
+suid 37,0
+)
+)
+)
+*193 (CptPort
+uid 3129,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3130,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,16625,140000,17375"
+)
+tg (CPTG
+uid 3131,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3132,0
+va (VaSet
+)
+xt "141000,16500,142900,17500"
+st "CLK"
+blo "141000,17300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "CLK"
+t "std_logic"
+o 1
+suid 38,0
+)
+)
+)
+*194 (CptPort
+uid 3133,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3134,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,37625,140000,38375"
+)
+tg (CPTG
+uid 3135,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3136,0
+va (VaSet
+)
+xt "141000,37500,149000,38500"
+st "adc_otr_array : (3:0)"
+blo "141000,38300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "adc_otr_array"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 9
+suid 40,0
+)
+)
+)
+*195 (CptPort
+uid 3137,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3138,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,43625,140000,44375"
+)
+tg (CPTG
+uid 3139,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3140,0
+va (VaSet
+)
+xt "141000,43500,146900,44500"
+st "adc_data_array"
+blo "141000,44300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "adc_data_array"
+t "adc_data_array_type"
+o 8
+suid 41,0
+)
+)
+)
+*196 (CptPort
+uid 3141,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3142,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,57625,140000,58375"
+)
+tg (CPTG
+uid 3143,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3144,0
+va (VaSet
+)
+xt "141000,57500,149500,58500"
+st "drs_channel_id : (3:0)"
+blo "141000,58300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_channel_id"
+t "std_logic_vector"
+b "(3 downto 0)"
+o 35
+suid 48,0
+i "(others => '0')"
+)
+)
+)
+*197 (CptPort
+uid 3145,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3146,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,62625,140000,63375"
+)
+tg (CPTG
+uid 3147,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3148,0
+va (VaSet
+)
+xt "141000,62500,145300,63500"
+st "drs_dwrite"
+blo "141000,63300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_dwrite"
+t "std_logic"
+o 36
+suid 49,0
+i "'1'"
+)
+)
+)
+*198 (CptPort
+uid 3149,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3150,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,53625,140000,54375"
+)
+tg (CPTG
+uid 3151,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3152,0
+va (VaSet
+)
+xt "141000,53500,146400,54500"
+st "SROUT_in_0"
+blo "141000,54300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "SROUT_in_0"
+t "std_logic"
+o 4
+suid 52,0
+)
+)
+)
+*199 (CptPort
+uid 3153,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3154,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,54625,140000,55375"
+)
+tg (CPTG
+uid 3155,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3156,0
+va (VaSet
+)
+xt "141000,54500,146400,55500"
+st "SROUT_in_1"
+blo "141000,55300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "SROUT_in_1"
+t "std_logic"
+o 5
+suid 53,0
+)
+)
+)
+*200 (CptPort
+uid 3157,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3158,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,55625,140000,56375"
+)
+tg (CPTG
+uid 3159,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3160,0
+va (VaSet
+)
+xt "141000,55500,146400,56500"
+st "SROUT_in_2"
+blo "141000,56300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "SROUT_in_2"
+t "std_logic"
+o 6
+suid 54,0
+)
+)
+)
+*201 (CptPort
+uid 3161,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3162,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,56625,140000,57375"
+)
+tg (CPTG
+uid 3163,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3164,0
+va (VaSet
+)
+xt "141000,56500,146400,57500"
+st "SROUT_in_3"
+blo "141000,57300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "SROUT_in_3"
+t "std_logic"
+o 7
+suid 55,0
+)
+)
+)
+*202 (CptPort
+uid 3165,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3166,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,59625,140000,60375"
+)
+tg (CPTG
+uid 3167,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3168,0
+va (VaSet
+)
+xt "141000,59500,145200,60500"
+st "RSRLOAD"
+blo "141000,60300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "RSRLOAD"
+t "std_logic"
+o 23
+suid 56,0
+i "'0'"
+)
+)
+)
+*203 (CptPort
+uid 3169,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3170,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,60625,140000,61375"
+)
+tg (CPTG
+uid 3171,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3172,0
+va (VaSet
+)
+xt "141000,60500,144000,61500"
+st "SRCLK"
+blo "141000,61300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "SRCLK"
+t "std_logic"
+o 24
+suid 57,0
+i "'0'"
+)
+)
+)
+*204 (CptPort
+uid 3173,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3174,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,46625,168750,47375"
+)
+tg (CPTG
+uid 3175,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3176,0
+va (VaSet
+)
+xt "165300,46500,167000,47500"
+st "sclk"
+ju 2
+blo "167000,47300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "sclk"
+t "std_logic"
+o 42
+suid 62,0
+)
+)
+)
+*205 (CptPort
+uid 3177,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 3178,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,47625,168750,48375"
+)
+tg (CPTG
+uid 3179,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3180,0
+va (VaSet
+)
+xt "165600,47500,167000,48500"
+st "sio"
+ju 2
+blo "167000,48300"
+)
+)
+thePort (LogicalPort
+m 2
+decl (Decl
+n "sio"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 52
+suid 63,0
+)
+)
+)
+*206 (CptPort
+uid 3181,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3182,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,35625,168750,36375"
+)
+tg (CPTG
+uid 3183,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3184,0
+va (VaSet
+)
+xt "164200,35500,167000,36500"
+st "dac_cs"
+ju 2
+blo "167000,36300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "dac_cs"
+t "std_logic"
+o 31
+suid 64,0
+)
+)
+)
+*207 (CptPort
+uid 3185,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3186,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,37625,168750,38375"
+)
+tg (CPTG
+uid 3187,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3188,0
+va (VaSet
+)
+xt "160500,37500,167000,38500"
+st "sensor_cs : (3:0)"
+ju 2
+blo "167000,38300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "sensor_cs"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 43
+suid 65,0
+)
+)
+)
+*208 (CptPort
+uid 3189,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3190,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,48625,168750,49375"
+)
+tg (CPTG
+uid 3191,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3192,0
+va (VaSet
+)
+xt "165000,48500,167000,49500"
+st "mosi"
+ju 2
+blo "167000,49300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "mosi"
+t "std_logic"
+o 40
+suid 66,0
+i "'0'"
+)
+)
+)
+*209 (CptPort
+uid 3193,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3194,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,61625,140000,62375"
+)
+tg (CPTG
+uid 3195,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3196,0
+va (VaSet
+)
+xt "141000,61500,144000,62500"
+st "denable"
+blo "141000,62300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "denable"
+t "std_logic"
+eolc "-- default domino wave off"
+posAdd 0
+o 34
+suid 67,0
+i "'0'"
+)
+)
+)
+*210 (CptPort
+uid 3197,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3198,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,67625,140000,68375"
+)
+tg (CPTG
+uid 3199,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3200,0
+va (VaSet
+)
+xt "141000,67500,144700,68500"
+st "SRIN_out"
+blo "141000,68300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "SRIN_out"
+t "std_logic"
+o 25
+suid 85,0
+i "'0'"
+)
+)
+)
+*211 (CptPort
+uid 3201,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3202,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,73625,168750,74375"
+)
+tg (CPTG
+uid 3203,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3204,0
+va (VaSet
+)
+xt "164600,73500,167000,74500"
+st "green"
+ju 2
+blo "167000,74300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "green"
+t "std_logic"
+o 37
+suid 86,0
+)
+)
+)
+*212 (CptPort
+uid 3205,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3206,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,75625,168750,76375"
+)
+tg (CPTG
+uid 3207,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3208,0
+va (VaSet
+)
+xt "164500,75500,167000,76500"
+st "amber"
+ju 2
+blo "167000,76300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "amber"
+t "std_logic"
+o 29
+suid 87,0
+)
+)
+)
+*213 (CptPort
+uid 3209,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3210,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,74625,168750,75375"
+)
+tg (CPTG
+uid 3211,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3212,0
+va (VaSet
+)
+xt "165500,74500,167000,75500"
+st "red"
+ju 2
+blo "167000,75300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "red"
+t "std_logic"
+o 41
+suid 88,0
+)
+)
+)
+*214 (CptPort
+uid 3213,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3214,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,70625,140000,71375"
+)
+tg (CPTG
+uid 3215,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3216,0
+va (VaSet
+)
+xt "141000,70500,146500,71500"
+st "D_T_in : (1:0)"
+blo "141000,71300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "D_T_in"
+t "std_logic_vector"
+b "(1 DOWNTO 0)"
+o 2
+suid 91,0
+)
+)
+)
+*215 (CptPort
+uid 3217,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3218,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,71625,140000,72375"
+)
+tg (CPTG
+uid 3219,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3220,0
+va (VaSet
+)
+xt "141000,71500,146100,72500"
+st "drs_refclk_in"
+blo "141000,72300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "drs_refclk_in"
+t "std_logic"
+eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
+o 12
+suid 92,0
+)
+)
+)
+*216 (CptPort
+uid 3221,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3222,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,72625,140000,73375"
+)
+tg (CPTG
+uid 3223,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3224,0
+va (VaSet
+)
+xt "141000,72500,147100,73500"
+st "plllock_in : (3:0)"
+blo "141000,73300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "plllock_in"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+eolc "-- high level, if dominowave is running and DRS PLL locked"
+o 13
+suid 93,0
+)
+)
+)
+*217 (CptPort
+uid 3225,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3226,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,72625,168750,73375"
+)
+tg (CPTG
+uid 3227,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3228,0
+va (VaSet
+)
+xt "158400,72500,167000,73500"
+st "counter_result : (11:0)"
+ju 2
+blo "167000,73300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "counter_result"
+t "std_logic_vector"
+b "(11 DOWNTO 0)"
+o 30
+suid 94,0
+)
+)
+)
+*218 (CptPort
+uid 3229,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3230,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,69625,168750,70375"
+)
+tg (CPTG
+uid 3231,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3232,0
+va (VaSet
+)
+xt "158400,69500,167000,70500"
+st "alarm_refclk_too_high"
+ju 2
+blo "167000,70300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "alarm_refclk_too_high"
+t "std_logic"
+o 27
+suid 95,0
+)
+)
+)
+*219 (CptPort
+uid 3233,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3234,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,70625,168750,71375"
+)
+tg (CPTG
+uid 3235,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3236,0
+va (VaSet
+)
+xt "158800,70500,167000,71500"
+st "alarm_refclk_too_low"
+ju 2
+blo "167000,71300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "alarm_refclk_too_low"
+t "std_logic"
+posAdd 0
+o 28
+suid 96,0
+)
+)
+)
+*220 (CptPort
+uid 3237,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3238,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,19625,140000,20375"
+)
+tg (CPTG
+uid 3239,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3240,0
+va (VaSet
+)
+xt "141000,19500,145000,20500"
+st "ADC_CLK"
+blo "141000,20300"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "ADC_CLK"
+t "std_logic"
+o 16
+suid 97,0
+)
+)
+)
+*221 (CptPort
+uid 3241,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3242,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,83625,168750,84375"
+)
+tg (CPTG
+uid 3243,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3244,0
+va (VaSet
+)
+xt "162100,83500,167000,84500"
+st "trigger_veto"
+ju 2
+blo "167000,84300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "trigger_veto"
+t "std_logic"
+o 45
+suid 98,0
+i "'1'"
+)
+)
+)
+*222 (CptPort
+uid 3245,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3246,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,73625,140000,74375"
+)
+tg (CPTG
+uid 3247,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3248,0
+va (VaSet
+)
+xt "141000,73500,148000,74500"
+st "FTM_RS485_rx_d"
+blo "141000,74300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "FTM_RS485_rx_d"
+t "std_logic"
+o 3
+suid 99,0
+)
+)
+)
+*223 (CptPort
+uid 3249,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3250,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,80625,168750,81375"
+)
+tg (CPTG
+uid 3251,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3252,0
+va (VaSet
+)
+xt "160100,80500,167000,81500"
+st "FTM_RS485_tx_d"
+ju 2
+blo "167000,81300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "FTM_RS485_tx_d"
+t "std_logic"
+o 21
+suid 100,0
+)
+)
+)
+*224 (CptPort
+uid 3253,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3254,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,79625,168750,80375"
+)
+tg (CPTG
+uid 3255,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3256,0
+va (VaSet
+)
+xt "159600,79500,167000,80500"
+st "FTM_RS485_rx_en"
+ju 2
+blo "167000,80300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "FTM_RS485_rx_en"
+t "std_logic"
+o 20
+suid 101,0
+)
+)
+)
+*225 (CptPort
+uid 3257,0
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+)
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+)
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+stg "RightVerticalLayoutStrategy"
+f (Text
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+va (VaSet
+)
+xt "159700,81500,167000,82500"
+st "FTM_RS485_tx_en"
+ju 2
+blo "167000,82300"
+)
+)
+thePort (LogicalPort
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+t "std_logic"
+o 22
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+)
+)
+)
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+)
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+)
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+)
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+st "w5300_state : (7:0)"
+ju 2
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+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "w5300_state"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+eolc "-- state is encoded here ... useful for debugging."
+posAdd 0
+o 46
+suid 103,0
+)
+)
+)
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+)
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+)
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+va (VaSet
+)
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+st "debug_data_ram_empty"
+ju 2
+blo "167000,77300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
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+t "std_logic"
+o 32
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+)
+)
+)
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+)
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+)
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+va (VaSet
+)
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+ju 2
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+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
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+t "std_logic"
+o 33
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+)
+)
+)
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+)
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+)
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+va (VaSet
+)
+xt "156600,82500,167000,83500"
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+ju 2
+blo "167000,83300"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "mem_manager_state"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+eolc "-- state is encoded here ... useful for debugging."
+posAdd 0
+o 39
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+)
+)
+)
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+)
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+)
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+f (Text
+uid 3280,0
+va (VaSet
+)
+xt "160800,78500,167000,79500"
+st "DG_state : (7:0)"
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+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "DG_state"
+t "std_logic_vector"
+b "(7 downto 0)"
+prec "-- for debugging"
+preAdd 0
+o 19
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+)
+)
+)
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+)
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+)
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+va (VaSet
+)
+xt "157100,85500,167000,86500"
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+)
+)
+thePort (LogicalPort
+m 1
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+t "std_logic_vector"
+b "(16 DOWNTO 0)"
+eolc "-- 17bit value .. that's true"
+posAdd 0
+o 44
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+)
+)
+)
+]
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+)
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+)
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+)
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+)
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+)
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+)
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+)
+xt "144200,82000,145200,83000"
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+)
+]
+)
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+)
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 "
 )
-)
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+)
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+)
+]
+)
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+)
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+)
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+)
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+)
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 ]
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@@ -5259 +7291 @@
 )
 )
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-)
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+)
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 )
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 sat 32
 eat 32
@@ -5297 +7329 @@
 )
 )
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-)
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+)
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 )
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 sat 32
 eat 32
@@ -5335 +7367 @@
 )
 )
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-)
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+)
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 )
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 sat 32
 eat 32
@@ -5371 +7403 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
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 )
 start &22
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 sat 32
 eat 32
@@ -5407 +7439 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -5426 +7458 @@
 )
 start &41
-end &82
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 sat 32
 eat 32
@@ -5447 +7479 @@
 )
 )
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-)
-*182 (Wire
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+)
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 shape (OrthoPolyLine
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 )
 start &38
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 sat 32
 eat 32
@@ -5483 +7515 @@
 )
 )
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-)
-*183 (Wire
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+)
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 )
 start &39
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 sat 32
 eat 32
@@ -5519 +7551 @@
 )
 )
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-)
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+)
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 ]
 )
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 end &15
 sat 32
@@ -5554 +7586 @@
 )
 )
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-)
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+)
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 )
 start &17
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 sat 32
 eat 2
@@ -5594 +7626 @@
 )
 )
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-)
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+)
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@@ -5613 +7645 @@
 )
 start &18
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 sat 32
 eat 2
@@ -5634 +7666 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -5653 +7685 @@
 )
 start &28
-end &109
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 sat 32
 eat 2
@@ -5674 +7706 @@
 )
 )
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-)
-*188 (Wire
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+)
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 shape (OrthoPolyLine
@@ -5693 +7725 @@
 )
 start &29
-end &109
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 sat 32
 eat 2
@@ -5714 +7746 @@
 )
 )
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-)
-*189 (Wire
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+)
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@@ -5732 +7764 @@
 )
 start &16
-end &109
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 sat 32
 eat 1
@@ -5752 +7784 @@
 )
 )
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-)
-*190 (Wire
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+)
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@@ -5767 +7799 @@
 ]
 )
-start &109
-end &105
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 sat 2
 eat 32
@@ -5787 +7819 @@
 )
 )
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-)
-*191 (Wire
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+)
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@@ -5802 +7834 @@
 ]
 )
-start &104
-end &109
+start &105
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 sat 32
 eat 1
@@ -5822 +7854 @@
 )
 )
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-)
-*192 (Wire
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+)
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 shape (OrthoPolyLine
@@ -5838 +7870 @@
 ]
 )
-start &103
-end &109
+start &104
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 sat 32
 eat 1
@@ -5859 +7891 @@
 )
 )
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-)
-*193 (Wire
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+)
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 shape (OrthoPolyLine
@@ -5874 +7906 @@
 ]
 )
-start &102
+start &103
 sat 32
 eat 16
@@ -5893 +7925 @@
 )
 )
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-)
-*194 (Wire
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+)
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 shape (OrthoPolyLine
@@ -5928 +7960 @@
 )
 )
-on &118
-)
-*195 (Wire
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+)
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 shape (OrthoPolyLine
@@ -5965 +7997 @@
 )
 )
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-)
-*196 (Wire
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+)
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 shape (OrthoPolyLine
@@ -5981 +8013 @@
 )
 start &21
-end &162
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 sat 32
 eat 32
@@ -6001 +8033 @@
 )
 )
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-)
-*197 (Wire
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+)
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@@ -6016 +8048 @@
 ]
 )
-start &161
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 end &24
 sat 32
@@ -6037 +8069 @@
 )
 )
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-)
-*198 (Wire
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+)
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@@ -6072 +8104 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -6107 +8139 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
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 )
 )
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-)
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+)
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 )
 )
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-)
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+)
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 shape (OrthoPolyLine
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 )
 )
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-)
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+)
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 )
 )
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-)
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+)
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@@ -6285 +8317 @@
 )
 )
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-)
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+)
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 )
 )
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-)
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+)
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@@ -6355 +8387 @@
 )
 )
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-)
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+)
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@@ -6390 +8422 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -6425 +8457 @@
 )
 )
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-)
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+)
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@@ -6460 +8492 @@
 )
 )
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-)
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+)
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@@ -6495 +8527 @@
 )
 )
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-)
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+)
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@@ -6530 +8562 @@
 )
 )
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-)
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+)
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@@ -6565 +8597 @@
 )
 )
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-)
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+)
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@@ -6600 +8632 @@
 )
 )
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-)
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+)
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 )
 )
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-)
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 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -6707 +8739 @@
 )
 )
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-)
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+)
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@@ -6742 +8774 @@
 )
 )
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-)
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+)
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@@ -6779 +8811 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -6796 +8828 @@
 ]
 )
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 end &49
 sat 32
@@ -6817 +8849 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -6832 +8864 @@
 ]
 )
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 sat 2
 eat 16
@@ -6852 +8884 @@
 )
 )
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-)
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+)
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@@ -6889 +8921 @@
 )
 )
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-)
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+)
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@@ -6904 +8936 @@
 ]
 )
-start &142
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 sat 2
 eat 16
@@ -6924 +8956 @@
 )
 )
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-)
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+)
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@@ -6959 +8991 @@
 )
 )
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-)
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 )
 )
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-)
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 )
 )
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-)
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 )
 )
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-)
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 )
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-)
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 )
 )
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-)
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 )
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-)
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-)
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-)
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 )
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-)
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@@ -7315 +9347 @@
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 )
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+)
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+)
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+"109750,90000"
+"124000,90000"
+]
+)
+start &65
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+)
+)
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 ]
@@ -7329 +9398 @@
 color "26368,26368,26368"
 )
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 blo "-87000,800"
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 va (VaSet
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@@ -7365 +9434 @@
 stg "VerticalLayoutStrategy"
 textVec [
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 va (VaSet
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 )
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@@ -7448 +9517 @@
 hasePageBreakOrigin 1
 pageBreakOrigin "-146000,0"
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 defaultCommentText (CommentText
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 fg "0,0,32768"
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 st "
 Text
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 stg "VerticalLayoutStrategy"
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 tm "BdLibraryNameMgr"
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 stg "VerticalLayoutStrategy"
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 va (VaSet
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 stg "VerticalLayoutStrategy"
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 va (VaSet
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-xt "0,-1100,7700,-100"
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 st "b0: BLOCK (guard)"
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 stg "VerticalLayoutStrategy"
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 blo "14100,20800"
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+n "socket_tx_free_out"
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-*397 (MRCItem
-litem &276
+*459 (MRCItem
+litem &336
 pos 6
 dimension 50
 uid 80,0
 )
-*398 (MRCItem
-litem &277
+*460 (MRCItem
+litem &337
 pos 7
 dimension 80
@@ -9649 +11739 @@
 genericsCommonDM (CommonDM
 ldm (LogicalDM
-emptyRow *399 (LEmptyRow
+emptyRow *461 (LEmptyRow
 )
 uid 83,0
 optionalChildren [
-*400 (RefLabelRowHdr
-)
-*401 (TitleRowHdr
-)
-*402 (FilterRowHdr
-)
-*403 (RefLabelColHdr
+*462 (RefLabelRowHdr
+)
+*463 (TitleRowHdr
+)
+*464 (FilterRowHdr
+)
+*465 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*404 (RowExpandColHdr
+*466 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*405 (GroupColHdr
+*467 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*406 (NameColHdr
+*468 (NameColHdr
 tm "GenericNameColHdrMgr"
 )
-*407 (TypeColHdr
+*469 (TypeColHdr
 tm "GenericTypeColHdrMgr"
 )
-*408 (InitColHdr
+*470 (InitColHdr
 tm "GenericValueColHdrMgr"
 )
-*409 (PragmaColHdr
+*471 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
 )
-*410 (EolColHdr
+*472 (EolColHdr
 tm "GenericEolColHdrMgr"
 )
@@ -9690 +11780 @@
 uid 95,0
 optionalChildren [
-*411 (Sheet
+*473 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -9707 +11797 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *412 (MRCItem
-litem &399
+emptyMRCItem *474 (MRCItem
+litem &461
 pos 0
 dimension 20
@@ -9714 +11804 @@
 uid 97,0
 optionalChildren [
-*413 (MRCItem
-litem &400
+*475 (MRCItem
+litem &462
 pos 0
 dimension 20
 uid 98,0
 )
-*414 (MRCItem
-litem &401
+*476 (MRCItem
+litem &463
 pos 1
 dimension 23
 uid 99,0
 )
-*415 (MRCItem
-litem &402
+*477 (MRCItem
+litem &464
 pos 2
 hidden 1
@@ -9744 +11834 @@
 uid 101,0
 optionalChildren [
-*416 (MRCItem
-litem &403
+*478 (MRCItem
+litem &465
 pos 0
 dimension 20
 uid 102,0
 )
-*417 (MRCItem
-litem &405
+*479 (MRCItem
+litem &467
 pos 1
 dimension 50
 uid 103,0
 )
-*418 (MRCItem
-litem &406
+*480 (MRCItem
+litem &468
 pos 2
 dimension 100
 uid 104,0
 )
-*419 (MRCItem
-litem &407
+*481 (MRCItem
+litem &469
 pos 3
 dimension 100
 uid 105,0
 )
-*420 (MRCItem
-litem &408
+*482 (MRCItem
+litem &470
 pos 4
 dimension 50
 uid 106,0
 )
-*421 (MRCItem
-litem &409
+*483 (MRCItem
+litem &471
 pos 5
 dimension 50
 uid 107,0
 )
-*422 (MRCItem
-litem &410
+*484 (MRCItem
+litem &472
 pos 6
 dimension 80