- Timestamp:
- 06/09/11 19:35:20 (13 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 10 edited
-
data_generator.vhd (modified) (1 diff)
-
fad_board.ucf (modified) (1 diff)
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fad_board_struct.vhd (modified) (10 diffs)
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fad_definitions.vhd (modified) (1 diff)
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fad_main_struct.vhd (modified) (8 diffs)
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memory_manager_2.vhd (modified) (1 diff)
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spi_controller_beha.vhd (modified) (5 diffs)
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spi_distributor_beha.vhd (modified) (6 diffs)
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spi_interface_struct.vhd (modified) (7 diffs)
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w5300_modul.vhd (modified) (14 diffs)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10883 r10957 389 389 when WRITE_CHANNEL_ID => -- write DRS and Channel IDs 390 390 state_sig <= X"1B"; 391 data_out <= conv_std_logic_vector(3,12) & conv_std_logic_vector(channel_id,4) & 391 data_out <= conv_std_logic_vector(3,12) & conv_std_logic_vector(channel_id,4) & 392 392 conv_std_logic_vector(2,12) & conv_std_logic_vector(channel_id,4) & 393 393 conv_std_logic_vector(1,12) & conv_std_logic_vector(channel_id,4) & -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf
r10883 r10957 83 83 #NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; #ok 84 84 # Testpoint near W5300 85 #NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok86 #NET W_T<2> LOC = N21 | IOSTANDARD=LVCMOS33; #ok87 #NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; #ok88 #NET W_T<0> LOC = K21 | IOSTANDARD=LVCMOS33; #ok85 NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok 86 NET W_T<2> LOC = N21 | IOSTANDARD=LVCMOS33; #ok 87 NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; #ok 88 NET W_T<0> LOC = K21 | IOSTANDARD=LVCMOS33; #ok 89 89 90 90 # Platform Flash - serial connection -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10908 r10957 2 2 -- 3 3 -- Created: 4 -- by - d neise.UNKNOWN (E5B-LABOR6)5 -- at - 1 4:33:27 03.06.20116 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 16:56:38 09.06.2011 6 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 8 8 -- 9 9 LIBRARY ieee; … … 30 30 W_INT : IN std_logic; 31 31 X_50M : IN STD_LOGIC; 32 A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');33 A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');32 A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 33 A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 34 34 AMBER_LED : OUT std_logic; 35 35 A_CLK : OUT std_logic_vector (3 DOWNTO 0); 36 36 DAC_CS : OUT std_logic; 37 DENABLE : OUT std_logic := '0';38 DSRCLK : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');39 DWRITE : OUT std_logic := '0';40 D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');41 D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');42 D_T2 : OUT std_logic_vector (1 DOWNTO 0) := (others => '0');37 DENABLE : OUT std_logic := '0'; 38 DSRCLK : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 39 DWRITE : OUT std_logic := '0'; 40 D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 41 D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 42 D_T2 : OUT std_logic_vector (1 DOWNTO 0) := (others => '0'); 43 43 EE_CS : OUT std_logic; 44 44 GREEN_LED : OUT std_logic; 45 MOSI : OUT std_logic := '0';45 MOSI : OUT std_logic := '0'; 46 46 OE_ADC : OUT STD_LOGIC; 47 47 RED_LED : OUT std_logic; … … 52 52 RS485_E_DO : OUT std_logic; 53 53 RS485_E_RE : OUT std_logic; 54 RSRLOAD : OUT std_logic := '0';55 SRIN : OUT std_logic := '0';54 RSRLOAD : OUT std_logic := '0'; 55 SRIN : OUT std_logic := '0'; 56 56 S_CLK : OUT std_logic; 57 57 TCS : OUT std_logic_vector (3 DOWNTO 0); 58 TRG_V : OUT std_logic := '0';58 TRG_V : OUT std_logic := '0'; 59 59 W_A : OUT std_logic_vector (9 DOWNTO 0); 60 W_CS : OUT std_logic := '1'; 61 W_RD : OUT std_logic := '1'; 62 W_RES : OUT std_logic := '1'; 63 W_WR : OUT std_logic := '1'; 60 W_CS : OUT std_logic := '1'; 61 W_RD : OUT std_logic := '1'; 62 W_RES : OUT std_logic := '1'; 63 W_T : OUT std_logic_vector ( 3 DOWNTO 0 ) := (others => '0'); 64 W_WR : OUT std_logic := '1'; 64 65 MISO : INOUT std_logic; 65 66 W_D : INOUT std_logic_vector (15 DOWNTO 0) … … 74 75 -- 75 76 -- Created: 76 -- by - d neise.UNKNOWN (E5B-LABOR6)77 -- at - 1 4:33:27 03.06.201178 -- 79 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)77 -- by - daqct3.UNKNOWN (IHP110) 78 -- at - 16:56:38 09.06.2011 79 -- 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 80 81 -- 81 82 LIBRARY ieee; … … 106 107 SIGNAL counter_result : std_logic_vector(11 DOWNTO 0) := (others => '0'); 107 108 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); 109 SIGNAL dac_cs1 : std_logic; 108 110 SIGNAL debug_data_ram_empty : std_logic; 109 111 SIGNAL debug_data_valid : std_logic; 110 112 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 111 113 SIGNAL mem_manager_state : std_logic_vector(3 DOWNTO 0); -- state is encoded here ... useful for debugging. 114 SIGNAL mosi1 : std_logic; 115 SIGNAL sclk : std_logic; 116 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); 112 117 SIGNAL socket_tx_free_out : std_logic_vector(16 DOWNTO 0); -- 17bit value .. that's true 113 118 SIGNAL w5300_state : std_logic_vector(7 DOWNTO 0); -- state is encoded here ... useful for debugging. 119 120 -- Implicit buffer signal declarations 121 SIGNAL TRG_V_internal : std_logic; 114 122 115 123 … … 209 217 --D_T <= (others => '0'); 210 218 D_T <= w5300_state; 211 D_T2(0) <= debug_data_valid; 212 --D_T2(1) <= debug_data_ram_empty; 213 D_T2(1) <= socket_tx_free_out(16); 219 --D_T2(0) <= debug_data_valid; 220 D_T2(0) <= debug_data_ram_empty; 221 --D_T2(1) <= socket_tx_free_out(16); 222 223 D_T2(1) <= TRG_V_internal; 214 224 --D_T2 <= ( others => '0' ); 215 225 216 226 227 A0_T <= (others => '0'); 228 A1_T <= (others => '1'); 217 229 218 230 219 231 --A0_T <= DG_state; 220 --A1_T(3 downto 0) <= mem_manager_state;232 W_T(3 downto 0) <= mem_manager_state; 221 233 --A1_T(7 downto 4) <= "1100"; 222 234 223 A0_T <= socket_tx_free_out(7 downto 0); 224 A1_T <= socket_tx_free_out(15 downto 8); 235 --A0_T <= socket_tx_free_out(7 downto 0); 236 --A0_T <= spi_debug_16bit(7 downto 0); 237 --A1_T <= spi_debug_16bit(15 downto 8); 238 --A1_T <= socket_tx_free_out(15 downto 8); 239 240 -- check SPI interfac 241 --A1_T(7) <= sclk; 242 --A1_T(6) <= MISO; 243 --A1_T(5) <= mosi1; 244 245 --A1_T(4) <= dac_cs1; 246 --A1_T( 3 downto 0) <= sensor_cs; 247 225 248 226 249 --D_T(3 downto 0) <= counter_result ( 11 downto 8); … … 242 265 EE_CS <= '1'; 243 266 267 268 -- ModuleWare code(v1.9) for instance 'I0' of 'assignment' 269 DAC_CS <= dac_cs1; 270 271 -- ModuleWare code(v1.9) for instance 'I1' of 'assignment' 272 TCS <= sensor_cs; 273 274 -- ModuleWare code(v1.9) for instance 'I2' of 'assignment' 275 S_CLK <= sclk; 276 277 -- ModuleWare code(v1.9) for instance 'I3' of 'assignment' 278 MOSI <= mosi1; 244 279 245 280 -- Instance port mappings. … … 279 314 amber => AMBER_LED, 280 315 counter_result => counter_result, 281 dac_cs => DAC_CS,316 dac_cs => dac_cs1, 282 317 debug_data_ram_empty => debug_data_ram_empty, 283 318 debug_data_valid => debug_data_valid, … … 288 323 led => led, 289 324 mem_manager_state => mem_manager_state, 290 mosi => MOSI,325 mosi => mosi1, 291 326 red => GREEN_LED, 292 sclk => S_CLK,293 sensor_cs => TCS,327 sclk => sclk, 328 sensor_cs => sensor_cs, 294 329 socket_tx_free_out => socket_tx_free_out, 295 trigger_veto => TRG_V ,330 trigger_veto => TRG_V_internal, 296 331 w5300_state => w5300_state, 297 332 wiz_addr => W_A, … … 304 339 ); 305 340 341 -- Implicit buffered output assignments 342 TRG_V <= TRG_V_internal; 343 306 344 END struct; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10908 r10957 195 195 -- for W5300 modul2 196 196 constant W5300_RAM_ADDR_WIDTH : integer := 17; 197 constant TX_FIFO_MAX_FREE : std_logic_vector(16 downto 0) := conv_std_logic_vector(15360 ,1 6);197 constant TX_FIFO_MAX_FREE : std_logic_vector(16 downto 0) := conv_std_logic_vector(15360 ,17); 198 198 199 199 -- not needed -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10908 r10957 2 2 -- 3 3 -- Created: 4 -- by - d neise.UNKNOWN (E5B-LABOR6)5 -- at - 1 4:33:25 03.06.20114 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 16:56:36 09.06.2011 6 6 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 8 8 -- 9 9 LIBRARY ieee; … … 82 82 -- 83 83 -- Created: 84 -- by - d neise.UNKNOWN (E5B-LABOR6)85 -- at - 1 4:33:26 03.06.201184 -- by - daqct3.UNKNOWN (IHP110) 85 -- at - 16:56:37 09.06.2011 86 86 -- 87 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)87 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 88 88 -- 89 89 library ieee; … … 100 100 USE IEEE.std_logic_signed.all; 101 101 USE fact_fad_lib.fad_rs485_constants.all; 102 LIBRARY hds_package_library; 103 USE hds_package_library.random_generators.all; 102 104 103 105 LIBRARY FACT_FAD_lib; … … 144 146 SIGNAL dout3 : STD_LOGIC; 145 147 SIGNAL dout4 : STD_LOGIC; 148 SIGNAL dout5 : std_logic; 146 149 SIGNAL drs_clk_en : std_logic := '0'; 147 150 SIGNAL drs_read_s_cell : std_logic := '0'; … … 199 202 SIGNAL trigger_or_s_trigger : std_logic; 200 203 SIGNAL trigger_out : std_logic; 204 SIGNAL trigger_veto1 : std_logic := '1'; 201 205 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); 202 206 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); … … 626 630 din1 <= NOT(alarm_refclk_too_low_internal); 627 631 632 -- ModuleWare code(v1.9) for instance 'inverter_2' of 'inv' 633 dout5 <= NOT(ram_write_ea); 634 628 635 -- ModuleWare code(v1.9) for instance 'U_2' of 'or' 629 636 dout4 <= dout OR I_really_want_dwrite; … … 631 638 -- ModuleWare code(v1.9) for instance 'or_1' of 'or' 632 639 s_trigger_or_cont_trigger <= s_trigger OR cont_trigger; 640 641 -- ModuleWare code(v1.9) for instance 'or_2' of 'or' 642 trigger_veto <= trigger_veto1 OR dout5; 633 643 634 644 -- ModuleWare code(v1.9) for instance 'or_5' of 'or' … … 780 790 drs_s_cell_array => drs_s_cell_array, 781 791 drs_readout_started => drs_readout_started, 782 trigger_veto => trigger_veto 792 trigger_veto => trigger_veto1 783 793 ); 784 794 dna_gen_instance : dna_gen -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_2.vhd
r10889 r10957 360 360 wiz_write_header <= '0'; 361 361 end if; 362 362 363 if (package_index = (number_of_packages - 1)) then 363 364 -- last package -> write end-flag -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_controller_beha.vhd
r10729 r10957 18 18 miso : INOUT std_logic := 'Z'; 19 19 mosi : OUT std_logic := '0'; 20 dac_cs : OUT std_logic := '1'; 21 sensor_cs : OUT std_logic_vector (3 DOWNTO 0) := (others => '1'); 22 20 23 dac_id : IN std_logic_vector (2 DOWNTO 0); 21 24 sensor_id : IN std_logic_vector (1 downto 0); 22 25 data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 23 dac_cs : OUT std_logic := '1';24 sensor_cs : OUT std_logic_vector (3 DOWNTO 0) := (others => '1');26 measured_temp_data : out std_logic_vector (15 DOWNTO 0) := (others => '0'); 27 25 28 dac_start : IN std_logic; 26 29 dac_ready : OUT std_logic := '0'; 27 30 sensor_start : IN std_logic; 28 sensor_valid : OUT std_logic := '0' 31 sensor_valid : OUT std_logic := '0'; 32 spi_channel_ready : OUT std_logic := '1' 29 33 ); 30 34 END spi_controller ; … … 58 62 case spi_state is 59 63 when SPI_IDLE => 64 spi_channel_ready <= '1'; 60 65 if (dac_start_sr(1) = '1') then 66 spi_channel_ready <= '0'; 61 67 dac_ready <= '0'; 62 68 spi_state <= SPI_LOAD_COMMAND; 63 69 elsif (sensor_start_sr(1) = '1') then 70 spi_channel_ready <= '0'; 64 71 sensor_valid <= '0'; 65 72 spi_state <= SPI_LOAD_COMMAND; … … 68 75 when SPI_LOAD_COMMAND => 69 76 spi_cycle_cnt <= 0; 77 spi_channel_ready <= '0'; 78 70 79 if (sensor_start_sr(1) = '1') then 71 shift_reg <= X"C1" & X"0000"; -- command: Temperature register read 80 81 --shift_reg <= X"C1" & X"0000"; -- command: Temperature register read 82 shift_reg <= X"C1" & "ZZZZZZZZZZZZZZZZ"; -- command: Temperature register read 72 83 spi_state <= SPI_GET_TEMP; 73 84 elsif (dac_start_sr(1) = '1') then … … 78 89 -- start temperature sensor read 79 90 when SPI_GET_TEMP => 80 if (spi_cycle_cnt < 24) then -- must be on more cause MAX6662 provides data on falling edge91 if (spi_cycle_cnt < 24) then -- must be one more cause MAX6662 provides data on falling edge 81 92 sensor_cs(conv_integer(sensor_id)) <= '0'; 82 93 sensor_valid <= '0'; … … 87 98 end if; 88 99 else 89 data <= data_reg; 100 data <= data_reg; 101 measured_temp_data <= data_reg; 90 102 sensor_valid <= '1'; 91 103 spi_state <= SPI_IDLE; 92 104 end if; 93 105 94 106 -- start loading DACs 95 107 when SPI_LOAD_DAC => -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_distributor_beha.vhd
r10738 r10957 26 26 27 27 PORT( 28 clk : IN std_logic; -- 50MHz 28 clk : IN std_logic; 29 30 -- interface nach aussen 29 31 config_start : IN std_logic; 30 32 config_ready : OUT std_logic := '1'; 33 34 dac_array : IN dac_array_type; 35 current_dac_array : OUT dac_array_type := ( others => 0); 36 sensor_array : OUT sensor_array_type; 31 37 sensor_valid : OUT std_logic := '0'; 32 dac_array : IN dac_array_type; 33 current_dac_array : OUT dac_array_type := ( others => 0); 34 sensor_array : OUT sensor_array_type; 38 39 40 sensor_read_start : OUT std_logic := '0'; 41 sensor_read_valid : IN std_logic; 35 42 dac_config_start : OUT std_logic := '0'; 36 43 dac_config_ready : IN std_logic; 37 sclk_enable_override : OUT std_logic := '0';38 sensor_read_start : OUT std_logic := '0';39 sensor_read_valid : IN std_logic;44 spi_channel_ready : IN std_logic; 45 46 sclk_enable_override : OUT std_logic := '0'; 40 47 dac_id : OUT std_logic_vector(2 downto 0) := (others => '0'); 41 48 sensor_id : OUT std_logic_vector(1 downto 0) := (others => '0'); 42 data : INOUT std_logic_vector(15 downto 0) := (others => 'Z') 49 data : INOUT std_logic_vector(15 downto 0) := (others => 'Z'); 50 measured_temp_data : IN std_logic_vector(15 downto 0) 43 51 ); 44 52 END ENTITY spi_distributor; … … 46 54 ARCHITECTURE beha OF spi_distributor IS 47 55 48 type TYPE_SPI_DISTRIBUTION_STATE is (INIT, IDLE, READ_SENSOR, CONFIG_DAC); 56 type TYPE_SPI_DISTRIBUTION_STATE is (INIT, IDLE, 57 PRE_READ_SENSOR, 58 SENSOR_READ_START_ACK, 59 READ_SENSOR, 60 PRE_CONFIG_DAC, 61 DAC_CONFIG_START_ACK, 62 CONFIG_DAC); 49 63 50 64 signal spi_distr_state : TYPE_SPI_DISTRIBUTION_STATE := INIT; … … 61 75 signal config_start_sr : std_logic_vector (1 downto 0) := "00"; 62 76 77 78 signal sensor_read_valid_sr : std_logic_vector (1 downto 0) := "00"; 79 signal dac_config_ready_sr : std_logic_vector (1 downto 0) := "00"; 80 signal spi_channel_ready_sr : std_logic_vector (1 downto 0) := "00"; 81 63 82 BEGIN 64 83 sclk_enable_override <= sclk_enable_override_sig; … … 69 88 70 89 if rising_edge(clk) then 90 sensor_read_valid_sr <= sensor_read_valid_sr(0) & sensor_read_valid; 91 dac_config_ready_sr <= dac_config_ready_sr(0) & dac_config_ready; 92 spi_channel_ready_sr <= spi_channel_ready_sr(0) & spi_channel_ready; 71 93 -- synch in 72 94 config_start_sr <= config_start_sr(0) & config_start; … … 77 99 data <= (others => 'Z'); 78 100 int_sensor_valid <= '0'; 79 spi_distr_state <= READ_SENSOR; 101 spi_distr_state <= PRE_READ_SENSOR; 102 80 103 when IDLE => 81 104 sclk_enable_override_sig <= '0'; … … 87 110 -- start DAC configuration 88 111 if (config_start_sr(1) = '1' AND int_sensor_valid = '1') then 89 config_ready <= '0'; 112 internal_dac_array <= dac_array; 113 spi_distr_state <= PRE_CONFIG_DAC; 114 -- start temperature sensor reading 115 elsif (dac_config_ready <= '1' AND int_sensor_read_start = '1' ) then 116 spi_distr_state <= PRE_READ_SENSOR; 117 end if; 118 119 when PRE_READ_SENSOR => 120 121 int_sensor_valid <= '0'; 122 sensor_read_start <= '1'; 123 sensor_id <= conv_std_logic_vector(sensor_id_cnt, sensor_id'length); 124 spi_distr_state <= SENSOR_READ_START_ACK; 125 126 when SENSOR_READ_START_ACK => 127 if (spi_channel_ready_sr(1) = '0') then 128 sensor_read_start <= '0'; 129 spi_distr_state <= READ_SENSOR; 130 end if; 131 132 when PRE_CONFIG_DAC => 133 config_ready <= '0'; 90 134 sclk_enable_override_sig <= '1'; 91 135 dac_config_start <= '1'; 92 136 dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); 93 data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); 94 internal_dac_array <= dac_array; 95 spi_distr_state <= CONFIG_DAC; 96 -- start temperature sensor reading 97 elsif (dac_config_ready <= '1' AND int_sensor_read_start = '1') then 98 int_sensor_valid <= '0'; 99 sensor_read_start <= '1'; 100 sensor_id <= conv_std_logic_vector(sensor_id_cnt, sensor_id'length); 101 spi_distr_state <= READ_SENSOR; 102 end if; 103 137 data <= conv_std_logic_vector(internal_dac_array(dac_id_cnt),data'length); 138 spi_distr_state <= DAC_CONFIG_START_ACK; 139 140 141 when DAC_CONFIG_START_ACK => 142 dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); 143 data <= conv_std_logic_vector(internal_dac_array(dac_id_cnt),data'length); 144 145 if (spi_channel_ready_sr(1) = '0') then 146 dac_config_start <= '0'; 147 spi_distr_state <= CONFIG_DAC; 148 end if; 149 104 150 -- sensor reading 105 151 when READ_SENSOR => 106 sensor_read_start <= '1'; 107 sensor_id <= conv_std_logic_vector(sensor_id_cnt, sensor_id'length); 108 if (sensor_read_valid = '1') then 109 int_sensor_array(sensor_id_cnt) <= conv_integer(data); 110 sensor_read_start <= '0'; 111 if (sensor_id_cnt < 3) then 112 sensor_id_cnt <= sensor_id_cnt + 1; 113 sensor_read_start <= '1'; 114 spi_distr_state <= READ_SENSOR; 115 else 116 sensor_id_cnt <= 0; 117 sensor_valid <= '0'; 118 int_sensor_valid <= '1'; 119 spi_distr_state <= IDLE; 120 end if; 121 end if; 122 152 153 if (sensor_read_valid_sr(1) = '1') then 154 int_sensor_array(sensor_id_cnt) <= conv_integer(measured_temp_data); 155 --sensor_read_start <= '0'; 156 if (sensor_id_cnt < 3) then 157 sensor_id_cnt <= sensor_id_cnt + 1; 158 --sensor_read_start <= '1'; 159 spi_distr_state <= PRE_READ_SENSOR; 160 else 161 sensor_id_cnt <= 0; 162 sensor_valid <= '0'; 163 int_sensor_valid <= '1'; 164 spi_distr_state <= IDLE; 165 end if; 166 end if; 167 168 169 170 123 171 -- DAC configuration 124 172 when CONFIG_DAC => 125 dac_config_start <= '1'; 126 dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); 127 data <= conv_std_logic_vector(internal_dac_array(dac_id_cnt),data'length); 128 if (dac_config_ready = '1') then 129 dac_config_start <= '0'; 173 --dac_config_start <= '1'; 174 --dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); 175 --data <= conv_std_logic_vector(internal_dac_array(dac_id_cnt),data'length); 176 --if (dac_config_ready = '1') then 177 if (spi_channel_ready_sr(1) = '1') then 178 --dac_config_start <= '0'; 130 179 if (dac_id_cnt < 7) then 131 180 dac_id_cnt <= dac_id_cnt + 1; 132 dac_config_start <= '1';133 spi_distr_state <= CONFIG_DAC;181 --dac_config_start <= '1'; 182 spi_distr_state <= PRE_CONFIG_DAC; 134 183 else 135 184 dac_id_cnt <= 0; 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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd
r10900 r10957 2 2 -- 3 3 -- Created: 4 -- by - d neise.UNKNOWN (E5B-LABOR6)5 -- at - 1 3:20:48 01.06.20116 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 16:56:36 09.06.2011 6 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 8 8 -- 9 9 LIBRARY ieee; … … 38 38 -- 39 39 -- Created: 40 -- by - d neise.UNKNOWN (E5B-LABOR6)41 -- at - 1 3:20:48 01.06.201142 -- 43 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 2 (Build 10)40 -- by - daqct3.UNKNOWN (IHP110) 41 -- at - 16:56:36 09.06.2011 42 -- 43 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) 44 44 -- 45 45 LIBRARY ieee; … … 59 59 -- Internal signal declarations 60 60 SIGNAL T_sensor_start : std_logic; 61 SIGNAL clk_2Mhz : std_logic := '0';61 SIGNAL clk_2Mhz : std_logic := '0'; 62 62 SIGNAL dac_config_ready : std_logic; 63 63 SIGNAL dac_config_start : std_logic; 64 64 SIGNAL dac_id : std_logic_vector(2 DOWNTO 0); 65 65 SIGNAL data : std_logic_vector(15 DOWNTO 0); 66 SIGNAL sclk_enable_override : std_logic := '0'; 67 SIGNAL sclk_enable_sig : std_logic := '0'; 66 SIGNAL measured_temp_data : std_logic_vector(15 DOWNTO 0) := (others => '0'); 67 SIGNAL sclk_enable_override : std_logic := '0'; 68 SIGNAL sclk_enable_sig : std_logic := '0'; 68 69 SIGNAL sensor_id : std_logic_vector(1 DOWNTO 0); 69 70 SIGNAL sensor_start : std_logic; 70 71 SIGNAL sensor_valid : std_logic; 72 SIGNAL spi_channel_ready : std_logic := '1'; 71 73 72 74 -- Implicit buffer signal declarations … … 86 88 COMPONENT spi_controller 87 89 PORT ( 88 clk : IN std_logic; 89 dac_id : IN std_logic_vector (2 DOWNTO 0); 90 dac_start : IN std_logic; 91 sensor_id : IN std_logic_vector (1 DOWNTO 0); 92 sensor_start : IN std_logic; 93 dac_cs : OUT std_logic := '1'; 94 dac_ready : OUT std_logic := '0'; 95 mosi : OUT std_logic := '0'; 96 sensor_cs : OUT std_logic_vector (3 DOWNTO 0) := (others => '1'); 97 sensor_valid : OUT std_logic := '0'; 98 data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 99 miso : INOUT std_logic := 'Z' 90 clk : IN std_logic; 91 dac_id : IN std_logic_vector (2 DOWNTO 0); 92 dac_start : IN std_logic; 93 sensor_id : IN std_logic_vector (1 DOWNTO 0); 94 sensor_start : IN std_logic; 95 dac_cs : OUT std_logic := '1'; 96 dac_ready : OUT std_logic := '0'; 97 measured_temp_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 98 mosi : OUT std_logic := '0'; 99 sensor_cs : OUT std_logic_vector (3 DOWNTO 0) := (others => '1'); 100 sensor_valid : OUT std_logic := '0'; 101 spi_channel_ready : OUT std_logic := '1'; 102 data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 103 miso : INOUT std_logic := 'Z' 100 104 ); 101 105 END COMPONENT; … … 109 113 dac_array : IN dac_array_type; 110 114 dac_config_ready : IN std_logic; 115 measured_temp_data : IN std_logic_vector (15 DOWNTO 0); 111 116 sensor_read_valid : IN std_logic; 112 config_ready : OUT std_logic := '0'; 117 spi_channel_ready : IN std_logic; 118 config_ready : OUT std_logic := '1'; 113 119 current_dac_array : OUT dac_array_type := ( others => 0); 114 120 dac_config_start : OUT std_logic := '0'; … … 158 164 I_spi_controller : spi_controller 159 165 PORT MAP ( 160 clk => sclk_internal, 161 miso => miso, 162 mosi => mosi, 163 dac_id => dac_id, 164 sensor_id => sensor_id, 165 data => data, 166 dac_cs => dac_cs, 167 sensor_cs => sensor_cs, 168 dac_start => dac_config_start, 169 dac_ready => dac_config_ready, 170 sensor_start => sensor_start, 171 sensor_valid => sensor_valid 166 clk => sclk_internal, 167 miso => miso, 168 mosi => mosi, 169 dac_cs => dac_cs, 170 sensor_cs => sensor_cs, 171 dac_id => dac_id, 172 sensor_id => sensor_id, 173 data => data, 174 measured_temp_data => measured_temp_data, 175 dac_start => dac_config_start, 176 dac_ready => dac_config_ready, 177 sensor_start => sensor_start, 178 sensor_valid => sensor_valid, 179 spi_channel_ready => spi_channel_ready 172 180 ); 173 181 I_spi_distributor : spi_distributor … … 179 187 config_start => config_start, 180 188 config_ready => config_ready, 181 sensor_valid => sensor_ready,182 189 dac_array => dac_array, 183 190 current_dac_array => current_dac_array, 184 191 sensor_array => sensor_array, 192 sensor_valid => sensor_ready, 193 sensor_read_start => sensor_start, 194 sensor_read_valid => sensor_valid, 185 195 dac_config_start => dac_config_start, 186 196 dac_config_ready => dac_config_ready, 197 spi_channel_ready => spi_channel_ready, 187 198 sclk_enable_override => sclk_enable_override, 188 sensor_read_start => sensor_start,189 sensor_read_valid => sensor_valid,190 199 dac_id => dac_id, 191 200 sensor_id => sensor_id, 192 data => data 201 data => data, 202 measured_temp_data => measured_temp_data 193 203 ); 194 204 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10908 r10957 124 124 WORKAROUND_CHECK_FIFO_SPACE_01, WORKAROUND_CHECK_FIFO_SPACE_02, WORKAROUND_CHECK_FIFO_SPACE_03, WORKAROUND_CHECK_FIFO_SPACE_04, 125 125 WR_05a, WR_05b, WR_06, WR_07, 126 WR_ACK, WR_WAIT_FOR_ACK, 126 WR_ACK, WR_WAIT_FOR_ACK, WAIT_FOR_DATA_VALID_HIGH_AGAIN, 127 127 WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, 128 128 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3 … … 196 196 signal local_fifo_channels : std_logic_vector (3 downto 0); 197 197 198 signal wait_100ns_sig : std_logic_vector ( 2 downto 0) := "000";199 200 signal config_addr : integer range 0 to 4 4;201 type config_data_type is array (0 to 4 6) of std_logic_vector(15 downto 0);198 signal wait_100ns_sig : std_logic_vector (5 downto 0) := "000000"; 199 200 signal config_addr : integer range 0 to 47; 201 type config_data_type is array (0 to 47) of std_logic_vector(15 downto 0); 202 202 signal config_setting : config_data_type := ( 203 203 -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs = 10 TESTING ONLY … … 213 213 X"61A8", X"0000", X"0000", X"0000", X"7080", X"7080", X"7080", X"7080", --<<-- DACs 214 214 X"0000", 215 X"0000", X"0000" -- MSword // LSword 215 X"0000", X"0000", -- MSword // LSword 216 X"0000" -- this is a dummy address; this address is used only, if the user sent an invalid address within a WRITE command 216 217 ); 217 218 … … 303 304 -- output config settings as DAC and ROI arrays. 304 305 state <= state_sig; 305 debug_data_ram_empty <= int_flag; 306 306 307 debug_data_valid <= interrupt_ignore; 307 308 --debug_data_ram_empty <= data_ram_empty_sr(1); … … 315 316 c_trigger_mult <= config_setting(44); 316 317 317 runnumber <= config_setting(45) & config_setting(46); 318 318 319 319 320 trigger_enable <= trigger_enable_sig; … … 740 741 state_sig <= X"15"; 741 742 wait_100ns_sig <= wait_100ns_sig + 1; 742 if (wait_100ns_sig = "1 00") then743 wait_100ns_sig <= "000 ";743 if (wait_100ns_sig = "110010") then 744 wait_100ns_sig <= "000000"; 744 745 state_init <= WAIT_UNTIL_DG_IDLE; 745 746 end if; … … 749 750 if (data_generator_idle_sr = "111") then 750 751 --state_init <= CONFIG_MEMORY_MANAGER; 751 state_init <= MAIN;752 state_init <= CONFIG_MEMORY_MANAGER; 752 753 end if; 753 754 … … 774 775 if (memory_manager_config_valid_i_sr(1) = '1') then 775 776 --state_init <= CONFIG_DATA_GENERATOR; 777 trigger_enable_sig <= trigger_enable_storage_sig; 776 778 state_init <= MAIN; 777 779 end if; … … 821 823 if (update_of_rois = '1') then 822 824 update_of_rois <= '0'; 823 state_init <= CONFIG _MEMORY_MANAGER;825 state_init <= CONFIG; 824 826 -- if (trigger_enable_sig = '1') then 825 827 -- trigger_enable_storage_sig <= trigger_enable_sig; … … 876 878 end if; 877 879 when MAIN3 => 880 debug_data_ram_empty <= local_write_end_flag; 878 881 state_sig <= X"23"; 879 882 -- needed for the check: if there is enough space in W5300 FIFO … … 1009 1012 1010 1013 when CMD_WRITE => 1011 config_addr <= conv_integer(data_read (7 downto 0)); 1012 state_read_data <= READ_COMMAND_DATA_SECTION; 1014 if ( (conv_integer(data_read (7 downto 0)) >= 0) and (conv_integer(data_read (7 downto 0)) <= 46) ) then 1015 config_addr <= conv_integer(data_read (7 downto 0)); 1016 state_read_data <= READ_COMMAND_DATA_SECTION; 1017 else 1018 config_addr <= 47; 1019 state_read_data <= READ_COMMAND_DATA_SECTION; 1020 end if; 1013 1021 1014 1022 when CMD_EXECUTE => … … 1057 1065 update_of_rois <= '1'; 1058 1066 update_of_lessimportant <= '1'; 1067 runnumber <= config_setting(45) & config_setting(46); 1059 1068 1060 1069 state_read_data <= RD_5; … … 1299 1308 number_of_bytes_written_to_fifo <= number_of_words_written_to_fifo(15 downto 0) & '0'; 1300 1309 state_init <= WRITE_DATA; 1301 state_write <= W ORKAROUND_CHECK_FIFO_SPACE_01;1310 state_write <= WR_05; 1302 1311 1303 1312 … … 1347 1356 state_init <= WRITE_REG; 1348 1357 state_write <= WR_ACK; 1349 when WR_ACK => 1358 when WR_ACK => -- handshake with MM 1350 1359 data_valid_ack <= '1'; 1351 1360 state_write <= WR_WAIT_FOR_ACK; 1352 when WR_WAIT_FOR_ACK => 1361 when WR_WAIT_FOR_ACK => -- handshake ACK with MM 1353 1362 state_write <= WR_WAIT_FOR_ACK; 1354 1363 if (data_valid_sr(1) = '0') then 1355 1364 data_valid_ack <= '0'; 1356 state_init <= next_state_tmp; 1365 1366 if (local_write_end_flag = '1') then 1367 -- the last package was just written, and we can go back to the main state 1368 state_init <= MAIN; 1369 state_write <= WR_START; 1370 else 1371 -- we just wrote, a part of an event and should not go back to main, in order to avoid 1372 -- intermediate reconfiguration of the MM, in case an 'EXECUTE' command just arrived. 1373 -- but neither we should not go back to MAIN2, because data_valid is still low, as part of the MM-handshake. 1374 -- so we have to wait, until data_valid goes back high. 1375 -- if it never goes high, this can be a deadlock again, but it MUST go high, 1376 -- because we did not send away the entire event, yet. 1377 state_init <= WRITE_DATA; 1378 state_write <= WAIT_FOR_DATA_VALID_HIGH_AGAIN; 1379 end if; 1380 1381 1382 end if; 1383 1384 when WAIT_FOR_DATA_VALID_HIGH_AGAIN => 1385 if (data_valid_sr(1) = '1') then 1386 state_init <= MAIN2; 1357 1387 state_write <= WR_START; 1358 1388 end if; 1359 1360 1389 1361 1390 when others =>
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