Changeset 11122
- Timestamp:
- 06/22/11 22:36:18 (13 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 5 edited
-
fad_board_struct.vhd (modified) (5 diffs)
-
fad_definitions.vhd (modified) (2 diffs)
-
fad_main_struct.vhd (modified) (13 diffs)
-
led_controller_bahavior.vhd (modified) (7 diffs)
-
w5300_modul.vhd (modified) (16 diffs)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10957 r11122 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 16:56:38 09.06.20115 -- at - 21:52:14 22.06.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 76 76 -- Created: 77 77 -- by - daqct3.UNKNOWN (IHP110) 78 -- at - 16:56:38 09.06.201178 -- at - 21:52:15 22.06.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 116 116 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); 117 117 SIGNAL socket_tx_free_out : std_logic_vector(16 DOWNTO 0); -- 17bit value .. that's true 118 SIGNAL trigger_veto : std_logic := '1'; 118 119 SIGNAL w5300_state : std_logic_vector(7 DOWNTO 0); -- state is encoded here ... useful for debugging. 119 120 … … 278 279 MOSI <= mosi1; 279 280 281 -- ModuleWare code(v1.9) for instance 'I4' of 'assignment' 282 TRG_V_internal <= trigger_veto; 283 280 284 -- Instance port mappings. 281 285 I_board_main : FAD_main … … 320 324 drs_channel_id => D_A, 321 325 drs_dwrite => DWRITE, 322 green => RED_LED,326 green => GREEN_LED, 323 327 led => led, 324 328 mem_manager_state => mem_manager_state, 325 329 mosi => mosi1, 326 red => GREEN_LED,330 red => RED_LED, 327 331 sclk => sclk, 328 332 sensor_cs => sensor_cs, 329 333 socket_tx_free_out => socket_tx_free_out, 330 trigger_veto => TRG_V_internal,334 trigger_veto => trigger_veto, 331 335 w5300_state => w5300_state, 332 336 wiz_addr => W_A, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10970 r11122 57 57 --constant SUBVERSION_NUMBER : std_logic_vector (15 downto 0) := conv_std_logic_vector(str_to_int(SUBVERSION_STRING),16); 58 58 constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"02"; 59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"0 0";59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"02"; 60 60 constant PACKAGE_HEADER_LENGTH : integer := 36; 61 61 constant PACKAGE_HEADER_ZEROS : integer := 0; … … 105 105 -- End W5300 registers 106 106 107 -- START W5300 Socket State Codes 108 constant SOCKET_CLOSED : std_logic_vector (7 downto 0) := X"00"; 109 107 110 -- 108 111 constant W5300_TX_FIFO_SIZE_8B : integer := 15360; -- Socket TX FIFO-Size in Bytes -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10957 r11122 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 16:56:36 09.06.20115 -- at - 21:52:13 22.06.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 83 83 -- Created: 84 84 -- by - daqct3.UNKNOWN (IHP110) 85 -- at - 16:56:37 09.06.201185 -- at - 21:52:14 22.06.2011 86 86 -- 87 87 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 147 147 SIGNAL dout4 : STD_LOGIC; 148 148 SIGNAL dout5 : std_logic; 149 SIGNAL dout6 : std_logic; 149 150 SIGNAL drs_clk_en : std_logic := '0'; 150 151 SIGNAL drs_read_s_cell : std_logic := '0'; … … 184 185 SIGNAL runnumber : std_logic_vector(31 DOWNTO 0); 185 186 SIGNAL s_trigger : std_logic; 186 SIGNAL s_trigger_or_cont_trigger : std_logic;187 187 SIGNAL sclk_enable : std_logic; 188 188 SIGNAL sensor_array : sensor_array_type; … … 198 198 SIGNAL start_srin_write_8b : std_logic; 199 199 SIGNAL time : std_logic_vector(31 DOWNTO 0); 200 SIGNAL trig_veto : std_logic; 200 201 SIGNAL trigger_enable : std_logic; 201 202 SIGNAL trigger_id : std_logic_vector(31 DOWNTO 0); … … 205 206 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); 206 207 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); 208 SIGNAL wiz_reset_sig : std_logic := '1'; 207 209 SIGNAL wiz_write_ea : std_logic := '0'; 208 210 SIGNAL wiz_write_end : std_logic := '0'; … … 408 410 socks_waiting : IN std_logic; 409 411 trigger : IN std_logic; 412 trigger_veto : IN std_logic; 413 w5300_reset : IN std_logic; 410 414 additional_flasher_out : OUT std_logic; 411 415 amber : OUT std_logic; … … 612 616 613 617 -- ModuleWare code(v1.9) for instance 'and_4' of 'and' 614 enabled_trigger_or_s_trigger <= trigger_or_s_trigger 615 AND trigger_enable; 618 dout6 <= trigger_or_s_trigger AND trigger_enable; 616 619 617 620 -- ModuleWare code(v1.9) for instance 'and_5' of 'and' … … 621 624 denable <= denable_sig; 622 625 626 -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment' 627 trigger_veto <= trig_veto; 628 629 -- ModuleWare code(v1.9) for instance 'U_8' of 'assignment' 630 wiz_reset <= wiz_reset_sig; 631 623 632 -- ModuleWare code(v1.9) for instance 'U_6' of 'gnd' 624 633 software_trigger_in <= '0'; … … 636 645 dout4 <= dout OR I_really_want_dwrite; 637 646 638 -- ModuleWare code(v1.9) for instance 'or_1' of 'or'639 s_trigger_or_cont_trigger <= s_trigger OR cont_trigger;640 641 647 -- ModuleWare code(v1.9) for instance 'or_2' of 'or' 642 trig ger_veto <= trigger_veto1 OR dout5;648 trig_veto <= trigger_veto1 OR dout5; 643 649 644 650 -- ModuleWare code(v1.9) for instance 'or_5' of 'or' 645 trigger_or_s_trigger <= s_trigger_or_cont_trigger OR trigger; 651 trigger_or_s_trigger <= cont_trigger OR trigger; 652 653 -- ModuleWare code(v1.9) for instance 'or_6' of 'or' 654 enabled_trigger_or_s_trigger <= s_trigger OR dout6; 646 655 647 656 -- ModuleWare code(v1.9) for instance 'U_0' of 'split' … … 664 673 665 674 -- Instance port mappings. 666 U_7: FAD_rs485_receiver675 Inst_rs485_receiver : FAD_rs485_receiver 667 676 GENERIC MAP ( 668 677 RX_BYTES => RS485_MESSAGE_LEN_BYTES, -- no. of bytes to receive … … 829 838 additional_flasher_out => OPEN, 830 839 trigger => drs_readout_started, 840 w5300_reset => wiz_reset_sig, 841 trigger_veto => trig_veto, 831 842 refclk_too_high => alarm_refclk_too_high_internal, 832 843 refclk_too_low => alarm_refclk_too_low_internal, … … 917 928 socket_tx_free_out => socket_tx_free_out, 918 929 clk => CLK_50_internal, 919 wiz_reset => wiz_reset ,930 wiz_reset => wiz_reset_sig, 920 931 addr => wiz_addr, 921 932 data => wiz_data, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/led_controller_bahavior.vhd
r10225 r11122 36 36 -- status INs 37 37 trigger : IN std_logic; -- when trigger is received green should toggle 38 39 w5300_reset : in std_logic; 40 trigger_veto : in std_logic; 38 41 39 42 refclk_too_high : in std_logic; … … 71 74 -- since leds have inverted logic, the outs are inverted at this point. 72 75 green <= not green_loc; 73 amber <= not amber_loc; 74 red <= not red_loc; 76 77 --amber <= not amber_loc; 78 amber <= w5300_reset; 79 80 --red <= not red_loc; 81 red <= trigger_veto; 82 75 83 additional_flasher_out <= flasher; 76 84 … … 91 99 92 100 when INIT => 93 amber_loc <= '0';101 green_loc <= '0'; 94 102 if (socks_waiting = '1') then 95 103 next_state <= WAITING; … … 99 107 100 108 when WAITING => 101 amber_loc <= flasher;109 green_loc <= flasher; 102 110 if (socks_connected = '1') then 103 111 next_state <= CONNECTED; … … 107 115 108 116 when CONNECTED => 109 amber_loc <= '1';117 green_loc <= '1'; 110 118 if (socks_connected = '0') then 111 119 next_state <= INIT; … … 117 125 118 126 119 -- if trigger is received green_loc toggles127 -- if trigger is received red_loc toggles 120 128 trigger_proc : process (trigger) 121 129 begin 122 130 if Rising_edge(trigger) then 123 green_loc <= not green_loc;131 red_loc <= not red_loc; 124 132 end if; 125 133 end process trigger_proc; … … 178 186 179 187 if (heartbeat_counter = 0) then 180 red_loc <= '1';188 amber_loc <= '1'; 181 189 end if; 182 190 if (heartbeat_counter = on_time) then 183 red_loc <= '0';191 amber_loc <= '0'; 184 192 end if; 185 193 end if; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10957 r11122 109 109 SI, SI1, SI1b, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, 110 110 111 CONFIG, WAIT_100NS, WAIT_UNTIL_DG_IDLE, WAIT_FOR_DATA_RAM_EMPTY, -- <-- this is THE deadlock state111 CONFIG, WAIT_100NS, WAIT_UNTIL_DG_IDLE, 112 112 CONFIG_MEMORY_MANAGER, WAIT_FOR_CONFIG_MEMORY_MANAGER, 113 113 CONFIG_DATA_GENERATOR, WAIT_FOR_CONFIG_DATA_GENERATOR, … … 123 123 WR_05, WR_05_PREPARE_LENGTH_INFO, WR_05_POSTPREPARE_LENGTH_INFO, 124 124 WORKAROUND_CHECK_FIFO_SPACE_01, WORKAROUND_CHECK_FIFO_SPACE_02, WORKAROUND_CHECK_FIFO_SPACE_03, WORKAROUND_CHECK_FIFO_SPACE_04, 125 WR_05a, WR_05b, WR_06, WR_07, 125 WR_05a, WR_05b, WR_06, 126 WAIT_BEFORE_SEND, -- new state for serializing the 'send' 127 WR_07, 126 128 WR_ACK, WR_WAIT_FOR_ACK, WAIT_FOR_DATA_VALID_HIGH_AGAIN, 127 129 WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, … … 129 131 ); 130 132 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); 131 type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); 133 type state_interrupt_2_type is ( 134 IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, 135 IR2_CHECK_SOCKET_STATE, IR2_WAIT_FOR_SOCKETS_IN_CLOSED_STATE, 136 IR2_06); 137 132 138 type state_read_data_type is ( 133 139 RD_1, … … 152 158 153 159 signal state_init, next_state , next_state_tmp : state_init_type := RESET; 160 signal state_after_config : state_init_type := MAIN; 154 161 signal count : std_logic_vector (2 downto 0) := "000"; 155 162 signal state_write : state_write_type := WR_START; … … 226 233 signal bid : std_logic_vector (3 downto 0); 227 234 signal cid : std_logic_vector (1 downto 0); 235 236 -- for 'send'-serialization 237 signal FADid : integer range 0 to 39 := 0; -- 39 = number of FADs in camera minus 1 238 constant MICROSEC_TO_WAIT_BEFORE_SEND : integer := 25; 239 signal wait_before_send_counter : integer range 0 to 50*39*MICROSEC_TO_WAIT_BEFORE_SEND := 0; 240 signal wait_before_send_counter_goal : integer range 0 to 50*39*MICROSEC_TO_WAIT_BEFORE_SEND := 0; 241 228 242 -- these are just used as local variables, to make reading easier. 229 243 signal mac_loc : mac_type; … … 268 282 signal number_of_words_written_to_fifo : std_logic_vector(15 downto 0) := (others => '0'); 269 283 signal number_of_bytes_written_to_fifo : std_logic_vector(16 downto 0) := (others => '0'); 284 285 286 287 signal wait_for_sockets_closed_counter_overflow : std_logic := '0'; 288 signal wait_for_sockets_closed_counter_enable : std_logic := '0'; 289 signal wfscc_1 : integer range 0 to 50000 := 0; 290 signal wfscc_2 : integer range 0 to 2000 := 0; 291 292 270 293 271 294 COMPONENT mod7 … … 391 414 socket_cnt <= socket_cnt + 1; 392 415 if (socket_cnt = 7) then 393 state_interrupt_2 <= IR2_0 6;416 state_interrupt_2 <= IR2_05; 394 417 else 395 418 state_interrupt_2 <= IR2_02; -- go on with loop … … 418 441 state_sig <= X"F7"; 419 442 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; 420 par_data <= X"0010"; -- CLOSE 443 --par_data <= X"0010"; -- CLOSE 444 par_data <= X"0008"; -- DISCON 421 445 state_init <= WRITE_REG; 422 446 next_state <= INTERRUPT; 423 447 socket_cnt <= socket_cnt + 1; 424 448 if (socket_cnt = 7) then 425 state_interrupt_2 <= IR2_06; 449 socket_cnt <= "000"; 450 state_interrupt_2 <= IR2_06; 426 451 else 427 452 state_interrupt_2 <= IR2_01; 428 453 end if; 429 454 455 when IR2_CHECK_SOCKET_STATE => 456 wait_for_sockets_closed_counter_enable <= '1'; 457 458 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; -- READ Socket Status Register 459 state_init <= READ_REG; 460 next_state <= INTERRUPT; 461 state_interrupt_2 <= IR2_WAIT_FOR_SOCKETS_IN_CLOSED_STATE; 462 463 when IR2_WAIT_FOR_SOCKETS_IN_CLOSED_STATE => 464 if ( wait_for_sockets_closed_counter_overflow = '1') then 465 wait_for_sockets_closed_counter_enable <= '0'; 466 socket_cnt <= "000"; 467 state_interrupt_2 <= IR2_06; 468 else 469 if ( data_read(7 downto 0) = SOCKET_CLOSED ) then 470 if ( socket_cnt = 7 ) then 471 socket_cnt <= "000"; 472 state_interrupt_2 <= IR2_06; 473 else 474 socket_cnt <= socket_cnt + 1; 475 state_interrupt_2 <= IR2_CHECK_SOCKET_STATE; 476 end if; 477 else 478 state_interrupt_2 <= IR2_CHECK_SOCKET_STATE; 479 end if; 480 end if; 481 482 483 484 485 430 486 -- we go on and reset, the W5300 and this entire state machine. 431 487 when IR2_06 => … … 465 521 cs <= '1'; 466 522 state_write <= WR_START; 467 state_init <= INIT; 523 --state_init <= INIT; 524 525 -- I do this early configuration here, in order to get rid of all events in RAM. 526 -- in order to end up, with disabled trigger lines, I set trigger enable to 0. 527 -- So busy should vanish, once we are here. 528 trigger_enable_sig <= '0'; 529 state_init <= CONFIG; 530 state_after_config <= INIT; 468 531 end if; 469 532 … … 483 546 484 547 when LOCATE => 485 548 state_sig <= X"03"; 486 549 state_init <= IM; 550 551 -- calculate FADid for 'send'-ing serialization 552 FADid <= conv_integer(cid)*10+conv_integer(bid); 487 553 488 554 if (FAD_in_cam = '1') then … … 749 815 state_sig <= X"16"; 750 816 if (data_generator_idle_sr = "111") then 751 --state_init <= CONFIG_MEMORY_MANAGER;752 817 state_init <= CONFIG_MEMORY_MANAGER; 753 818 end if; 754 819 755 756 757 758 759 when WAIT_FOR_DATA_RAM_EMPTY => -- GUARANTIED DEAD LOCK HERE, because RAM will never empty, when staying in this state.760 state_sig <= X"17";761 if (data_ram_empty_sr(1) = '1') then762 state_init <= CONFIG_MEMORY_MANAGER;763 end if;764 820 765 821 when CONFIG_MEMORY_MANAGER => … … 776 832 --state_init <= CONFIG_DATA_GENERATOR; 777 833 trigger_enable_sig <= trigger_enable_storage_sig; 778 state_init <= MAIN; 834 state_init <= state_after_config; 835 --state_init <= MAIN; 779 836 end if; 780 781 -- when CONFIG_DATA_GENERATOR =>782 -- state_sig <= X"1A";783 -- data_generator_config_start_o <= '1';784 -- if (data_generator_config_valid_i_sr = "00") then785 -- state_init <= WAIT_FOR_CONFIG_DATA_GENERATOR;786 -- end if;787 -- when WAIT_FOR_CONFIG_DATA_GENERATOR =>788 -- state_sig <= X"1B";789 -- data_generator_config_start_o <= '0';790 -- if (data_generator_config_valid_i_sr ="11") then791 -- trigger_enable_sig <= trigger_enable_storage_sig; --restore value of this signal to the value it had before CONFIG792 -- state_init <= MAIN;793 -- end if;794 837 795 838 … … 823 866 if (update_of_rois = '1') then 824 867 update_of_rois <= '0'; 868 869 state_after_config <= MAIN; --this needs to be set to main, in order to return here, after configuration 825 870 state_init <= CONFIG; 826 871 -- if (trigger_enable_sig = '1') then … … 1330 1375 1331 1376 1332 1333 1334 1335 1336 1377 when WR_05 => 1337 1378 ram_access <= '0'; … … 1347 1388 --par_data <= number_of_bytes_written_to_fifo(15 downto 0); 1348 1389 1390 -- prepare this value here, so I have it in the next state. 1391 wait_before_send_counter_goal <= FADid*50*MICROSEC_TO_WAIT_BEFORE_SEND; 1392 1349 1393 state_init <= WRITE_REG; 1350 1394 state_write <= WR_07; 1395 1396 when WAIT_BEFORE_SEND => 1397 state_init <= WRITE_DATA; 1398 state_write <= WAIT_BEFORE_SEND; 1399 1400 if (wait_before_send_counter = wait_before_send_counter_goal) then 1401 wait_before_send_counter <= 0; 1402 state_write <= WR_07; 1403 else 1404 wait_before_send_counter <= wait_before_send_counter + 1; 1405 end if; 1406 1351 1407 when WR_07 => 1352 1408 number_of_words_written_to_fifo <= (others => '0'); … … 1458 1514 1459 1515 end process w5300_proc; 1516 1517 1518 1519 --signal wait_for_sockets_closed_counter_overflow : std_logic := '0'; 1520 --signal wait_for_sockets_closed_counter_enable : std_logic := '0'; 1521 --signal wfscc_1 : integer range 0 to 50000 := 0; 1522 --signal wfscc_2 : integer range 0 to 2000 := 0; 1523 counter_before_reset_proc : process (clk) 1524 begin 1525 if rising_edge (clk) then 1526 if (wait_for_sockets_closed_counter_enable = '1') then 1527 wait_for_sockets_closed_counter_overflow <= '0'; 1528 if (wfscc_1 = 50000) then 1529 if (wfscc_2 = 2000) then 1530 wait_for_sockets_closed_counter_overflow <= '1'; 1531 wfscc_2 <= 2000; 1532 wfscc_1 <= 50000; 1533 else 1534 wfscc_2 <= wfscc_2 + 1; 1535 wfscc_1 <= 0; 1536 end if; 1537 else 1538 wfscc_1 <= wfscc_1 + 1; 1539 end if; 1540 else 1541 wfscc_1 <= 0; 1542 wfscc_2 <= 0; 1543 wait_for_sockets_closed_counter_overflow <= '0'; 1544 end if; 1545 1546 end if; 1547 end process counter_before_reset_proc; 1548 1549 1460 1550 1461 1551 end Behavioral;
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