Changeset 158

Timestamp:

02/04/10 13:06:46 (15 years ago)

Author:

qweitzel

Message:

testbench adjusted to last FTU_top entity changes

File:

• FPGA/FTU/FTU_top_tb.vhd (modified) (2 diffs)

FPGA/FTU/FTU_top_tb.vhd

@@ -40 +40 @@
   component FTU_top
     port(
-      ext_clk   : IN  STD_LOGIC;
-      brd_add   : IN  STD_LOGIC_VECTOR(7 downto 0);
-      patch1    : IN  STD_LOGIC;
-      patch2    : IN  STD_LOGIC;
-      patch3    : IN  STD_LOGIC;
-      patch4    : IN  STD_LOGIC;
-      trig_prim : IN  STD_LOGIC;
-      miso      : IN  STD_LOGIC;
-      rx        : IN  STD_LOGIC;
-      enables   : OUT STD_LOGIC_VECTOR(35 downto 0);
-      clr       : OUT STD_LOGIC;
-      cs_ld     : OUT STD_LOGIC;
-      sck       : OUT STD_LOGIC;
-      mosi      : OUT STD_LOGIC;
-      tx        : OUT STD_LOGIC
+      -- global control
+      ext_clk   : IN  STD_LOGIC;                      -- external clock from FTU board
+      reset     : in  STD_LOGIC;                      -- reset
+      brd_add   : IN  STD_LOGIC_VECTOR(7 downto 0);   -- global board address
+
+      -- rate counters LVDS inputs
+      -- use IBUFDS differential input buffer
+      patch_A_p     : IN  STD_LOGIC;                  -- logic signal from first trigger patch
+      patch_A_n     : IN  STD_LOGIC;
+      patch_B_p     : IN  STD_LOGIC;                  -- logic signal from second trigger patch
+      patch_B_n     : IN  STD_LOGIC;
+      patch_C_p     : IN  STD_LOGIC;                  -- logic signal from third trigger patch
+      patch_C_n     : IN  STD_LOGIC;
+      patch_D_p     : IN  STD_LOGIC;                  -- logic signal from fourth trigger patch
+      patch_D_n     : IN  STD_LOGIC;
+      trig_prim_p   : IN  STD_LOGIC;                  -- logic signal from n-out-of-4 circuit
+      trig_prim_n   : IN  STD_LOGIC;
+
+      -- DAC interface
+      -- miso          : IN  STD_LOGIC;                  -- master-in-slave-out
+      sck           : OUT STD_LOGIC;                  -- serial clock to DAC
+      mosi          : OUT STD_LOGIC;                  -- serial data to DAC, master-out-slave-in
+      clr           : OUT STD_LOGIC;                  -- clear signal to DAC
+      cs_ld         : OUT STD_LOGIC;                  -- chip select or load to DAC
+
+      -- RS-485 interface to FTM
+      rx            : IN  STD_LOGIC;                  -- serial data from FTM
+      tx            : OUT STD_LOGIC;                  -- serial data to FTM
+      rx_en         : OUT STD_LOGIC;                  -- enable RS-485 receiver
+      tx_en         : OUT STD_LOGIC;                  -- enable RS-485 transmitter
+
+      -- analog buffer enable
+      enables_A   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+      enables_B   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+      enables_C   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+      enables_D   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
+
+      -- testpoints
+      TP_A       : out STD_LOGIC_VECTOR(7 downto 0)   -- testpoints
     );
   end component;
     
   --Inputs
-  signal ext_clk   : STD_LOGIC := '0';
-  signal brd_add   : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
-  signal patch1    : STD_LOGIC := '0';
-  signal patch2    : STD_LOGIC := '0';
-  signal patch3    : STD_LOGIC := '0';
-  signal patch4    : STD_LOGIC := '0';
-  signal trig_prim : STD_LOGIC := '0';
-  signal miso      : STD_LOGIC := '0';
-  signal rx        : STD_LOGIC := '0';
+  signal ext_clk     : STD_LOGIC := '0';
+  signal reset       : STD_LOGIC := '0';
+  signal brd_add     : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
+  signal patch_A_p   : STD_LOGIC := '0';
+  signal patch_A_n   : STD_LOGIC := '0';
+  signal patch_B_p   : STD_LOGIC := '0';
+  signal patch_B_n   : STD_LOGIC := '0';
+  signal patch_C_p   : STD_LOGIC := '0';
+  signal patch_C_n   : STD_LOGIC := '0';
+  signal patch_D_p   : STD_LOGIC := '0';
+  signal patch_D_n   : STD_LOGIC := '0';
+  signal trig_prim_p : STD_LOGIC := '0';
+  signal trig_prim_n : STD_LOGIC := '0';
+  -- signal miso        : STD_LOGIC := '0';
+  signal rx          : STD_LOGIC := '0';
 
   --Outputs
-  signal enables : STD_LOGIC_VECTOR(35 downto 0);
-  signal clr     : STD_LOGIC;
-  signal cs_ld   : STD_LOGIC;
-  signal sck     : STD_LOGIC;
-  signal mosi    : STD_LOGIC;
-  signal tx      : STD_LOGIC;
+  signal enables_A : STD_LOGIC_VECTOR(8 downto 0);
+  signal enables_B : STD_LOGIC_VECTOR(8 downto 0);
+  signal enables_C : STD_LOGIC_VECTOR(8 downto 0);
+  signal enables_D : STD_LOGIC_VECTOR(8 downto 0);
+  signal clr       : STD_LOGIC;
+  signal cs_ld     : STD_LOGIC;
+  signal sck       : STD_LOGIC;
+  signal mosi      : STD_LOGIC;
+  signal tx        : STD_LOGIC;
+  signal rx_en     : STD_LOGIC;
+  signal tx_en     : STD_LOGIC;
+  signal TP_A      : STD_LOGIC_VECTOR(7 downto 0);
   
   -- Clock period definitions
@@ -85 +121 @@
   uut: FTU_top
     port map(
-      ext_clk   => ext_clk,
-      brd_add   => brd_add,
-      patch1    => patch1,
-      patch2    => patch2,
-      patch3    => patch3,
-      patch4    => patch4,
-      trig_prim => trig_prim,
-      miso      => miso,
-      rx        => rx,
-      enables   => enables,
-      clr       => clr,
-      cs_ld     => cs_ld,
-      sck       => sck,
-      mosi      => mosi,
-      tx        => tx
+      ext_clk     => ext_clk,
+      reset       => reset,
+      brd_add     => brd_add,
+      patch_A_p   => patch_A_p,
+      patch_A_n   => patch_A_n,
+      patch_B_p   => patch_B_p,
+      patch_B_n   => patch_B_n,
+      patch_C_p   => patch_C_p,
+      patch_C_n   => patch_C_n,
+      patch_D_p   => patch_D_p,
+      patch_D_n   => patch_D_n,
+      trig_prim_p => trig_prim_p,
+      trig_prim_n => trig_prim_n,
+      -- miso        => miso,
+      rx          => rx,
+      rx_en       => rx_en,
+      enables_A   => enables_A,
+      enables_B   => enables_B,
+      enables_C   => enables_C,
+      enables_D   => enables_D,
+      clr         => clr,
+      cs_ld       => cs_ld,
+      sck         => sck,
+      mosi        => mosi,
+      tx          => tx,
+      tx_en       => tx_en,
+      TP_A        => TP_A
     );