- Timestamp:
- 07/05/10 16:49:07 (14 years ago)
- Location:
- FPGA/FTU/test_firmware/FTU_test2
- Files:
-
- 2 edited
-
FTU_test2.vhd (modified) (2 diffs)
-
FTU_test2_dac_control.vhd (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
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FPGA/FTU/test_firmware/FTU_test2/FTU_test2.vhd
r236 r237 89 89 clk : IN STD_LOGIC; 90 90 reset : IN STD_LOGIC; 91 miso : IN STD_LOGIC;92 91 clr : OUT STD_LOGIC; 93 92 mosi : OUT STD_LOGIC; … … 118 117 clk => clk_50M_sig, 119 118 reset => reset_sig, 120 miso => '0',121 119 clr => clr, 122 120 mosi => mosi, -
FPGA/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd
r236 r237 34 34 clk : IN STD_LOGIC; 35 35 reset : IN STD_LOGIC; 36 miso : IN STD_LOGIC;37 36 clr : OUT STD_LOGIC; 38 37 mosi : OUT STD_LOGIC; … … 70 69 signal reset_sig : std_logic; 71 70 72 signal miso_sig : std_logic;73 71 signal clr_sig : std_logic; 74 72 signal mosi_sig : std_logic := '0'; … … 95 93 reset_sig <= reset; 96 94 clk_sig <= clk; 97 miso_sig <= miso;98 95 mosi <= mosi_sig; 99 96 sck <= serial_clock_sig; … … 139 136 mosi => mosi_sig, 140 137 sclk => serial_clock_sig, 141 miso => miso_sig138 miso => open 142 139 ); 143 140
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