Ignore:
Timestamp:
07/07/10 16:30:13 (14 years ago)
Author:
qweitzel
Message:
FTU_test2 is now working
Location:
FPGA/FTU/test_firmware/FTU_test2
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • FPGA/FTU/test_firmware/FTU_test2/FTU_test2.vhd

    r241 r243  
    33-- Engineer:       P. Vogler, Q. Weitzel
    44--
    5 -- Create Date:    05/17/2010
     5-- Create Date:    05/07/2010
    66-- Design Name:   
    77-- Module Name:    FTU_test2 - Behavioral

  • FPGA/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd

    r241 r243  
    33-- Engineer:       P. Vogler, Q. Weitzel
    44--
    5 -- Create Date:    05/17/2010
     5-- Create Date:    05/07/2010
    66-- Design Name:
    77-- Module Name:    FTU_test2_dac_control - Behavioral
    … …  
    6060  end component;
    6161
    62   --component FTU_test2_upcnt16
    63   --  port(
    64   --    full  : out STD_LOGIC;
    65   --    clr   : in STD_LOGIC;
    66   --    reset : in STD_Logic;
    67   --    clk   : in STD_LOGIC
    68   --  );
    69   --end component;
    70  
    7162  signal clk_sig            : std_logic;
    7263  signal reset_sig          : std_logic;
    … …  
    8172  signal config_started_sig : std_logic := '0';
    8273  signal dac_array_sig      : dac_array_type := (100,200,300,400,500);
    83    
    84   --signal full_sig           : std_logic;
    85   --signal clr_wcnt_sig       : std_logic;
    86    
     74 
    8775  -- Build an enumerated type for the state machine
    8876  type state_type is (START, WAITING, STOP);
    8977
    9078  -- Register to hold the current state
    91   signal state, next_state: state_type;
     79  signal state, next_state : state_type;
    9280 
    9381begin
    9482
    95   --to be checked
    9683  reset_sig <= reset;
    9784  clk_sig <= clk;
    … …  
    122109        next_state <= WAITING;       
    123110      when WAITING =>
     111        config_start_sig <= '1';
    124112        enable1 <= '0';
    125113        enable2 <= '1';
    … …  
    134122        enable2 <= '0';
    135123        enable3 <= '1';
    136         config_start_sig <= '0';       
     124        config_start_sig <= '0';
    137125    end case;
    138126  end process;
    … …  
    151139    );
    152140
    153   --Inst_FTU_test2_upcnt16: FTU_test2_upcnt16
    154   --  port map(
    155   --    full  => full_sig,
    156   --    clr   => clr_wcnt_sig,
    157   --    reset => reset_sig,
    158   --    clk   => serial_clock_sig
    159   --  );
    160  
    161141end Behavioral;
    162142

  • FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_controller.vhd

    r242 r243  
    77--
    88-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
     9--
     10-- modified by Q. Weitzel
    911--
    1012LIBRARY ieee;
    … …  
    5557          spi_cycle_cnt <= 0;   
    5658            if (dac_start = '1') then
    57               shift_reg <= "0011" & '0' & dac_id & data;
     59              shift_reg <= "0011" & '0' & dac_id & data(11 downto 0) & "0000";
    5860              spi_state <= SPI_LOAD_DAC;
    5961            end if;

  • FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_distributor.vhd

    r242 r243  
    88-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
    99--
    10 
     10-- modified by Q. Weitzel
     11--
    1112LIBRARY ieee;
    1213USE ieee.std_logic_1164.all;
    … …  
    3738  signal spi_distr_state       : TYPE_SPI_DISTRIBUTION_STATE := INIT;
    3839  signal dac_id_cnt            : integer range 0 to 4 := 0;
    39   signal wait_cnt              : integer range 0 to 3 := 0;
    4040 
    4141BEGIN
    … …  
    5151          --data <= (others => 'Z');
    5252          data <= (others => '0');
    53           if wait_cnt < 3 then
    54             wait_cnt <= wait_cnt + 1;
    55             spi_distr_state <= INIT;
    56           else
    57             spi_distr_state <= IDLE;
    58           end if;
     53          spi_distr_state <= IDLE;
    5954        when IDLE =>
    6055          --data <= (others => 'Z');
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