Changeset 242 for FPGA/FTU/test_firmware/FTU_test2
- Timestamp:
- 07/06/10 16:46:25 (14 years ago)
- Location:
- FPGA/FTU/test_firmware/FTU_test2
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_controller.vhd
r236 r242 19 19 mosi : OUT std_logic := '0'; 20 20 dac_id : IN std_logic_vector (2 DOWNTO 0); 21 data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 21 --data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 22 data : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); 22 23 dac_cs : OUT std_logic := '1'; 23 24 dac_start : IN std_logic; … … 43 44 miso <= 'Z'; 44 45 mosi <= '0'; 45 data <= (others => 'Z');46 --data <= (others => 'Z'); 46 47 case spi_state is 47 48 when SPI_IDLE => -
FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_distributor.vhd
r238 r242 26 26 dac_config_ready : IN std_logic; 27 27 dac_id : OUT std_logic_vector(2 downto 0) := (others => '0'); 28 data : INOUT std_logic_vector(15 downto 0) := (others => 'Z') 28 --data : INOUT std_logic_vector(15 downto 0) := (others => 'Z') 29 data : OUT std_logic_vector(15 downto 0) := (others => '0') 29 30 ); 30 31 END ENTITY FTU_test2_spi_distributor; … … 36 37 signal spi_distr_state : TYPE_SPI_DISTRIBUTION_STATE := INIT; 37 38 signal dac_id_cnt : integer range 0 to 4 := 0; 39 signal wait_cnt : integer range 0 to 3 := 0; 38 40 39 41 BEGIN … … 43 45 44 46 if rising_edge(clk) then 45 data <= (others => 'Z'); 47 --data <= (others => 'Z'); 48 data <= (others => '0'); 46 49 case spi_distr_state is 47 50 when INIT => 48 data <= (others => 'Z'); 49 spi_distr_state <= IDLE; 51 --data <= (others => 'Z'); 52 data <= (others => '0'); 53 if wait_cnt < 3 then 54 wait_cnt <= wait_cnt + 1; 55 spi_distr_state <= INIT; 56 else 57 spi_distr_state <= IDLE; 58 end if; 50 59 when IDLE => 51 data <= (others => 'Z'); 60 --data <= (others => 'Z'); 61 data <= (others => '0'); 52 62 -- start DAC configuration 53 63 if (config_start = '1') then … … 56 66 dac_config_start <= '1'; 57 67 dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); 58 data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); 68 data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); 59 69 spi_distr_state <= CONFIG_DAC; 60 70 end if; -
FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_interface.vhd
r236 r242 75 75 dac_ready : OUT std_logic := '0'; 76 76 mosi : OUT std_logic := '0'; 77 data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 77 --data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 78 data : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); 78 79 miso : INOUT std_logic := 'Z' 79 80 ); … … 90 91 dac_config_start : OUT std_logic := '0'; 91 92 dac_id : OUT std_logic_vector (2 DOWNTO 0) := (others => '0'); 92 data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z') 93 --data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z') 94 data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') 93 95 ); 94 96 END COMPONENT;
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