Changeset 241 for FPGA/FTU/test_firmware/FTU_test2
- Timestamp:
- 07/06/10 14:17:20 (14 years ago)
- Location:
- FPGA/FTU/test_firmware/FTU_test2
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
FPGA/FTU/test_firmware/FTU_test2/FTU_test2.vhd
r237 r241 92 92 mosi : OUT STD_LOGIC; 93 93 sck : OUT STD_LOGIC; 94 cs_ld : OUT STD_LOGIC 94 cs_ld : OUT STD_LOGIC; 95 enable1 : out STD_LOGIC; 96 enable2 : out STD_LOGIC; 97 enable3 : out STD_LOGIC 95 98 ); 96 99 end component; … … 115 118 Inst_FTU_test2_dac_control : FTU_test2_dac_control 116 119 port map( 117 clk => clk_50M_sig, 118 reset => reset_sig, 119 clr => clr, 120 mosi => mosi, 121 sck => sck, 122 cs_ld => cs_ld 120 clk => clk_50M_sig, 121 reset => reset_sig, 122 clr => clr, 123 mosi => mosi, 124 sck => sck, 125 cs_ld => cs_ld, 126 enable1 => enables_A(1), 127 enable2 => enables_A(2), 128 enable3 => enables_A(3) 123 129 ); 124 130 … … 138 144 when Running => 139 145 reset_sig <= '0'; 146 enables_A(0) <= '1'; 140 147 end case; 141 148 end process FTU_test2_C_logic; -
FPGA/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd
r238 r241 37 37 mosi : OUT STD_LOGIC; 38 38 sck : OUT STD_LOGIC; 39 cs_ld : out STD_LOGIC 39 cs_ld : out STD_LOGIC; 40 enable1 : out STD_LOGIC; 41 enable2 : out STD_LOGIC; 42 enable3 : out STD_LOGIC 40 43 ); 41 44 end FTU_test2_dac_control; … … 114 117 when START => 115 118 config_start_sig <= '1'; 116 next_state <= WAITING; 119 enable1 <= '1'; 120 enable2 <= '0'; 121 enable3 <= '0'; 122 next_state <= WAITING; 117 123 when WAITING => 118 if (config_ready_sig = '1') then 119 next_state <= STOP; 124 enable1 <= '0'; 125 enable2 <= '1'; 126 enable3 <= '0'; 127 if (config_ready_sig = '1') then 128 next_state <= STOP; 120 129 else 121 130 next_state <= WAITING; 122 131 end if; 123 132 when STOP => 124 config_start_sig <= '0'; 133 enable1 <= '0'; 134 enable2 <= '0'; 135 enable3 <= '1'; 136 config_start_sig <= '0'; 125 137 end case; 126 138 end process; -
FPGA/FTU/test_firmware/FTU_test2/ftu_board_test2.ucf
r236 r241 102 102 ###################################################### 103 103 # Patch 0 104 #NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0105 #NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1106 #NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2107 #NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3104 NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0 105 NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1 106 NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2 107 NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3 108 108 #NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4 109 109 #NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5
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