Changeset 252 for FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl
- Timestamp:
- 07/16/10 16:25:44 (15 years ago)
- Location:
- FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl
- Files:
-
- 7 edited
-
control_manager_beha.vhd (modified) (6 diffs)
-
control_unit_struct.vhd (modified) (5 diffs)
-
fad_board.ucf (modified) (2 diffs)
-
fad_board_struct.vhd (modified) (9 diffs)
-
fad_definitions.vhd (modified) (1 diff)
-
fad_definitions.vhd.bak (modified) (3 diffs)
-
fad_main_struct.vhd (modified) (7 diffs)
Legend:
- Unmodified
- Added
- Removed
-
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd
r246 r252 36 36 ram_write_en : OUT std_logic_vector (0 DOWNTO 0); 37 37 dac_array : OUT dac_array_type; 38 roi_array : OUT roi_array_type 38 roi_array : OUT roi_array_type; 39 drs_address : OUT std_logic_vector (3 DOWNTO 0); 40 drs_address_mode : OUT std_logic 39 41 ); 40 42 … … 53 55 signal int_dac_array : dac_array_type := DEFAULT_DAC; 54 56 signal int_roi_array : roi_array_type := DEFAULT_ROI; 57 signal int_drs_address: std_logic_vector (3 DOWNTO 0) := DEFAULT_DRSADDR; 58 signal int_drs_address_mode: std_logic := DEFAULT_DRSADDR_MODE; 55 59 56 60 BEGIN … … 66 70 67 71 when CTRL_INIT => 72 -- WRITES DEFAULT VALUES IN config ram 68 73 addr_cntr <= addr_cntr + 1; 69 74 ram_addr <= conv_std_logic_vector(addr_cntr, ADDR_WIDTH); … … 76 81 elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then 77 82 ram_data_in <= conv_std_logic_vector(int_dac_array(addr_cntr - NO_OF_ROI), 16); 83 elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then 84 ram_data_in <= "0000" & "0000" 85 & "000" & conv_std_logic_vector(int_drs_address_mode, 1) 86 & int_drs_address; 78 87 else 79 88 ram_write_en <= "0"; … … 82 91 83 92 when CTRL_IDLE => 93 -- 84 94 addr_cntr <= 0; 85 95 ram_write_en <= "0"; … … 119 129 dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out); 120 130 ctrl_state <= CTRL_LOAD_ADDR; 121 else 131 elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then 132 drs_address <= ram_data_out(3 downto 0); 133 drs_address_mode <= ram_data_out(4); 134 ctrl_state <= CTRL_LOAD_ADDR; 135 else 122 136 addr_cntr <= 0; 123 137 config_started <= '0'; -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd
r246 r252 2 2 -- 3 3 -- Created: 4 -- by - Benjamin Krumm.UNKNOWN (EEPC8)5 -- at - 1 2:04:03 23.06.20104 -- by - dneise.UNKNOWN (TU-CC4900F8C7D2) 5 -- at - 14:46:37 12.07.2010 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 25 25 config_started : OUT std_logic := '0'; 26 26 dac_array : OUT dac_array_type; 27 drs_address : OUT std_logic_vector (3 DOWNTO 0); 28 drs_address_mode : OUT std_logic; 27 29 roi_array : OUT roi_array_type; 28 30 config_data : INOUT std_logic_vector (15 DOWNTO 0) … … 37 39 -- 38 40 -- Created: 39 -- by - Benjamin Krumm.UNKNOWN (EEPC8)40 -- at - 1 2:04:03 23.06.201041 -- by - dneise.UNKNOWN (TU-CC4900F8C7D2) 42 -- at - 14:46:37 12.07.2010 41 43 -- 42 44 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 93 95 ram_write_en : OUT std_logic_vector (0 DOWNTO 0); 94 96 dac_array : OUT dac_array_type ; 95 roi_array : OUT roi_array_type 97 roi_array : OUT roi_array_type ; 98 drs_address : OUT std_logic_vector (3 DOWNTO 0); 99 drs_address_mode : OUT std_logic 96 100 ); 97 101 END COMPONENT; … … 137 141 ram_write_en => ram_wren, 138 142 dac_array => dac_array, 139 roi_array => roi_array 143 roi_array => roi_array, 144 drs_address => drs_address, 145 drs_address_mode => drs_address_mode 140 146 ); 141 147 -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board.ucf
r246 r252 10 10 11 11 #Test Trigger input on 'Testpoint near W5300' 12 #NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok13 NET TEST_TRG LOC = R19 | IOSTANDARD=LVCMOS33 | PULLUP;12 #NET _TW<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok 13 NET TEST_TRG LOC = R19 | IOSTANDARD=LVCMOS33; 14 14 15 15 … … 229 229 NET A1_T<2> LOC = AC12 | IOSTANDARD=LVCMOS33; #ok 230 230 NET A1_T<3> LOC = AC14 | IOSTANDARD=LVCMOS33; #ok 231 #NET A1_T<4> LOC = AC15 | IOSTANDARD=LVCMOS33; #ok231 NET A1_T<4> LOC = AC15 | IOSTANDARD=LVCMOS33; #ok 232 232 #NET A1_T<5> LOC = AB16 | IOSTANDARD=LVCMOS33; #ok 233 233 #NET A1_T<6> LOC = AC16 | IOSTANDARD=LVCMOS33; #ok -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd
r246 r252 2 2 -- 3 3 -- Created: 4 -- by - dneise.UNKNOWN ( TU-CC4900F8C7D2)5 -- at - 1 2:42:19 02.07.20104 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 15:25:14 14.07.2010 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 27 27 W_INT : IN std_logic; 28 28 X_50M : IN STD_LOGIC; 29 A1_T : OUT std_logic_vector ( 3 DOWNTO 0);29 A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 30 30 A_CLK : OUT std_logic_vector (3 DOWNTO 0); 31 31 D0_SRCLK : OUT STD_LOGIC; … … 72 72 -- 73 73 -- Created: 74 -- by - dneise.UNKNOWN ( TU-CC4900F8C7D2)75 -- at - 1 2:42:20 02.07.201074 -- by - dneise.UNKNOWN (E5B-LABOR6) 75 -- at - 15:25:14 14.07.2010 76 76 -- 77 77 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 95 95 SIGNAL CLK_25_PS : std_logic; 96 96 SIGNAL CLK_50 : std_logic; 97 SIGNAL SRCLK : std_logic := '0';97 SIGNAL SRCLK : std_logic := '0'; 98 98 SIGNAL TRG_OR : std_logic; 99 99 SIGNAL adc_data_array : adc_data_array_type; 100 100 SIGNAL board_id : std_logic_vector(3 DOWNTO 0); 101 101 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); 102 SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); 102 103 SIGNAL dummy : std_logic; 103 SIGNAL not_TEST_TRG : STD_LOGIC;104 104 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); 105 SIGNAL trigger_out : STD_LOGIC := '0';106 107 -- Implicit buffer signal declarations108 SIGNAL RSRLOAD_internal : std_logic;109 105 110 106 … … 148 144 ); 149 145 END COMPONENT; 150 COMPONENT debouncer151 GENERIC (152 WIDTH : INTEGER := 17153 );154 PORT (155 clk : IN STD_LOGIC ;156 -- rst : in STD_LOGIC;157 trigger_in : IN STD_LOGIC ;158 trigger_out : OUT STD_LOGIC := '0'159 );160 END COMPONENT;161 146 162 147 -- Optional embedded configurations 163 148 -- pragma synthesis_off 164 149 FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main; 165 FOR ALL : debouncer USE ENTITY FACT_FAD_lib.debouncer;166 150 -- pragma synthesis_on 167 151 … … 228 212 -- HDL Embedded Text Block 8 eb2 229 213 -- eb2 8 230 A1_T(0) <= dummy; 231 A1_T(1) <= RSRLOAD_internal; 232 A1_T(2) <= D0_SROUT; 233 A1_T(3) <= D1_SROUT; 214 A1_T(3 downto 0) <= drs_channel_id; 215 D_A <= drs_channel_id; 216 A1_T(4) <= TRG_OR; 234 217 235 218 … … 237 220 DAC_CS <= dummy; 238 221 239 -- ModuleWare code(v1.9) for instance 'I1' of 'inv'240 not_TEST_TRG <= NOT(TEST_TRG);241 242 222 -- ModuleWare code(v1.9) for instance 'I2' of 'or' 243 TRG_OR <= TRG OR trigger_out;223 TRG_OR <= TRG OR TEST_TRG; 244 224 245 225 -- Instance port mappings. … … 262 242 CLK_25_PS => CLK_25_PS, 263 243 CLK_50 => CLK_50, 264 RSRLOAD => RSRLOAD _internal,244 RSRLOAD => RSRLOAD, 265 245 SRCLK => SRCLK, 266 246 adc_oeb => OE_ADC, 267 247 dac_cs => dummy, 268 248 denable => DENABLE, 269 drs_channel_id => D_A,249 drs_channel_id => drs_channel_id, 270 250 drs_dwrite => DWRITE, 271 251 led => D_T, … … 281 261 wiz_data => W_D 282 262 ); 283 I_debouncer : debouncer284 GENERIC MAP (285 WIDTH => 17286 )287 PORT MAP (288 clk => CLK_50,289 trigger_in => not_TEST_TRG,290 trigger_out => trigger_out291 );292 293 -- Implicit buffered output assignments294 RSRLOAD <= RSRLOAD_internal;295 263 296 264 END struct; -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd
r246 r252 104 104 constant DEFAULT_DAC : dac_array_type := (20972, 34079, 20526, 0, 28836, 28836, 28836, 28836); 105 105 --constant DEFAULT_DAC : dac_array_type := (others => 0); 106 107 constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= "0000"; 108 constant DEFAULT_DRSADDR_MODE : std_logic := '0'; 109 110 106 111 107 112 -- Commands -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd.bak
r246 r252 51 51 constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14"; 52 52 constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18"; 53 constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C"; 54 constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E"; 53 55 constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20"; 54 56 constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22"; … … 80 82 81 83 constant LOG2_OF_RAM_SIZE_64B : integer := 15; 82 constant RAM_SIZE_64B : integer := 2**LOG2_OF_RAM_SIZE_64B; 84 --constant RAM_SIZE_64B : integer := 2**LOG2_OF_RAM_SIZE_64B; 85 constant RAM_SIZE_64B : integer := 24576; 83 86 constant RAM_SIZE_16B : integer := RAM_SIZE_64B * 4; 84 87 … … 101 104 constant DEFAULT_DAC : dac_array_type := (20972, 34079, 20526, 0, 28836, 28836, 28836, 28836); 102 105 --constant DEFAULT_DAC : dac_array_type := (others => 0); 106 107 constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= X"0"; 108 constant DEFAULT_DRSADDR_MODE : std_logic := '0'; 109 110 103 111 104 112 -- Commands -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd
r246 r252 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (TU-CC4900F8C7D2) 5 -- at - 1 2:42:19 02.07.20105 -- at - 14:46:38 12.07.2010 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 60 60 -- Created: 61 61 -- by - dneise.UNKNOWN (TU-CC4900F8C7D2) 62 -- at - 1 2:42:19 02.07.201062 -- at - 14:46:38 12.07.2010 63 63 -- 64 64 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 106 106 SIGNAL dac_array : dac_array_type; 107 107 SIGNAL data_out : std_logic_vector(63 DOWNTO 0); 108 SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0'); 109 SIGNAL drs_address_mode : std_logic; 110 SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0'); 108 111 SIGNAL drs_clk_en : std_logic := '0'; 109 112 SIGNAL drs_read_s_cell : std_logic := '0'; … … 170 173 config_started : OUT std_logic := '0'; 171 174 dac_array : OUT dac_array_type ; 175 drs_address : OUT std_logic_vector (3 DOWNTO 0); 176 drs_address_mode : OUT std_logic ; 172 177 roi_array : OUT roi_array_type ; 173 178 config_data : INOUT std_logic_vector (15 DOWNTO 0) … … 351 356 drs_dwrite <= dwrite AND dwrite_enable; 352 357 358 -- ModuleWare code(v1.9) for instance 'U_0' of 'mux' 359 u_0combo_proc: PROCESS(drs_channel_internal, drs_address, 360 drs_address_mode) 361 BEGIN 362 CASE drs_address_mode IS 363 WHEN '0' => drs_channel_id <= drs_channel_internal; 364 WHEN '1' => drs_channel_id <= drs_address; 365 WHEN OTHERS => drs_channel_id <= (OTHERS => 'X'); 366 END CASE; 367 END PROCESS u_0combo_proc; 368 353 369 -- Instance port mappings. 354 370 I_main_adc_buffer : adc_buffer … … 379 395 config_started => config_started_cu, 380 396 dac_array => dac_array, 397 drs_address => drs_address, 398 drs_address_mode => drs_address_mode, 381 399 roi_array => roi_array, 382 400 config_data => config_data … … 429 447 adc_oeb => adc_oeb, 430 448 adc_otr => adc_otr, 431 drs_channel_id => drs_channel_i d,449 drs_channel_id => drs_channel_internal, 432 450 drs_dwrite => dwrite, 433 451 drs_clk_en => drs_clk_en,
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