Changeset 9890 for firmware/FTU/FTU_top.vhd
- Timestamp:
- 08/24/10 13:39:00 (14 years ago)
- File:
-
- 1 edited
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firmware/FTU/FTU_top.vhd
r9880 r9890 97 97 98 98 --rate counter signals 99 signal cntr_reset_sig : STD_LOGIC; -- initialized in FTU_control 100 signal rate_array_sig : rate_array_type := (0,0,0,0,0);101 signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0); 99 signal cntr_reset_sig : STD_LOGIC; -- initialized in FTU_control 100 signal rate_array_sig : rate_array_type; -- initialized by counters 101 signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0); -- initialized in FTU_control 102 102 signal overflow_array : STD_LOGIC_VECTOR(7 downto 0) := "00000000"; 103 signal new_rate_A_sig : STD_LOGIC; -- initialized by patch A counter 104 signal new_rate_B_sig : STD_LOGIC; -- initialized by patch B counter 105 signal new_rate_C_sig : STD_LOGIC; -- initialized by patch C counter 106 signal new_rate_D_sig : STD_LOGIC; -- initialized by patch D counter 107 signal new_rate_t_sig : STD_LOGIC; -- initialized by trigger counter 108 signal new_rates_sig : STD_LOGIC := '0'; 103 109 104 110 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM … … 133 139 prescaling : in std_logic_vector(7 downto 0); 134 140 counts : out integer range 0 to 2**16 - 1; 135 overflow : out std_logic 141 overflow : out std_logic; 142 new_rate : out std_logic 136 143 ); 137 144 end component; … … 146 153 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0); 147 154 rate_array : IN rate_array_type; 155 overflow_array : in STD_LOGIC_VECTOR(7 downto 0); 156 new_rates : IN std_logic; 148 157 reset : OUT std_logic; 149 158 config_start : OUT std_logic; … … 206 215 enables_D <= enable_array_sig(3)(8 downto 0); 207 216 217 new_rates_sig <= new_rate_A_sig and new_rate_B_sig and new_rate_C_sig and new_rate_D_sig and new_rate_t_sig; 218 208 219 --differential input buffer for patch A 209 220 IBUFDS_LVDS_33_A : IBUFDS_LVDS_33 … … 261 272 prescaling => prescaling_sig, 262 273 counts => rate_array_sig(0), 263 overflow => overflow_array(0) 274 overflow => overflow_array(0), 275 new_rate => new_rate_A_sig 264 276 ); 265 277 … … 271 283 prescaling => prescaling_sig, 272 284 counts => rate_array_sig(1), 273 overflow => overflow_array(1) 285 overflow => overflow_array(1), 286 new_rate => new_rate_B_sig 274 287 ); 275 288 … … 281 294 prescaling => prescaling_sig, 282 295 counts => rate_array_sig(2), 283 overflow => overflow_array(2) 296 overflow => overflow_array(2), 297 new_rate => new_rate_C_sig 284 298 ); 285 299 … … 291 305 prescaling => prescaling_sig, 292 306 counts => rate_array_sig(3), 293 overflow => overflow_array(3) 307 overflow => overflow_array(3), 308 new_rate => new_rate_D_sig 294 309 ); 295 310 … … 301 316 prescaling => prescaling_sig, 302 317 counts => rate_array_sig(4), 303 overflow => overflow_array(4) 318 overflow => overflow_array(4), 319 new_rate => new_rate_t_sig 304 320 ); 305 321 … … 313 329 ram_dob => ram_dob_sig, 314 330 rate_array => rate_array_sig, 331 overflow_array => overflow_array, 332 new_rates => new_rates_sig, 315 333 reset => reset_sig, 316 334 config_start => config_start_sig,
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