- Timestamp:
- 09/22/10 18:08:06 (14 years ago)
- Location:
- firmware/FTU
- Files:
-
- 9 edited
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FTU_control.vhd (modified) (15 diffs)
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FTU_top.vhd (modified) (9 diffs)
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FTU_top_tb.vhd (modified) (3 diffs)
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counter/FTU_rate_counter.vhd (modified) (1 diff)
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dac_spi/FTU_spi_controller.vhd (modified) (1 diff)
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dac_spi/FTU_spi_distributor.vhd (modified) (1 diff)
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ftu_definitions.vhd (modified) (1 diff)
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rs485/FTU_rs485_control.vhd (modified) (10 diffs)
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rs485/FTU_rs485_interpreter.vhd (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTU/FTU_control.vhd
r9911 r9939 35 35 entity FTU_control is 36 36 port( 37 clk_50MHz : IN std_logic; 38 clk_ready : IN std_logic; 39 config_started : IN std_logic; 40 config_ready : IN std_logic; 41 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0); 42 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0); 43 rate_array : IN rate_array_type; 44 overflow_array : in STD_LOGIC_VECTOR(7 downto 0); 45 new_rates : IN std_logic; 46 reset : OUT std_logic; 47 config_start : OUT std_logic; 48 ram_ena : OUT std_logic; 49 ram_enb : OUT std_logic; 50 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0); 51 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0); 52 ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0); 53 ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0); 54 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0); 55 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0); 56 dac_array : OUT dac_array_type; 57 enable_array : OUT enable_array_type; 58 cntr_reset : OUT STD_LOGIC; 59 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0) 37 clk_50MHz : IN std_logic; 38 clk_ready : IN std_logic; -- from DCM 39 config_started : IN std_logic; -- from DAC/SPI 40 config_ready : IN std_logic; -- from DAC/SPI 41 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0); 42 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0); 43 rate_array : IN rate_array_type; -- from counters 44 overflow_array : IN STD_LOGIC_VECTOR(7 downto 0); -- from counters 45 new_rates : IN std_logic; -- from counters 46 new_DACs : IN std_logic; -- from RS485 module 47 new_enables : IN std_logic; -- from RS485 module 48 new_prescaling : IN std_logic; -- from RS485 module 49 read_rates : IN std_logic; -- from RS485 module 50 read_DACs : IN std_logic; -- from RS485 module 51 read_enables : IN std_logic; -- from RS485 module 52 read_prescaling : IN std_logic; -- from RS485 module 53 dac_array_rs485_out : IN dac_array_type; -- from RS485 module 54 enable_array_rs485_out : IN enable_array_type; -- from RS485 module 55 prescaling_rs485_out : IN STD_LOGIC_VECTOR(7 downto 0); -- from RS485 module 56 reset : OUT std_logic; 57 config_start : OUT std_logic; 58 ram_ena : OUT std_logic; 59 ram_enb : OUT std_logic; 60 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0); 61 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0); 62 ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0); 63 ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0); 64 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0); 65 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0); 66 rate_array_rs485 : OUT rate_array_type := (0,0,0,0,0); -- to RS485 module 67 overflow_array_rs485_in : OUT STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- to RS485 module 68 rates_ready : OUT std_logic := '0'; -- to RS485 module 69 DACs_ready : OUT std_logic := '0'; -- to RS485 module 70 enables_ready : OUT std_logic := '0'; -- to RS485 module 71 prescaling_ready : OUT std_logic := '0'; -- to RS485 module 72 dac_array : OUT dac_array_type; 73 enable_array : OUT enable_array_type; 74 cntr_reset : OUT STD_LOGIC; 75 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0) 60 76 ); 61 77 end FTU_control; … … 90 106 --counter to loop through RAM 91 107 signal ram_ada_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0; 92 signal ram_adb_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_B := 0;93 108 signal ram_dac_cntr : INTEGER range 0 to (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2) := 0; 94 109 signal ram_enable_cntr : INTEGER range 0 to (NO_OF_ENABLE + 1) := 0; … … 104 119 signal new_prescaling_in_RAM : STD_LOGIC := '0'; 105 120 106 type FTU_control_StateType is (IDLE, INIT, RUNNING, CONFIG_ENABLE, CONFIG_DAC, CONFIG_COUNTER, WRITE_RATES, RESET_ALL); 121 type FTU_control_StateType is (IDLE, INIT, RUNNING, 122 CONFIG_ENABLE, CONFIG_DAC, CONFIG_COUNTER, 123 WRITE_RATES, WRITE_DAC, WRITE_ENABLE, WRITE_PRESCALING, 124 READOUT_RATES, READOUT_DAC, READOUT_ENABLE, READOUT_PRESCALING); 107 125 signal FTU_control_State : FTU_control_StateType; 108 126 … … 115 133 begin 116 134 135 reset_sig <= '0'; 136 117 137 if Rising_edge(clk_50MHz) then 118 138 119 139 case FTU_control_State is 120 140 121 141 when IDLE => -- wait for DCMs to lock 122 reset_sig <= '0';123 142 config_start_sig <= '0'; 124 143 ram_ena_sig <= '0'; … … 126 145 if (clk_ready = '1') then 127 146 FTU_control_State <= INIT; 147 else 148 FTU_control_State <= IDLE; 128 149 end if; 129 150 130 151 when INIT => -- load default config data to RAM, see also ftu_definitions.vhd for more info 131 reset_sig <= '0';132 152 new_rates_busy <= '1'; 133 153 config_start_sig <= '0'; … … 189 209 when RUNNING => -- count triggers and react to commands from FTM 190 210 cntr_reset_sig <= '0'; 191 reset_sig <= '0';192 211 config_start_sig <= '0'; 193 if (new_rates_sig = '1') then 212 if (new_rates_sig = '1') then -- counters have finished a period 194 213 FTU_control_State <= WRITE_RATES; 195 else 214 else -- update FTU settings if necessary 196 215 if (new_DACs_in_RAM = '1') then 197 216 ram_enb_sig <= '1'; … … 206 225 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A); 207 226 FTU_control_State <= CONFIG_COUNTER; 208 else 209 FTU_control_State <= RUNNING; 227 else -- nothing to be updated, check new commands from RS485 228 if (new_DACs = '1') then 229 FTU_control_State <= WRITE_DAC; 230 elsif (new_DACs = '0' and new_enables = '1') then 231 FTU_control_State <= WRITE_ENABLE; 232 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '1') then 233 FTU_control_State <= WRITE_PRESCALING; 234 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and 235 read_rates = '1') then 236 ram_enb_sig <= '1'; 237 ram_adb_sig <= conv_std_logic_vector(NO_OF_ENABLE, RAM_ADDR_WIDTH_B); 238 FTU_control_State <= READOUT_RATES; 239 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and 240 read_rates = '0' and read_DACs = '1') then 241 ram_enb_sig <= '1'; 242 ram_adb_sig <= conv_std_logic_vector(NO_OF_ENABLE + NO_OF_COUNTER, RAM_ADDR_WIDTH_B); 243 FTU_control_State <= READOUT_DAC; 244 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and 245 read_rates = '0' and read_DACs = '0' and read_enables = '1') then 246 ram_enb_sig <= '1'; 247 ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B); 248 FTU_control_State <= READOUT_ENABLE; 249 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and 250 read_rates = '0' and read_DACs = '0' and read_enables = '0' and read_prescaling = '1') then 251 ram_ena_sig <= '1'; 252 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A); 253 FTU_control_State <= READOUT_PRESCALING; 254 else 255 FTU_control_State <= RUNNING; --no commands from RS485 -> stay running 256 end if; 210 257 end if; 211 258 end if; … … 219 266 prescaling_sig <= ram_doa; 220 267 FTU_control_State <= CONFIG_COUNTER; 268 prescaling_ready <= '1'; 221 269 else 222 270 cntr_reset_sig <= '1'; … … 226 274 ram_ena_sig <= '0'; 227 275 new_rates_busy <= '0'; 276 prescaling_ready <= '0'; 228 277 FTU_control_State <= RUNNING; 229 278 end if; … … 238 287 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B); 239 288 enable_array_sig(ram_enable_cntr - 1) <= ram_dob; 289 enables_ready <= '1'; 240 290 FTU_control_State <= CONFIG_ENABLE; 241 291 else … … 246 296 cntr_reset_sig <= '1'; 247 297 new_rates_busy <= '0'; 298 enables_ready <= '0'; 248 299 FTU_control_State <= RUNNING; 249 300 end if; … … 257 308 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); 258 309 elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then 259 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob ));310 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0))); 260 311 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); 261 312 FTU_control_State <= CONFIG_DAC; 262 313 elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED + 1)) then 263 dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob ));314 dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob(11 downto 0))); 264 315 ram_adb_sig <= (others => '0'); 265 316 FTU_control_State <= CONFIG_DAC; 317 DACs_ready <= '1'; 266 318 else 267 319 ram_adb_sig <= (others => '0'); 268 320 config_start_sig <= '1'; 321 DACs_ready <= '0'; 269 322 FTU_control_State <= CONFIG_DAC; 270 323 end if; … … 286 339 287 340 when WRITE_RATES => -- write trigger/patch rates to RAM B and overflow register to RAM A 288 new_rates_busy <= '1'; 341 new_rates_busy <= '1'; 289 342 ram_counter_cntr <= ram_counter_cntr + 1; 290 343 if (ram_counter_cntr < NO_OF_COUNTER) then … … 306 359 else 307 360 ram_ena_sig <= '0'; 308 ram_wea_sig <= "0"; 309 ram_counter_cntr <= 0; 361 ram_wea_sig <= "0"; 362 ram_counter_cntr <= 0; 310 363 new_rates_busy <= '0'; 311 364 FTU_control_State <= RUNNING; 312 365 end if; 313 314 when RESET_ALL => -- reset/clear and start from scratch 315 reset_sig <= '1'; 316 config_start_sig <= '0'; 317 FTU_control_State <= IDLE; 366 367 when WRITE_DAC => -- write new DAC values from RS485 to RAM 368 ram_dac_cntr <= ram_dac_cntr + 1; 369 if (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)) then 370 ram_enb_sig <= '1'; 371 ram_web_sig <= "1"; 372 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr), RAM_ADDR_WIDTH_B); 373 ram_dib_sig <= conv_std_logic_vector(dac_array_rs485_out(ram_dac_cntr), 16); 374 FTU_control_State <= WRITE_DAC; 375 elsif (ram_dac_cntr = (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)) then 376 ram_enb_sig <= '1'; 377 ram_web_sig <= "1"; 378 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr), RAM_ADDR_WIDTH_B); 379 ram_dib_sig <= conv_std_logic_vector(dac_array_rs485_out(ram_dac_cntr + NO_OF_DAC_NOT_USED), 16); 380 FTU_control_State <= WRITE_DAC; 381 else 382 ram_enb_sig <= '0'; 383 ram_web_sig <= "0"; 384 new_DACs_in_RAM <= '1'; 385 ram_dib_sig <= (others => '0'); 386 ram_adb_sig <= (others => '0'); 387 ram_dac_cntr <= 0; 388 FTU_control_State <= RUNNING; 389 end if; 390 391 when WRITE_ENABLE => -- write new enable patterns from RS485 to RAM 392 ram_enable_cntr <= ram_enable_cntr + 1; 393 if (ram_enable_cntr < NO_OF_ENABLE) then 394 ram_enb_sig <= '1'; 395 ram_web_sig <= "1"; 396 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr, RAM_ADDR_WIDTH_B); 397 ram_dib_sig <= enable_array_rs485_out(ram_enable_cntr); 398 else 399 ram_enb_sig <= '0'; 400 ram_web_sig <= "0"; 401 new_enables_in_RAM <= '1'; 402 ram_dib_sig <= (others => '0'); 403 ram_adb_sig <= (others => '0'); 404 ram_enable_cntr <= 0; 405 FTU_control_State <= RUNNING; 406 end if; 407 408 when WRITE_PRESCALING => -- write new prescaling from RS485 to RAM 409 wait_cntr <= wait_cntr + 1; 410 if (wait_cntr = 0) then 411 ram_ena_sig <= '1'; 412 ram_wea_sig <= "1"; 413 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A); 414 ram_dia_sig <= prescaling_rs485_out; 415 else 416 ram_ena_sig <= '0'; 417 ram_wea_sig <= "0"; 418 new_prescaling_in_RAM <= '1'; 419 ram_dia_sig <= (others => '0'); 420 ram_ada_sig <= (others => '0'); 421 wait_cntr <= 0; 422 FTU_control_State <= RUNNING; 423 end if; 424 425 when READOUT_RATES => -- read most recent rate values from RAM and send them to RS485 module 426 ram_counter_cntr <= ram_counter_cntr + 1; 427 if (ram_counter_cntr = 0) then 428 ram_enb_sig <= '1'; 429 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B); 430 FTU_control_State <= READOUT_RATES; 431 elsif (ram_counter_cntr < NO_OF_COUNTER) then 432 ram_ena_sig <= '1'; 433 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A); 434 ram_enb_sig <= '1'; 435 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B); 436 rate_array_rs485(ram_counter_cntr - 1) <= conv_integer(unsigned(ram_dob)); 437 FTU_control_State <= READOUT_RATES; 438 elsif (ram_counter_cntr = NO_Of_COUNTER) then 439 ram_enb_sig <= '0'; 440 ram_adb_sig <= (others => '0'); 441 rate_array_rs485(ram_counter_cntr - 1) <= conv_integer(unsigned(ram_dob)); 442 ram_ena_sig <= '1'; 443 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A); 444 FTU_control_State <= READOUT_RATES; 445 elsif (ram_counter_cntr = NO_Of_COUNTER + 1) then 446 ram_enb_sig <= '0'; 447 ram_adb_sig <= (others => '0'); 448 ram_ena_sig <= '0'; 449 ram_ada_sig <= (others => '0'); 450 overflow_array_rs485_in <= ram_doa; 451 rates_ready <= '1'; 452 FTU_control_State <= READOUT_RATES; 453 else 454 ram_enb_sig <= '0'; 455 ram_adb_sig <= (others => '0'); 456 ram_ena_sig <= '0'; 457 ram_ada_sig <= (others => '0'); 458 ram_counter_cntr <= 0; 459 rates_ready <= '0'; 460 FTU_control_State <= RUNNING; 461 end if; 462 463 when READOUT_DAC => -- read most recent DAC values from RAM and send them to RS485 module 464 ram_dac_cntr <= ram_dac_cntr + 1; 465 if (ram_dac_cntr = 0) then 466 ram_enb_sig <= '1'; 467 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); 468 FTU_control_State <= READOUT_DAC; 469 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then 470 ram_enb_sig <= '1'; 471 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); 472 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0))); 473 FTU_control_State <= READOUT_DAC; 474 elsif (ram_dac_cntr = (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then 475 ram_enb_sig <= '0'; 476 ram_adb_sig <= (others => '0'); 477 dac_array_sig(ram_dac_cntr + NO_OF_DAC_NOT_USED - 1) <= conv_integer(unsigned(ram_dob(11 downto 0))); 478 DACs_ready <= '1'; 479 FTU_control_State <= READOUT_DAC; 480 else 481 ram_enb_sig <= '0'; 482 ram_adb_sig <= (others => '0'); 483 DACs_ready <= '0'; 484 ram_dac_cntr <= 0; 485 FTU_control_State <= RUNNING; 486 end if; 487 488 when READOUT_ENABLE => -- read most recent enable patterns from RAM and send them to RS485 module 489 ram_enable_cntr <= ram_enable_cntr + 1; 490 if (ram_enable_cntr = 0) then 491 ram_enb_sig <= '1'; 492 ram_adb_sig <= conv_std_logic_vector((ram_enable_cntr + 1), RAM_ADDR_WIDTH_B); 493 FTU_control_State <= READOUT_ENABLE; 494 elsif (ram_enable_cntr < NO_OF_ENABLE) then 495 ram_enb_sig <= '1'; 496 ram_adb_sig <= conv_std_logic_vector((ram_enable_cntr + 1), RAM_ADDR_WIDTH_B); 497 enable_array_sig(ram_enable_cntr - 1) <= ram_dob; 498 FTU_control_State <= READOUT_ENABLE; 499 elsif (ram_enable_cntr = NO_OF_ENABLE) then 500 ram_enb_sig <= '0'; 501 ram_adb_sig <= (others => '0'); 502 enable_array_sig(ram_enable_cntr - 1) <= ram_dob; 503 enables_ready <= '1'; 504 FTU_control_State <= READOUT_ENABLE; 505 else 506 ram_enb_sig <= '0'; 507 ram_adb_sig <= (others => '0'); 508 enables_ready <= '0'; 509 ram_enable_cntr <= 0; 510 FTU_control_State <= RUNNING; 511 end if; 512 513 when READOUT_PRESCALING => -- read most recent prescaling value from RAM and send it to RS485 module 514 wait_cntr <= wait_cntr + 1; 515 if (wait_cntr = 0) then 516 ram_ena_sig <= '1'; 517 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1, RAM_ADDR_WIDTH_A); 518 FTU_control_State <= READOUT_PRESCALING; 519 elsif (wait_cntr = 1) then 520 ram_ena_sig <= '1'; 521 ram_ada_sig <= (others => '0'); 522 prescaling_sig <= ram_doa; 523 FTU_control_State <= READOUT_PRESCALING; 524 elsif (wait_cntr = 2) then 525 ram_ena_sig <= '0'; 526 ram_ada_sig <= (others => '0'); 527 overflow_array_rs485_in <= ram_doa; 528 prescaling_ready <= '1'; 529 FTU_control_State <= READOUT_PRESCALING; 530 else 531 ram_ena_sig <= '0'; 532 ram_ada_sig <= (others => '0'); 533 prescaling_ready <= '0'; 534 wait_cntr <= 0; 535 FTU_control_State <= RUNNING; 536 end if; 537 318 538 end case; 319 539 end if; … … 330 550 331 551 reset <= reset_sig; 332 333 config_start <= config_start_sig; 334 dac_array <= dac_array_sig;552 553 config_start <= config_start_sig; 554 dac_array <= dac_array_sig; 335 555 336 556 enable_array <= enable_array_sig; 337 557 prescaling <= prescaling_sig; 558 338 559 rate_array_sig <= rate_array; 339 340 cntr_reset <= cntr_reset_sig; 341 prescaling <= prescaling_sig; 342 560 cntr_reset <= cntr_reset_sig; 561 343 562 ram_ena <= ram_ena_sig; 344 563 ram_enb <= ram_enb_sig; -
firmware/FTU/FTU_top.vhd
r9928 r9939 80 80 81 81 signal reset_sig : STD_LOGIC; -- initialized in FTU_control 82 signal dac_clr_sig : STD_LOGIC := '1'; -- not used in hardware, initialize to 1 at power up83 82 84 83 --single-ended trigger signals for rate counter … … 124 123 signal ram_dob_sig : STD_LOGIC_VECTOR(15 downto 0); 125 124 125 --signals from RS485 module, all initialized in FTU_rs485_control (or deeper) 126 signal new_DACs_sig : std_logic; 127 signal new_enables_sig : std_logic; 128 signal new_prescaling_sig : std_logic; 129 signal read_rates_sig : std_logic; 130 signal read_DACs_sig : std_logic; 131 signal read_enables_sig : std_logic; 132 signal read_prescaling_sig : std_logic; 133 signal dac_array_rs485_out_sig : dac_array_type; 134 signal enable_array_rs485_out_sig : enable_array_type; 135 signal prescaling_rs485_out_sig : STD_LOGIC_VECTOR(7 downto 0); 136 137 --signals to RS485 module, all initialized in FTU_control 138 signal rates_ready_sig : std_logic; 139 signal DACs_ready_sig : std_logic; 140 signal enables_ready_sig : std_logic; 141 signal prescaling_ready_sig : std_logic; 142 signal rate_array_rs485_sig : rate_array_type; 143 signal overflow_array_rs485_in_sig : STD_LOGIC_VECTOR(7 downto 0); 144 126 145 component FTU_clk_gen 127 146 port( … … 145 164 end component; 146 165 147 component FTU_control 148 port( 149 clk_50MHz : IN std_logic; 150 clk_ready : IN std_logic; 151 config_started : IN std_logic; 152 config_ready : IN std_logic; 153 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0); 154 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0); 155 rate_array : IN rate_array_type; 156 overflow_array : in STD_LOGIC_VECTOR(7 downto 0); 157 new_rates : IN std_logic; 158 reset : OUT std_logic; 159 config_start : OUT std_logic; 160 ram_ena : OUT std_logic; 161 ram_enb : OUT std_logic; 162 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0); 163 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0); 164 ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0); 165 ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0); 166 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0); 167 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0); 168 dac_array : OUT dac_array_type; 169 enable_array : OUT enable_array_type; 170 cntr_reset : OUT STD_LOGIC; 171 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0) 166 component FTU_control -- comments: see entity file 167 port( 168 clk_50MHz : IN std_logic; 169 clk_ready : IN std_logic; 170 config_started : IN std_logic; 171 config_ready : IN std_logic; 172 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0); 173 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0); 174 rate_array : IN rate_array_type; 175 overflow_array : in STD_LOGIC_VECTOR(7 downto 0); 176 new_rates : IN std_logic; 177 new_DACs : IN std_logic; 178 new_enables : IN std_logic; 179 new_prescaling : IN std_logic; 180 read_rates : IN std_logic; 181 read_DACs : IN std_logic; 182 read_enables : IN std_logic; 183 read_prescaling : IN std_logic; 184 dac_array_rs485_out : IN dac_array_type; 185 enable_array_rs485_out : IN enable_array_type; 186 prescaling_rs485_out : IN STD_LOGIC_VECTOR(7 downto 0); 187 reset : OUT std_logic; 188 config_start : OUT std_logic; 189 ram_ena : OUT std_logic; 190 ram_enb : OUT std_logic; 191 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0); 192 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0); 193 ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0); 194 ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0); 195 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0); 196 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0); 197 rate_array_rs485 : OUT rate_array_type; 198 overflow_array_rs485_in : OUT STD_LOGIC_VECTOR(7 downto 0); 199 rates_ready : OUT std_logic; 200 DACs_ready : OUT std_logic; 201 enables_ready : OUT std_logic; 202 prescaling_ready : OUT std_logic; 203 dac_array : OUT dac_array_type; 204 enable_array : OUT enable_array_type; 205 cntr_reset : OUT STD_LOGIC; 206 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0) 172 207 ); 173 208 end component; … … 186 221 end component; 187 222 188 component FTU_rs485_control 223 component FTU_rs485_control -- comments: see entity file 189 224 port( 190 225 main_clk : IN std_logic; … … 210 245 read_enables : OUT std_logic; 211 246 read_prescaling : OUT std_logic; 212 --rs485_error : OUT std_logic; -- to be discussed!213 247 dac_array_rs485_out : OUT dac_array_type; 214 248 enable_array_rs485_out : OUT enable_array_type; … … 243 277 begin 244 278 245 clr <= dac_clr_sig; 246 279 clr <= '1'; 280 TP_A <= "000000000000"; 281 247 282 enables_A <= enable_array_sig(0)(8 downto 0); 248 283 enables_B <= enable_array_sig(1)(8 downto 0); … … 251 286 252 287 new_rates_sig <= new_rate_A_sig and new_rate_B_sig and new_rate_C_sig and new_rate_D_sig and new_rate_t_sig; 288 289 --these bits are not used, others come from rate counters 290 overflow_array(5) <= '0'; 291 overflow_array(6) <= '0'; 292 overflow_array(7) <= '0'; 253 293 254 294 --differential input buffer for patch A … … 357 397 Inst_FTU_control : FTU_control 358 398 port map( 359 clk_50MHz => clk_50M_sig, 360 clk_ready => clk_ready_sig, 361 config_started => config_started_sig, 362 config_ready => config_ready_sig, 363 ram_doa => ram_doa_sig, 364 ram_dob => ram_dob_sig, 365 rate_array => rate_array_sig, 366 overflow_array => overflow_array, 367 new_rates => new_rates_sig, 368 reset => reset_sig, 369 config_start => config_start_sig, 370 ram_ena => ram_ena_sig, 371 ram_enb => ram_enb_sig, 372 ram_wea => ram_wea_sig, 373 ram_web => ram_web_sig, 374 ram_ada => ram_ada_sig, 375 ram_adb => ram_adb_sig, 376 ram_dia => ram_dia_sig, 377 ram_dib => ram_dib_sig, 378 dac_array => dac_array_sig, 379 enable_array => enable_array_sig, 380 cntr_reset => cntr_reset_sig, 381 prescaling => prescaling_sig 399 clk_50MHz => clk_50M_sig, 400 clk_ready => clk_ready_sig, 401 config_started => config_started_sig, 402 config_ready => config_ready_sig, 403 ram_doa => ram_doa_sig, 404 ram_dob => ram_dob_sig, 405 rate_array => rate_array_sig, 406 overflow_array => overflow_array, 407 new_rates => new_rates_sig, 408 new_DACs => new_DACs_sig, 409 new_enables => new_enables_sig, 410 new_prescaling => new_prescaling_sig, 411 read_rates => read_rates_sig, 412 read_DACs => read_DACs_sig, 413 read_enables => read_enables_sig, 414 read_prescaling => read_prescaling_sig, 415 dac_array_rs485_out => dac_array_rs485_out_sig, 416 enable_array_rs485_out => enable_array_rs485_out_sig, 417 prescaling_rs485_out => prescaling_rs485_out_sig, 418 reset => reset_sig, 419 config_start => config_start_sig, 420 ram_ena => ram_ena_sig, 421 ram_enb => ram_enb_sig, 422 ram_wea => ram_wea_sig, 423 ram_web => ram_web_sig, 424 ram_ada => ram_ada_sig, 425 ram_adb => ram_adb_sig, 426 ram_dia => ram_dia_sig, 427 ram_dib => ram_dib_sig, 428 rate_array_rs485 => rate_array_rs485_sig, 429 overflow_array_rs485_in => overflow_array_rs485_in_sig, 430 rates_ready => rates_ready_sig, 431 DACs_ready => DACs_ready_sig, 432 enables_ready => enables_ready_sig, 433 prescaling_ready => prescaling_ready_sig, 434 dac_array => dac_array_sig, 435 enable_array => enable_array_sig, 436 cntr_reset => cntr_reset_sig, 437 prescaling => prescaling_sig 382 438 ); 383 439 … … 399 455 brd_add => brd_add, 400 456 rx_d => rx, 401 rates_ready => '0',402 DACs_ready => '0',403 enables_ready => '0',404 prescaling_ready => '0',405 rate_array_rs485 => (0,0,0,0,0),406 overflow_array_rs485_in => "00000000",407 dac_array_rs485_in => DEFAULT_DAC,408 enable_array_rs485_in => DEFAULT_ENABLE,409 prescaling_rs485_in => conv_std_logic_vector(DEFAULT_PRESCALING,8),457 rates_ready => rates_ready_sig, 458 DACs_ready => DACs_ready_sig, 459 enables_ready => enables_ready_sig, 460 prescaling_ready => prescaling_ready_sig, 461 rate_array_rs485 => rate_array_rs485_sig, 462 overflow_array_rs485_in => overflow_array_rs485_in_sig, 463 dac_array_rs485_in => dac_array_sig, 464 enable_array_rs485_in => enable_array_sig, 465 prescaling_rs485_in => prescaling_sig, 410 466 rx_en => rx_en, 411 467 tx_d => tx, 412 468 tx_en => tx_en, 413 new_DACs => open, 414 new_enables => open, 415 new_prescaling => open, 416 read_rates => open, 417 read_DACs => open, 418 read_enables => open, 419 read_prescaling => open, 420 --rs485_error =>, -- to be discussed! 421 dac_array_rs485_out => open, 422 enable_array_rs485_out => open, 423 prescaling_rs485_out => open 469 new_DACs => new_DACs_sig, 470 new_enables => new_enables_sig, 471 new_prescaling => new_prescaling_sig, 472 read_rates => read_rates_sig, 473 read_DACs => read_DACs_sig, 474 read_enables => read_enables_sig, 475 read_prescaling => read_prescaling_sig, 476 dac_array_rs485_out => dac_array_rs485_out_sig, 477 enable_array_rs485_out => enable_array_rs485_out_sig, 478 prescaling_rs485_out => prescaling_rs485_out_sig 424 479 ); 425 480 -
firmware/FTU/FTU_top_tb.vhd
r9928 r9939 194 194 ); 195 195 196 -- Clock process definitions196 -- Stimulus process for clock 197 197 ext_clk_proc: process 198 198 begin … … 203 203 end process ext_clk_proc; 204 204 205 -- Stimulus process 206 stim_proc: process205 -- Stimulus process for trigger 206 trigger_proc: process 207 207 begin 208 208 --------------------------------------------------------------------------- … … 236 236 wait for 5ns; 237 237 trigger_sig <= '0'; 238 --------------------------------------------------------------------------- 239 -- test now RS485 240 --------------------------------------------------------------------------- 241 wait for 100us; 242 rx <= '0'; --start bit 243 wait for baud_rate_period; 244 rx <= '0'; --start delimiter bit 0 245 wait for baud_rate_period; 246 rx <= '0'; --start delimiter bit 1 247 wait for baud_rate_period; 248 rx <= '0'; --start delimiter bit 2 249 wait for baud_rate_period; 250 rx <= '0'; --start delimiter bit 3 251 wait for baud_rate_period; 252 rx <= '0'; --start delimiter bit 4 253 wait for baud_rate_period; 254 rx <= '0'; --start delimiter bit 5 255 wait for baud_rate_period; 256 rx <= '1'; --start delimiter bit 6 257 wait for baud_rate_period; 258 rx <= '0'; --start delimiter bit 7 259 wait for baud_rate_period; 260 rx <= '1'; --stop bit 261 wait for baud_rate_period; 262 rx <= '1'; --stop bit 263 wait for baud_rate_period; 264 --------------------------------------------------------------------------- 238 wait for 1430us; 239 trigger_sig <= '1'; 240 wait for 5ns; 241 trigger_sig <= '0'; 242 wait for 400us; 243 trigger_sig <= '1'; 244 wait for 5ns; 245 trigger_sig <= '0'; 246 wait; 247 end process trigger_proc; 248 249 -- Stimulus process for RS485 250 rs485_proc: process 251 252 procedure assign_rs485 (data: std_logic_vector(7 downto 0)) is 253 begin 254 rx <= '0'; --start bit 255 wait for baud_rate_period; 256 rx <= data(0); --bit 0 257 wait for baud_rate_period; 258 rx <= data(1); --bit 1 259 wait for baud_rate_period; 260 rx <= data(2); --bit 2 261 wait for baud_rate_period; 262 rx <= data(3); --bit 3 263 wait for baud_rate_period; 264 rx <= data(4); --bit 4 265 wait for baud_rate_period; 266 rx <= data(5); --bit 5 267 wait for baud_rate_period; 268 rx <= data(6); --bit 6 269 wait for baud_rate_period; 270 rx <= data(7); --bit 7 271 wait for baud_rate_period; 272 rx <= '1'; --stop bit 273 wait for baud_rate_period; 274 rx <= '1'; --stop bit 275 wait for baud_rate_period; 276 end assign_rs485; 277 278 begin 279 --------------------------------------------------------------------------- 280 -- wait until FTU is initialized 281 --------------------------------------------------------------------------- 282 wait for 150us; 283 --------------------------------------------------------------------------- 284 -- test one RS485 command (16 byte) 285 --------------------------------------------------------------------------- 286 assign_rs485("01000000"); --start delimiter 265 287 wait for 1us; 266 rx <= '0'; --start bit 267 wait for baud_rate_period; 268 rx <= '0'; --FTU address bit 0 269 wait for baud_rate_period; 270 rx <= '0'; --FTU address bit 1 271 wait for baud_rate_period; 272 rx <= '0'; --FTU address bit 2 273 wait for baud_rate_period; 274 rx <= '0'; --FTU address bit 3 275 wait for baud_rate_period; 276 rx <= '0'; --FTU address bit 4 277 wait for baud_rate_period; 278 rx <= '0'; --FTU address bit 5 279 wait for baud_rate_period; 280 rx <= '0'; --FTU address bit 6 281 wait for baud_rate_period; 282 rx <= '0'; --FTU address bit 7 283 wait for baud_rate_period; 284 rx <= '1'; --stop bit 285 wait for baud_rate_period; 286 rx <= '1'; --stop bit 287 wait for baud_rate_period; 288 --------------------------------------------------------------------------- 288 assign_rs485("00000000"); --FTU address 289 289 wait for 10ns; 290 rx <= '0'; --start bit 291 wait for baud_rate_period; 292 rx <= '0'; --FTM address bit 0 293 wait for baud_rate_period; 294 rx <= '0'; --FTM address bit 1 295 wait for baud_rate_period; 296 rx <= '0'; --FTM address bit 2 297 wait for baud_rate_period; 298 rx <= '0'; --FTM address bit 3 299 wait for baud_rate_period; 300 rx <= '0'; --FTM address bit 4 301 wait for baud_rate_period; 302 rx <= '0'; --FTM address bit 5 303 wait for baud_rate_period; 304 rx <= '1'; --FTM address bit 6 305 wait for baud_rate_period; 306 rx <= '1'; --FTM address bit 7 307 wait for baud_rate_period; 308 rx <= '1'; --stop bit 309 wait for baud_rate_period; 310 rx <= '1'; --stop bit 311 wait for baud_rate_period; 312 --------------------------------------------------------------------------- 313 wait for 100ns; 314 rx <= '0'; --start bit 315 wait for baud_rate_period; 316 rx <= '0'; --instruction bit 0 317 wait for baud_rate_period; 318 rx <= '1'; --instruction bit 1 319 wait for baud_rate_period; 320 rx <= '0'; --instruction bit 2 321 wait for baud_rate_period; 322 rx <= '0'; --instruction bit 3 323 wait for baud_rate_period; 324 rx <= '0'; --instruction bit 4 325 wait for baud_rate_period; 326 rx <= '0'; --instruction bit 5 327 wait for baud_rate_period; 328 rx <= '0'; --instruction bit 6 329 wait for baud_rate_period; 330 rx <= '0'; --instruction bit 7 331 wait for baud_rate_period; 332 rx <= '1'; --stop bit 333 wait for baud_rate_period; 334 rx <= '1'; --stop bit 335 wait for baud_rate_period; 336 --------------------------------------------------------------------------- 290 assign_rs485("11000000"); --FTM address 291 wait for 100ns; 292 assign_rs485("00000000"); --instruction 337 293 wait for 200us; 338 rx <= '0'; --start bit 339 wait for baud_rate_period; 340 rx <= '0'; --data1 bit 0 341 wait for baud_rate_period; 342 rx <= '0'; --data1 bit 1 343 wait for baud_rate_period; 344 rx <= '0'; --data1 bit 2 345 wait for baud_rate_period; 346 rx <= '0'; --data1 bit 3 347 wait for baud_rate_period; 348 rx <= '0'; --data1 bit 4 349 wait for baud_rate_period; 350 rx <= '0'; --data1 bit 5 351 wait for baud_rate_period; 352 rx <= '0'; --data1 bit 6 353 wait for baud_rate_period; 354 rx <= '0'; --data1 bit 7 355 wait for baud_rate_period; 356 rx <= '1'; --stop bit 357 wait for baud_rate_period; 358 rx <= '1'; --stop bit 359 wait for baud_rate_period; 360 --------------------------------------------------------------------------- 361 wait for 100ns; 362 rx <= '0'; --start bit 363 wait for baud_rate_period; 364 rx <= '0'; --data2 bit 0 365 wait for baud_rate_period; 366 rx <= '0'; --data2 bit 1 367 wait for baud_rate_period; 368 rx <= '0'; --data2 bit 2 369 wait for baud_rate_period; 370 rx <= '0'; --data2 bit 3 371 wait for baud_rate_period; 372 rx <= '0'; --data2 bit 4 373 wait for baud_rate_period; 374 rx <= '0'; --data2 bit 5 375 wait for baud_rate_period; 376 rx <= '0'; --data2 bit 6 377 wait for baud_rate_period; 378 rx <= '0'; --data2 bit 7 379 wait for baud_rate_period; 380 rx <= '1'; --stop bit 381 wait for baud_rate_period; 382 rx <= '1'; --stop bit 383 wait for baud_rate_period; 384 --------------------------------------------------------------------------- 385 wait for 100ns; 386 rx <= '0'; --start bit 387 wait for baud_rate_period; 388 rx <= '0'; --data3 bit 0 389 wait for baud_rate_period; 390 rx <= '0'; --data3 bit 1 391 wait for baud_rate_period; 392 rx <= '0'; --data3 bit 2 393 wait for baud_rate_period; 394 rx <= '0'; --data3 bit 3 395 wait for baud_rate_period; 396 rx <= '0'; --data3 bit 4 397 wait for baud_rate_period; 398 rx <= '0'; --data3 bit 5 399 wait for baud_rate_period; 400 rx <= '0'; --data3 bit 6 401 wait for baud_rate_period; 402 rx <= '0'; --data3 bit 7 403 wait for baud_rate_period; 404 rx <= '1'; --stop bit 405 wait for baud_rate_period; 406 rx <= '1'; --stop bit 407 wait for baud_rate_period; 408 --------------------------------------------------------------------------- 409 wait for 100ns; 410 rx <= '0'; --start bit 411 wait for baud_rate_period; 412 rx <= '0'; --data4 bit 0 413 wait for baud_rate_period; 414 rx <= '0'; --data4 bit 1 415 wait for baud_rate_period; 416 rx <= '0'; --data4 bit 2 417 wait for baud_rate_period; 418 rx <= '0'; --data4 bit 3 419 wait for baud_rate_period; 420 rx <= '0'; --data4 bit 4 421 wait for baud_rate_period; 422 rx <= '0'; --data4 bit 5 423 wait for baud_rate_period; 424 rx <= '0'; --data4 bit 6 425 wait for baud_rate_period; 426 rx <= '0'; --data4 bit 7 427 wait for baud_rate_period; 428 rx <= '1'; --stop bit 429 wait for baud_rate_period; 430 rx <= '1'; --stop bit 431 wait for baud_rate_period; 432 --------------------------------------------------------------------------- 433 wait for 100ns; 434 rx <= '0'; --start bit 435 wait for baud_rate_period; 436 rx <= '0'; --data5 bit 0 437 wait for baud_rate_period; 438 rx <= '0'; --data5 bit 1 439 wait for baud_rate_period; 440 rx <= '0'; --data5 bit 2 441 wait for baud_rate_period; 442 rx <= '0'; --data5 bit 3 443 wait for baud_rate_period; 444 rx <= '0'; --data5 bit 4 445 wait for baud_rate_period; 446 rx <= '0'; --data5 bit 5 447 wait for baud_rate_period; 448 rx <= '0'; --data5 bit 6 449 wait for baud_rate_period; 450 rx <= '0'; --data5 bit 7 451 wait for baud_rate_period; 452 rx <= '1'; --stop bit 453 wait for baud_rate_period; 454 rx <= '1'; --stop bit 455 wait for baud_rate_period; 456 --------------------------------------------------------------------------- 457 wait for 100ns; 458 rx <= '0'; --start bit 459 wait for baud_rate_period; 460 rx <= '0'; --data6 bit 0 461 wait for baud_rate_period; 462 rx <= '0'; --data6 bit 1 463 wait for baud_rate_period; 464 rx <= '0'; --data6 bit 2 465 wait for baud_rate_period; 466 rx <= '0'; --data6 bit 3 467 wait for baud_rate_period; 468 rx <= '0'; --data6 bit 4 469 wait for baud_rate_period; 470 rx <= '0'; --data6 bit 5 471 wait for baud_rate_period; 472 rx <= '0'; --data6 bit 6 473 wait for baud_rate_period; 474 rx <= '0'; --data6 bit 7 475 wait for baud_rate_period; 476 rx <= '1'; --stop bit 477 wait for baud_rate_period; 478 rx <= '1'; --stop bit 479 wait for baud_rate_period; 480 --------------------------------------------------------------------------- 481 wait for 100ns; 482 rx <= '0'; --start bit 483 wait for baud_rate_period; 484 rx <= '0'; --data7 bit 0 485 wait for baud_rate_period; 486 rx <= '0'; --data7 bit 1 487 wait for baud_rate_period; 488 rx <= '0'; --data7 bit 2 489 wait for baud_rate_period; 490 rx <= '0'; --data7 bit 3 491 wait for baud_rate_period; 492 rx <= '0'; --data7 bit 4 493 wait for baud_rate_period; 494 rx <= '0'; --data7 bit 5 495 wait for baud_rate_period; 496 rx <= '0'; --data7 bit 6 497 wait for baud_rate_period; 498 rx <= '0'; --data7 bit 7 499 wait for baud_rate_period; 500 rx <= '1'; --stop bit 501 wait for baud_rate_period; 502 rx <= '1'; --stop bit 503 wait for baud_rate_period; 504 --------------------------------------------------------------------------- 505 wait for 100ns; 506 rx <= '0'; --start bit 507 wait for baud_rate_period; 508 rx <= '0'; --data8 bit 0 509 wait for baud_rate_period; 510 rx <= '0'; --data8 bit 1 511 wait for baud_rate_period; 512 rx <= '0'; --data8 bit 2 513 wait for baud_rate_period; 514 rx <= '0'; --data8 bit 3 515 wait for baud_rate_period; 516 rx <= '0'; --data8 bit 4 517 wait for baud_rate_period; 518 rx <= '0'; --data8 bit 5 519 wait for baud_rate_period; 520 rx <= '0'; --data8 bit 6 521 wait for baud_rate_period; 522 rx <= '0'; --data8 bit 7 523 wait for baud_rate_period; 524 rx <= '1'; --stop bit 525 wait for baud_rate_period; 526 rx <= '1'; --stop bit 527 wait for baud_rate_period; 528 --------------------------------------------------------------------------- 529 wait for 100ns; 530 rx <= '0'; --start bit 531 wait for baud_rate_period; 532 rx <= '0'; --data9 bit 0 533 wait for baud_rate_period; 534 rx <= '0'; --data9 bit 1 535 wait for baud_rate_period; 536 rx <= '0'; --data9 bit 2 537 wait for baud_rate_period; 538 rx <= '0'; --data9 bit 3 539 wait for baud_rate_period; 540 rx <= '0'; --data9 bit 4 541 wait for baud_rate_period; 542 rx <= '0'; --data9 bit 5 543 wait for baud_rate_period; 544 rx <= '0'; --data9 bit 6 545 wait for baud_rate_period; 546 rx <= '0'; --data9 bit 7 547 wait for baud_rate_period; 548 rx <= '1'; --stop bit 549 wait for baud_rate_period; 550 rx <= '1'; --stop bit 551 wait for baud_rate_period; 552 --------------------------------------------------------------------------- 553 wait for 100ns; 554 rx <= '0'; --start bit 555 wait for baud_rate_period; 556 rx <= '0'; --data10 bit 0 557 wait for baud_rate_period; 558 rx <= '0'; --data10 bit 1 559 wait for baud_rate_period; 560 rx <= '0'; --data10 bit 2 561 wait for baud_rate_period; 562 rx <= '0'; --data10 bit 3 563 wait for baud_rate_period; 564 rx <= '0'; --data10 bit 4 565 wait for baud_rate_period; 566 rx <= '0'; --data10 bit 5 567 wait for baud_rate_period; 568 rx <= '0'; --data10 bit 6 569 wait for baud_rate_period; 570 rx <= '0'; --data10 bit 7 571 wait for baud_rate_period; 572 rx <= '1'; --stop bit 573 wait for baud_rate_period; 574 rx <= '1'; --stop bit 575 wait for baud_rate_period; 576 --------------------------------------------------------------------------- 577 wait for 100ns; 578 rx <= '0'; --start bit 579 wait for baud_rate_period; 580 rx <= '0'; --data11 bit 0 581 wait for baud_rate_period; 582 rx <= '0'; --data11 bit 1 583 wait for baud_rate_period; 584 rx <= '0'; --data11 bit 2 585 wait for baud_rate_period; 586 rx <= '0'; --data11 bit 3 587 wait for baud_rate_period; 588 rx <= '0'; --data11 bit 4 589 wait for baud_rate_period; 590 rx <= '0'; --data11 bit 5 591 wait for baud_rate_period; 592 rx <= '0'; --data11 bit 6 593 wait for baud_rate_period; 594 rx <= '0'; --data11 bit 7 595 wait for baud_rate_period; 596 rx <= '1'; --stop bit 597 wait for baud_rate_period; 598 rx <= '1'; --stop bit 599 wait for baud_rate_period; 600 --------------------------------------------------------------------------- 601 wait for 100ns; 602 rx <= '0'; --start bit 603 wait for baud_rate_period; 604 rx <= '0'; --check sum bit 0 605 wait for baud_rate_period; 606 rx <= '0'; --check sum bit 1 607 wait for baud_rate_period; 608 rx <= '0'; --check sum bit 2 609 wait for baud_rate_period; 610 rx <= '0'; --check sum bit 3 611 wait for baud_rate_period; 612 rx <= '0'; --check sum bit 4 613 wait for baud_rate_period; 614 rx <= '0'; --check sum bit 5 615 wait for baud_rate_period; 616 rx <= '0'; --check sum bit 6 617 wait for baud_rate_period; 618 rx <= '0'; --check sum bit 7 619 wait for baud_rate_period; 620 rx <= '1'; --stop bit 621 wait for baud_rate_period; 622 rx <= '1'; --stop bit 623 wait for baud_rate_period; 294 assign_rs485("00010000"); --data byte 01 295 wait for 100ns; 296 assign_rs485("00000000"); --data byte 02 297 wait for 100ns; 298 assign_rs485("10111100"); --data byte 03 299 wait for 100ns; 300 assign_rs485("00000001"); --data byte 04 301 wait for 100ns; 302 assign_rs485("00000000"); --data byte 05 303 wait for 100ns; 304 assign_rs485("00000000"); --data byte 06 305 wait for 100ns; 306 assign_rs485("00000000"); --data byte 07 307 wait for 100ns; 308 assign_rs485("00000000"); --data byte 08 309 wait for 100ns; 310 assign_rs485("00000000"); --data byte 09 311 wait for 100ns; 312 assign_rs485("00000000"); --data byte 10 313 wait for 100ns; 314 assign_rs485("00000000"); --data byte 11 315 wait for 100ns; 316 assign_rs485("00000000"); --check sum 317 wait for 100ns; 318 --------------------------------------------------------------------------- 319 -- keep rx line high 624 320 --------------------------------------------------------------------------- 625 321 rx <= '1'; 626 322 wait; 627 323 628 end process stim_proc;324 end process rs485_proc; 629 325 630 326 end; -
firmware/FTU/counter/FTU_rate_counter.vhd
r9911 r9939 119 119 begin 120 120 if rising_edge(cntr_reset) then 121 --formula to calculate counting period from prescaling value 121 --calculate counting period from prescaling value 122 --default is 0.5s - 128s if CNTR_FREQ_DIVIDER = 1 122 123 if (prescaling = "00000000") then 123 124 counting_period <= COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER); 125 elsif (prescaling = "11111111") then 126 counting_period <= 128 * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER); 124 127 else 125 128 counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER); -
firmware/FTU/dac_spi/FTU_spi_controller.vhd
r273 r9939 35 35 signal spi_cycle_cnt : integer range 0 to 25 := 0; 36 36 signal shift_reg : std_logic_vector (23 downto 0) := (others => '0'); 37 signal data_reg : std_logic_vector (15 downto 0) := (others => '0');38 37 39 38 BEGIN -
firmware/FTU/dac_spi/FTU_spi_distributor.vhd
r273 r9939 51 51 spi_distr_state <= IDLE; 52 52 when IDLE => 53 config_ready <= '0'; 53 54 data <= (others => '0'); 54 55 -- start DAC configuration -
firmware/FTU/ftu_definitions.vhd
r9928 r9939 58 58 constant INT_CLK_FREQUENCY : integer := 50000000; -- 50MHz 59 59 constant COUNTER_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY 60 constant CNTR_FREQ_DIVIDER : integer := 500000; -- for simulation, should normally be 160 constant CNTR_FREQ_DIVIDER : integer := 50000; -- for simulation, should normally be 1 61 61 62 62 --32byte dual-port RAM, port A: 8byte, port B: 16byte -
firmware/FTU/rs485/FTU_rs485_control.vhd
r9928 r9939 3 3 -- Engineer: Q. Weitzel, P. Vogler 4 4 -- 5 -- Create Date: 09/13/2010 5 -- Create Date: 09/13/2010 6 6 -- Design Name: 7 -- Module Name: FTU_rs485_control - Behavioral 7 -- Module Name: FTU_rs485_control - Behavioral 8 8 -- Project Name: 9 9 -- Target Devices: … … 11 11 -- Description: top level entity of FTU RS485 module 12 12 -- 13 -- Dependencies: 13 -- Dependencies: 14 14 -- 15 15 -- Revision: … … 50 50 tx_d : OUT std_logic; 51 51 tx_en : OUT std_logic; 52 new_DACs : OUT std_logic; -- new DACs arrived via RS485 53 new_enables : OUT std_logic; -- new enables arrived via RS485 54 new_prescaling : OUT std_logic; -- new prescaling arrived via RS485 55 read_rates : OUT std_logic; -- FTM wants to read rates 56 read_DACs : OUT std_logic; -- FTM wants to read DACs 57 read_enables : OUT std_logic; -- FTM wants to read enable pattern 58 read_prescaling : OUT std_logic; -- FTM wants to read prescaling value 59 --rs485_error : OUT std_logic; -- to be discussed! 52 new_DACs : OUT std_logic := '0'; -- new DACs arrived via RS485 53 new_enables : OUT std_logic := '0'; -- new enables arrived via RS485 54 new_prescaling : OUT std_logic := '0'; -- new prescaling arrived via RS485 55 read_rates : OUT std_logic := '0'; -- FTM wants to read rates 56 read_DACs : OUT std_logic := '0'; -- FTM wants to read DACs 57 read_enables : OUT std_logic := '0'; -- FTM wants to read enable pattern 58 read_prescaling : OUT std_logic := '0'; -- FTM wants to read prescaling value 60 59 dac_array_rs485_out : OUT dac_array_type; 61 60 enable_array_rs485_out : OUT enable_array_type; … … 278 277 when SET_DAC_WAIT=> -- wait until FTU control says "done" and then answer to FTM 279 278 if (DACs_ready = '1') then 280 new_DACs <= '0'; 279 new_DACs <= '0'; 281 280 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 282 281 else … … 288 287 if (enables_ready = '1') then 289 288 new_enables <= '0'; 290 FTU_rs485_control_State <= RECEIVE;289 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 291 290 else 292 291 new_enables <= '1'; … … 297 296 if (prescaling_ready = '1') then 298 297 new_prescaling <= '0'; 299 FTU_rs485_control_State <= RECEIVE;298 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 300 299 else 301 300 new_prescaling <= '1'; … … 306 305 if (rates_ready = '1') then 307 306 read_rates <= '0'; 308 FTU_rs485_control_State <= RE CEIVE;307 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 309 308 else 310 309 read_rates <= '1'; … … 315 314 if (DACs_ready = '1') then 316 315 read_DACs <= '0'; 317 FTU_rs485_control_State <= RE CEIVE;316 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 318 317 else 319 318 read_DACs <= '1'; … … 324 323 if (enables_ready = '1') then 325 324 read_enables <= '0'; 326 FTU_rs485_control_State <= RE CEIVE;325 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 327 326 else 328 327 read_enables <= '1'; … … 333 332 if (prescaling_ready = '1') then 334 333 read_prescaling <= '0'; 335 FTU_rs485_control_State <= RE CEIVE;334 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 336 335 else 337 336 read_prescaling <= '1'; -
firmware/FTU/rs485/FTU_rs485_interpreter.vhd
r9928 r9939 110 110 int_read_enables <= '0'; 111 111 int_read_prescaling <= '0'; 112 dac_array_rs485_out_sig <= (conv_integer(unsigned(data_block(47 downto 32))), 113 conv_integer(unsigned(data_block(63 downto 48))), 114 conv_integer(unsigned(data_block(79 downto 64))), 115 conv_integer(unsigned(data_block(95 downto 80))), 116 0,0,0, 117 conv_integer(unsigned(data_block(111 downto 96))) 112 dac_array_rs485_out_sig <= (conv_integer(unsigned(data_block(43 downto 32))), 113 conv_integer(unsigned(data_block(59 downto 48))), 114 conv_integer(unsigned(data_block(75 downto 64))), 115 conv_integer(unsigned(data_block(91 downto 80))), 116 DEFAULT_DAC(4), 117 DEFAULT_DAC(5), 118 DEFAULT_DAC(6), 119 conv_integer(unsigned(data_block(107 downto 96))) 118 120 ); 119 121 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
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