Changeset 10729 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Timestamp:
- 05/17/11 18:29:09 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 9 edited
-
data_generator.vhd (modified) (3 diffs)
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fad_board_struct.vhd (modified) (9 diffs)
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fad_definitions.vhd (modified) (2 diffs)
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fad_main_struct.vhd (modified) (6 diffs)
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memory_manager_beha.vhd (modified) (9 diffs)
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spi_controller_beha.vhd (modified) (4 diffs)
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spi_distributor_beha.vhd (modified) (3 diffs)
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spi_interface_struct.vhd (modified) (2 diffs)
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w5300_modul.vhd (modified) (43 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10502 r10729 161 161 signal internal_roi_max : roi_max_type; 162 162 163 signal config_start_sr : std_logic_vector(1 downto 0) := "00"; 164 165 signal adc_data_sig : adc_data_array_type; 166 signal adc_otr_sig : std_logic_vector(3 downto 0) ; 167 type adc_data_16bit_t is array (3 downto 0) of sdt_logic_vector(15 downto 0); 168 signal data_16bit : adc_data_16bit_t; 169 163 170 begin 164 171 drs_readout_started <= sig_drs_readout_started; … … 166 173 begin 167 174 if rising_edge (clk) then 168 169 if (config_start = '1') then 175 -- synch 176 config_start_sr <= config_start_sr(0) & config_start; 177 178 if (config_start_sr(1) = '1') then 170 179 config_start_sig <= '1'; 171 180 config_done <= '0'; … … 393 402 state_generate <= WRITE_ADC_DATA; 394 403 end if; 404 405 -- when CATCH_ADC_DATA => 406 -- adc_data_sig <= adc_data_array; 407 -- adc_otr_sig <= adc_otr; 408 -- state_generate <= PREPARE_ADC_DATA_01; 409 -- 410 -- when PREPARE_ADC_DATA_01 => 411 -- for i in 3 downto 0 loop 412 -- if (adc_otr_sig(i)='1') then 413 -- if (adc_data_sig(i)(11)='1') then 414 -- data_16bit(i) = X"8000" --this is decimal -1 415 -- else -- adc_data_sig(i)(11)='0' 416 -- data_16bit(i) = X"1001" --this is decimal +4097 417 -- end if; 418 -- else -- no over/underflow 419 -- data_16bit(i) = 420 -- end loop; 421 422 423 395 424 when WRITE_ADC_DATA => 396 425 if (data_cntr < roi_max_int (channel_id)) then -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10567 r10729 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 1 5:22:10 04.05.20115 -- at - 17:58:44 17.05.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 76 76 -- Created: 77 77 -- by - daqct3.UNKNOWN (IHP110) 78 -- at - 1 5:22:11 04.05.201178 -- at - 17:58:44 17.05.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 105 105 SIGNAL counter_result : std_logic_vector(11 DOWNTO 0) := (others => '0'); 106 106 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); 107 SIGNAL debug_data_ram_empty : std_logic; 108 SIGNAL debug_data_valid : std_logic; 107 109 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 110 SIGNAL w5300_state : std_logic_vector(7 DOWNTO 0); -- state is encoded here ... useful for debugging. 108 111 109 112 … … 144 147 counter_result : OUT std_logic_vector (11 DOWNTO 0); 145 148 dac_cs : OUT std_logic ; 149 debug_data_ram_empty : OUT std_logic ; 150 debug_data_valid : OUT std_logic ; 146 151 denable : OUT std_logic := '0'; -- default domino wave off 147 152 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); … … 154 159 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 155 160 trigger_veto : OUT std_logic := '1'; 161 w5300_state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging. 156 162 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 157 163 wiz_cs : OUT std_logic := '1'; … … 195 201 196 202 --D_T <= (others => '0'); 203 D_T <= w5300_state; 204 D_T2(0) <= debug_data_valid; 205 D_T2(1) <= debug_data_ram_empty; 197 206 --D_T2 <= ( others => '0' ); 198 D_T2(1) <= '0';207 199 208 -- A0_T(7 downto 0) <= (others => '0'); 200 209 --A1_T(7 downto 0) <= (others => '0'); 201 210 202 211 A1_T <= counter_result ( 7 downto 0); 203 D_T(3 downto 0) <= counter_result ( 11 downto 8);204 D_T(4) <= alarm_refclk_too_low;205 D_T(5) <= alarm_refclk_too_high;206 D_T(6) <= '0';207 D_T(7) <= '0';212 --D_T(3 downto 0) <= counter_result ( 11 downto 8); 213 --D_T(4) <= alarm_refclk_too_low; 214 --D_T(5) <= alarm_refclk_too_high; 215 --D_T(6) <= '0'; 216 --D_T(7) <= '0'; 208 217 209 218 -- led output is driven by w5300 modul … … 216 225 RS485_C_DO <= '0'; 217 226 -- MAX3485 receiver out pit is fed out... should be HIGH-Z 218 D_T2(0) <= RS485_C_DI;227 219 228 220 229 -- EEPROM is not used on FAD. CS is always high. … … 258 267 counter_result => counter_result, 259 268 dac_cs => DAC_CS, 269 debug_data_ram_empty => debug_data_ram_empty, 270 debug_data_valid => debug_data_valid, 260 271 denable => DENABLE, 261 272 drs_channel_id => D_A, … … 268 279 sensor_cs => TCS, 269 280 trigger_veto => TRG_V, 281 w5300_state => w5300_state, 270 282 wiz_addr => W_A, 271 283 wiz_cs => W_CS, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10567 r10729 57 57 --constant SUBVERSION_NUMBER : std_logic_vector (15 downto 0) := conv_std_logic_vector(str_to_int(SUBVERSION_STRING),16); 58 58 constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01"; 59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"0 4";59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"07"; 60 60 constant PACKAGE_HEADER_LENGTH : integer := 36; 61 61 constant PACKAGE_HEADER_ZEROS : integer := 0; … … 89 89 constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30"; 90 90 91 constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0"; 92 constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2"; 93 constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4"; 94 constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6"; 95 constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8"; 96 constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A"; 97 constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12"; 98 constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14"; 99 constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20"; 100 constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24"; 101 constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28"; 102 constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E"; 103 constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30"; 91 constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0"; 92 constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2"; 93 constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4"; 94 constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6"; 95 constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8"; 96 constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A"; 97 constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12"; 98 constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14"; 99 constant W5300_S0_PORTOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"1A"; -- HIGH byte is S0_KPALVTR register 100 constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20"; 101 constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24"; 102 constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28"; 103 constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E"; 104 constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30"; 104 105 -- End W5300 registers 105 106 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10567 r10729 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 1 5:22:09 04.05.20115 -- at - 17:58:42 17.05.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 48 48 counter_result : OUT std_logic_vector (11 DOWNTO 0); 49 49 dac_cs : OUT std_logic; 50 debug_data_ram_empty : OUT std_logic; 51 debug_data_valid : OUT std_logic; 50 52 denable : OUT std_logic := '0'; -- default domino wave off 51 53 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); … … 58 60 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 59 61 trigger_veto : OUT std_logic := '1'; 62 w5300_state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging. 60 63 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 61 64 wiz_cs : OUT std_logic := '1'; … … 76 79 -- Created: 77 80 -- by - daqct3.UNKNOWN (IHP110) 78 -- at - 1 5:22:10 04.05.201181 -- at - 17:58:43 17.05.2011 79 82 -- 80 83 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 484 487 ); 485 488 PORT ( 489 state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging. 490 debug_data_ram_empty : OUT std_logic ; 491 debug_data_valid : OUT std_logic ; 486 492 clk : IN std_logic ; 487 493 wiz_reset : OUT std_logic := '1'; … … 886 892 ) 887 893 PORT MAP ( 894 state => w5300_state, 895 debug_data_ram_empty => debug_data_ram_empty, 896 debug_data_valid => debug_data_valid, 888 897 clk => CLK_50_internal, 889 898 wiz_reset => wiz_reset, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd
r10225 r10729 102 102 signal temp_roi : integer range 0 to 1024 := 0; 103 103 104 -- SYNCH IN INPUT SIGNALS ----------------------------------------- 105 106 signal config_start_sr : std_logic_vector(1 downto 0) := "00"; 107 signal ram_write_ready_sr : std_logic_vector(1 downto 0) := "00"; 108 signal wiz_busy_sr : std_logic_vector(1 downto 0) := "00"; 109 signal wiz_ack_sr : std_logic_vector(1 downto 0) := "00"; 110 -- no shift register, but local copy. 111 signal roi_array_local : roi_array_type; 112 104 113 BEGIN 105 114 … … 110 119 begin 111 120 if rising_edge (clk) then 121 -- here: the synchin in of asynchronous input signals takes place. 122 config_start_sr <= config_start_sr(0) & config_start; 123 ram_write_ready_sr <= ram_write_ready_sr(0) & ram_write_ready; 124 wiz_busy_sr <= wiz_busy_sr(0) & wiz_busy; 125 wiz_ack_sr <= wiz_ack_sr(0) & wiz_ack; 126 127 roi_array_local <= roi_array; 128 112 129 case state_mm is 113 130 114 131 when MM_CONFIG => 115 if (config_start = '1') then 132 -- this if clause was doubled ... already in MAIN state config_start = '1' was checked... 133 -- this is imho not needed and can cause trouble... DN 17.05.11 134 --if (config_start_sr = "11") then 116 135 config_ready <= '0'; 117 136 roi_max_array <= (others => 0); … … 122 141 ram_write_ea <= '0'; 123 142 state_mm <= MAX_ROI; 124 end if;143 --end if; 125 144 126 145 -- calculate max ROIs and channel sizes … … 129 148 state_mm <= MAX_ROI1; 130 149 when MAX_ROI1 => 131 temp_roi <= roi_array (roi_index);150 temp_roi <= roi_array_local (roi_index); 132 151 state_mm <= MAX_ROI2; 133 152 when MAX_ROI2 => … … 222 241 when MM_MAIN => 223 242 state_mm <= MM_MAIN1; 224 if (config_start = '1') then243 if (config_start_sr = "11") then 225 244 --config_ready <= '0'; 226 245 if (events_in_ram = 0) then … … 231 250 when MM_MAIN1 => 232 251 state_mm <= MM_MAIN2; 233 if ((ram_write_ready = '1') and (event_ready_flag = '0')) then252 if ((ram_write_ready_sr = "11") and (event_ready_flag = '0')) then 234 253 ram_write_ea <= '0'; 235 254 -- -- … … 248 267 when MM_MAIN2 => 249 268 state_mm <= MM_MAIN3; 250 if ((event_ready_flag = '1') and (ram_write_ready = '0')) then269 if ((event_ready_flag = '1') and (ram_write_ready_sr = "00")) then 251 270 if (events_in_ram < max_events_ram) then 252 271 ram_write_ea <= '1'; … … 261 280 when MM_MAIN3 => 262 281 state_mm <= MM_MAIN4; 263 if ((wiz_ack = '1') and (wiz_ack_flag = '0')) then282 if ((wiz_ack_sr = "11") and (wiz_ack_flag = '0')) then 264 283 wiz_ack_flag <= '1'; 265 284 wiz_write_ea <= '0'; … … 279 298 when MM_MAIN4 => 280 299 state_mm <= MM_MAIN; 281 if ((events_in_ram > 0) and (wiz_busy = '0')) then300 if ((events_in_ram > 0) and (wiz_busy_sr = "00")) then 282 301 if (package_index < number_of_packages) then 283 302 wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, RAM_ADDR_WIDTH_16B); -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_controller_beha.vhd
r9912 r10729 39 39 signal data_reg : std_logic_vector (15 downto 0) := (others => '0'); 40 40 41 signal dac_start_sr : std_logic_vector (1 downto 0) := "00"; 42 signal sensor_start_sr : std_logic_vector (1 downto 0) := "00"; 43 41 44 BEGIN 42 45 … … 44 47 begin 45 48 if falling_edge(clk) then 49 dac_start_sr <= dac_start_sr(0) & dac_start; 50 sensor_start_sr <= sensor_start_sr(0) & sensor_start; 51 52 46 53 dac_cs <= '1'; 47 54 sensor_cs <= (others => '1'); … … 51 58 case spi_state is 52 59 when SPI_IDLE => 53 if (dac_start = '1') then60 if (dac_start_sr(1) = '1') then 54 61 dac_ready <= '0'; 55 62 spi_state <= SPI_LOAD_COMMAND; 56 elsif (sensor_start = '1') then63 elsif (sensor_start_sr(1) = '1') then 57 64 sensor_valid <= '0'; 58 65 spi_state <= SPI_LOAD_COMMAND; … … 61 68 when SPI_LOAD_COMMAND => 62 69 spi_cycle_cnt <= 0; 63 if (sensor_start = '1') then70 if (sensor_start_sr(1) = '1') then 64 71 shift_reg <= X"C1" & X"0000"; -- command: Temperature register read 65 72 spi_state <= SPI_GET_TEMP; 66 elsif (dac_start = '1') then73 elsif (dac_start_sr(1) = '1') then 67 74 shift_reg <= "0011" & '0' & dac_id & data; 68 75 spi_state <= SPI_LOAD_DAC; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_distributor_beha.vhd
r10225 r10729 58 58 signal sclk_enable_override_sig : std_logic := '0'; 59 59 60 -- synching signals 61 signal config_start_sr : std_logic_vector (1 downto 0) := "00"; 62 60 63 BEGIN 61 64 sclk_enable_override <= sclk_enable_override_sig; … … 66 69 67 70 if rising_edge(clk) then 71 -- synch in 72 config_start_sr <= config_start_sr(0) & config_start; 73 68 74 data <= (others => 'Z'); 69 75 case spi_distr_state is … … 80 86 data <= (others => 'Z'); 81 87 -- start DAC configuration 82 if (config_start = '1' AND int_sensor_valid = '1') then88 if (config_start_sr(1) = '1' AND int_sensor_valid = '1') then 83 89 config_ready <= '0'; 84 90 sclk_enable_override_sig <= '1'; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd
r10225 r10729 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 1 6:52:21 02.03.20115 -- at - 10:39:55 17.05.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 39 39 -- Created: 40 40 -- by - daqct3.UNKNOWN (IHP110) 41 -- at - 1 6:52:21 02.03.201141 -- at - 10:39:56 17.05.2011 42 42 -- 43 43 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10565 r10729 12 12 ); 13 13 PORT( 14 state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging. 15 debug_data_ram_empty : OUT std_logic; 16 debug_data_valid : OUT std_logic; 17 14 18 clk : IN std_logic; 15 19 wiz_reset : OUT std_logic := '1'; … … 34 38 c_trigger_enable: out std_logic := '0'; 35 39 c_trigger_mult: out std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(0 ,16); --subject to changes 40 41 36 42 37 43 -- FAD configuration signals: … … 94 100 END w5300_modul ; 95 101 96 architecture Behavioral of w5300_modul is 102 architecture Behavioral of w5300_modul is 97 103 98 104 type state_init_type is ( 99 105 INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, 100 106 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 101 SI, SI1, SI 2, SI3, SI4, SI5, SI6, ESTABLISH, EST1,107 SI, SI1, SI1b, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, 102 108 103 CONFIG, 104 WAIT_FOR_OLLI, 105 WAIT_FOR_DATA_RAM_EMPTY, 109 --CONFIG, WAIT_FOR_OLLI, WAIT_FOR_DATA_RAM_EMPTY, 106 110 CONFIG_MEMORY_MANAGER, WAIT_FOR_CONFIG_MEMORY_MANAGER, 107 111 CONFIG_DATA_GENERATOR, WAIT_FOR_CONFIG_DATA_GENERATOR, … … 185 189 signal local_fifo_channels : std_logic_vector (3 downto 0); 186 190 187 signal data_ram_empty_sr : std_logic_vector (3 downto 0) := "0000";188 189 191 signal config_addr : integer range 0 to 44; 190 192 type config_data_type is array (0 to 46) of std_logic_vector(15 downto 0); … … 219 221 220 222 -- signals for synching in asynchronous input signals 221 ------------------------------------------------------------------------------ 222 signal w5300_interrupt_sr : std_logic_vector(1 downto 0) := "11"; 223 --?? not sure if this init value is good 224 -- but should be no problem, because interrupt_ignore is not true during the first 2 clock cycles. 225 -- I hope! 226 signal data_valid_sr : std_logic_vector(1 downto 0) := "00"; 227 ------------------------------------------------------------------------------ 228 223 ------------------------------------------------------------------------------ 224 signal w5300_interrupt_sr : std_logic_vector(1 downto 0) := "11"; 225 --?? not sure if this init value is good 226 -- but should be no problem, because interrupt_ignore is not true during the first 2 clock cycles. 227 -- I hope! 228 signal data_valid_sr : std_logic_vector(1 downto 0) := "00"; 229 ------------------------------------------------------------------------------ 230 -- synch in CONFIG inputs 231 signal memory_manager_config_valid_i_sr : std_logic_vector(1 downto 0) := "00"; 232 signal spi_interface_config_valid_i_sr : std_logic_vector(1 downto 0) := "00"; 233 signal data_generator_config_valid_i_sr : std_logic_vector(1 downto 0) := "00"; 234 signal data_ram_empty_sr : std_logic_vector(1 downto 0) := (OTHERS => '0'); 235 236 237 229 238 230 239 -- only for debugging … … 243 252 signal mod7_result : std_logic_vector(2 downto 0); 244 253 254 signal state_sig : std_logic_vector(7 downto 0) := X"FF"; 245 255 246 256 … … 279 289 280 290 -- output config settings as DAC and ROI arrays. 281 291 state <= state_sig; 292 debug_data_ram_empty <= data_ram_empty_sr(1); 293 debug_data_valid <= data_valid_sr(1); 282 294 283 295 roi_mapping : for i in 0 to 35 generate … … 296 308 begin 297 309 if rising_edge (clk) then 298 -- synch asynchronous input in: 299 data_ram_empty_sr <= data_ram_empty_sr(2 downto 0) & data_ram_empty; 300 w5300_interrupt_sr <= w5300_interrupt_sr(1) & int; 301 data_valid_sr <= data_valid_sr(1) & data_valid; 310 -- synch asynchronous inputs in: 311 memory_manager_config_valid_i_sr <= memory_manager_config_valid_i_sr(0) & memory_manager_config_valid_i; 312 spi_interface_config_valid_i_sr <= spi_interface_config_valid_i_sr(0) & spi_interface_config_valid_i; 313 data_generator_config_valid_i_sr <= data_generator_config_valid_i_sr(0) & data_generator_config_valid_i; 314 data_ram_empty_sr <= data_ram_empty_sr(0) & data_ram_empty; 315 316 w5300_interrupt_sr <= w5300_interrupt_sr(0) & int; 317 data_valid_sr <= data_valid_sr(0) & data_valid; 302 318 303 319 -- interrupt is handled synchronously … … 393 409 -- reset W5300 394 410 when RESET => 411 state_sig <= X"01"; 395 412 socket_send_mode <= '0'; 396 413 busy <= '1'; … … 418 435 -- Init 419 436 when INIT => 437 state_sig <= X"02"; 420 438 -- status of MAC jumpers is synched in 421 439 -- and Board- and CrateID are synched in … … 429 447 next_state <= LOCATE; 430 448 431 when LOCATE => 449 when LOCATE => 450 state_sig <= X"03"; 432 451 state_init <= IM; 433 452 … … 481 500 -- Interrupt Mask 482 501 when IM => 502 state_sig <= X"04"; 483 503 par_addr <= W5300_IMR; 484 504 par_data <= X"00FF"; -- S0-S7 Interrupts … … 604 624 -- Socket Init 605 625 when SI => 626 state_sig <= X"05"; 606 627 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; 607 628 par_data <= X"0101"; -- ALIGN, TCP … … 613 634 par_data <= X"000A"; -- TIMEOUT, DISCON 614 635 state_init <= WRITE_REG; 615 next_state <= SI2; 636 next_state <= SI1b; 637 when SI1b => 638 par_addr <= W5300_S0_PORTOR + socket_cnt * W5300_S_INC; 639 par_data <= X"0606"; -- send automatic KEEP ALIVE every 30s. 640 state_init <= WRITE_REG; 641 next_state <= SI2; 616 642 when SI2 => 617 643 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC; … … 668 694 end case; 669 695 670 when CONFIG => -- Triggers are disabled here! 671 trigger_enable_storage_sig <= trigger_enable_sig; -- store last value of this signal. 672 trigger_enable_sig <= '0'; --no triggers must occur, while configurating. 673 state_init <= WAIT_FOR_OLLI; -- now wait until the last event was send down.. 674 675 when WAIT_FOR_OLLI => -- This single wait state is not needed, I guess. 676 state_init <= WAIT_FOR_DATA_RAM_EMPTY; -- should be removed asap, but not now. 28.04.11 DN 677 678 679 when WAIT_FOR_DATA_RAM_EMPTY => 680 if (data_ram_empty_sr(3) = '1') then 681 state_init <= CONFIG_MEMORY_MANAGER; 682 end if; 696 -- when CONFIG => -- Triggers are disabled here! 697 -- state_sig <= X"06"; 698 -- trigger_enable_storage_sig <= trigger_enable_sig; -- store last value of this signal. 699 -- trigger_enable_sig <= '0'; --no triggers must occur, while configurating. 700 -- state_init <= WAIT_FOR_OLLI; -- now wait until the last event was send down.. 701 -- 702 -- when WAIT_FOR_OLLI => -- This single wait state is not needed, I guess. 703 -- state_sig <= X"16"; 704 -- state_init <= WAIT_FOR_DATA_RAM_EMPTY; -- should be removed asap, but not now. 28.04.11 DN 705 -- 706 -- 707 -- when WAIT_FOR_DATA_RAM_EMPTY => 708 -- state_sig <= X"17"; 709 -- if (data_ram_empty_sr(1) = '1') then 710 -- state_init <= CONFIG_MEMORY_MANAGER; 711 -- end if; 683 712 684 713 when CONFIG_MEMORY_MANAGER => 714 state_sig <= X"18"; 685 715 memory_manager_config_start_o <= '1'; 686 if (memory_manager_config_valid_i = '0') then716 if (memory_manager_config_valid_i_sr = "00") then 687 717 state_init <= WAIT_FOR_CONFIG_MEMORY_MANAGER; 688 718 end if; 689 719 690 720 when WAIT_FOR_CONFIG_MEMORY_MANAGER => 721 state_sig <= X"19"; 691 722 memory_manager_config_start_o <= '0'; 692 if (memory_manager_config_valid_i = '1') then723 if (memory_manager_config_valid_i_sr = "11") then 693 724 state_init <= CONFIG_DATA_GENERATOR; 694 725 end if; 695 726 696 727 when CONFIG_DATA_GENERATOR => 728 state_sig <= X"1A"; 697 729 data_generator_config_start_o <= '1'; 698 if (data_generator_config_valid_i = '0') then730 if (data_generator_config_valid_i_sr = "00") then 699 731 state_init <= WAIT_FOR_CONFIG_DATA_GENERATOR; 700 732 end if; 701 733 when WAIT_FOR_CONFIG_DATA_GENERATOR => 734 state_sig <= X"1B"; 702 735 data_generator_config_start_o <= '0'; 703 if (data_generator_config_valid_i = '1') then736 if (data_generator_config_valid_i_sr ="11") then 704 737 trigger_enable_sig <= trigger_enable_storage_sig; --restore value of this signal to the value it had before CONFIG 705 738 state_init <= MAIN; … … 708 741 709 742 when CONFIG_DAC_ONLY => 743 state_sig <= X"1C"; 710 744 spi_interface_config_start_o <= '1'; 711 if (spi_interface_config_valid_i ='0') then745 if (spi_interface_config_valid_i_sr ="00") then 712 746 state_init <= WAIT_FOR_CONFIG_DAC_ONLY; 713 747 end if; 714 748 715 749 when WAIT_FOR_CONFIG_DAC_ONLY => 750 state_sig <= X"1D"; 716 751 spi_interface_config_start_o <= '0'; 717 if (spi_interface_config_valid_i ='1') then752 if (spi_interface_config_valid_i_sr ="11") then 718 753 state_init <= MAIN; 719 754 end if; … … 724 759 725 760 when MAIN => 761 state_sig <= X"20"; 762 socks_waiting <= '0'; 763 socks_connected <= '1'; 764 ps_do_phase_shift <= '0'; 765 ps_reset <= '0'; 766 data_valid_ack <= '0'; 726 767 727 768 728 if (update_of_rois = '1') then 729 update_of_rois <= '0'; 730 state_init <= CONFIG; 769 if (update_of_rois = '1') then 770 trigger_enable_storage_sig <= trigger_enable_sig; 771 trigger_enable_sig <= '0'; 772 773 if (data_ram_empty_sr(1) = '1') then 774 update_of_rois <= '0'; 775 state_init <= CONFIG_MEMORY_MANAGER; 776 else 777 state_init <= MAIN2; 778 end if; 731 779 elsif (update_of_lessimportant = '1') then 732 780 update_of_lessimportant <= '0'; 733 781 state_init <= CONFIG_DAC_ONLY; 734 782 elsif ( update_of_rois='0' and update_of_lessimportant='0' ) then 735 socks_waiting <= '0';736 socks_connected <= '1';737 ps_do_phase_shift <= '0';738 ps_reset <= '0';739 data_valid_ack <= '0';740 783 state_init <= MAIN1; 741 784 --data_valid_int <= data_valid; … … 743 786 744 787 when MAIN1 => 788 state_sig <= X"21"; 745 789 if (chk_recv_cntr = 1000) then 746 790 chk_recv_cntr <= 0; … … 753 797 end if; 754 798 when MAIN2 => 799 state_sig <= X"22"; 755 800 busy <= '0'; 756 801 --if (data_valid = '1') then 757 if (data_valid_sr = "01" or data_valid_sr = "11") then802 if (data_valid_sr(1) = '1') then 758 803 --data_valid_int <= '0'; 759 804 busy <= '1'; … … 769 814 state_init <= MAIN3; 770 815 else 771 state_init <= MAIN 1;816 state_init <= MAIN; -- MAIN1 772 817 end if; 773 818 when MAIN3 => 819 state_sig <= X"23"; 774 820 -- needed for the check: if there is enough space in W5300 FIFO 775 821 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2) … … 786 832 case state_read_data is 787 833 when RD_1 => 834 state_sig <= X"30"; 788 835 par_addr <= W5300_S0_RX_RSR; 789 836 state_init <= READ_REG; … … 791 838 state_read_data <= RD_2; 792 839 when RD_2 => 840 state_sig <= X"31"; 793 841 socket_rx_received (16) <= data_read(0); 794 842 par_addr <= W5300_S0_RX_RSR + X"2"; … … 797 845 state_read_data <= RD_3; 798 846 when RD_3 => 847 state_sig <= X"32"; 799 848 socket_rx_received (15 downto 0) <= data_read; 800 849 state_read_data <= RD_4; 801 850 when RD_4 => 851 state_sig <= X"33"; 802 852 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then 803 853 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2 … … 808 858 end if; 809 859 when RD_5 => 860 state_sig <= X"34"; 810 861 s_trigger <= '0'; 811 862 ps_do_phase_shift <= '0'; … … 823 874 824 875 when RD_6 => 876 state_sig <= X"35"; 825 877 -- The next 16bit word is assumed to contain a 'command' so it is 826 878 -- beeing parsed in this state … … 905 957 906 958 when WAIT_FOR_TRIGGER_ID_RESET_1 => 959 state_sig <= X"36"; 907 960 state_read_data <= WAIT_FOR_TRIGGER_ID_RESET_2; 908 961 when WAIT_FOR_TRIGGER_ID_RESET_2 => 962 state_sig <= X"37"; 909 963 state_read_data <= RD_5; 910 964 -- these states are beeing processed, if the 'command' was a 'write command' 911 965 -- so it is assumed, that some data in config RAM changed, and we need full (re)config 912 966 when READ_COMMAND_DATA_SECTION => 967 state_sig <= X"38"; 913 968 if (rx_packets_cnt > 0) then 914 969 rx_packets_cnt <= rx_packets_cnt - '1'; … … 922 977 923 978 when PUT_COMMAND_DATA_SECTION => 979 state_sig <= X"39"; 924 980 config_setting(config_addr) <= data_read; 925 981 if (config_addr < 36) then … … 934 990 935 991 when RD_END => 992 state_sig <= X"3A"; 936 993 par_addr <= W5300_S0_CR; 937 994 par_data <= X"0040"; -- RECV 938 995 state_init <= WRITE_REG; 939 996 next_state <= MAIN; 940 941 997 998 when others => 999 state_sig <= X"3F"; 1000 942 1001 end case; -- state_data_read 943 1002 … … 948 1007 949 1008 when WR_START => 1009 state_sig <= X"40"; 950 1010 if (local_write_header_flag = '1') then 951 1011 ram_addr <= local_ram_start_addr + 6; -- Address of HIGH word of Event ID … … 956 1016 957 1017 when WR_GET_EVT_ID_WAIT1 => 1018 state_sig <= X"41"; 958 1019 state_write <= WR_GET_EVT_ID1; 959 1020 when WR_GET_EVT_ID1 => 1021 state_sig <= X"42"; 960 1022 event_number(31 downto 16) <= ram_data; 961 1023 ram_addr <= local_ram_start_addr + 9; -- Address of LOW word of Event ID … … 964 1026 state_write <= WR_GET_EVT_ID2; 965 1027 when WR_GET_EVT_ID2 => 1028 state_sig <= X"43"; 966 1029 event_number(15 downto 0) <= ram_data; 967 1030 mod7_start <= '1'; … … 973 1036 974 1037 when WR_MOD7_STARTED => 1038 state_sig <= X"44"; 975 1039 if (mod7_started = '1') then 976 1040 mod7_start <= '0'; … … 979 1043 980 1044 when WR_WAIT_FOR_MOD7 => 1045 state_sig <= X"45"; 981 1046 if (mod7_valid = '1') then 982 1047 if (socket_send_mode = '1') then -- send via all sockets … … 994 1059 -- Check FIFO Size 995 1060 when WR_CHECK_FOR_FIFO_SPACE_01 => 1061 state_sig <= X"46"; 996 1062 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; 997 1063 state_init <= READ_REG; … … 999 1065 state_write <= WR_CHECK_FOR_FIFO_SPACE_02; 1000 1066 when WR_CHECK_FOR_FIFO_SPACE_02 => 1067 state_sig <= X"47"; 1001 1068 socket_tx_free (16) <= data_read(0); 1002 1069 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; … … 1005 1072 state_write <= WR_CHECK_FOR_FIFO_SPACE_03; 1006 1073 when WR_CHECK_FOR_FIFO_SPACE_03 => 1074 state_sig <= X"48"; 1007 1075 socket_tx_free (15 downto 0) <= data_read; 1008 1076 state_write <= WR_CHECK_FOR_FIFO_SPACE_04; 1009 1077 when WR_CHECK_FOR_FIFO_SPACE_04 => 1078 state_sig <= X"49"; 1010 1079 -- if (socket_tx_free (16 downto 0) < write_length_bytes) then 1011 1080 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then … … 1023 1092 -- Write Header 1024 1093 when WR_FIFO => 1094 state_sig <= X"4A"; 1025 1095 ram_addr <= local_ram_start_addr + local_ram_addr; 1026 1096 state_write <= WR_FIFO1; 1027 1097 when WR_FIFO1 => 1098 state_sig <= X"4B"; 1028 1099 data_cnt <= data_cnt + 1; 1029 1100 if (data_cnt < PACKAGE_HEADER_LENGTH) then --??? … … 1048 1119 ---- Start... 1049 1120 when WR_ADC => 1121 state_sig <= X"4C"; 1050 1122 adc_data_addr <= local_ram_start_addr + local_ram_addr; 1051 1123 drs_cnt <= 0; … … 1058 1130 ---- Write Channel 1059 1131 when WR_ADC1 => 1132 state_sig <= X"4D"; 1060 1133 -- read ROI and set end of Channel-Data 1061 1134 if (data_cnt = POSITION_OF_ROI_IN_CHANNEL_HEADER) then … … 1106 1179 -- Write End Package Flag 1107 1180 when WR_ENDFLAG => 1181 state_sig <= X"4E"; 1108 1182 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4); 1109 1183 state_write <= WR_ENDFLAG1; … … 1155 1229 state_init <= next_state_tmp; 1156 1230 state_write <= WR_START; 1231 state_sig <= X"4F"; 1157 1232 end case; 1158 1233 -- End WRITE_DATA 1159 1234 1160 1235 when READ_REG => 1236 state_sig <= X"50"; 1161 1237 case count is 1162 1238 when "000" => … … 1186 1262 1187 1263 when WRITE_REG => 1264 state_sig <= X"60"; 1188 1265 case count is 1189 1266 when "000" => … … 1208 1285 count <= "000"; 1209 1286 when others => 1287 state_sig <= X"E0"; 1210 1288 null; 1211 1289 end case; 1212 1290 1213 1291 when others => 1292 state_sig <= X"F0"; 1214 1293 null; 1215 1294 end case;
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