Changeset 10879 for firmware/FTM/Lightpulser_interface/Basic_Version
- Timestamp:
- 05/27/11 17:28:59 (14 years ago)
- Location:
- firmware/FTM/Lightpulser_interface/Basic_Version
- Files:
-
- 3 edited
-
FM_pulse_generator_Basic.vhd (modified) (3 diffs)
-
Lightpulser_interface_Basic.vhd (modified) (5 diffs)
-
single_LP_Basic.vhd (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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firmware/FTM/Lightpulser_interface/Basic_Version/FM_pulse_generator_Basic.vhd
r10855 r10879 11 11 -- by Patrick Vogler 12 12 -- "Lightpulser Basic Version" 13 -- 14 -- modified: May 27 2011 15 -- by Patrick Vogler, Quirin Weitzel 16 -- -> clean up 17 13 18 14 19 LIBRARY ieee; … … 24 29 ENTITY FM_pulse_generator_Basic IS 25 30 GENERIC( 26 pulse_length : integer := FLD_PULSE_LENGTH -- 48ns31 pulse_length : integer := FLD_PULSE_LENGTH_BASIC -- 60ns 27 32 ); 28 33 PORT( … … 52 57 Z := Z + 1; 53 58 else 54 Z := - FLD_MIN_FREQ_DIV ;59 Z := - FLD_MIN_FREQ_DIV_BASIC; 55 60 Y := 0; 56 61 end if; 57 62 end if; 58 63 59 if (Y < FLD_PULSE_LENGTH_BASIC) then64 if (Y < pulse_length) then 60 65 Y := Y + 1; 61 66 FM_out <= '1'; -
firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic.vhd
r10855 r10879 5 5 -- Create Date: 24 February 2010 6 6 -- Design Name: 7 -- Module Name: FTM Lightpulser interface 7 -- Module Name: FTM Lightpulser interface Basic 8 8 -- Project Name: 9 9 -- Target Devices: … … 28 28 -- "Lightpulser Basic Version" 29 29 -- 30 -- modified: May 27 2011 31 -- by Patrick Vogler, Quirin Weitzel 32 -- -> clean up 33 -- 30 34 ---------------------------------------------------------------------------------- 31 35 … … 45 49 46 50 47 48 entity Lightpulser_interface is 51 entity Lightpulser_interface_Basic is 49 52 port( 50 53 … … 99 102 100 103 ); 101 end Lightpulser_interface; 102 103 104 architecture Behavioral of Lightpulser_interface is 105 104 end Lightpulser_interface_Basic; 105 106 107 architecture Behavioral of Lightpulser_interface_Basic is 106 108 107 109 108 110 component FM_pulse_generator_Basic is 109 110 111 112 113 111 port( 112 clk : in std_logic; -- 50 MHz 113 pulse_freq : in std_logic_vector (5 downto 0); 114 FM_out : out std_logic := '0' 115 ); 114 116 end component; 115 117 116 118 117 119 component single_LP_Basic is 118 120 port( 119 clk_50 : in STD_LOGIC;120 LP_Pulse_out: out STD_LOGIC;121 LP_pulse_in : instd_logic122 121 clk_50 : in STD_LOGIC; 122 LP_Pulse_out : out STD_LOGIC; 123 LP_pulse_in : in std_logic 124 ); 123 125 end component; 124 126 125 127 126 127 128 -- LP1: mirror dish 129 signal Cal_0_1 : STD_LOGIC := '0'; 128 -- LP1: mirror dish 129 signal Cal_0_1 : STD_LOGIC := '0'; 130 130 -- signal Cal_1_1 : STD_LOGIC; 131 131 132 133 132 -- LP2: shutter 133 signal Cal_0_2 : STD_LOGIC := '0'; 134 134 -- signal Cal_1_2 : STD_LOGIC; 135 135 136 137 138 139 140 141 142 136 -- PWM for amplitude stabilization 137 signal PWM_sig_1 : std_logic := '0'; -- LP1: mirror dish 138 signal PWM_sig_2 : std_logic := '0'; -- LP2: shutter 139 140 -- control data latch 141 signal LP1_ampl_sig : std_logic_vector (15 downto 0) := (others => '0'); 142 signal LP2_ampl_sig : std_logic_vector (15 downto 0) := (others => '0'); 143 143 144 144 145 type type_latch_state is (IDLE, COPY, CONFIGURED); 146 signal latch_state : type_latch_state := IDLE; 147 148 149 150 145 type type_latch_state is (IDLE, COPY, CONFIGURED); 146 signal latch_state : type_latch_state := IDLE; 147 151 148 152 149 begin 153 150 154 151 155 -- input latch156 input_latch : process (clk_50)152 -- input latch 153 input_latch : process (clk_50) 157 154 begin 158 155 if rising_edge(clk_50) then … … 180 177 end case; 181 178 end if; 182 end process input_latch;179 end process input_latch; 183 180 184 185 181 186 182 Inst_LP1_mirror_dish:single_LP_Basic 187 183 port map ( 188 189 190 191 192 193 194 184 clk_50 => clk_50, 185 LP_Pulse_out => Cal_0_1, 186 LP_pulse_in => LP1_pulse 187 ); 188 189 190 Inst_LP2_shutter:single_LP_Basic 195 191 port map ( 196 197 198 199 200 201 Inst_LP1_FM_pulse_generator:FM_pulse_generator_Basic -- LP1: mirror dish202 port map(192 clk_50 => clk_50, 193 LP_Pulse_out => Cal_0_2, 194 LP_pulse_in => LP2_pulse 195 ); 196 197 Inst_LP1_FM_pulse_generator:FM_pulse_generator_Basic -- LP1: mirror dish 198 port map( 203 199 clk => clk_50, 204 200 pulse_freq => LP1_ampl_sig(5 downto 0), 205 201 FM_out => PWM_sig_1 206 207 208 209 Inst_LP2_FM_pulse_generator:FM_pulse_generator_Basic -- LP2: shutter210 port map(202 ); 203 204 205 Inst_LP2_FM_pulse_generator:FM_pulse_generator_Basic -- LP2: shutter 206 port map( 211 207 clk => clk_50, 212 208 pulse_freq => LP2_ampl_sig(5 downto 0), 213 209 FM_out => PWM_sig_2 214 215 216 217 -- Light Pulser 1 (in the mirror dish): differential output buffers210 ); 211 212 213 -- Light Pulser 1 (in the mirror dish): differential output buffers 218 214 219 215 OBUFDS_inst_Cal_0 : OBUFDS 220 generic map (221 IOSTANDARD => "DEFAULT") 222 port map ( O => Cal_0_p ,-- Diff_p output (connect directly to top-level port)223 OB => Cal_0_n , -- Diff_n output (connect directly to top-level port)224 I => Cal_0_1 -- Buffer input225 );226 227 228 generic map (229 IOSTANDARD => "DEFAULT") 230 port map ( O => Cal_1_p ,-- Diff_p output (connect directly to top-level port)231 OB => Cal_1_n , -- Diff_n output (connect directly to top-level port)232 I => PWM_sig_1 -- Buffer input233 );234 235 236 generic map (237 IOSTANDARD => "DEFAULT") 238 port map ( O => Cal_2_p , -- Diff_p output (connect directly to top-level port)239 OB => Cal_2_n ,-- Diff_n output (connect directly to top-level port)240 I => LP1_ampl_sig(14) -- Buffer input241 );242 243 244 generic map (245 IOSTANDARD => "DEFAULT") 246 port map ( O => Cal_3_p , -- Diff_p output (connect directly to top-level port)247 OB => Cal_3_n ,-- Diff_n output (connect directly to top-level port)248 I => LP1_ampl_sig(15) -- Buffer input249 );216 generic map ( 217 IOSTANDARD => "DEFAULT") 218 port map ( O => Cal_0_p , -- Diff_p output (connect directly to top-level port) 219 OB => Cal_0_n , -- Diff_n output (connect directly to top-level port) 220 I => Cal_0_1 -- Buffer input 221 ); 222 223 OBUFDS_inst_Cal_1 : OBUFDS 224 generic map ( 225 IOSTANDARD => "DEFAULT") 226 port map ( O => Cal_1_p , -- Diff_p output (connect directly to top-level port) 227 OB => Cal_1_n , -- Diff_n output (connect directly to top-level port) 228 I => PWM_sig_1 -- Buffer input 229 ); 230 231 OBUFDS_inst_Cal_2 : OBUFDS 232 generic map ( 233 IOSTANDARD => "DEFAULT") 234 port map ( O => Cal_2_p , -- Diff_p output (connect directly to top-level port) 235 OB => Cal_2_n , -- Diff_n output (connect directly to top-level port) 236 I => LP1_ampl_sig(14) -- Buffer input 237 ); 238 239 OBUFDS_inst_Cal_3 : OBUFDS 240 generic map ( 241 IOSTANDARD => "DEFAULT") 242 port map ( O => Cal_3_p , -- Diff_p output (connect directly to top-level port) 243 OB => Cal_3_n , -- Diff_n output (connect directly to top-level port) 244 I => LP1_ampl_sig(15) -- Buffer input 245 ); 250 246 251 247 252 248 253 -- Light Pulser 2 (in the shutter): differential output buffers249 -- Light Pulser 2 (in the shutter): differential output buffers 254 250 255 OBUFDS_inst_Cal_4 : OBUFDS256 generic map (257 IOSTANDARD => "DEFAULT") 258 port map ( O => Cal_4_p ,-- Diff_p output (connect directly to top-level port)259 OB => Cal_4_n , -- Diff_n output (connect directly to top-level port)260 I => Cal_0_2-- Buffer input261 );262 263 264 generic map (265 IOSTANDARD => "DEFAULT") 266 port map ( O => Cal_5_p ,-- Diff_p output (connect directly to top-level port)267 OB => Cal_5_n , -- Diff_n output (connect directly to top-level port)268 I => PWM_sig_2-- Buffer input269 );270 271 272 generic map (273 IOSTANDARD => "DEFAULT") 274 port map ( O => Cal_6_p , -- Diff_p output (connect directly to top-level port)275 OB => Cal_6_n ,-- Diff_n output (connect directly to top-level port)276 I => LP2_ampl_sig(14)277 );278 279 280 generic map (281 IOSTANDARD => "DEFAULT") 282 port map ( O => Cal_7_p , -- Diff_p output (connect directly to top-level port)283 OB => Cal_7_n ,-- Diff_n output (connect directly to top-level port)284 I => LP2_ampl_sig(15) -- Buffer input285 );251 OBUFDS_inst_Cal_4 : OBUFDS 252 generic map ( 253 IOSTANDARD => "DEFAULT") 254 port map ( O => Cal_4_p , -- Diff_p output (connect directly to top-level port) 255 OB => Cal_4_n , -- Diff_n output (connect directly to top-level port) 256 I => Cal_0_2 -- Buffer input 257 ); 258 259 OBUFDS_inst_Cal_5 : OBUFDS 260 generic map ( 261 IOSTANDARD => "DEFAULT") 262 port map ( O => Cal_5_p , -- Diff_p output (connect directly to top-level port) 263 OB => Cal_5_n , -- Diff_n output (connect directly to top-level port) 264 I => PWM_sig_2 -- Buffer input 265 ); 266 267 OBUFDS_inst_Cal_6 : OBUFDS 268 generic map ( 269 IOSTANDARD => "DEFAULT") 270 port map ( O => Cal_6_p , -- Diff_p output (connect directly to top-level port) 271 OB => Cal_6_n , -- Diff_n output (connect directly to top-level port) 272 I => LP2_ampl_sig(14) 273 ); 274 275 OBUFDS_inst_Cal_7 : OBUFDS 276 generic map ( 277 IOSTANDARD => "DEFAULT") 278 port map ( O => Cal_7_p , -- Diff_p output (connect directly to top-level port) 279 OB => Cal_7_n , -- Diff_n output (connect directly to top-level port) 280 I => LP2_ampl_sig(15) -- Buffer input 281 ); 286 282 287 283 288 284 end Behavioral; 289 290 -
firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basic.vhd
r10855 r10879 28 28 -- modified: May 27 2011 29 29 -- by Patrick Vogler 30 -- 31 -- modified: May 27 2011 32 -- by Patrick Vogler, Quirin Weitzel 33 -- -> clean up 30 34 ---------------------------------------------------------------------------------- 31 35 ----------------------------------------------------------------------------------
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