Changeset 9880 for firmware


Ignore:
Timestamp:
Aug 18, 2010, 6:02:48 PM (9 years ago)
Author:
weitzel
Message:
FTU_rate_counter added and FTU_control state machine extended
Location:
firmware/FTU
Files:
1 added
5 edited

Legend:

Unmodified
Added
Removed
  • firmware/FTU/FTU_control.vhd

    r9828 r9880  
    11----------------------------------------------------------------------------------
    22-- Company:        ETH Zurich, Institute for Particle Physics
    3 -- Engineer:       P. Vogler, Q. Weitzel
     3-- Engineer:       Q. Weitzel, P. Vogler
    44--
    55-- Create Date:    08/06/2010
     
    2626library ftu_definitions;
    2727USE ftu_definitions.ftu_array_types.all;
     28USE ftu_definitions.ftu_constants.all;
    2829
    2930---- Uncomment the following library declaration if instantiating
     
    3435entity FTU_control is
    3536  port(
    36     clk_50MHz    : IN  std_logic;
    37     clk_ready    : IN  std_logic;
    38     config_ready : IN std_logic;
    39     reset        : OUT std_logic;
    40     config_start : OUT std_logic
     37    clk_50MHz      : IN  std_logic;
     38    clk_ready      : IN  std_logic;
     39    config_started : IN  std_logic;
     40    config_ready   : IN  std_logic;
     41    ram_doa        : IN  STD_LOGIC_VECTOR(7 downto 0);
     42    ram_dob        : IN  STD_LOGIC_VECTOR(15 downto 0);
     43    rate_array     : IN  rate_array_type;
     44    reset          : OUT std_logic;
     45    config_start   : OUT std_logic;
     46    ram_ena        : OUT std_logic;
     47    ram_enb        : OUT std_logic;
     48    ram_wea        : OUT STD_LOGIC_VECTOR(0 downto 0);
     49    ram_web        : OUT STD_LOGIC_VECTOR(0 downto 0);
     50    ram_ada        : OUT STD_LOGIC_VECTOR(4 downto 0);
     51    ram_adb        : OUT STD_LOGIC_VECTOR(3 downto 0);
     52    ram_dia        : OUT STD_LOGIC_VECTOR(7 downto 0);
     53    ram_dib        : OUT STD_LOGIC_VECTOR(15 downto 0);
     54    dac_array      : OUT dac_array_type;
     55    enable_array   : OUT enable_array_type;
     56    cntr_reset     : OUT STD_LOGIC;
     57    prescaling     : OUT STD_LOGIC_VECTOR(7 downto 0)
    4158  );
    4259end FTU_control;
     
    4461architecture Behavioral of FTU_control is
    4562
    46   signal reset_sig : STD_LOGIC := '0';
    47 
     63  signal reset_sig : STD_LOGIC := '0';  --initialize reset to 0 at power up
     64
     65  --DAC/SPI interface, default DACs come from RAM during INIT
    4866  signal config_start_sig : STD_LOGIC := '0';
    49   signal config_ready_sig : STD_LOGIC := '0';
    50  
    51   type FTU_control_StateType is (IDLE, INIT, RUNNING, RESET_ALL);
    52   signal FTU_control_State, FTU_control_NextState: FTU_control_StateType;
     67  signal dac_array_sig : dac_array_type := (0,0,0,0,0,0,0,0);
     68
     69  --enable signals for pixels in trigger, default values come from RAM during INIT
     70  signal enable_array_sig : enable_array_type := ("0000000000000000", --patch A
     71                                                  "0000000000000000", --patch B
     72                                                  "0000000000000000", --patch C
     73                                                  "0000000000000000");--patch D
     74
     75  signal rate_array_sig : rate_array_type;  -- initialized in FTU_top 
     76  signal cntr_reset_sig : STD_LOGIC := '0';
     77  signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
     78 
     79  signal ram_ena_sig  : STD_LOGIC := '0';  -- RAM enable for port A
     80  signal ram_enb_sig  : STD_LOGIC := '0';  -- RAM enable for port B
     81  signal ram_wea_sig  : STD_LOGIC_VECTOR(0 downto 0) := "0";  -- RAM write enable for port A
     82  signal ram_web_sig  : STD_LOGIC_VECTOR(0 downto 0) := "0";  -- RAM write enable for port B 
     83  signal ram_ada_sig  : STD_LOGIC_VECTOR(4 downto 0) := (others => '0');  --RAM port A address
     84  signal ram_adb_sig  : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');  --RAM port B address
     85  signal ram_dia_sig  : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');  --RAM data in A
     86  signal ram_dib_sig  : STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); --RAM data in B
     87
     88  --counter to loop through RAM
     89  signal ram_ada_cntr    : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
     90  signal ram_adb_cntr    : INTEGER range 0 to 2**RAM_ADDR_WIDTH_B := 0;
     91  signal ram_dac_cntr    : INTEGER range 0 to (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2) := 0;
     92  signal ram_enable_cntr : INTEGER range 0 to (NO_OF_ENABLE + 1) := 0;
     93
     94  signal wait_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
     95 
     96  signal new_DACs_in_RAM       : STD_LOGIC := '0';
     97  signal new_enables_in_RAM    : STD_LOGIC := '0';
     98  signal new_prescaling_in_RAM : STD_LOGIC := '0';
     99
     100  type FTU_control_StateType is (IDLE, INIT, RUNNING, CONFIG_ENABLE, CONFIG_DAC, CONFIG_COUNTER, RESET_ALL);
     101  signal FTU_control_State : FTU_control_StateType;
    53102 
    54103begin
    55104   
    56   --FTU control state machine (two-process implementation)
    57 
    58   FTU_control_Registers: process (clk_50MHz)
     105  --FTU control finite state machine
     106
     107  FTU_control_FSM: process (clk_50MHz)
     108
    59109  begin
     110
    60111    if Rising_edge(clk_50MHz) then
    61       FTU_control_State <= FTU_control_NextState;
     112
     113      case FTU_control_State is
     114       
     115        when IDLE =>  -- wait for DCMs to lock
     116          reset_sig <= '0';
     117          config_start_sig <= '0';
     118          ram_ena_sig <= '0';
     119          ram_wea_sig <= "0";                   
     120          if (clk_ready = '1') then
     121            FTU_control_State <= INIT;
     122          end if;
     123         
     124        when INIT =>  -- load default config data to RAM, see also ftu_definitions.vhd for more info
     125          reset_sig <= '0';
     126          config_start_sig <= '0';
     127          ram_ena_sig <= '1';
     128          ram_wea_sig <= "1";
     129          ram_ada_cntr <= ram_ada_cntr + 1;
     130          ram_ada_sig <= conv_std_logic_vector(ram_ada_cntr, RAM_ADDR_WIDTH_A);       
     131          if (ram_ada_cntr < NO_OF_ENABLE*RAM_ADDR_RATIO) then  -- default enables
     132            if (ram_ada_cntr mod 2 = 0) then
     133              ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(7 downto 0);
     134            else
     135              ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(15 downto 8);
     136            end if;
     137            FTU_control_State <= INIT;
     138          elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) then  -- default counter values
     139            ram_dia_sig <= (others => '0');
     140            FTU_control_State <= INIT;
     141          elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then  -- default DACs
     142            if (ram_ada_cntr < NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO) then
     143              if (ram_ada_cntr mod 2 = 0) then
     144                ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2),16)(7 downto 0);
     145              else
     146                ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2),16)(15 downto 8);
     147              end if;
     148            else
     149              if (ram_ada_cntr mod 2 = 0) then
     150                ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2) + NO_OF_DAC_NOT_USED),16)(7 downto 0);
     151              else
     152                ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2) + NO_OF_DAC_NOT_USED),16)(15 downto 8);
     153              end if;
     154            end if;
     155            FTU_control_State <= INIT;
     156          elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then  -- default prescaling
     157            ram_dia_sig <= conv_std_logic_vector(DEFAULT_PRESCALING,8);
     158            FTU_control_State <= INIT;
     159          elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1) then  -- default overflow register
     160            ram_dia_sig <= (others => '0');
     161            FTU_control_State <= INIT;
     162          elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then  -- default checksum
     163            ram_dia_sig <= (others => '0');
     164            FTU_control_State <= INIT;
     165          elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 3) then  -- empty RAM cell
     166            ram_dia_sig <= (others => '0');
     167            FTU_control_State <= INIT;
     168          else
     169            ram_dia_sig <= (others => '0');
     170            ram_ada_cntr <= 0;
     171            ram_ada_sig <= (others => '0');
     172            ram_ena_sig <= '0';
     173            ram_wea_sig <= "0";
     174            new_DACs_in_RAM <= '1';
     175            new_enables_in_RAM <= '1';
     176            new_prescaling_in_RAM <= '1';
     177            FTU_control_State <= RUNNING;
     178          end if;
     179                   
     180        when RUNNING =>  -- count triggers and react to commands from FTM
     181          reset_sig <= '0';
     182          config_start_sig <= '0';
     183          if (new_DACs_in_RAM = '1') then
     184            ram_enb_sig <= '1';
     185            ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER), RAM_ADDR_WIDTH_B);
     186            FTU_control_State <= CONFIG_DAC;
     187          elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '1') then
     188            ram_enb_sig <= '1';
     189            ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
     190            FTU_control_State <= CONFIG_ENABLE;
     191          elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '0' and new_prescaling_in_RAM = '1') then
     192            ram_ena_sig <= '1';
     193            ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
     194            FTU_control_State <= CONFIG_COUNTER;
     195          else
     196            FTU_control_State <= RUNNING;
     197          end if;
     198
     199        when CONFIG_COUNTER =>
     200          wait_cntr <= wait_cntr + 1;
     201          if (wait_cntr = 0) then
     202            FTU_control_State <= CONFIG_COUNTER;
     203          elsif (wait_cntr = 1) then
     204            prescaling_sig <= ram_doa;
     205            cntr_reset_sig <= '1';
     206            FTU_control_State <= CONFIG_COUNTER;
     207          else
     208            cntr_reset_sig <= '0';
     209            ram_ada_sig <= (others => '0');
     210            wait_cntr <= 0;
     211            new_prescaling_in_RAM <= '0';
     212            ram_ena_sig <= '0';
     213            FTU_control_State <= RUNNING;
     214          end if;
     215         
     216        when CONFIG_ENABLE =>
     217          ram_enable_cntr <= ram_enable_cntr + 1;
     218          if (ram_enable_cntr = 0) then
     219            ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
     220            FTU_control_State <= CONFIG_ENABLE;
     221          elsif (ram_enable_cntr > 0 and ram_enable_cntr < NO_OF_ENABLE + 1) then
     222            ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
     223            enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
     224            FTU_control_State <= CONFIG_ENABLE;           
     225          else
     226            ram_adb_sig <= (others => '0');
     227            ram_enable_cntr <= 0;
     228            new_enables_in_RAM <= '0';
     229            ram_enb_sig <= '0';
     230            FTU_control_State <= RUNNING;
     231          end if;
     232         
     233        when CONFIG_DAC =>
     234          if (ram_dac_cntr <= (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2)) then           
     235            ram_dac_cntr <= ram_dac_cntr + 1;
     236            if (ram_dac_cntr = 0) then
     237              FTU_control_State <= CONFIG_DAC;
     238              ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
     239            elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
     240              dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob));
     241              ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
     242              FTU_control_State <= CONFIG_DAC;
     243            elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED + 1)) then
     244              dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob));
     245              ram_adb_sig <= (others => '0');
     246              FTU_control_State <= CONFIG_DAC;
     247            else
     248              ram_adb_sig <= (others => '0');
     249              config_start_sig <= '1';
     250              FTU_control_State <= CONFIG_DAC;
     251            end if;
     252          else
     253            if (config_ready = '1') then
     254              ram_dac_cntr <= 0;
     255              new_DACs_in_RAM <= '0';
     256              FTU_control_State <= RUNNING;
     257            elsif (config_ready = '0' and config_started = '1') then
     258              ram_enb_sig <= '0';
     259              config_start_sig <= '0';
     260              FTU_control_State <= CONFIG_DAC;
     261            else
     262              FTU_control_State <= CONFIG_DAC;
     263            end if;
     264          end if;
     265         
     266        when RESET_ALL =>  -- reset/clear and start from scratch
     267          reset_sig <= '1';
     268          config_start_sig <= '0';
     269          FTU_control_State <= IDLE;
     270      end case;
    62271    end if;
    63   end process FTU_control_Registers;
    64 
    65   FTU_control_C_logic: process (FTU_control_State, clk_ready, config_ready_sig)
    66   begin
    67     FTU_control_NextState <= FTU_control_State;
    68     case FTU_control_State is
    69       when IDLE =>                      -- wait for DMCs to lock
    70         reset_sig <= '0';
    71         config_start_sig <= '0';
    72         --ram_web_sig <= "0";
    73         if (clk_ready = '1') then
    74           FTU_control_NextState <= RUNNING;
    75         end if;         
    76       when INIT =>                      -- load default config data to RAM
    77         reset_sig <= '0';
    78         config_start_sig <= '0';
    79         --ram_web_sig <= "1";
    80         --ram_adb_cntr <= ram_adb_cntr + 1;
    81         --ram_adb_sig <= conv_std_logic_vector(ram_adb_cntr, 4);       
    82         --if (ram_adb_cntr < 4) then
    83         --  ram_dib_sig <= DEFAULT_ENABLE(ram_adb_cntr);
    84         --  FTU_top_NextState <= INIT;
    85         --elsif (ram_adb_cntr < 4 + 5) then
    86         --  ram_dib_sig <= conv_std_logic_vector(DEFAULT_DAC(ram_adb_cntr - 4), 16);
    87         --  FTU_top_NextState <= INIT;
    88         --elsif (ram_adb_cntr < 32) then
    89         --  ram_dib_sig <= (others => '0');
    90         --  FTU_top_NextState <= INIT;
    91         --else
    92         --  ram_adb_cntr <= 0;
    93         --  ram_web_sig <= "0";
    94         --  FTU_top_NextState <= RUNNING;
    95         --end if;
    96       when RUNNING =>                   -- count triggers and react to commands
    97         reset_sig <= '0';
    98         config_start_sig <= '0';
    99         --ram_web_sig <= "0";
    100       when RESET_ALL =>                     -- reset/clear and start from scratch
    101         reset_sig <= '1';
    102         config_start_sig <= '0';
    103         --ram_web_sig <= "0";
    104         FTU_control_NextState <= IDLE;
    105     end case;
    106   end process FTU_control_C_logic;
     272  end process FTU_control_FSM;
    107273
    108274  reset <= reset_sig;
    109275 
     276  config_start <= config_start_sig;
     277  dac_array <= dac_array_sig;
     278
     279  enable_array <= enable_array_sig;
     280
     281  rate_array_sig <= rate_array;
     282  cntr_reset <= cntr_reset_sig;
     283  prescaling <= prescaling_sig;
     284 
     285  ram_ena <= ram_ena_sig;
     286  ram_enb <= ram_enb_sig;
     287  ram_wea <= ram_wea_sig;
     288  ram_web <= ram_web_sig;
     289  ram_ada <= ram_ada_sig;
     290  ram_adb <= ram_adb_sig;
     291  ram_dia <= ram_dia_sig;
     292  ram_dib <= ram_dib_sig;
     293     
    110294end Behavioral;
  • firmware/FTU/FTU_top.vhd

    r9827 r9880  
    11----------------------------------------------------------------------------------
    22-- Company:        ETH Zurich, Institute for Particle Physics
    3 -- Engineer:       P. Vogler, Q. Weitzel
     3-- Engineer:       Q. Weitzel, P. Vogler
    44--
    55-- Create Date:    11:59:40 01/19/2010
     
    3030---- Uncomment the following library declaration if instantiating
    3131---- any Xilinx primitives in this code.
    32 --library UNISIM;
    33 --use UNISIM.VComponents.all;
     32library UNISIM;
     33use UNISIM.VComponents.all;
    3434
    3535entity FTU_top is
     
    7878architecture Behavioral of FTU_top is
    7979
    80   signal reset_sig   : STD_LOGIC := '0';  -- initialize reset to 0 at power up
    81   signal dac_clr_sig : STD_LOGIC := '1';  -- initialize dac_clr to 1 at power up
    82  
    83   signal config_start_sig : STD_LOGIC := '0';
    84   signal config_ready_sig : STD_LOGIC := '0';
     80  signal reset_sig   : STD_LOGIC;         -- initialized in FTU_control
     81  signal dac_clr_sig : STD_LOGIC := '1';  -- not used in hardware, initialize to 1 at power up
     82
     83  --single-ended trigger signals for rate counter
     84  signal patch_A_sig : STD_LOGIC := '0';
     85  signal patch_B_sig : STD_LOGIC := '0';
     86  signal patch_C_sig : STD_LOGIC := '0';
     87  signal patch_D_sig : STD_LOGIC := '0';
     88  signal trigger_sig : STD_LOGIC := '0';
     89 
     90  --DAC/SPI interface
     91  signal config_start_sig   : STD_LOGIC;  -- initialized in FTU_control
     92  signal config_started_sig : STD_LOGIC;  -- initialized in spi_interface
     93  signal config_ready_sig   : STD_LOGIC;  -- initialized in spi_interface
     94  signal dac_array_sig      : dac_array_type;  -- initialized in FTU_control
     95
     96  signal enable_array_sig : enable_array_type;  -- initialized in FTU_control
     97
     98  --rate counter signals
     99  signal cntr_reset_sig : STD_LOGIC;  -- initialized in FTU_control 
     100  signal rate_array_sig : rate_array_type := (0,0,0,0,0);
     101  signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0);
     102  signal overflow_array : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
    85103 
    86104  signal clk_50M_sig   : STD_LOGIC;         -- generated by internal DCM
    87105  signal clk_ready_sig : STD_LOGIC := '0';  -- set high by FTU_clk_gen when DCMs have locked
    88106
    89   --signal ram_wea_sig  : STD_LOGIC_VECTOR(0 downto 0) := "0";  -- RAM write enable for port A
    90   --signal ram_web_sig  : STD_LOGIC_VECTOR(0 downto 0) := "0";  -- RAM write enable for port B
    91   --signal ram_ada_cntr : INTEGER range 0 to 2**5 - 1 := 0;
    92   --signal ram_adb_cntr : INTEGER range 0 to 2**4 - 1 := 0;
    93   --signal ram_ada_sig  : STD_LOGIC_VECTOR(4 downto 0);
    94   --signal ram_adb_sig  : STD_LOGIC_VECTOR(3 downto 0);
    95   --signal ram_dia_sig  : STD_LOGIC_VECTOR(7 downto 0);
    96   --signal ram_dib_sig  : STD_LOGIC_VECTOR(15 downto 0);
    97   --signal ram_doa_sig  : STD_LOGIC_VECTOR(7 downto 0);
    98   --signal ram_dob_sig  : STD_LOGIC_VECTOR(15 downto 0);
    99    
     107  --signals for RAM control, all initialized in FTU_control
     108  signal ram_ena_sig : STD_LOGIC;
     109  signal ram_enb_sig : STD_LOGIC;
     110  signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0);
     111  signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0);
     112  signal ram_ada_sig : STD_LOGIC_VECTOR(4 downto 0);
     113  signal ram_adb_sig : STD_LOGIC_VECTOR(3 downto 0);
     114  signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0);
     115  signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0);
     116  signal ram_doa_sig : STD_LOGIC_VECTOR(7 downto 0);
     117  signal ram_dob_sig : STD_LOGIC_VECTOR(15 downto 0);
     118
    100119  component FTU_clk_gen
    101120    port(
     
    107126  end component;
    108127
     128  component FTU_rate_counter is
     129    port(
     130      clk        : in  std_logic;
     131      cntr_reset : in  std_logic;
     132      trigger    : in  std_logic;
     133      prescaling : in  std_logic_vector(7 downto 0);
     134      counts     : out integer range 0 to 2**16 - 1;
     135      overflow   : out std_logic
     136      );
     137  end component;
     138 
    109139  component FTU_control
    110140    port(
    111       clk_50MHz    : IN std_logic;
    112       clk_ready    : IN std_logic;
    113       config_ready : IN std_logic;
    114       reset        : OUT std_logic;
    115       config_start : OUT std_logic
     141      clk_50MHz      : IN  std_logic;
     142      clk_ready      : IN  std_logic;
     143      config_started : IN  std_logic;
     144      config_ready   : IN  std_logic;
     145      ram_doa        : IN  STD_LOGIC_VECTOR(7 downto 0);
     146      ram_dob        : IN  STD_LOGIC_VECTOR(15 downto 0);
     147      rate_array     : IN  rate_array_type;
     148      reset          : OUT std_logic;
     149      config_start   : OUT std_logic;
     150      ram_ena        : OUT std_logic;
     151      ram_enb        : OUT std_logic;
     152      ram_wea        : OUT STD_LOGIC_VECTOR(0 downto 0);
     153      ram_web        : OUT STD_LOGIC_VECTOR(0 downto 0);
     154      ram_ada        : OUT STD_LOGIC_VECTOR(4 downto 0);
     155      ram_adb        : OUT STD_LOGIC_VECTOR(3 downto 0);
     156      ram_dia        : OUT STD_LOGIC_VECTOR(7 downto 0);
     157      ram_dib        : OUT STD_LOGIC_VECTOR(15 downto 0);
     158      dac_array      : OUT dac_array_type;
     159      enable_array   : OUT enable_array_type;
     160      cntr_reset     : OUT STD_LOGIC;
     161      prescaling     : OUT STD_LOGIC_VECTOR(7 downto 0)
    116162    );
    117163  end component;
     
    130176  end component;
    131177
    132   --component FTU_dual_port_ram
    133   --  port(
    134   --    clka  : IN  std_logic;
    135   --    ena   : IN  std_logic;
    136   --    wea   : IN  std_logic_VECTOR(0 downto 0);
    137   --    addra : IN  std_logic_VECTOR(4 downto 0);
    138   --    dina  : IN  std_logic_VECTOR(7 downto 0);
    139   --    douta : OUT std_logic_VECTOR(7 downto 0);
    140   --    clkb  : IN  std_logic;
    141   --    enb   : IN  std_logic;
    142   --    web   : IN  std_logic_VECTOR(0 downto 0);
    143   --    addrb : IN  std_logic_VECTOR(3 downto 0);
    144   --    dinb  : IN  std_logic_VECTOR(15 downto 0);
    145   --    doutb : OUT std_logic_VECTOR(15 downto 0)
    146   --  );
    147   --end component;
     178  component FTU_dual_port_ram
     179    port(
     180      clka  : IN  std_logic;
     181      ena   : IN  std_logic;
     182      wea   : IN  std_logic_VECTOR(0 downto 0);
     183      addra : IN  std_logic_VECTOR(4 downto 0);
     184      dina  : IN  std_logic_VECTOR(7 downto 0);
     185      douta : OUT std_logic_VECTOR(7 downto 0);
     186      clkb  : IN  std_logic;
     187      enb   : IN  std_logic;
     188      web   : IN  std_logic_VECTOR(0 downto 0);
     189      addrb : IN  std_logic_VECTOR(3 downto 0);
     190      dinb  : IN  std_logic_VECTOR(15 downto 0);
     191      doutb : OUT std_logic_VECTOR(15 downto 0)
     192    );
     193  end component;
    148194
    149195  -- Synplicity black box declaration
    150   --attribute syn_black_box : boolean;
    151   --attribute syn_black_box of FTU_dual_port_ram: component is true;
     196  attribute syn_black_box : boolean;
     197  attribute syn_black_box of FTU_dual_port_ram: component is true;
    152198 
    153199begin
    154200
    155201  clr <= dac_clr_sig;
     202
     203  enables_A <= enable_array_sig(0)(8 downto 0);
     204  enables_B <= enable_array_sig(1)(8 downto 0);
     205  enables_C <= enable_array_sig(2)(8 downto 0);
     206  enables_D <= enable_array_sig(3)(8 downto 0);
     207
     208  --differential input buffer for patch A
     209  IBUFDS_LVDS_33_A : IBUFDS_LVDS_33
     210    port map(
     211      O  => patch_A_sig,
     212      I  => patch_A_p,
     213      IB => patch_A_n
     214    );
     215
     216  --differential input buffer for patch B
     217  IBUFDS_LVDS_33_B : IBUFDS_LVDS_33
     218    port map(
     219      O  => patch_B_sig,
     220      I  => patch_B_p,
     221      IB => patch_B_n
     222    );
     223
     224  --differential input buffer for patch C
     225  IBUFDS_LVDS_33_C : IBUFDS_LVDS_33
     226    port map(
     227      O  => patch_C_sig,
     228      I  => patch_C_p,
     229      IB => patch_C_n
     230    );
     231
     232  --differential input buffer for patch D
     233  IBUFDS_LVDS_33_D : IBUFDS_LVDS_33
     234    port map(
     235      O  => patch_D_sig,
     236      I  => patch_D_p,
     237      IB => patch_D_n
     238    );
     239
     240  --differential input buffer for trigger
     241  IBUFDS_LVDS_33_t : IBUFDS_LVDS_33
     242    port map(
     243      O  => trigger_sig,
     244      I  => trig_prim_p,
     245      IB => trig_prim_n
     246    );
    156247 
    157248  Inst_FTU_clk_gen : FTU_clk_gen
     
    163254    );
    164255
     256  Inst_FTU_rate_counter_A : FTU_rate_counter
     257    port map(
     258      clk        => clk_50M_sig,
     259      cntr_reset => cntr_reset_sig,
     260      trigger    => patch_A_sig,
     261      prescaling => prescaling_sig,
     262      counts     => rate_array_sig(0),
     263      overflow   => overflow_array(0)
     264    );
     265
     266  Inst_FTU_rate_counter_B : FTU_rate_counter
     267    port map(
     268      clk        => clk_50M_sig,
     269      cntr_reset => cntr_reset_sig,
     270      trigger    => patch_B_sig,
     271      prescaling => prescaling_sig,
     272      counts     => rate_array_sig(1),
     273      overflow   => overflow_array(1)
     274    );
     275
     276  Inst_FTU_rate_counter_C : FTU_rate_counter
     277    port map(
     278      clk        => clk_50M_sig,
     279      cntr_reset => cntr_reset_sig,
     280      trigger    => patch_C_sig,
     281      prescaling => prescaling_sig,
     282      counts     => rate_array_sig(2),
     283      overflow   => overflow_array(2)
     284    );
     285
     286  Inst_FTU_rate_counter_D : FTU_rate_counter
     287    port map(
     288      clk        => clk_50M_sig,
     289      cntr_reset => cntr_reset_sig,
     290      trigger    => patch_D_sig,
     291      prescaling => prescaling_sig,
     292      counts     => rate_array_sig(3),
     293      overflow   => overflow_array(3)
     294    );
     295
     296  Inst_FTU_rate_counter_t : FTU_rate_counter
     297    port map(
     298      clk        => clk_50M_sig,
     299      cntr_reset => cntr_reset_sig,
     300      trigger    => trigger_sig,
     301      prescaling => prescaling_sig,
     302      counts     => rate_array_sig(4),
     303      overflow   => overflow_array(4)
     304    );
     305 
    165306  Inst_FTU_control : FTU_control
    166307    port map(
    167       clk_50MHz    => clk_50M_sig,
    168       clk_ready    => clk_ready_sig,
    169       config_ready => config_ready_sig,
    170       reset        => reset_sig,
    171       config_start => config_start_sig
     308      clk_50MHz      => clk_50M_sig,
     309      clk_ready      => clk_ready_sig,
     310      config_started => config_started_sig,
     311      config_ready   => config_ready_sig,
     312      ram_doa        => ram_doa_sig,
     313      ram_dob        => ram_dob_sig,
     314      rate_array     => rate_array_sig,
     315      reset          => reset_sig,
     316      config_start   => config_start_sig,
     317      ram_ena        => ram_ena_sig,
     318      ram_enb        => ram_enb_sig,
     319      ram_wea        => ram_wea_sig,
     320      ram_web        => ram_web_sig,
     321      ram_ada        => ram_ada_sig,
     322      ram_adb        => ram_adb_sig,
     323      ram_dia        => ram_dia_sig,
     324      ram_dib        => ram_dib_sig,
     325      dac_array      => dac_array_sig,
     326      enable_array   => enable_array_sig,
     327      cntr_reset     => cntr_reset_sig,
     328      prescaling     => prescaling_sig
    172329    );
    173330 
     
    176333      clk_50MHz      => clk_50M_sig,
    177334      config_start   => config_start_sig,
    178       dac_array      => DEFAULT_DAC,  -- has to come from RAM
     335      dac_array      => dac_array_sig,
    179336      config_ready   => config_ready_sig,
    180       config_started => open,
     337      config_started => config_started_sig,
    181338      dac_cs         => cs_ld,
    182339      mosi           => mosi,
     
    184341    );
    185342
    186   --Inst_FTU_dual_port_ram : FTU_dual_port_ram
    187   --  port map(
    188   --    clka  => clk_50M_sig,
    189   --    ena   => '1',
    190   --    wea   => ram_wea_sig,
    191   --    addra => ram_ada_sig,
    192   --    dina  => ram_dia_sig,
    193   --    douta => ram_doa_sig,
    194   --    clkb  => clk_50M_sig,
    195   --    enb   => '1',
    196   --    web   => ram_web_sig,
    197   --    addrb => ram_adb_sig,
    198   --    dinb  => ram_dib_sig,
    199   --    doutb => ram_dob_sig
    200   --  );
     343  Inst_FTU_dual_port_ram : FTU_dual_port_ram
     344    port map(
     345      clka  => clk_50M_sig,
     346      ena   => ram_ena_sig,
     347      wea   => ram_wea_sig,
     348      addra => ram_ada_sig,
     349      dina  => ram_dia_sig,
     350      douta => ram_doa_sig,
     351      clkb  => clk_50M_sig,
     352      enb   => ram_enb_sig,
     353      web   => ram_web_sig,
     354      addrb => ram_adb_sig,
     355      dinb  => ram_dib_sig,
     356      doutb => ram_dob_sig
     357    );
    201358 
    202359end Behavioral;
  • firmware/FTU/FTU_top_tb.vhd

    r273 r9880  
    11--------------------------------------------------------------------------------
    22-- Company:       ETH Zurich, Institute for Particle Physics
    3 -- Engineer:      P. Vogler, Q. Weitzel
     3-- Engineer:      Q. Weitzel, P. Vogler
    44--
    55-- Create Date:   12.07.2010
     
    3030use IEEE.STD_LOGIC_UNSIGNED.ALL;
    3131use IEEE.NUMERIC_STD.ALL;
    32  
     32
     33library UNISIM;
     34use UNISIM.VComponents.all;
     35
    3336entity FTU_top_tb is
    3437end FTU_top_tb;
     
    110113  signal tx_en     : STD_LOGIC;
    111114  signal TP_A      : STD_LOGIC_VECTOR(11 downto 0);
     115
     116  --single-ended trigger signals
     117  signal patch_A_sig : STD_LOGIC := '0';
     118  signal patch_B_sig : STD_LOGIC := '0';
     119  signal patch_C_sig : STD_LOGIC := '0';
     120  signal patch_D_sig : STD_LOGIC := '0';
     121  signal trigger_sig : STD_LOGIC := '0';
    112122 
    113123  -- Clock period definitions
     
    147157    );
    148158
     159  --differential output buffer for patch A
     160  OBUFDS_LVDS_33_A : OBUFDS_LVDS_33
     161    port map(
     162      O  => patch_A_p,
     163      OB => patch_A_n,
     164      I  => patch_A_sig
     165    );
     166
     167  OBUFDS_LVDS_33_B : OBUFDS_LVDS_33
     168    port map(
     169      O  => patch_B_p,
     170      OB => patch_B_n,
     171      I  => patch_B_sig
     172    );
     173
     174  OBUFDS_LVDS_33_C : OBUFDS_LVDS_33
     175    port map(
     176      O  => patch_C_p,
     177      OB => patch_C_n,
     178      I  => patch_C_sig
     179    );
     180
     181  OBUFDS_LVDS_33_D : OBUFDS_LVDS_33
     182    port map(
     183      O  => patch_D_p,
     184      OB => patch_D_n,
     185      I  => patch_D_sig
     186    );
     187
     188  OBUFDS_LVDS_33_t : OBUFDS_LVDS_33
     189    port map(
     190      O  => trig_prim_p,
     191      OB => trig_prim_n,
     192      I  => trigger_sig
     193    );
     194 
    149195  -- Clock process definitions
    150196  ext_clk_proc: process
     
    158204  -- Stimulus process
    159205  stim_proc: process
    160   begin         
    161     -- hold reset state for 100ms.
    162     wait for 100ms;     
     206  begin
     207    -- FTU not yet initialized
     208    wait for 10us;
     209    trigger_sig <= '1';
     210    wait for 5ns;
     211    trigger_sig <= '0';
     212    wait for 100us;
     213    trigger_sig <= '1';
     214    wait for 5ns;
     215    trigger_sig <= '0';
     216    -- now FTU is initialized
     217    wait for 4us;
     218    trigger_sig <= '1';
     219    wait for 5ns;
     220    trigger_sig <= '0';
     221    wait for 4us;
     222    trigger_sig <= '1';
     223    wait for 5ns;
     224    trigger_sig <= '0';
     225    wait for 22us;
     226    trigger_sig <= '1';
     227    wait for 5ns;
     228    trigger_sig <= '0';
     229    wait;
    163230   
    164     wait for ext_clk_period*10;
    165 
    166     -- insert stimulus here
    167 
    168     wait;
    169231  end process stim_proc;
    170232
  • firmware/FTU/clock/FTU_clk_gen.vhd

    r273 r9880  
    6161 
    6262end Behavioral;
    63 
  • firmware/FTU/ftu_definitions.vhd

    r273 r9880  
     1----------------------------------------------------------------------------------
     2-- Company:        ETH Zurich, Institute for Particle Physics
     3-- Engineer:       Q. Weitzel
     4--
     5-- Create Date:    July 2010
     6-- Design Name:   
     7-- Module Name:    ftu_definitions
     8-- Project Name:
     9-- Target Devices:
     10-- Tool versions:
     11-- Description:    library file for FTU design                                                                         
     12--
     13-- Dependencies:
     14--
     15-- Revision:
     16-- Revision 0.01 - File Created
     17-- Revision 0.02 - New package "ftu_constants" added, Aug 2010, Q. Weitzel
     18-- Additional Comments:
     19--
     20----------------------------------------------------------------------------------
     21
     22
    123library IEEE;
    224use IEEE.STD_LOGIC_1164.all;
     
    729package ftu_array_types is
    830
     31  --enable signals to switch on/off pixels in trigger (9 pixels per patch)
    932  type enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
    1033  constant DEFAULT_ENABLE : enable_array_type := ("0000000111111111", --patch A
     
    1235                                                  "0000000111111111", --patch C
    1336                                                  "0000000111111111");--patch D
    14  
     37
     38  --DAC values to steer trigger thresholds, 12bit octal DAC, 2.5V reference voltage
     39  --First 4 values: patches A-D, DACs 5-7 not used, last value: majority coincidence
    1540  type dac_array_type is array (0 to 7) of integer range 0 to 2**12 - 1;
    1641  constant DEFAULT_DAC : dac_array_type := (500, 500, 500, 500, 0, 0, 0, 100);
    17    
     42
     43  --array to hold current values of rate counters (as integers)
     44  type rate_array_type is array (0 to 4) of integer range 0 to 2**16 - 1;
     45 
    1846end ftu_array_types;
     47
     48
     49library IEEE;
     50use IEEE.STD_LOGIC_1164.all;
     51use IEEE.STD_LOGIC_ARITH.ALL;
     52use IEEE.STD_LOGIC_UNSIGNED.ALL;
     53-- use IEEE.NUMERIC_STD.ALL;
     54
     55package ftu_constants is
     56
     57  --internal FPGA clock frequency and rate counter frequency
     58  constant INT_CLK_FREQUENCY : integer := 50000000;  -- 50MHz
     59  constant COUNTER_FREQUENCY : integer :=  1000000;  --  1MHZ, has to be smaller than INT_CLK_FREQUENCY
     60   
     61  --32byte dual-port RAM, port A: 8byte, port B: 16byte
     62  constant RAM_ADDR_WIDTH_A : integer := 5;
     63  constant RAM_ADDR_WIDTH_B : integer := 4;
     64  constant RAM_ADDR_RATIO   : integer := 2;
     65
     66  --normalization time for trigger counters
     67  constant DEFAULT_PRESCALING : integer := 59; --30s integration time
     68
     69  constant NO_OF_ENABLE       : integer := 4;
     70  constant NO_OF_DAC          : integer := 8;
     71  constant NO_OF_DAC_NOT_USED : integer := 3;
     72  constant NO_OF_COUNTER      : integer := 5;
     73 
     74end ftu_constants;
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