- Timestamp:
- 08/30/10 16:01:15 (14 years ago)
- Location:
- firmware/FTU
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTU/FTU_control.vhd
r9890 r9911 147 147 FTU_control_State <= INIT; 148 148 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default DACs 149 if (ram_ada_cntr < NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO) then149 if (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO)) then 150 150 if (ram_ada_cntr mod 2 = 0) then 151 151 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2),16)(7 downto 0); … … 322 322 detect_new_rates: process(new_rates, new_rates_busy) 323 323 begin 324 if (new_rates_busy = '0' and rising_edge(new_rates)) then 324 if(new_rates_busy = '1') then 325 new_rates_sig <= '0'; 326 elsif rising_edge(new_rates) then 325 327 new_rates_sig <= '1'; 326 else327 new_rates_sig <= '0';328 328 end if; 329 329 end process detect_new_rates; -
firmware/FTU/FTU_top.vhd
r9890 r9911 205 205 attribute syn_black_box : boolean; 206 206 attribute syn_black_box of FTU_dual_port_ram: component is true; 207 -- avoid "black box" warning during synthesis 208 attribute box_type : string; 209 attribute box_type of FTU_dual_port_ram: component is "black_box"; 207 210 208 211 begin … … 215 218 enables_D <= enable_array_sig(3)(8 downto 0); 216 219 217 new_rates_sig <= new_rate_A_sig and new_rate_B_sig and new_rate_C_sig and new_rate_D_sig and new_rate_t_sig; 220 new_rates_sig <= new_rate_A_sig and new_rate_B_sig and new_rate_C_sig and new_rate_D_sig and new_rate_t_sig; 218 221 219 222 --differential input buffer for patch A -
firmware/FTU/counter/FTU_rate_counter.vhd
r9890 r9911 75 75 begin 76 76 77 if rising_edge(cntr_reset) then 78 79 --formula to calculate counting period from prescaling value 80 if (prescaling = "00000000") then 81 counting_period <= COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER); 82 else 83 counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER); 84 end if; 85 77 if cntr_reset = '1' then 78 86 79 clk_cntr := 0; 87 80 period_finished <= '1'; … … 91 84 92 85 elsif rising_edge(clk_1M_sig) then 86 93 87 if (clk_cntr < counting_period - 1) then 94 88 clk_cntr := clk_cntr + 1; … … 107 101 process(trigger, period_finished) 108 102 begin 109 if rising_edge(period_finished)then103 if period_finished = '1' then 110 104 trigger_counts <= 0; 111 105 overflow_sig <= '0'; … … 118 112 overflow_sig <= '1'; 119 113 end if; 114 end if; 115 end if; 116 end process; 117 118 process(cntr_reset, prescaling) 119 begin 120 if rising_edge(cntr_reset) then 121 --formula to calculate counting period from prescaling value 122 if (prescaling = "00000000") then 123 counting_period <= COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER); 124 else 125 counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER); 120 126 end if; 121 127 end if;
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