Changeset 9890 for firmware


Ignore:
Timestamp:
Aug 24, 2010, 1:39:00 PM (9 years ago)
Author:
weitzel
Message:
overflow register implemented for FTU rate counter
Location:
firmware/FTU
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • firmware/FTU/FTU_control.vhd

    r9880 r9890  
    4242    ram_dob        : IN  STD_LOGIC_VECTOR(15 downto 0);
    4343    rate_array     : IN  rate_array_type;
     44    overflow_array : in  STD_LOGIC_VECTOR(7 downto 0);
     45    new_rates      : IN  std_logic;
    4446    reset          : OUT std_logic;
    4547    config_start   : OUT std_logic;
     
    7375                                                  "0000000000000000");--patch D
    7476
    75   signal rate_array_sig : rate_array_type;  -- initialized in FTU_top 
     77  signal rate_array_sig : rate_array_type;  -- initialized in FTU_top
    7678  signal cntr_reset_sig : STD_LOGIC := '0';
    77   signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
     79  signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0) := "00011101";  -- 29
    7880 
    7981  signal ram_ena_sig  : STD_LOGIC := '0';  -- RAM enable for port A
     
    8789
    8890  --counter to loop through RAM
    89   signal ram_ada_cntr    : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
    90   signal ram_adb_cntr    : INTEGER range 0 to 2**RAM_ADDR_WIDTH_B := 0;
    91   signal ram_dac_cntr    : INTEGER range 0 to (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2) := 0;
    92   signal ram_enable_cntr : INTEGER range 0 to (NO_OF_ENABLE + 1) := 0;
    93 
     91  signal ram_ada_cntr     : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
     92  signal ram_adb_cntr     : INTEGER range 0 to 2**RAM_ADDR_WIDTH_B := 0;
     93  signal ram_dac_cntr     : INTEGER range 0 to (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2) := 0;
     94  signal ram_enable_cntr  : INTEGER range 0 to (NO_OF_ENABLE + 1) := 0;
     95  signal ram_counter_cntr : INTEGER range 0 to (NO_OF_COUNTER + 2) := 0;  --includes overflow register
     96 
    9497  signal wait_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
     98
     99  signal new_rates_sig  : STD_LOGIC := '0';
     100  signal new_rates_busy : STD_LOGIC := '0';
    95101 
    96102  signal new_DACs_in_RAM       : STD_LOGIC := '0';
     
    98104  signal new_prescaling_in_RAM : STD_LOGIC := '0';
    99105
    100   type FTU_control_StateType is (IDLE, INIT, RUNNING, CONFIG_ENABLE, CONFIG_DAC, CONFIG_COUNTER, RESET_ALL);
     106  type FTU_control_StateType is (IDLE, INIT, RUNNING, CONFIG_ENABLE, CONFIG_DAC, CONFIG_COUNTER, WRITE_RATES, RESET_ALL);
    101107  signal FTU_control_State : FTU_control_StateType;
    102108 
     
    117123          config_start_sig <= '0';
    118124          ram_ena_sig <= '0';
    119           ram_wea_sig <= "0";                   
     125          ram_wea_sig <= "0";
    120126          if (clk_ready = '1') then
    121127            FTU_control_State <= INIT;
     
    124130        when INIT =>  -- load default config data to RAM, see also ftu_definitions.vhd for more info
    125131          reset_sig <= '0';
     132          new_rates_busy <= '1';
    126133          config_start_sig <= '0';
    127134          ram_ena_sig <= '1';
     
    175182            new_enables_in_RAM <= '1';
    176183            new_prescaling_in_RAM <= '1';
     184            cntr_reset_sig <= '1';
     185            new_rates_busy <= '0';
    177186            FTU_control_State <= RUNNING;
    178187          end if;
    179188                   
    180189        when RUNNING =>  -- count triggers and react to commands from FTM
     190          cntr_reset_sig <= '0';
    181191          reset_sig <= '0';
    182192          config_start_sig <= '0';
    183           if (new_DACs_in_RAM = '1') then
    184             ram_enb_sig <= '1';
    185             ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER), RAM_ADDR_WIDTH_B);
    186             FTU_control_State <= CONFIG_DAC;
    187           elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '1') then
    188             ram_enb_sig <= '1';
    189             ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
    190             FTU_control_State <= CONFIG_ENABLE;
    191           elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '0' and new_prescaling_in_RAM = '1') then
    192             ram_ena_sig <= '1';
    193             ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
    194             FTU_control_State <= CONFIG_COUNTER;
    195           else
    196             FTU_control_State <= RUNNING;
     193          if (new_rates_sig = '1') then
     194            FTU_control_State <= WRITE_RATES;
     195          else
     196            if (new_DACs_in_RAM = '1') then
     197              ram_enb_sig <= '1';
     198              ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER), RAM_ADDR_WIDTH_B);
     199              FTU_control_State <= CONFIG_DAC;
     200            elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '1') then
     201              ram_enb_sig <= '1';
     202              ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
     203              FTU_control_State <= CONFIG_ENABLE;
     204            elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '0' and new_prescaling_in_RAM = '1') then
     205              ram_ena_sig <= '1';
     206              ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
     207              FTU_control_State <= CONFIG_COUNTER;
     208            else
     209              FTU_control_State <= RUNNING;
     210            end if;
    197211          end if;
    198212
    199213        when CONFIG_COUNTER =>
    200214          wait_cntr <= wait_cntr + 1;
     215          new_rates_busy <= '1';
    201216          if (wait_cntr = 0) then
    202217            FTU_control_State <= CONFIG_COUNTER;
    203218          elsif (wait_cntr = 1) then
    204219            prescaling_sig <= ram_doa;
     220            FTU_control_State <= CONFIG_COUNTER;
     221          else
    205222            cntr_reset_sig <= '1';
    206             FTU_control_State <= CONFIG_COUNTER;
    207           else
    208             cntr_reset_sig <= '0';
    209223            ram_ada_sig <= (others => '0');
    210224            wait_cntr <= 0;
    211225            new_prescaling_in_RAM <= '0';
    212226            ram_ena_sig <= '0';
     227            new_rates_busy <= '0';
    213228            FTU_control_State <= RUNNING;
    214229          end if;
     
    216231        when CONFIG_ENABLE =>
    217232          ram_enable_cntr <= ram_enable_cntr + 1;
     233          new_rates_busy <= '1';
    218234          if (ram_enable_cntr = 0) then
    219235            ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
     
    222238            ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
    223239            enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
    224             FTU_control_State <= CONFIG_ENABLE;           
     240            FTU_control_State <= CONFIG_ENABLE;
    225241          else
    226242            ram_adb_sig <= (others => '0');
     
    228244            new_enables_in_RAM <= '0';
    229245            ram_enb_sig <= '0';
     246            cntr_reset_sig <= '1';
     247            new_rates_busy <= '0';
    230248            FTU_control_State <= RUNNING;
    231249          end if;
    232250         
    233251        when CONFIG_DAC =>
     252          new_rates_busy <= '1';
    234253          if (ram_dac_cntr <= (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2)) then           
    235254            ram_dac_cntr <= ram_dac_cntr + 1;
     
    254273              ram_dac_cntr <= 0;
    255274              new_DACs_in_RAM <= '0';
     275              cntr_reset_sig <= '1';
     276              new_rates_busy <= '0';
    256277              FTU_control_State <= RUNNING;
    257278            elsif (config_ready = '0' and config_started = '1') then
     
    263284            end if;
    264285          end if;
    265          
     286
     287        when WRITE_RATES =>  -- write trigger/patch rates to RAM B and overflow register to RAM A
     288          new_rates_busy <= '1';         
     289          ram_counter_cntr <= ram_counter_cntr + 1;
     290          if (ram_counter_cntr < NO_OF_COUNTER) then
     291            ram_enb_sig <= '1';
     292            ram_web_sig <= "1";         
     293            ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr), RAM_ADDR_WIDTH_B);
     294            ram_dib_sig <= conv_std_logic_vector(rate_array_sig(ram_counter_cntr), 16);
     295            FTU_control_State <= WRITE_RATES;
     296          elsif (ram_counter_cntr = NO_Of_COUNTER) then
     297            ram_dib_sig <= (others => '0');
     298            ram_adb_sig <= (others => '0');
     299            ram_enb_sig <= '0';
     300            ram_web_sig <= "0";
     301            ram_ena_sig <= '1';
     302            ram_wea_sig <= "1";
     303            ram_ada_sig <= conv_std_logic_vector(NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1, RAM_ADDR_WIDTH_A);
     304            ram_dia_sig <= overflow_array;
     305            FTU_control_State <= WRITE_RATES;
     306          else             
     307            ram_ena_sig <= '0';
     308            ram_wea_sig <= "0";
     309            ram_counter_cntr <= 0;           
     310            new_rates_busy <= '0';
     311            FTU_control_State <= RUNNING;
     312          end if;
     313           
    266314        when RESET_ALL =>  -- reset/clear and start from scratch
    267315          reset_sig <= '1';
     
    272320  end process FTU_control_FSM;
    273321
     322  detect_new_rates: process(new_rates, new_rates_busy)
     323  begin
     324    if (new_rates_busy = '0' and rising_edge(new_rates)) then
     325      new_rates_sig <= '1';
     326    else
     327      new_rates_sig <= '0';
     328    end if;
     329  end process detect_new_rates;
     330 
    274331  reset <= reset_sig;
    275332 
     
    280337
    281338  rate_array_sig <= rate_array;
     339 
    282340  cntr_reset <= cntr_reset_sig;
    283341  prescaling <= prescaling_sig;
  • firmware/FTU/FTU_top.vhd

    r9880 r9890  
    9797
    9898  --rate counter signals
    99   signal cntr_reset_sig : STD_LOGIC;  -- initialized in FTU_control 
    100   signal rate_array_sig : rate_array_type := (0,0,0,0,0);
    101   signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0);
     99  signal cntr_reset_sig : STD_LOGIC;  -- initialized in FTU_control
     100  signal rate_array_sig : rate_array_type;  -- initialized by counters
     101  signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0);  -- initialized in FTU_control 
    102102  signal overflow_array : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
     103  signal new_rate_A_sig : STD_LOGIC;  -- initialized by patch A counter
     104  signal new_rate_B_sig : STD_LOGIC;  -- initialized by patch B counter
     105  signal new_rate_C_sig : STD_LOGIC;  -- initialized by patch C counter
     106  signal new_rate_D_sig : STD_LOGIC;  -- initialized by patch D counter
     107  signal new_rate_t_sig : STD_LOGIC;  -- initialized by trigger counter
     108  signal new_rates_sig  : STD_LOGIC := '0';
    103109 
    104110  signal clk_50M_sig   : STD_LOGIC;         -- generated by internal DCM
     
    133139      prescaling : in  std_logic_vector(7 downto 0);
    134140      counts     : out integer range 0 to 2**16 - 1;
    135       overflow   : out std_logic
     141      overflow   : out std_logic;
     142      new_rate   : out std_logic
    136143      );
    137144  end component;
     
    146153      ram_dob        : IN  STD_LOGIC_VECTOR(15 downto 0);
    147154      rate_array     : IN  rate_array_type;
     155      overflow_array : in  STD_LOGIC_VECTOR(7 downto 0);
     156      new_rates      : IN  std_logic;
    148157      reset          : OUT std_logic;
    149158      config_start   : OUT std_logic;
     
    206215  enables_D <= enable_array_sig(3)(8 downto 0);
    207216
     217  new_rates_sig <= new_rate_A_sig and new_rate_B_sig and new_rate_C_sig and new_rate_D_sig and new_rate_t_sig;
     218 
    208219  --differential input buffer for patch A
    209220  IBUFDS_LVDS_33_A : IBUFDS_LVDS_33
     
    261272      prescaling => prescaling_sig,
    262273      counts     => rate_array_sig(0),
    263       overflow   => overflow_array(0)
     274      overflow   => overflow_array(0),
     275      new_rate   => new_rate_A_sig
    264276    );
    265277
     
    271283      prescaling => prescaling_sig,
    272284      counts     => rate_array_sig(1),
    273       overflow   => overflow_array(1)
     285      overflow   => overflow_array(1),
     286      new_rate   => new_rate_B_sig
    274287    );
    275288
     
    281294      prescaling => prescaling_sig,
    282295      counts     => rate_array_sig(2),
    283       overflow   => overflow_array(2)
     296      overflow   => overflow_array(2),
     297      new_rate   => new_rate_C_sig
    284298    );
    285299
     
    291305      prescaling => prescaling_sig,
    292306      counts     => rate_array_sig(3),
    293       overflow   => overflow_array(3)
     307      overflow   => overflow_array(3),
     308      new_rate   => new_rate_D_sig
    294309    );
    295310
     
    301316      prescaling => prescaling_sig,
    302317      counts     => rate_array_sig(4),
    303       overflow   => overflow_array(4)
     318      overflow   => overflow_array(4),
     319      new_rate   => new_rate_t_sig
    304320    );
    305321 
     
    313329      ram_dob        => ram_dob_sig,
    314330      rate_array     => rate_array_sig,
     331      overflow_array => overflow_array,
     332      new_rates      => new_rates_sig,
    315333      reset          => reset_sig,
    316334      config_start   => config_start_sig,
  • firmware/FTU/FTU_top_tb.vhd

    r9880 r9890  
    210210    wait for 5ns;
    211211    trigger_sig <= '0';
    212     wait for 100us;
     212    wait for 99us;
     213    trigger_sig <= '1';
     214    wait for 5ns;
     215    trigger_sig <= '0';
     216    wait for 1us;
    213217    trigger_sig <= '1';
    214218    wait for 5ns;
  • firmware/FTU/counter/FTU_rate_counter.vhd

    r9880 r9890  
    3939    trigger    : in  std_logic;
    4040    prescaling : in  std_logic_vector(7 downto 0);
    41     counts     : out integer range 0 to 2**16 - 1;
    42     overflow   : out std_logic
     41    counts     : out integer range 0 to 2**16 - 1 := 0;
     42    overflow   : out std_logic := '0';
     43    new_rate   : out std_logic
    4344  );
    4445end FTU_rate_counter;
     
    5152  signal clk_1M_sig      : std_logic;
    5253  signal overflow_sig    : std_logic := '0';
     54  signal new_rate_sig    : std_logic := '0';
    5355 
    5456  component Clock_Divider
     
    6769    );
    6870 
    69   process(cntr_reset, clk_1M_sig)   
     71  process(cntr_reset, clk_1M_sig)
     72
    7073    variable clk_cntr : integer range 0 to 128*COUNTER_FREQUENCY := 0;
     74
    7175  begin
    72     if (cntr_reset = '1') then
    73       counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2)*COUNTER_FREQUENCY;
    74       clk_cntr := 0;
     76
     77    if rising_edge(cntr_reset) then
     78     
     79      --formula to calculate counting period from prescaling value
     80      if (prescaling = "00000000") then
     81        counting_period <= COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER);
     82      else
     83        counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER);
     84      end if;
     85     
     86      clk_cntr := 0;     
    7587      period_finished <= '1';
     88      new_rate_sig <= '0';
     89      counts <= 0;
     90      overflow <= '0';
     91     
    7692    elsif rising_edge(clk_1M_sig) then
    7793      if (clk_cntr < counting_period - 1) then
    7894        clk_cntr := clk_cntr + 1;
    7995        period_finished <= '0';
     96        new_rate_sig <= '0';
    8097      else
    8198        clk_cntr := 0;
    8299        period_finished <= '1';
     100        new_rate_sig <= '1';
    83101        counts <= trigger_counts;
     102        overflow <= overflow_sig;
    84103      end if;
    85104    end if;
     
    90109    if rising_edge(period_finished) then
    91110      trigger_counts <= 0;
     111      overflow_sig <= '0';
    92112    else
    93113      if rising_edge(trigger) then
    94         trigger_counts <= trigger_counts + 1;
     114        if (trigger_counts < 2**16 - 1) then
     115          trigger_counts <= trigger_counts + 1;
     116        else
     117          trigger_counts <= 0;
     118          overflow_sig <= '1';
     119        end if;
    95120      end if;
    96121    end if;
    97122  end process;
    98 
    99   overflow <= overflow_sig;
     123 
     124  new_rate <= new_rate_sig;
    100125 
    101126end Behavioral;
  • firmware/FTU/ftu_definitions.vhd

    r9880 r9890  
    5757  --internal FPGA clock frequency and rate counter frequency
    5858  constant INT_CLK_FREQUENCY : integer := 50000000;  -- 50MHz
    59   constant COUNTER_FREQUENCY : integer :=  1000000;  --  1MHZ, has to be smaller than INT_CLK_FREQUENCY
     59  constant COUNTER_FREQUENCY : integer :=  1000000;  -- has to be smaller than INT_CLK_FREQUENCY
     60  constant CNTR_FREQ_DIVIDER : integer :=   500000;
    6061   
    6162  --32byte dual-port RAM, port A: 8byte, port B: 16byte
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