Changeset 10123 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Timestamp:
- 01/27/11 17:10:41 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd
r10121 r10123 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 11:57:15 26.01.20115 -- at - 09:36:36 27.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 40 40 -- Created: 41 41 -- by - dneise.UNKNOWN (E5B-LABOR6) 42 -- at - 11:57:15 26.01.201142 -- at - 09:36:36 27.01.2011 43 43 -- 44 44 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf
r10121 r10123 35 35 36 36 # BOARD ID - inputs 37 NET POSITION_ID<0> LOC = Y1 | IOSTANDARD=LVCMOS33; #ok name was LINE befoer i changed it38 NET POSITION_ID<1> LOC = Y2 | IOSTANDARD=LVCMOS33; #ok39 NET POSITION_ID<2> LOC = AB1 | IOSTANDARD=LVCMOS33; #ok40 NET POSITION_ID<3> LOC = AC1 | IOSTANDARD=LVCMOS33; #ok41 NET POSITION_ID<4> LOC = AD1 | IOSTANDARD=LVCMOS33; #ok42 NET POSITION_ID<5> LOC = AD2 | IOSTANDARD=LVCMOS33; #ok37 NET LINE<0> LOC = Y1 | IOSTANDARD=LVCMOS33; #ok 38 NET LINE<1> LOC = Y2 | IOSTANDARD=LVCMOS33; #ok 39 NET LINE<2> LOC = AB1 | IOSTANDARD=LVCMOS33; #ok 40 NET LINE<3> LOC = AC1 | IOSTANDARD=LVCMOS33; #ok 41 NET LINE<4> LOC = AD1 | IOSTANDARD=LVCMOS33; #ok 42 NET LINE<5> LOC = AD2 | IOSTANDARD=LVCMOS33; #ok 43 43 44 44 # W5300 … … 138 138 NET D_T<4> LOC = K5 | IOSTANDARD=LVCMOS25; #ok 139 139 NET D_T<5> LOC = L4 | IOSTANDARD=LVCMOS25; #ok 140 NET D_T<6> LOC = M3 | IOSTANDARD=LVCMOS25; #ok 141 NET D_T<7> LOC = T3 | IOSTANDARD=LVCMOS25; #ok 140 NET D_T_in<0> LOC = M3 | IOSTANDARD=LVCMOS25 | pullup; #ok was: NET D_T<6> LOC = M3 141 NET D_T_in<1> LOC = T3 | IOSTANDARD=LVCMOS25 | pullup; #ok was: NET D_T<7> LOC = T3 142 #NET D_T<6> LOC = M3 | IOSTANDARD=LVCMOS25; #ok 143 #NET D_T<7> LOC = T3 | IOSTANDARD=LVCMOS25; #ok 142 144 NET D_T2<0> LOC = U2 | IOSTANDARD=LVCMOS25; #ok was D_T<8> 143 145 NET D_T2<1> LOC = V2 | IOSTANDARD=LVCMOS25; #ok was D_T<9> -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf.bak
r10121 r10123 35 35 36 36 # BOARD ID - inputs 37 NET POSITION_ID<0> LOC = Y1 | IOSTANDARD=LVCMOS33; #ok name was LINE befoer i changed it38 NET POSITION_ID<1> LOC = Y2 | IOSTANDARD=LVCMOS33; #ok39 NET POSITION_ID<2> LOC = AB1 | IOSTANDARD=LVCMOS33; #ok40 NET POSITION_ID<3> LOC = AC1 | IOSTANDARD=LVCMOS33; #ok41 NET POSITION_ID<4> LOC = AD1 | IOSTANDARD=LVCMOS33; #ok42 NET POSITION_ID<5> LOC = AD2 | IOSTANDARD=LVCMOS33; #ok37 NET LINE<0> LOC = Y1 | IOSTANDARD=LVCMOS33; #ok 38 NET LINE<1> LOC = Y2 | IOSTANDARD=LVCMOS33; #ok 39 NET LINE<2> LOC = AB1 | IOSTANDARD=LVCMOS33; #ok 40 NET LINE<3> LOC = AC1 | IOSTANDARD=LVCMOS33; #ok 41 NET LINE<4> LOC = AD1 | IOSTANDARD=LVCMOS33; #ok 42 NET LINE<5> LOC = AD2 | IOSTANDARD=LVCMOS33; #ok 43 43 44 44 # W5300 … … 99 99 100 100 NET SRIN LOC = E1 | IOSTANDARD=LVCMOS25; #ok -- nur fuer vollauslese noetig; auf Z legen. 101 #NET REFCLK LOC = AC11 | IOSTANDARD=LVCMOS25; #ok -- listen to REFCLK possible101 NET REFCLK LOC = AC11 | IOSTANDARD=LVCMOS25; #ok -- listen to REFCLK possible 102 102 103 103 … … 138 138 NET D_T<4> LOC = K5 | IOSTANDARD=LVCMOS25; #ok 139 139 NET D_T<5> LOC = L4 | IOSTANDARD=LVCMOS25; #ok 140 NET D_T<6> LOC = M3 | IOSTANDARD=LVCMOS25; #ok 141 NET D_T<7> LOC = T3 | IOSTANDARD=LVCMOS25; #ok 140 #NET D_T_in<0> LOC = M3 | IOSTANDARD=LVCMOS25 | pullup; #ok was: NET D_T<6> LOC = M3 141 #NET D_T_in<1> LOC = T3 | IOSTANDARD=LVCMOS25 | pullup; #ok was: NET D_T<7> LOC = T3 142 NET D_T<6> LOC = M3 | IOSTANDARD=LVCMOS25 | pullup; #ok 143 NET D_T<7> LOC = T3 | IOSTANDARD=LVCMOS25 | pullup; #ok 142 144 NET D_T2<0> LOC = U2 | IOSTANDARD=LVCMOS25; #ok was D_T<8> 143 145 NET D_T2<1> LOC = V2 | IOSTANDARD=LVCMOS25; #ok was D_T<9> -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10121 r10123 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 6:46:19 26.01.20115 -- at - 17:58:59 27.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 13 13 ENTITY FAD_Board IS 14 14 PORT( 15 A0_D : IN std_logic_vector (11 DOWNTO 0); 16 A1_D : IN std_logic_vector (11 DOWNTO 0); 17 A2_D : IN std_logic_vector (11 DOWNTO 0); 18 A3_D : IN std_logic_vector (11 DOWNTO 0); 19 A_OTR : IN std_logic_vector (3 DOWNTO 0); 20 D0_SROUT : IN std_logic; 21 D1_SROUT : IN std_logic; 22 D2_SROUT : IN std_logic; 23 D3_SROUT : IN std_logic; 24 D_PLLLCK : IN std_logic_vector (3 DOWNTO 0); 25 POSITION_ID : IN std_logic_vector ( 5 DOWNTO 0 ); 26 REFCLK : IN std_logic; 27 RS485_C_DI : IN std_logic; 28 RS485_E_DI : IN std_logic; 29 RS485_E_DO : IN std_logic; 30 TRG : IN STD_LOGIC; 31 W_INT : IN std_logic; 32 X_50M : IN STD_LOGIC; 33 A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 34 A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 35 AMBER_LED : OUT std_logic; 36 A_CLK : OUT std_logic_vector (3 DOWNTO 0); 37 D0_SRCLK : OUT STD_LOGIC; 38 D1_SRCLK : OUT STD_LOGIC; 39 D2_SRCLK : OUT STD_LOGIC; 40 D3_SRCLK : OUT STD_LOGIC; 41 DAC_CS : OUT std_logic; 42 DENABLE : OUT std_logic := '0'; 43 DWRITE : OUT std_logic := '0'; 44 D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 45 D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 46 D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 47 EE_CS : OUT std_logic; 48 GREEN_LED : OUT std_logic; 49 MOSI : OUT std_logic := '0'; 50 OE_ADC : OUT STD_LOGIC; 51 RED_LED : OUT std_logic; 52 RS485_C_DE : OUT std_logic; 53 RS485_C_DO : OUT std_logic; 54 RS485_C_RE : OUT std_logic; 55 RS485_E_DE : OUT std_logic; 56 RS485_E_RE : OUT std_logic; 57 RSRLOAD : OUT std_logic := '0'; 58 SRIN : OUT std_logic := '0'; 59 S_CLK : OUT std_logic; 60 T0_CS : OUT std_logic; 61 T1_CS : OUT std_logic; 62 T2_CS : OUT std_logic; 63 T3_CS : OUT std_logic; 64 TRG_V : OUT std_logic; 65 W_A : OUT std_logic_vector (9 DOWNTO 0); 66 W_CS : OUT std_logic := '1'; 67 W_RD : OUT std_logic := '1'; 68 W_RES : OUT std_logic := '1'; 69 W_WR : OUT std_logic := '1'; 70 MISO : INOUT std_logic; 71 W_D : INOUT std_logic_vector (15 DOWNTO 0) 15 A0_D : IN std_logic_vector (11 DOWNTO 0); 16 A1_D : IN std_logic_vector (11 DOWNTO 0); 17 A2_D : IN std_logic_vector (11 DOWNTO 0); 18 A3_D : IN std_logic_vector (11 DOWNTO 0); 19 A_OTR : IN std_logic_vector (3 DOWNTO 0); 20 D0_SROUT : IN std_logic; 21 D1_SROUT : IN std_logic; 22 D2_SROUT : IN std_logic; 23 D3_SROUT : IN std_logic; 24 D_PLLLCK : IN std_logic_vector (3 DOWNTO 0); 25 D_T_in : IN std_logic_vector (1 DOWNTO 0); 26 LINE : IN std_logic_vector ( 5 DOWNTO 0 ); 27 REFCLK : IN std_logic; 28 RS485_C_DI : IN std_logic; 29 RS485_E_DI : IN std_logic; 30 RS485_E_DO : IN std_logic; 31 TRG : IN STD_LOGIC; 32 W_INT : IN std_logic; 33 X_50M : IN STD_LOGIC; 34 A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 35 A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 36 AMBER_LED : OUT std_logic; 37 A_CLK : OUT std_logic_vector (3 DOWNTO 0); 38 D0_SRCLK : OUT STD_LOGIC; 39 D1_SRCLK : OUT STD_LOGIC; 40 D2_SRCLK : OUT STD_LOGIC; 41 D3_SRCLK : OUT STD_LOGIC; 42 DAC_CS : OUT std_logic; 43 DENABLE : OUT std_logic := '0'; 44 DWRITE : OUT std_logic := '0'; 45 D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 46 D_T : OUT std_logic_vector (5 DOWNTO 0) := (OTHERS => '0'); 47 D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 48 EE_CS : OUT std_logic; 49 GREEN_LED : OUT std_logic; 50 MOSI : OUT std_logic := '0'; 51 OE_ADC : OUT STD_LOGIC; 52 RED_LED : OUT std_logic; 53 RS485_C_DE : OUT std_logic; 54 RS485_C_DO : OUT std_logic; 55 RS485_C_RE : OUT std_logic; 56 RS485_E_DE : OUT std_logic; 57 RS485_E_RE : OUT std_logic; 58 RSRLOAD : OUT std_logic := '0'; 59 SRIN : OUT std_logic := '0'; 60 S_CLK : OUT std_logic; 61 T0_CS : OUT std_logic; 62 T1_CS : OUT std_logic; 63 T2_CS : OUT std_logic; 64 T3_CS : OUT std_logic; 65 TRG_V : OUT std_logic; 66 W_A : OUT std_logic_vector (9 DOWNTO 0); 67 W_CS : OUT std_logic := '1'; 68 W_RD : OUT std_logic := '1'; 69 W_RES : OUT std_logic := '1'; 70 W_WR : OUT std_logic := '1'; 71 MISO : INOUT std_logic; 72 W_D : INOUT std_logic_vector (15 DOWNTO 0) 72 73 ); 73 74 … … 81 82 -- Created: 82 83 -- by - dneise.UNKNOWN (E5B-LABOR6) 83 -- at - 1 6:46:20 26.01.201184 -- at - 17:58:59 27.01.2011 84 85 -- 85 86 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 120 121 SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); 121 122 SIGNAL dummy : std_logic; 123 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 122 124 SIGNAL ready : std_logic := '0'; 123 125 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); … … 136 138 PORT ( 137 139 CLK : IN std_logic ; 140 D_T_in : IN std_logic_vector (1 DOWNTO 0); 138 141 SROUT_in_0 : IN std_logic ; 139 142 SROUT_in_1 : IN std_logic ; … … 198 201 -- HDL Embedded Text Block 1 eb_ID 199 202 -- hard-wired IDs 200 board_id <= "0101";201 crate_id <= "01";203 board_id <= LINE(5 downto 2); 204 crate_id <= LINE(1 downto 0); 202 205 203 206 -- HDL Embedded Text Block 2 ADC_CLK … … 243 246 244 247 EE_CS <= '1'; 248 249 -- HDL Embedded Text Block 7 eb1 250 D_T(5 downto 0) <= (others => '0'); 245 251 246 252 -- HDL Embedded Text Block 8 eb2 … … 269 275 A1_T(7) <= drs_channel_id(3); 270 276 271 A0_T(5 downto 0) <= POSITION_ID;277 A0_T(5 downto 0) <= (others => '0'); 272 278 A0_T(6) <= REFCLK; 273 279 A0_T(7) <= RS485_E_DI; … … 291 297 PORT MAP ( 292 298 CLK => X_50M, 299 D_T_in => D_T_in, 293 300 SROUT_in_0 => D0_SROUT, 294 301 SROUT_in_1 => D1_SROUT, … … 324 331 drs_dwrite => DWRITE, 325 332 green => RED_LED, 326 led => D_T,333 led => led, 327 334 mosi => MOSI, 328 335 offset => OPEN, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10121 r10123 18 18 type mac_type is array (0 to 2) of std_logic_vector (15 downto 0); 19 19 type ip_type is array (0 to 3) of integer; 20 21 type mac_list_type is array (0 to 2) of mac_type; 22 type ip_list_type is array (0 to 2) of ip_type; 20 23 -- Network Settings 21 24 22 constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"97B4"); 25 constant ETHZ_GATEWAY : ip_type := (192, 33, 96, 1); 26 constant CAM_GATEWAY : ip_type := (192, 33, 96, 1); --??????????????? 27 constant TUDO_GATEWAY : ip_type := (129, 217, 160, 1); 23 28 24 -- @ ETH zurich 25 -- constant NETMASK : ip_type := (255, 255, 248, 0); 26 -- constant IP_ADDRESS : ip_type := (192, 33, 99, 225); 27 -- constant GATEWAY : ip_type := (192, 33, 96, 1); 29 constant ETHZ_NETMASK : ip_type := (255, 255, 248, 0); 30 constant CAM_NETMASK : ip_type := (255, 255, 248, 0); --??????????????? 31 constant TUDO_NETMASK : ip_type := (255, 255, 255, 0); 28 32 29 -- @ TU Dortmund 30 constant NETMASK : ip_type := (255, 255, 255, 0); 31 constant IP_ADDRESS : ip_type := (129, 217, 160, 119); 32 constant GATEWAY : ip_type := (129, 217, 160, 1); 33 --constant MAC_ZERO : mac_type := (X"0000", X"0000", X"0000"); 34 constant MAC_FAD0 : mac_type := (X"0011", X"9561", X"97B4"); 35 constant MAC_FAD1 : mac_type := (X"FAC7", X"0FAD", X"0001"); 36 constant MAC_FAD2 : mac_type := (X"FAC7", X"0FAD", X"0002"); 37 38 --constant IP_ZERO : ip_type := (0,0,0,0); 39 constant IP_TUDO : ip_type := (129, 217, 160, 119); 40 constant IP_ETHZ_FAD0 : ip_type := (192, 33, 99, 225); 41 constant IP_ETHZ_FAD1 : ip_type := (192, 33, 99, 226); 42 constant IP_ETHZ_FAD2 : ip_type := (192, 33, 99, 237); 43 44 -- IP lookup table used to convert CID,BID into IP, if not in camera. 45 constant IP_LIST : ip_list_type := (IP_ETHZ_FAD0, IP_ETHZ_FAD1, IP_ETHZ_FAD2); 46 constant MAC_LIST : mac_list_type := (MAC_FAD0,MAC_FAD1,MAC_FAD2); 33 47 34 48 constant FIRST_PORT : integer := 5000; 49 constant CAM_IP_PREFIX : ip_type := (192, 168, 0, 0); 50 constant IP_offset : integer := 128; 51 constant CAM_MAC_prefix : mac_type := (X"FAC7", X"0FAD", X"0000"); 35 52 -- Network Settings End 36 53 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd.bak
r10121 r10123 17 17 18 18 type mac_type is array (0 to 2) of std_logic_vector (15 downto 0); 19 type mac_list_type is array (0 to 3) of mac_type; 19 20 type ip_type is array (0 to 3) of integer; 21 type ip_list_type is array (0 to 3) of ip_type; 20 22 -- Network Settings 21 23 22 constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"97B4"); 24 constant ETHZ_GATEWAY : ip_type := (192, 33, 96, 1); 25 constant CAM_GATEWAY : ip_type := (192, 33, 96, 1); --??????????????? 26 constant TUDO_GATEWAY : ip_type := (129, 217, 160, 1); 23 27 24 -- @ ETH zurich 25 -- constant NETMASK : ip_type := (255, 255, 248, 0); 26 -- constant IP_ADDRESS : ip_type := (192, 33, 99, 225); 27 -- constant GATEWAY : ip_type := (192, 33, 96, 1); 28 constant ETHZ_NETMASK : ip_type := (255, 255, 248, 0); 29 constant CAM_NETMASK : ip_type := (255, 255, 248, 0); --??????????????? 30 constant TUDO_NETMASK : ip_type := (255, 255, 255, 0); 28 31 29 -- @ TU Dortmund 30 constant NETMASK : ip_type := (255, 255, 255, 0); 31 constant IP_ADDRESS : ip_type := (129, 217, 160, 119); 32 constant GATEWAY : ip_type := (129, 217, 160, 1); 32 --constant MAC_ZERO : mac_type := (X"0000", X"0000", X"0000"); 33 constant MAC_FAD0 : mac_type := (X"0011", X"9561", X"97B4"); 34 constant MAC_FAD1 : mac_type := (X"FAC7", X"0FAD", X"0001"); 35 constant MAC_FAD2 : mac_type := (X"FAC7", X"0FAD", X"0002"); 36 37 --constant IP_ZERO : ip_type := (0,0,0,0); 38 constant IP_TUDO : ip_type := (129, 217, 160, 119); 39 constant IP_ETHZ_FAD0 : ip_type := (192, 33, 99, 225); 40 constant IP_ETHZ_FAD1 : ip_type := (192, 33, 99, 226); 41 constant IP_ETHZ_FAD2 : ip_type := (192, 33, 99, 237); 42 43 -- IP lookup table used to convert CID,BID into IP, if not in camera. 44 constant IP_LIST : ip_list_type := (IP_ETHZ_FAD0, IP_ETHZ_FAD1, IP_ETHZ_FAD2); 45 constant MAC_LIST : mac_list_type := (MAC_FAD0,MAC_FAD1,MAC_FAD2); 33 46 34 47 constant FIRST_PORT : integer := 5000; 48 constant CAM_IP_PREFIX : ip_type := (192, 168, 0, 0); 49 constant IP_offset : integer := 128; 50 constant CAM_MAC_prefix : mac_type := (X"FAC7", X"0FAD", X"0000"); 35 51 -- Network Settings End 36 52 … … 142 158 143 159 constant CMD_PS_RESET : std_logic_vector := X"17"; 160 161 constant CMD_SET_TRIGGER_MULT : std_logic_vector := X"21"; 162 144 163 -- DRS Registers 145 164 constant DRS_CONFIG_REG : std_logic_vector := "1100"; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10121 r10123 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 6:46:18 26.01.20115 -- at - 17:58:58 27.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 19 19 PORT( 20 20 CLK : IN std_logic; 21 D_T_in : IN std_logic_vector (1 DOWNTO 0); 21 22 SROUT_in_0 : IN std_logic; 22 23 SROUT_in_1 : IN std_logic; … … 79 80 -- Created: 80 81 -- by - dneise.UNKNOWN (E5B-LABOR6) 81 -- at - 1 6:46:19 26.01.201182 -- at - 17:58:58 27.01.2011 82 83 -- 83 84 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 468 469 -- -- 469 470 config_busy : IN std_logic ; 471 MAC_jumper : IN std_logic_vector (1 DOWNTO 0); 472 BoardID : IN std_logic_vector (3 DOWNTO 0); 473 CrateID : IN std_logic_vector (1 DOWNTO 0); 470 474 denable : OUT std_logic := '0'; -- default domino wave off 471 475 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. … … 784 788 config_rw_ready => config_rw_ready, 785 789 config_busy => config_busy, 790 MAC_jumper => D_T_in, 791 BoardID => board_id, 792 CrateID => crate_id, 786 793 denable => denable, 787 794 dwrite_enable => dwrite_enable, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10121 r10123 69 69 config_busy : in std_logic; 70 70 71 71 MAC_jumper : in std_logic_vector (1 downto 0); 72 BoardID : in std_logic_vector (3 downto 0); 73 CrateID : in std_logic_vector (1 downto 0); 72 74 73 75 denable : out std_logic := '0'; -- default domino wave off … … 93 95 94 96 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, 95 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,97 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 96 98 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA); 97 99 type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, … … 152 154 signal data_valid_int : std_logic := '0'; 153 155 156 signal FAD_in_cam : std_logic := '0'; 157 signal FAD_at_ETHZ : std_logic := '0'; 158 signal bid : std_logic_vector (3 downto 0); 159 signal cid : std_logic_vector (1 downto 0); 160 161 154 162 -- only for debugging 155 163 --signal error_cnt : std_logic_vector (7 downto 0) := (others => '0'); … … 160 168 signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending 161 169 signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets. 170 171 signal mac_loc : mac_type; 172 signal ip_loc : ip_type; 173 signal gateway_loc : ip_type; 174 signal netmask_loc : ip_type; 175 162 176 163 177 begin … … 274 288 -- Init 275 289 when INIT => 290 -- status of MAC jumpers is synched in 291 -- and Board- and CrateID are synched in 292 FAD_in_cam <= MAC_jumper(1); -- see position of jumpers in FACT logbook 293 FAD_at_ETHZ <= MAC_jumper(0); -- MAC_jumper(1) is where D_T(7) was; MAC_jumper(0) is where D_T(6) was; 294 bid <= BoardID; 295 cid <= CrateID; 296 -- 276 297 par_addr <= W5300_MR; 277 298 par_data <= X"0000"; 278 299 state_init <= WRITE_REG; 279 next_state <= IM; 300 next_state <= LOCATE; 301 302 when LOCATE => 303 state_init <= IM; 304 305 if (FAD_in_cam = '1') then 306 -- if BID = "1111" and CID="11" then FAD is not really in cam 307 -- back to INIT !! endless loop 308 if (bid = "1111" and cid="11") then 309 -- this should never happen!!!!! 310 -- impossible to find this out, if in cam 311 state_init <= INIT; 312 else -- everything is fine 313 -- IP & MAC are calculated from BID & CID 314 -- code here 315 gateway_loc <= CAM_GATEWAY; 316 netmask_loc <= CAM_NETMASK; 317 mac_loc <= (CAM_MAC_prefix (0), CAM_MAC_prefix (1) , conv_std_logic_vector ( conv_integer(cid)*10+conv_integer(bid) , 16) ); 318 ip_loc <= ( CAM_IP_PREFIX(0) , CAM_IP_PREFIX(1) , IP_offset + conv_integer(cid) , IP_offset + conv_integer(bid) ); 319 end if; 320 else -- FAD is tested, eighther at ETHZ or at TUDO AND eighther with FMP or without. 321 if ( FAD_at_ETHZ = '0' ) then 322 -- easy FAD is at TUDO -> only one choice. 323 mac_loc <= MAC_FAD0; 324 ip_loc <= IP_TUDO; 325 gateway_loc <= TUDO_GATEWAY; 326 netmask_loc <= TUDO_NETMASK; 327 else -- FAD is at ETHZ but not in cam --> IP lookup table is needed. 328 if (bid = "1111" and cid="11") then -- FAD is not in crate 329 mac_loc <= MAC_FAD0; 330 ip_loc <= IP_ETHZ_FAD0; 331 gateway_loc <= ETHZ_GATEWAY; 332 netmask_loc <= ETHZ_NETMASK; 333 else 334 -- FAD is at ETHZ and in crate: 335 -- crate ID is not of importance. 336 -- we only have 3 MACs and IPs so far, so only the first boardIDs are allowed. 337 if ( conv_integer(bid) < MAC_LIST'length) then 338 gateway_loc <= ETHZ_GATEWAY; 339 netmask_loc <= ETHZ_NETMASK; 340 mac_loc <= MAC_LIST(conv_integer(bid)); 341 ip_loc <= IP_LIST(conv_integer(bid)); 342 end if; -- conv_integer 343 end if; -- bid=1111 & cid=11 344 end if; --FAD_at_ETHZ = 0 345 end if; --FAD_in_cam = 1 280 346 281 347 -- Interrupt Mask … … 336 402 when MAC => 337 403 par_addr <= W5300_SHAR; 338 par_data <= MAC_ADDRESS(0);404 par_data <= mac_loc(0); 339 405 state_init <= WRITE_REG; 340 406 next_state <= MAC1; 341 407 when MAC1 => 342 408 par_addr <= W5300_SHAR + 2; 343 par_data <= MAC_ADDRESS(1);409 par_data <= mac_loc(1); 344 410 state_init <= WRITE_REG; 345 411 next_state <= MAC2; 346 412 when MAC2 => 347 413 par_addr <= W5300_SHAR + 4; 348 par_data <= MAC_ADDRESS(2);414 par_data <= mac_loc(2); 349 415 state_init <= WRITE_REG; 350 416 next_state <= GW; … … 353 419 when GW => 354 420 par_addr <= W5300_GAR; 355 par_data (15 downto 8) <= conv_std_logic_vector( GATEWAY(0),8);356 par_data (7 downto 0) <= conv_std_logic_vector( GATEWAY(1),8);421 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(0),8); 422 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(1),8); 357 423 state_init <= WRITE_REG; 358 424 next_state <= GW1; 359 425 when GW1 => 360 426 par_addr <= W5300_GAR + 2; 361 par_data (15 downto 8) <= conv_std_logic_vector( GATEWAY(2),8);362 par_data (7 downto 0) <= conv_std_logic_vector( GATEWAY(3),8);427 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(2),8); 428 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(3),8); 363 429 state_init <= WRITE_REG; 364 430 next_state <= SNM; … … 367 433 when SNM => 368 434 par_addr <= W5300_SUBR; 369 par_data (15 downto 8) <= conv_std_logic_vector( NETMASK(0),8);370 par_data (7 downto 0) <= conv_std_logic_vector( NETMASK(1),8);435 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(0),8); 436 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(1),8); 371 437 state_init <= WRITE_REG; 372 438 next_state <= SNM1; 373 439 when SNM1 => 374 440 par_addr <= W5300_SUBR + 2; 375 par_data (15 downto 8) <= conv_std_logic_vector( NETMASK(2),8);376 par_data (7 downto 0) <= conv_std_logic_vector( NETMASK(3),8);441 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(2),8); 442 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(3),8); 377 443 state_init <= WRITE_REG; 378 444 next_state <= IP; … … 380 446 when IP => 381 447 par_addr <= W5300_SIPR; 382 par_data (15 downto 8) <= conv_std_logic_vector( IP_ADDRESS(0),8);383 par_data (7 downto 0) <= conv_std_logic_vector( IP_ADDRESS(1),8);448 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(0),8); 449 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(1),8); 384 450 state_init <= WRITE_REG; 385 451 next_state <= IP1; 386 452 when IP1 => 387 453 par_addr <= W5300_SIPR + 2; 388 par_data (15 downto 8) <= conv_std_logic_vector( IP_ADDRESS(2),8);389 par_data (7 downto 0) <= conv_std_logic_vector( IP_ADDRESS(3),8);454 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(2),8); 455 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(3),8); 390 456 state_init <= WRITE_REG; 391 457 next_state <= SI; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd.bak
r10121 r10123 69 69 config_busy : in std_logic; 70 70 71 71 MAC_jumper : in std_logic_vector (1 downto 0); 72 BoardID : in std_logic_vector (3 downto 0); 73 CrateID : in std_logic_vector (1 downto 0); 72 74 73 75 denable : out std_logic := '0'; -- default domino wave off … … 93 95 94 96 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, 95 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,97 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 96 98 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA); 97 99 type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, … … 152 154 signal data_valid_int : std_logic := '0'; 153 155 156 signal FAD_in_cam : std_logic := '0'; 157 signal FAD_at_ETHZ : std_logic := '0'; 158 signal bid : std_logic_vector (3 downto 0); 159 signal cid : std_logic_vector (1 downto 0); 160 161 154 162 -- only for debugging 155 163 --signal error_cnt : std_logic_vector (7 downto 0) := (others => '0'); … … 160 168 signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending 161 169 signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets. 170 171 signal mac_loc : mac_type; 172 signal ip_loc : ip_type; 173 signal gateway_loc : ip_type; 174 signal netmask_loc : ip_type; 175 162 176 163 177 begin … … 274 288 -- Init 275 289 when INIT => 290 -- status of MAC jumpers is synched in 291 -- and Board- and CrateID are synched in 292 FAD_in_cam <= MAC_jumper(1); -- see position of jumpers in FACT logbook 293 FAD_at_ETHZ <= MAC_jumper(0); -- MAC_jumper(1) is where D_T(7) was; MAC_jumper(0) is where D_T(6) was; 294 bid <= BoardID; 295 cid <= CrateID; 296 -- 276 297 par_addr <= W5300_MR; 277 298 par_data <= X"0000"; 278 299 state_init <= WRITE_REG; 279 next_state <= IM; 300 next_state <= LOCATE; 301 302 when LOCATE => 303 state_init <= IM; 304 305 if (FAD_in_cam = '1') then 306 -- if BID = "1111" and CID="11" then FAD is not really in cam 307 -- back to INIT !! endless loop 308 if (bid = "1111" and cid="11") then 309 -- this should never happen!!!!! 310 -- impossible to find this out, if in cam 311 state_init <= INIT; 312 else -- everything is fine 313 -- IP & MAC are calculated from BID & CID 314 -- code here 315 gateway_loc <= CAM_GATEWAY; 316 netmask_loc <= CAM_NETMASK; 317 mac_loc <= (CAM_MAC_prefix (0), CAM_MAC_prefix (1) , conv_std_logic_vector ( conv_integer(cid)*10+conv_integer(bid) , 16) ); 318 ip_loc <= ( CAM_IP_PREFIX(0) , CAM_IP_PREFIX(1) , IP_offset + conv_integer(cid) , IP_offset + conv_integer(bid) ); 319 end if; 320 else -- FAD is tested, eighther at ETHZ or at TUDO AND eighther with FMP or without. 321 if ( FAD_at_ETHZ = '0' ) then 322 -- easy FAD is at TUDO -> only one choice. 323 mac_loc <= MAC_FAD0; 324 ip_loc <= IP_TUDO; 325 gateway_loc <= TUDO_GATEWAY; 326 netmask_loc <= TUDO_NETMASK; 327 else -- FAD is at ETHZ but not in cam --> IP lookup table is needed. 328 if (bid = "1111" and cid="11") then -- FAD is not in crate 329 mac_loc <= MAC_FAD0; 330 ip_loc <= IP_ETHZ_FAD0; 331 gateway_loc <= ETHZ_GATEWAY; 332 netmask_loc <= ETHZ_NETMASK; 333 else 334 -- FAD is at ETHZ and in crate: 335 -- crate ID is not of importance. 336 -- we only have 3 MACs and IPs so far, so only the first boardIDs are allowed. 337 if ( conv_integer(bid) < MAC_LIST'length) then 338 gateway_loc <= ETHZ_GATEWAY; 339 netmask_loc <= ETHZ_NETMASK; 340 mac_loc <= MAC_LIST(conv_integer(bid)); 341 ip_loc <= IP_LIST(conv_integer(bid)); 342 end if; -- conv_integer 343 end if; -- bid=1111 & cid=11 344 end if; --FAD_at_ETHZ = 0 345 end if; --FAD_in_cam = 1 280 346 281 347 -- Interrupt Mask … … 336 402 when MAC => 337 403 par_addr <= W5300_SHAR; 338 par_data <= MAC_ADDRESS(0);404 par_data <= mac_loc(0); 339 405 state_init <= WRITE_REG; 340 406 next_state <= MAC1; 341 407 when MAC1 => 342 408 par_addr <= W5300_SHAR + 2; 343 par_data <= MAC_ADDRESS(1);409 par_data <= mac_loc(1); 344 410 state_init <= WRITE_REG; 345 411 next_state <= MAC2; 346 412 when MAC2 => 347 413 par_addr <= W5300_SHAR + 4; 348 par_data <= MAC_ADDRESS(2);414 par_data <= mac_loc(2); 349 415 state_init <= WRITE_REG; 350 416 next_state <= GW; … … 353 419 when GW => 354 420 par_addr <= W5300_GAR; 355 par_data (15 downto 8) <= conv_std_logic_vector( GATEWAY(0),8);356 par_data (7 downto 0) <= conv_std_logic_vector( GATEWAY(1),8);421 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(0),8); 422 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(1),8); 357 423 state_init <= WRITE_REG; 358 424 next_state <= GW1; 359 425 when GW1 => 360 426 par_addr <= W5300_GAR + 2; 361 par_data (15 downto 8) <= conv_std_logic_vector( GATEWAY(2),8);362 par_data (7 downto 0) <= conv_std_logic_vector( GATEWAY(3),8);427 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(2),8); 428 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(3),8); 363 429 state_init <= WRITE_REG; 364 430 next_state <= SNM; … … 367 433 when SNM => 368 434 par_addr <= W5300_SUBR; 369 par_data (15 downto 8) <= conv_std_logic_vector( NETMASK(0),8);370 par_data (7 downto 0) <= conv_std_logic_vector( NETMASK(1),8);435 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(0),8); 436 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(1),8); 371 437 state_init <= WRITE_REG; 372 438 next_state <= SNM1; 373 439 when SNM1 => 374 440 par_addr <= W5300_SUBR + 2; 375 par_data (15 downto 8) <= conv_std_logic_vector( NETMASK(2),8);376 par_data (7 downto 0) <= conv_std_logic_vector( NETMASK(3),8);441 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(2),8); 442 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(3),8); 377 443 state_init <= WRITE_REG; 378 444 next_state <= IP; 379 445 -- Own IP-Address 380 446 when IP => 447 led(0) <= '1'; 448 led(1) <= '1'; 449 led(2) <= '1'; 450 381 451 par_addr <= W5300_SIPR; 382 par_data (15 downto 8) <= conv_std_logic_vector( IP_ADDRESS(0),8);383 par_data (7 downto 0) <= conv_std_logic_vector( IP_ADDRESS(1),8);452 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(0),8); 453 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(1),8); 384 454 state_init <= WRITE_REG; 385 455 next_state <= IP1; 386 456 when IP1 => 387 457 par_addr <= W5300_SIPR + 2; 388 par_data (15 downto 8) <= conv_std_logic_vector( IP_ADDRESS(2),8);389 par_data (7 downto 0) <= conv_std_logic_vector( IP_ADDRESS(3),8);458 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(2),8); 459 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(3),8); 390 460 state_init <= WRITE_REG; 391 461 next_state <= SI; … … 404 474 -- Socket Init 405 475 when SI => 476 led(3) <= '1'; 406 477 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; 407 478 par_data <= X"0101"; -- ALIGN, TCP … … 435 506 end if; 436 507 when SI6 => 508 led(4) <= '1'; 437 509 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; 438 510 par_data <= X"0002"; -- LISTEN … … 448 520 449 521 when ESTABLISH => 522 led(5) <= '1'; 450 523 socks_waiting <= '1'; 451 524 socks_connected <= '0'; … … 607 680 --trigger_stop <= '1'; 608 681 state_read_data <= RD_5; 682 when CMD_SET_TRIGGER_MULT => 683 c_trigger_mult <= data_read (7 downto 0); 684 state_read_data <= RD_5; 685 609 686 -- phase shift commands here: 610 687 when CMD_PS_DO =>
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