Changeset 10441 for firmware/FTM
- Timestamp:
- 04/21/11 11:17:11 (14 years ago)
- Location:
- firmware/FTM
- Files:
-
- 2 added
- 7 edited
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FTM_central_control.vhd (modified) (9 diffs)
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FTM_top.vhd (modified) (6 diffs)
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ethernet/dd_write_general_modul_beha.vhd (modified) (9 diffs)
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ethernet/ethernet_modul_beha.vhd (modified) (12 diffs)
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ethernet/header_modul_beha.vhd (modified) (4 diffs)
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ethernet/w5300_modul.vhd (modified) (20 diffs)
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ftm_definitions.vhd (modified) (3 diffs)
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test_firmware/counter_dummy (added)
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test_firmware/counter_dummy/counter_dummy_beha.vhd (added)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTM/FTM_central_control.vhd
r10418 r10441 68 68 config_trigger_done : in std_logic; 69 69 dna_start : out std_logic := '0'; 70 dna_ready : in std_logic 70 dna_ready : in std_logic; 71 crate_reset : IN std_logic; 72 crate_reset_ack : OUT std_logic := '1'; 73 crate_reset_param : IN std_logic_vector (15 DOWNTO 0); 74 start_run : IN std_logic; 75 start_run_ack : OUT std_logic := '0'; 76 stop_run : IN std_logic; 77 stop_run_ack : OUT std_logic := '0'; 78 current_cc_state : OUT std_logic_vector (15 DOWNTO 0) := X"FFFF"; 79 start_run_param : IN std_logic_vector (15 DOWNTO 0); 80 start_run_num_events : IN std_logic_vector (31 DOWNTO 0); 81 trigger_start : out std_logic := '0'; 82 trigger_stop : out std_logic := '1' 71 83 ); 72 84 end FTM_central_control; … … 86 98 87 99 type state_central_proc_type is (CP_INIT, CP_INIT_DNA, 100 CP_RUNNING, CP_RUNNING_01, CP_RUNNING_02, CP_CONFIG_ACK, 88 101 CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01, 89 102 CP_CONFIG_CC, CP_CONFIG_CC_01, … … 94 107 CP_SEND_START, CP_SEND_END); 95 108 signal state_central_proc : state_central_proc_type := CP_INIT; 109 110 signal after_rates_state : state_central_proc_type := CP_IDLE; 111 signal after_ping_state : state_central_proc_type := CP_IDLE; 96 112 97 113 begin … … 189 205 190 206 when CP_IDLE => 207 current_cc_state <= FTM_STATE_IDLE; 208 stop_run_ack <= '1'; 209 start_run_ack <= '0'; 191 210 if (new_config = '1') then 192 211 config_started <= '1'; 212 start_run_ack <= '1'; 193 213 state_central_proc <= CP_CONFIG_START; 194 214 elsif (ping_ftu_start = '1') then … … 198 218 ping_ftu_started <= '1'; 199 219 ping_ftu_ready <= '0'; 220 after_ping_state <= CP_IDLE; 200 221 state_central_proc <= CP_PING; 201 222 end if; … … 205 226 --rates_ftu <= '1'; 206 227 --state_central_proc <= CP_READ_RATES; 228 after_rates_state <= CP_IDLE; 207 229 state_central_proc <= CP_START_RATES; 208 end if; 209 230 elsif (start_run = '1') then 231 start_run_ack <= '1'; 232 if (start_run_param = PAR_START_RUN) then 233 state_central_proc <= CP_RUNNING; 234 end if; 235 end if; 236 237 when CP_RUNNING => 238 current_cc_state <= FTM_STATE_RUN; 239 if (start_run = '0') then 240 start_run_ack <= '0'; 241 stop_run_ack <= '0'; 242 state_central_proc <= CP_RUNNING_01; 243 end if; 244 245 when CP_RUNNING_01 => 246 current_cc_state <= FTM_STATE_RUN; 247 start_run_ack <= '1'; 248 trigger_start <= '1'; 249 trigger_stop <= '0'; 250 if (new_config = '1') then 251 config_started <= '1'; 252 state_central_proc <= CP_CONFIG_ACK; 253 elsif (ping_ftu_start = '1') then 254 ping_ftu_start_ftu <= '1'; 255 if (ping_ftu_started_ftu = '1') then 256 ping_ftu_start_ftu <= '0'; 257 ping_ftu_started <= '1'; 258 ping_ftu_ready <= '0'; 259 after_ping_state <= CP_RUNNING_01; 260 state_central_proc <= CP_PING; 261 end if; 262 elsif (new_period_sig = '1') then 263 new_period_ack_sig <= '1'; 264 --rates_ftu <= '1'; 265 --state_central_proc <= CP_READ_RATES; 266 after_rates_state <= CP_RUNNING_01; 267 state_central_proc <= CP_START_RATES; 268 elsif (stop_run = '1') then 269 stop_run_ack <= '1'; 270 trigger_start <= '0'; 271 trigger_stop <= '1'; 272 state_central_proc <= CP_RUNNING_02; 273 end if; 274 275 when CP_RUNNING_02 => 276 if (stop_run = '0') then 277 stop_run_ack <= '0'; 278 state_central_proc <= CP_IDLE; 279 end if; 280 281 when CP_CONFIG_ACK => 282 if (config_started_ack = '1') then 283 config_started <= '0'; 284 state_central_proc <= CP_RUNNING_01; 285 end if; 286 210 287 when CP_PING => 211 288 if (ping_ftu_ready_ftu = '1') then … … 213 290 ping_ftu_started <= '0'; 214 291 ping_ftu_ready <= '1'; 215 state_central_proc <= CP_IDLE; 292 --state_central_proc <= CP_IDLE; 293 state_central_proc <= after_ping_state; 216 294 end if; 217 295 end if; … … 237 315 if (rates_ready_ftu = '1') then 238 316 dd_block_ready_ftu <= '1'; 239 state_central_proc <= CP_SEND_START; 317 if ( (start_run = '1') or (stop_run = '1') ) then 318 state_central_proc <= after_rates_state; 319 else 320 state_central_proc <= CP_SEND_START; 321 end if; 240 322 end if; 241 323 … … 249 331 when CP_SEND_END => 250 332 if (dd_send_ready = '1') then 251 state_central_proc <= CP_IDLE; 333 --state_central_proc <= CP_IDLE; 334 state_central_proc <= after_rates_state; 252 335 end if; 253 336 -
firmware/FTM/FTM_top.vhd
r10418 r10441 376 376 377 377 signal led_sig : std_logic_vector(7 downto 0) := (others => '0'); 378 379 signal get_ot_counter_sig : std_logic; 380 signal get_ot_counter_started_sig : std_logic; 381 signal get_ot_counter_ready_sig : std_logic; 382 signal on_time_counter_sig : std_logic_vector(47 downto 0); 383 384 signal get_ts_counter_sig : std_logic; 385 signal get_ts_counter_started_sig : std_logic; 386 signal get_ts_counter_ready_sig : std_logic; 387 signal timestamp_counter_sig : std_logic_vector(47 downto 0); 388 389 signal crate_reset_sig : std_logic; 390 signal crate_reset_ack_sig : std_logic; 391 signal crate_reset_param_sig : std_logic_vector (15 DOWNTO 0); 392 signal start_run_sig : std_logic; 393 signal start_run_ack_sig : std_logic; 394 signal stop_run_sig : std_logic; 395 signal stop_run_ack_sig : std_logic; 396 signal current_cc_state_sig : std_logic_vector (15 DOWNTO 0); 397 signal start_run_param_sig : std_logic_vector (15 DOWNTO 0); 398 signal start_run_num_events_sig : std_logic_vector (31 DOWNTO 0); 399 400 signal trigger_start_sig : std_logic; 401 signal trigger_stop_sig : std_logic; 378 402 379 403 -- component FTM_clk_gen … … 525 549 config_trigger_done : in std_logic; 526 550 dna_start : out std_logic; 527 dna_ready : in std_logic 551 dna_ready : in std_logic; 552 crate_reset : IN std_logic; 553 crate_reset_ack : OUT std_logic; 554 crate_reset_param : IN std_logic_vector (15 DOWNTO 0); 555 start_run : IN std_logic; 556 start_run_ack : OUT std_logic; 557 stop_run : IN std_logic; 558 stop_run_ack : OUT std_logic; 559 current_cc_state : OUT std_logic_vector (15 DOWNTO 0); 560 start_run_param : IN std_logic_vector (15 DOWNTO 0); 561 start_run_num_events : IN std_logic_vector (31 DOWNTO 0); 562 trigger_start : out std_logic; 563 trigger_stop : out std_logic 528 564 ); 529 565 end component; … … 683 719 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0'); 684 720 trigger_counter_read : OUT std_logic := '0'; 685 trigger_counter_valid : IN std_logic 721 trigger_counter_valid : IN std_logic; 722 --newest stuff 723 board_id : IN std_logic_vector (63 DOWNTO 0); 724 get_ts_counter : OUT std_logic := '0'; 725 get_ts_counter_ready : IN std_logic; 726 get_ts_counter_started : IN std_logic; 727 timestamp_counter : IN std_logic_vector (47 DOWNTO 0); 728 get_ot_counter : OUT std_logic := '0'; 729 get_ot_counter_ready : IN std_logic; 730 get_ot_counter_started : IN std_logic; 731 on_time_counter : IN std_logic_vector (47 DOWNTO 0); 732 temp_sensor_array : IN sensor_array_type; 733 temp_sensor_ready : IN std_logic; 734 crate_reset : OUT std_logic := '0'; 735 crate_reset_ack : IN std_logic; 736 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 737 start_run : OUT std_logic := '0'; 738 start_run_ack : IN std_logic; 739 stop_run : OUT std_logic := '0'; 740 stop_run_ack : IN std_logic; 741 current_cc_state : IN std_logic_vector (15 DOWNTO 0); 742 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 743 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0') 686 744 ); 687 745 end component; 688 746 747 component counter_dummy IS 748 PORT( 749 clk : IN std_logic; 750 get_counter : IN std_logic; 751 get_counter_started : OUT std_logic := '0'; 752 get_counter_ready : OUT std_logic := '0'; 753 counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') 754 ); 755 end component; 756 689 757 begin 690 758 … … 769 837 FAD_busy_3 => Busy3, --crate 3 770 838 --control signals from e.g. main control 771 start_run => '1', --enable trigger output772 stop_run => '0', --disable trigger output839 start_run => trigger_start_sig, --enable trigger output 840 stop_run => trigger_stop_sig, --disable trigger output 773 841 new_config => config_trigger_sig, 774 842 --settings register (see FTM Firmware Specifications) … … 862 930 config_trigger_done => config_trigger_done_sig, 863 931 dna_start => dna_start_sig, 864 dna_ready => dna_ready_sig 932 dna_ready => dna_ready_sig, 933 crate_reset => crate_reset_sig, 934 crate_reset_ack => crate_reset_ack_sig, 935 crate_reset_param => crate_reset_param_sig, 936 start_run => start_run_sig, 937 start_run_ack => start_run_ack_sig, 938 stop_run => stop_run_sig, 939 stop_run_ack => stop_run_ack_sig, 940 current_cc_state => current_cc_state_sig, 941 start_run_param => start_run_param_sig, 942 start_run_num_events => start_run_num_events_sig, 943 trigger_start => trigger_start_sig, 944 trigger_stop => trigger_stop_sig 865 945 ); 866 946 … … 1017 1097 trigger_counter => trigger_counter_sig, 1018 1098 trigger_counter_read => trigger_counter_read_sig, 1019 trigger_counter_valid => trigger_counter_valid_sig 1020 ); 1021 1099 trigger_counter_valid => trigger_counter_valid_sig, 1100 --newest stuff 1101 board_id => dna_sig, 1102 get_ts_counter => get_ts_counter_sig, 1103 get_ts_counter_ready => get_ts_counter_ready_sig, 1104 get_ts_counter_started => get_ts_counter_started_sig, 1105 timestamp_counter => timestamp_counter_sig, 1106 get_ot_counter => get_ot_counter_sig, 1107 get_ot_counter_ready => get_ot_counter_ready_sig, 1108 get_ot_counter_started => get_ot_counter_started_sig, 1109 on_time_counter => on_time_counter_sig, 1110 temp_sensor_array => (35, 45, 55, 65), 1111 temp_sensor_ready => '1', 1112 crate_reset => crate_reset_sig, 1113 crate_reset_ack => crate_reset_ack_sig, 1114 crate_reset_param => crate_reset_param_sig, 1115 start_run => start_run_sig, 1116 start_run_ack => start_run_ack_sig, 1117 stop_run => stop_run_sig, 1118 stop_run_ack => stop_run_ack_sig, 1119 current_cc_state => current_cc_state_sig, 1120 start_run_param => start_run_param_sig, 1121 start_run_num_events => start_run_num_events_sig 1122 ); 1123 1124 Inst_counter_dummy_ts : counter_dummy 1125 port map( 1126 clk => clk_50M_sig, 1127 get_counter => get_ts_counter_sig, 1128 get_counter_started => get_ts_counter_started_sig, 1129 get_counter_ready => get_ts_counter_ready_sig, 1130 counter => timestamp_counter_sig 1131 ); 1132 1133 Inst_counter_dummy_ot : counter_dummy 1134 port map( 1135 clk => clk_50M_sig, 1136 get_counter => get_ot_counter_sig, 1137 get_counter_started => get_ot_counter_started_sig, 1138 get_counter_ready => get_ot_counter_ready_sig, 1139 counter => on_time_counter_sig 1140 ); 1141 1022 1142 LED_red <= led_sig(3 downto 0); 1023 1143 LED_ye <= led_sig(5 downto 4); -
firmware/FTM/ethernet/dd_write_general_modul_beha.vhd
r10418 r10441 8 8 -- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) 9 9 -- 10 11 10 LIBRARY ieee; 12 11 USE ieee.std_logic_1164.all; 13 12 USE ieee.std_logic_arith.all; 14 13 USE IEEE.STD_LOGIC_UNSIGNED.all; 15 -- LIBRARY FACT_FTM_lib; 16 -- USE FACT_FTM_lib.ftm_array_types.all; 17 -- USE FACT_FTM_lib.ftm_constants.all; 14 18 15 library ftm_definitions; 19 16 USE ftm_definitions.ftm_array_types.all; … … 26 23 dd_write_general_started : OUT std_logic := '0'; 27 24 dd_write_general_ready : OUT std_logic := '0'; 28 dd_busy : IN std_logic; 29 dd_write : OUT std_logic := '0'; 30 dd_started : IN std_logic; 31 dd_ready : IN std_logic; 32 dd_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); 33 dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') 25 dd_busy : IN std_logic; 26 dd_write : OUT std_logic := '0'; 27 dd_started : IN std_logic; 28 dd_ready : IN std_logic; 29 dd_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); 30 dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 31 get_ot_counter : OUT std_logic := '0'; 32 get_ot_counter_started : IN std_logic; 33 get_ot_counter_ready : IN std_logic; 34 on_time_counter : IN std_logic_vector (47 DOWNTO 0); 35 temp_sensor_ready : IN std_logic; 36 temp_sensor_array : IN sensor_array_type 34 37 ); 35 38 END ENTITY dd_write_general_modul; … … 38 41 ARCHITECTURE beha OF dd_write_general_modul IS 39 42 40 type state_write_general_proc_type is (WGP_INIT, WGP_CONFIG, WGP_IDLE, WGP_WRITE_COUNTER_01, WGP_WRITE_COUNTER_02, WGP_WRITE_COUNTER_03, 43 type state_write_general_proc_type is (WGP_INIT, WGP_CONFIG, WGP_IDLE, 44 WGP_OT_CNT, WGP_OT_CNT_END, 45 WGP_WRITE_COUNTER_00, WGP_WRITE_COUNTER_01, WGP_WRITE_COUNTER_02, WGP_WRITE_COUNTER_03, 41 46 WGP_WRITE_TEMP_01, WGP_WRITE_TEMP_02, WGP_WRITE_TEMP_03, WGP_WRITE_TEMP_04, WGP_WRITE_READY, WRITE_TO_DD_ADDR); 42 47 type state_write_dd_type is (WRITE_DD_START, WRITE_DD_WAIT, WRITE_DD_END); … … 49 54 signal local_dd_data : std_logic_vector (15 DOWNTO 0) := (others => '0'); 50 55 51 signal on_time_counter : std_logic_vector (47 DOWNTO 0) := X"333322221111";52 signal temp_sensor_0 : std_logic_vector (15 DOWNTO 0) := X"00FF";53 signal temp_sensor_1 : std_logic_vector (15 DOWNTO 0) := X"11FF";54 signal temp_sensor_2 : std_logic_vector (15 DOWNTO 0) := X"22FF";55 signal temp_sensor_3 : std_logic_vector (15 DOWNTO 0) := X"33FF";56 56 57 57 BEGIN … … 71 71 dd_write_general_started <= '1'; 72 72 dd_write_general_ready <= '0'; 73 state_write_general_proc <= WGP_WRITE_COUNTER_01; 73 get_ot_counter <= '1'; 74 state_write_general_proc <= WGP_OT_CNT; 74 75 end if; 75 76 77 when WGP_OT_CNT => 78 if (get_ot_counter_started = '1') then 79 get_ot_counter <= '0'; 80 state_write_general_proc <= WGP_OT_CNT_END; 81 end if; 82 83 when WGP_OT_CNT_END => 84 if (get_ot_counter_ready = '1') then 85 state_write_general_proc <= WGP_WRITE_COUNTER_00; 86 end if; 87 88 when WGP_WRITE_COUNTER_00 => 89 local_dd_addr <= X"000"; 90 local_dd_data <= X"0000"; 91 next_state_dd <= WGP_WRITE_COUNTER_01; 92 state_write_general_proc <= WRITE_TO_DD_ADDR; 93 76 94 when WGP_WRITE_COUNTER_01 => 77 local_dd_addr <= X"00 0";95 local_dd_addr <= X"001"; 78 96 local_dd_data <= on_time_counter (47 DOWNTO 32); 79 97 next_state_dd <= WGP_WRITE_COUNTER_02; … … 81 99 82 100 when WGP_WRITE_COUNTER_02 => 83 local_dd_addr <= X"00 1";101 local_dd_addr <= X"002"; 84 102 local_dd_data <= on_time_counter (31 DOWNTO 16); 85 103 next_state_dd <= WGP_WRITE_COUNTER_03; … … 87 105 88 106 when WGP_WRITE_COUNTER_03 => 89 local_dd_addr <= X"00 2";107 local_dd_addr <= X"003"; 90 108 local_dd_data <= on_time_counter (15 DOWNTO 0); 91 109 next_state_dd <= WGP_WRITE_TEMP_01; … … 93 111 94 112 when WGP_WRITE_TEMP_01 => 95 local_dd_addr <= X"003"; 96 local_dd_data <= temp_sensor_0; 97 next_state_dd <= WGP_WRITE_TEMP_02; 98 state_write_general_proc <= WRITE_TO_DD_ADDR; 113 if (temp_sensor_ready = '1') then 114 local_dd_addr <= X"004"; 115 local_dd_data <= conv_std_logic_vector (temp_sensor_array (0), 16); 116 next_state_dd <= WGP_WRITE_TEMP_02; 117 state_write_general_proc <= WRITE_TO_DD_ADDR; 118 end if; 99 119 100 120 when WGP_WRITE_TEMP_02 => 101 local_dd_addr <= X"004"; 102 local_dd_data <= temp_sensor_1; 103 next_state_dd <= WGP_WRITE_TEMP_03; 104 state_write_general_proc <= WRITE_TO_DD_ADDR; 121 if (temp_sensor_ready = '1') then 122 local_dd_addr <= X"005"; 123 local_dd_data <= conv_std_logic_vector (temp_sensor_array (1), 16); 124 next_state_dd <= WGP_WRITE_TEMP_03; 125 state_write_general_proc <= WRITE_TO_DD_ADDR; 126 end if; 105 127 106 128 when WGP_WRITE_TEMP_03 => 107 local_dd_addr <= X"005"; 108 local_dd_data <= temp_sensor_2; 109 next_state_dd <= WGP_WRITE_TEMP_04; 110 state_write_general_proc <= WRITE_TO_DD_ADDR; 129 if (temp_sensor_ready = '1') then 130 local_dd_addr <= X"006"; 131 local_dd_data <= conv_std_logic_vector (temp_sensor_array (2), 16); 132 next_state_dd <= WGP_WRITE_TEMP_04; 133 state_write_general_proc <= WRITE_TO_DD_ADDR; 134 end if; 111 135 112 136 when WGP_WRITE_TEMP_04 => 113 local_dd_addr <= X"006"; 114 local_dd_data <= temp_sensor_3; 115 next_state_dd <= WGP_WRITE_READY; 116 state_write_general_proc <= WRITE_TO_DD_ADDR; 137 if (temp_sensor_ready = '1') then 138 local_dd_addr <= X"007"; 139 local_dd_data <= conv_std_logic_vector (temp_sensor_array (3), 16); 140 next_state_dd <= WGP_WRITE_READY; 141 state_write_general_proc <= WRITE_TO_DD_ADDR; 142 end if; 117 143 118 144 when WGP_WRITE_READY => … … 150 176 151 177 END ARCHITECTURE beha; 178 -
firmware/FTM/ethernet/ethernet_modul_beha.vhd
r10366 r10441 3 3 -- Created: 4 4 -- by - kai.users (tpkw.local.priv) 5 -- at - 1 0:39:41 04/13/115 -- at - 11:20:56 04/20/11 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 10 10 USE ieee.std_logic_1164.all; 11 11 USE ieee.std_logic_arith.all; 12 --LIBRARY FACT_FTM_lib; 12 13 13 library ftm_definitions; 14 14 USE ftm_definitions.ftm_array_types.all; 15 15 USE ftm_definitions.ftm_constants.all; 16 17 16 18 17 ENTITY ethernet_modul IS … … 70 69 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0); 71 70 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); 71 -- 72 72 ping_ftu_start : OUT std_logic := '0'; 73 73 ping_ftu_started : IN std_logic; … … 89 89 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0); 90 90 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1 91 -- 91 92 ftu_error_send : IN std_logic; 92 93 ftu_error_send_ack : OUT std_logic := '1'; … … 95 96 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0'); 96 97 trigger_counter_read : OUT std_logic := '0'; 97 trigger_counter_valid : IN std_logic 98 trigger_counter_valid : IN std_logic; 99 board_id : IN std_logic_vector (63 DOWNTO 0); 100 get_ts_counter : OUT std_logic := '0'; 101 get_ts_counter_ready : IN std_logic; 102 get_ts_counter_started : IN std_logic; 103 timestamp_counter : IN std_logic_vector (47 DOWNTO 0); 104 get_ot_counter : OUT std_logic := '0'; 105 get_ot_counter_ready : IN std_logic; 106 get_ot_counter_started : IN std_logic; 107 on_time_counter : IN std_logic_vector (47 DOWNTO 0); 108 temp_sensor_array : IN sensor_array_type; 109 temp_sensor_ready : IN std_logic; 110 crate_reset : OUT std_logic := '0'; 111 crate_reset_ack : IN std_logic; 112 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 113 -- 114 start_run : OUT std_logic := '0'; 115 start_run_ack : IN std_logic; 116 stop_run : OUT std_logic := '0'; 117 stop_run_ack : IN std_logic; 118 current_cc_state : IN std_logic_vector (15 DOWNTO 0); 119 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 120 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0') 98 121 ); 99 122 … … 159 182 SIGNAL header_timestamp_counter : std_logic_vector(47 DOWNTO 0); 160 183 SIGNAL header_trigger_counter : std_logic_vector(31 DOWNTO 0); 184 SIGNAL header_current_state : std_logic_vector(15 DOWNTO 0) := (others => '0'); 161 185 162 186 -- Implicit buffer signal declarations … … 268 292 dd_ready : IN std_logic ; 269 293 dd_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); 270 dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') 294 dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 295 get_ot_counter : OUT std_logic := '0'; 296 get_ot_counter_started : IN std_logic ; 297 get_ot_counter_ready : IN std_logic ; 298 on_time_counter : IN std_logic_vector (47 DOWNTO 0); 299 temp_sensor_ready : IN std_logic ; 300 temp_sensor_array : IN sensor_array_type 271 301 ); 272 302 END COMPONENT; … … 338 368 get_header_started : OUT std_logic := '0'; 339 369 get_header_ready : OUT std_logic := '0'; 370 board_id : IN std_logic_vector (63 DOWNTO 0); 340 371 trigger_counter_read : OUT std_logic := '0'; 341 372 trigger_counter_valid : IN std_logic ; 342 373 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0'); 374 get_ts_counter : OUT std_logic := '0'; 375 get_ts_counter_started : IN std_logic ; 376 get_ts_counter_ready : IN std_logic ; 377 timestamp_counter : IN std_logic_vector (47 DOWNTO 0); 343 378 header_board_id : OUT std_logic_vector (63 DOWNTO 0) := (others => '0'); 344 379 header_firmware_id : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 345 380 header_trigger_counter : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); 346 header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') 381 header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0'); 382 header_current_state : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 383 current_cc_state : IN std_logic_vector (15 DOWNTO 0) 347 384 ); 348 385 END COMPONENT; … … 411 448 header_firmware_id : IN std_logic_vector (15 DOWNTO 0); 412 449 header_trigger_counter : IN std_logic_vector (31 DOWNTO 0); 413 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0) 450 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0); 451 header_current_state : IN std_logic_vector (15 DOWNTO 0); 452 -- 453 start_run : OUT std_logic := '0'; 454 start_run_ack : IN std_logic ; 455 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 456 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); 457 stop_run : OUT std_logic := '0'; 458 stop_run_ack : IN std_logic ; 459 crate_reset : OUT std_logic := '0'; 460 crate_reset_ack : IN std_logic ; 461 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') 414 462 ); 415 463 END COMPONENT; … … 514 562 dd_ready => dd_ready_internal, 515 563 dd_addr => dd_addr1, 516 dd_data => dd_data 564 dd_data => dd_data, 565 get_ot_counter => get_ot_counter, 566 get_ot_counter_started => get_ot_counter_started, 567 get_ot_counter_ready => get_ot_counter_ready, 568 on_time_counter => on_time_counter, 569 temp_sensor_ready => temp_sensor_ready, 570 temp_sensor_array => temp_sensor_array 517 571 ); 518 572 U_8 : dram_control … … 580 634 get_header_started => get_header_started, 581 635 get_header_ready => get_header_ready, 636 board_id => board_id, 582 637 trigger_counter_read => trigger_counter_read, 583 638 trigger_counter_valid => trigger_counter_valid, 584 639 trigger_counter => trigger_counter, 640 get_ts_counter => get_ts_counter, 641 get_ts_counter_started => get_ts_counter_started, 642 get_ts_counter_ready => get_ts_counter_ready, 643 timestamp_counter => timestamp_counter, 585 644 header_board_id => header_board_id, 586 645 header_firmware_id => header_firmware_id, 587 646 header_trigger_counter => header_trigger_counter, 588 header_timestamp_counter => header_timestamp_counter 647 header_timestamp_counter => header_timestamp_counter, 648 header_current_state => header_current_state, 649 current_cc_state => current_cc_state 589 650 ); 590 651 U_0 : w5300_modul … … 646 707 header_firmware_id => header_firmware_id, 647 708 header_trigger_counter => header_trigger_counter, 648 header_timestamp_counter => header_timestamp_counter 709 header_timestamp_counter => header_timestamp_counter, 710 header_current_state => header_current_state, 711 start_run => start_run, 712 start_run_ack => start_run_ack, 713 start_run_param => start_run_param, 714 start_run_num_events => start_run_num_events, 715 stop_run => stop_run, 716 stop_run_ack => stop_run_ack, 717 crate_reset => crate_reset, 718 crate_reset_ack => crate_reset_ack, 719 crate_reset_param => crate_reset_param 649 720 ); 650 721 -
firmware/FTM/ethernet/header_modul_beha.vhd
r10366 r10441 12 12 USE ieee.std_logic_arith.all; 13 13 USE IEEE.STD_LOGIC_UNSIGNED.all; 14 --LIBRARY FACT_FTM_lib; 15 --USE FACT_FTM_lib.ftm_array_types.all; 16 --USE FACT_FTM_lib.ftm_constants.all; 14 17 15 library ftm_definitions; 18 16 USE ftm_definitions.ftm_array_types.all; … … 25 23 get_header_started : OUT std_logic := '0'; 26 24 get_header_ready : OUT std_logic := '0'; 25 board_id : IN std_logic_vector (63 DOWNTO 0); 27 26 trigger_counter_read : OUT std_logic := '0'; 28 27 trigger_counter_valid : IN std_logic; 29 28 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0'); 29 get_ts_counter : OUT std_logic := '0'; 30 get_ts_counter_started : IN std_logic; 31 get_ts_counter_ready : IN std_logic; 32 timestamp_counter : IN std_logic_vector (47 DOWNTO 0); 30 33 header_board_id : OUT std_logic_vector (63 DOWNTO 0) := (others => '0'); 31 34 header_firmware_id : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 32 35 header_trigger_counter : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); 33 header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') 36 header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0'); 37 header_current_state : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 38 current_cc_state : IN std_logic_vector (15 DOWNTO 0) 34 39 ); 35 40 END ENTITY header_modul; … … 38 43 ARCHITECTURE beha OF header_modul IS 39 44 40 type state_header_proc_type is (HP_INIT, HP_CONFIG, HP_IDLE, HP_START, HP_TRG_CNT, HP_END); 45 type state_header_proc_type is (HP_INIT, HP_CONFIG, HP_IDLE, HP_START, HP_TRG_CNT, 46 HP_TS_CNT, HP_TS_CNT_END, HP_END); 41 47 42 48 signal state_header_proc : state_header_proc_type := HP_INIT; … … 47 53 if rising_edge (clk) then 48 54 case state_header_proc is 49 50 when HP_INIT =>51 state_header_proc <= HP_CONFIG;52 55 53 when HP_CONFIG => 54 state_header_proc <= HP_IDLE; 56 when HP_INIT => 57 state_header_proc <= HP_CONFIG; 58 59 when HP_CONFIG => 60 state_header_proc <= HP_IDLE; 61 62 when HP_IDLE => 63 if (get_header = '1') then 64 get_header_started <= '1'; 65 get_header_ready <= '0'; 66 state_header_proc <= HP_START; 67 end if; 68 69 when HP_START => 70 header_board_id <= board_id; 71 header_firmware_id <= X"00" & FIRMWARE_ID; 72 header_current_state <= current_cc_state; 73 74 trigger_counter_read <= '1'; 75 state_header_proc <= HP_TRG_CNT; 76 77 when HP_TRG_CNT => 78 trigger_counter_read <= '0'; 79 if (trigger_counter_valid = '1') then 80 header_trigger_counter <= trigger_counter; 81 get_ts_counter <= '1'; 82 state_header_proc <= HP_TS_CNT; 83 end if; 84 85 when HP_TS_CNT => 86 if (get_ts_counter_started = '1') then 87 get_ts_counter <= '0'; 88 state_header_proc <= HP_TS_CNT_END; 89 end if; 90 91 when HP_TS_CNT_END => 92 if (get_ts_counter_ready = '1') then 93 header_timestamp_counter <= timestamp_counter; 94 state_header_proc <= HP_END; 95 end if; 96 97 when HP_END => 98 if (get_header <= '0') then 99 get_header_started <= '0'; 100 get_header_ready <= '1'; 101 state_header_proc <= HP_IDLE; 102 end if; 55 103 56 when HP_IDLE =>57 if (get_header = '1') then58 get_header_started <= '1';59 get_header_ready <= '0';60 state_header_proc <= HP_START;61 end if;62 63 when HP_START =>64 header_board_id <= to_stdlogicvector (DNA_FOR_SIM);65 header_firmware_id <= X"00" & FIRMWARE_ID;66 header_timestamp_counter <= X"333322221111";67 68 trigger_counter_read <= '1';69 state_header_proc <= HP_TRG_CNT;70 71 when HP_TRG_CNT =>72 trigger_counter_read <= '0';73 if (trigger_counter_valid = '1') then74 header_trigger_counter <= trigger_counter;75 state_header_proc <= HP_END;76 end if;77 78 when HP_END =>79 if (get_header <= '0') then80 get_header_started <= '0';81 get_header_ready <= '1';82 state_header_proc <= HP_IDLE;83 end if;84 85 104 end case; 86 105 end if; -
firmware/FTM/ethernet/w5300_modul.vhd
r10366 r10441 18 18 -- 19 19 ---------------------------------------------------------------------------------- 20 20 -- hds interface_start 21 21 LIBRARY IEEE; 22 22 USE IEEE.STD_LOGIC_1164.all; … … 24 24 USE IEEE.STD_LOGIC_UNSIGNED.all; 25 25 26 --LIBRARY FACT_FTM_lib;27 --USE FACT_FTM_lib.ftm_array_types.all;28 --USE FACT_FTM_lib.ftm_constants.all;29 26 library ftm_definitions; 30 27 USE ftm_definitions.ftm_array_types.all; … … 100 97 header_firmware_id : IN std_logic_vector (15 DOWNTO 0); 101 98 header_trigger_counter : IN std_logic_vector (31 DOWNTO 0); 102 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0) 103 99 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0); 100 header_current_state : IN std_logic_vector (15 DOWNTO 0); 101 -- 102 start_run : OUT std_logic := '0'; 103 start_run_ack : IN std_logic; 104 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 105 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); 106 stop_run : OUT std_logic := '0'; 107 stop_run_ack : IN std_logic; 108 crate_reset : OUT std_logic := '0'; 109 crate_reset_ack : IN std_logic; 110 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') 104 111 ); 105 112 … … 113 120 READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL); 114 121 type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, 115 WR_ GET_HEADER, WR_GET_HEADER_WAIT, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01);122 WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL); 116 123 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); 117 124 type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); 118 type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_READ_DD_BLOCK, RD_WRITE_SD_BLOCK, RD_ END);125 type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_READ_DD_BLOCK, RD_WRITE_SD_BLOCK, RD_X_EVNTS,RD_END); 119 126 type state_write_sd_type is (WRITE_SD_START, WRITE_SD_WAIT, WRITE_SD_END); 120 127 type state_read_sd_type is (READ_SD_START, READ_SD_WAIT, READ_SD_END); … … 163 170 164 171 signal next_packet_data_cnt : integer range 0 to 4095 := 0; 165 signal rx_packets_cnt : std_logic_vector (15 downto 0) ;172 signal rx_packets_cnt : std_logic_vector (15 downto 0) := X"0000"; 166 173 signal new_config_flag : std_logic := '0'; 167 174 … … 182 189 signal local_sd_addr : std_logic_vector (11 downto 0); 183 190 signal local_sd_data : std_logic_vector (15 downto 0); 191 192 signal data_package_type : std_logic_vector (15 downto 0) := X"0000"; 193 signal data_package_length : std_logic_vector (15 downto 0) := X"0000"; 184 194 185 195 … … 574 584 when SFE_START => 575 585 next_state <= SEND_FTU_ERROR; 586 data_package_type <= FTM_PACKAGE_TYPE_FTU_ERR; 587 data_package_length <= FTU_ERROR_LENGTH + 1; -- +1 := package end 576 588 read_addr_state <= READ_FTU_ERROR; 577 589 local_sd_addr <= X"000"; … … 626 638 627 639 when RD_END => 640 if (new_config_flag = '1') then 641 new_config_flag <= '0'; 642 next_state <= CONFIG; 643 else 644 next_state <= MAIN; 645 end if; 628 646 if (internal_cmd = '0') then 629 647 par_addr <= W5300_S0_CR; … … 632 650 else 633 651 internal_cmd <= '0'; 634 end if; 635 if (new_config_flag = '1') then 636 new_config_flag <= '0'; 637 next_state <= CONFIG; 638 else 639 next_state <= MAIN; 652 state_init <= MAIN; 640 653 end if; 641 654 … … 670 683 led_int <= NOT led_int; 671 684 state_read_data <= RD_5; 685 686 when CMD_START => 687 case cmd_array (2) is 688 -- start "normal" run 689 when PAR_START_RUN => 690 start_run <= '1'; 691 start_run_param <= cmd_array (2); 692 if (start_run_ack = '1') then 693 start_run <= '0'; 694 state_read_data <= RD_5; 695 end if; 696 -- start run an take X events 697 when PAR_START_X_EVNTS => 698 next_state_read_data <= RD_X_EVNTS; 699 state_read_data <= RD_5; 700 when others => 701 state_read_data <= RD_5; 702 end case; 703 704 when CMD_STOP => 705 stop_run <= '1'; 706 if (stop_run_ack = '1') then 707 stop_run <= '0'; 708 state_read_data <= RD_5; 709 end if; 710 711 when CMD_CRESET => 712 crate_reset <= '1'; 713 crate_reset_param <= cmd_array (2); 714 if (crate_reset_ack = '1') then 715 crate_reset <= '0'; 716 state_read_data <= RD_5; 717 end if; 672 718 673 719 when CMD_WRITE => … … 739 785 when PING_WRITE_LIST => 740 786 state_read_data <= RD_5; 787 data_package_type <= FTM_PACKAGE_TYPE_FTU_LIST; 788 data_package_length <= FL_BLOCK_SIZE + 1; -- +1 := package end 741 789 read_addr_state <= READ_FROM_FL_ADDR; 742 790 local_sd_addr <= X"000"; --start at address 0x000 … … 767 815 when READ_DD_BLOCK_WRITE => 768 816 if (dd_write_general_ready = '1') then 817 data_package_type <= FTM_PACKAGE_TYPE_DD; 818 data_package_length <= DD_BLOCK_SIZE + 1; -- +1 := package end 769 819 read_addr_state <= READ_FROM_DD_ADDR; 770 820 local_sd_addr <= X"000"; -- start at address 0x000 … … 796 846 -- read static data block and write it to ethernet 797 847 when RD_READ_SD_BLOCK => 848 data_package_type <= FTM_PACKAGE_TYPE_SD; 849 data_package_length <= SD_BLOCK_SIZE + 1; -- +1 := package end 798 850 state_read_data <= RD_5; 799 851 read_addr_state <= READ_FROM_SD_ADDR; … … 806 858 -- read from address in static data ram and write data to ethernet 807 859 when RD_READ_SD_ADDR => 860 data_package_type <= FTM_PACKAGE_TYPE_SD_WORD; 861 data_package_length <= SD_SINGLE_WORD_SIZE + 1; -- +1 := package end 808 862 state_read_data <= RD_5; 809 863 read_addr_state <= READ_FROM_SD_ADDR; … … 841 895 state_init <= WRITE_TO_SD_ADDR; 842 896 end if; 897 898 -- read X events 899 when RD_X_EVNTS => 900 if (next_packet_data_cnt = 0) then 901 start_run_num_events (31 downto 16) <= data_read; 902 else 903 start_run_num_events (15 downto 0) <= data_read; 904 start_run_param <= cmd_array (2); 905 start_run <= '1'; 906 if (start_run_ack = '1') then 907 start_run <= '0'; 908 next_packet_data_cnt <= 0; 909 next_state_read_data <= RD_CMD; 910 state_read_data <= RD_5; 911 end if; 912 end if; 843 913 844 914 end case; -- state_read_data … … 860 930 case header_cnt is 861 931 when X"00" => 932 local_sd_data <= data_package_type; 933 when X"01" => 934 local_sd_data <= data_package_length; 935 when X"02" => 936 local_sd_data <= header_current_state; 937 when X"03" => 862 938 local_sd_data <= header_board_id (63 DOWNTO 48); 863 when X"0 1" =>939 when X"04" => 864 940 local_sd_data <= header_board_id (47 DOWNTO 32); 865 when X"0 2" =>941 when X"05" => 866 942 local_sd_data <= header_board_id (31 DOWNTO 16); 867 when X"0 3" =>943 when X"06" => 868 944 local_sd_data <= header_board_id (15 DOWNTO 0); 869 when X"0 4" =>945 when X"07" => 870 946 local_sd_data <= header_firmware_id; 871 when X"0 5" =>947 when X"08" => 872 948 local_sd_data <= header_trigger_counter (31 DOWNTO 16); 873 when X"0 6" =>949 when X"09" => 874 950 local_sd_data <= header_trigger_counter (15 DOWNTO 0); 875 when X"07" => 951 when X"0A" => 952 local_sd_data <= X"0000"; 953 when X"0B" => 876 954 local_sd_data <= header_timestamp_counter (47 DOWNTO 32); 877 when X"0 8" =>955 when X"0C" => 878 956 local_sd_data <= header_timestamp_counter (31 DOWNTO 16); 879 when X"0 9" =>957 when X"0D" => 880 958 local_sd_data <= header_timestamp_counter (15 DOWNTO 0); 881 when X"0A" =>882 local_sd_data <= X"FFFF"; -- spare883 959 when others => 884 960 null; … … 981 1057 local_socket_nr <= "000"; 982 1058 next_state_tmp <= next_state; 983 write_length_bytes <= (FTM_HEADER_LENGTH + local_write_length (15 downto 0)) & '0'; -- shift left (*2) 1059 -- Write Length: 2 := START and END of package 1060 write_length_bytes <= (2 + FTM_HEADER_LENGTH + local_write_length (15 downto 0)) & '0'; -- shift left (*2) 984 1061 data_cnt <= 0; 985 1062 header_cnt <= X"00"; … … 1004 1081 state_write <= WR_01; 1005 1082 else 1006 state_write <= WR_GET_HEADER; 1007 end if; 1083 state_write <= WR_WRITE_START_DEL; 1084 end if; 1085 1086 -- write package start delimiter 1087 when WR_WRITE_START_DEL => 1088 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1089 par_data <= FTM_PACKAGE_START; 1090 state_init <= WRITE_REG; 1091 next_state <= WRITE_DATA; 1092 state_write <= WR_GET_HEADER; 1008 1093 1009 1094 -- get header data … … 1053 1138 state_write <= WR_FIFO_DATA; 1054 1139 else 1055 state_write <= WR_05; 1056 end if; 1140 state_write <= WR_WRITE_END_DEL; 1141 end if; 1142 1143 -- write package end delimiter 1144 when WR_WRITE_END_DEL => 1145 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1146 par_data <= FTM_PACKAGE_END; 1147 state_init <= WRITE_REG; 1148 next_state <= WRITE_DATA; 1149 state_write <= WR_05; 1057 1150 1058 1151 -- Send FIFO … … 1137 1230 1138 1231 end Behavioral; 1232 -
firmware/FTM/ftm_definitions.vhd
r10418 r10441 35 35 -- 36 36 ---kw 11.04.: added SD_ADDR_ftu_prescaling_0 37 -- 38 -- modified: Quirin Weitzel, April 20 2011 39 -- next merger with library file from dortmund (changes below) 40 -- kw 14.04.: added sensor_array_type (temperature sensors) 41 -- changed CMD_AUTOSEND to X"0040" 42 -- added "start run / take X events", "stop run", "crate reset" 43 -- kw 18.04.: removed PAR_READ_DD_ADDR, changed PAR_WRITE_SD_ADDR to 0x0004 44 -- added FTM_PACKAGE_START and FTM_PACKAGE_END 45 -- increased DD_BLOCK_SIZE and DD_BLOCK_SIZE_GENERAL by 1 (64 bit on-time counter) 46 -- changed FTM_HEADER_LENGTH to 0x0E 47 -- kw 20.04.: added "package types", SD_SINGLE_WORD_SIZE 37 48 -- 38 49 ---------------------------------------------------------------------------------- … … 196 207 -- only for debugging: data_block (0) = ADDR 197 208 constant PAR_READ_SD_ADDR : std_logic_vector := X"0004"; -- read from address in static data block 198 constant PAR_READ_DD_ADDR : std_logic_vector := X"0008"; -- read from address in dynamic data block199 209 constant CMD_WRITE : std_logic_vector := X"0002"; 200 210 constant PAR_WRITE_SD : std_logic_vector := X"0001"; -- write static data block 201 211 -- only for debugging: data_block (0) = ADDR, data_block (1) = DATA 202 constant PAR_WRITE_SD_ADDR : std_logic_vector := X"000 2"; -- write to address in static data ram212 constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0004"; -- write to address in static data ram 203 213 -- ping all FTUs 204 214 constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs 205 215 -- turn automatic sending of dd-block and ftu-error-list on or off 206 constant CMD_AUTOSEND : std_logic_vector := X"00 20";216 constant CMD_AUTOSEND : std_logic_vector := X"0040"; 207 217 constant PAR_AUTOSEND_EA : std_logic_vector := X"0001"; -- enable automatic sending 208 218 constant PAR_AUTOSEND_DA : std_logic_vector := X"0000"; -- disable automatic sending 209 219 220 -- start run / take X events 221 constant CMD_START : std_logic_vector := X"0004"; 222 constant PAR_START_RUN : std_logic_vector := X"0001"; 223 constant PAR_START_X_EVNTS : std_logic_vector := X"0002"; 224 225 -- stop run 226 constant CMD_STOP : std_logic_vector := X"0008"; 227 228 -- crate reset 229 constant CMD_CRESET : std_logic_vector := X"0020"; 230 231 -- start and end of package 232 constant FTM_PACKAGE_START : std_logic_vector := X"FB01"; 233 constant FTM_PACKAGE_END : std_logic_vector := X"04FE"; 234 235 -- package types 236 constant FTM_PACKAGE_TYPE_SD : std_logic_vector := X"0001"; 237 constant FTM_PACKAGE_TYPE_DD : std_logic_vector := X"0002"; 238 constant FTM_PACKAGE_TYPE_FTU_LIST : std_logic_vector := X"0003"; 239 constant FTM_PACKAGE_TYPE_FTU_ERR : std_logic_vector := X"0004"; 240 constant FTM_PACKAGE_TYPE_SD_WORD : std_logic_vector := X"0005"; 241 242 -- state types 243 constant FTM_STATE_IDLE : std_logic_vector := X"0001"; 244 constant FTM_STATE_CFG : std_logic_vector := X"0002"; 245 constant FTM_STATE_RUN : std_logic_vector := X"0003"; 246 constant FTM_STATE_CALIB : std_logic_vector := X"0004"; 247 210 248 -- header length of data packages 211 constant FTM_HEADER_LENGTH : std_logic_vector (7 DOWNTO 0) := X"0 B";249 constant FTM_HEADER_LENGTH : std_logic_vector (7 DOWNTO 0) := X"0E"; 212 250 213 251 -- FTU error message … … 232 270 constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3) 233 271 constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block 272 constant SD_SINGLE_WORD_SIZE : std_logic_vector := X"001"; 234 273 235 274 -- dynamic data block 236 --constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"010"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block 237 constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E7"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block 238 constant DD_BLOCK_SIZE_GENERAL : integer := 7; -- dynamic block size without FTU data 275 constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E8"; -- 8 + (40 * 12) = 0x1E8 --total size of dynamic data block 276 constant DD_BLOCK_SIZE_GENERAL : integer := 8; -- dynamic block size without FTU data 239 277 constant DYNAMIC_RAM_ADDR_WIDTH : integer := 12; 240 278
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