Changeset 260 for FPGA/FAD/stable
- Timestamp:
- 07/22/10 10:33:08 (14 years ago)
- Location:
- FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib
- Files:
-
- 11 edited
-
hdl/fad_board_struct.vhd (modified) (2 diffs)
-
hdl/fad_definitions.vhd (modified) (1 diff)
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hdl/fad_definitions.vhd.bak (modified) (2 diffs)
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hdl/fad_main_struct.vhd (modified) (7 diffs)
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hdl/w5300_modul.vhd (modified) (2 diffs)
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hdl/w5300_modul.vhd.bak (modified) (8 diffs)
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hds/.cache.dat (modified) ( previous)
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hds/.xrf/fad_main_struct.xrf (modified) (1 diff)
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hds/@f@a@d_main/struct.bd (modified) (550 diffs)
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hds/@f@a@d_main/struct.bd.bak (modified) (399 diffs)
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hds/w5300_modul/symbol.sb (modified) (109 diffs)
Legend:
- Unmodified
- Added
- Removed
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FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd
r252 r260 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 5:25:14 14.07.20105 -- at - 11:40:21 21.07.2010 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 73 73 -- Created: 74 74 -- by - dneise.UNKNOWN (E5B-LABOR6) 75 -- at - 1 5:25:14 14.07.201075 -- at - 11:40:21 21.07.2010 76 76 -- 77 77 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd
r252 r260 124 124 constant CMD_DWRITE_RUN : std_logic_vector := X"08"; 125 125 constant CMD_DWRITE_STOP : std_logic_vector := X"09"; 126 constant CMD_SCLK_ON : std_logic_vector := X"10"; 127 constant CMD_SCLK_OFF : std_logic_vector := X"11"; 128 129 126 130 -- Declare functions and procedure 127 131 -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd.bak
r252 r260 105 105 --constant DEFAULT_DAC : dac_array_type := (others => 0); 106 106 107 constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= X"0";107 constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= "0000"; 108 108 constant DEFAULT_DRSADDR_MODE : std_logic := '0'; 109 109 … … 124 124 constant CMD_DWRITE_RUN : std_logic_vector := X"08"; 125 125 constant CMD_DWRITE_STOP : std_logic_vector := X"09"; 126 constant CMD_SCLK_ON : std_logic_vector := X"10"; 127 constant CMD_SCLK_ON : std_logic_vector := X"11"; 128 129 126 130 -- Declare functions and procedure 127 131 -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd
r252 r260 2 2 -- 3 3 -- Created: 4 -- by - dneise.UNKNOWN ( TU-CC4900F8C7D2)5 -- at - 1 4:46:38 12.07.20104 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 11:40:17 21.07.2010 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 59 59 -- 60 60 -- Created: 61 -- by - dneise.UNKNOWN ( TU-CC4900F8C7D2)62 -- at - 1 4:46:38 12.07.201061 -- by - dneise.UNKNOWN (E5B-LABOR6) 62 -- at - 11:40:18 21.07.2010 63 63 -- 64 64 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 125 125 SIGNAL roi_max : roi_max_type; 126 126 SIGNAL s_trigger : std_logic := '0'; 127 SIGNAL sclk1 : std_logic; 128 SIGNAL sclk_enable : std_logic; 127 129 SIGNAL sensor_array : sensor_array_type; 128 130 SIGNAL sensor_ready : std_logic; … … 332 334 config_busy : IN std_logic ; 333 335 denable : OUT std_logic := '0'; -- default domino wave off 334 dwrite_enable : OUT std_logic := '0' -- default DWRITE low. 336 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. 337 sclk_enable : OUT std_logic := '1' -- default DWRITE HIGH. 335 338 ); 336 339 END COMPONENT; … … 355 358 -- ModuleWare code(v1.9) for instance 'I5' of 'and' 356 359 drs_dwrite <= dwrite AND dwrite_enable; 360 361 -- ModuleWare code(v1.9) for instance 'U_1' of 'and' 362 sclk <= sclk_enable AND sclk1; 357 363 358 364 -- ModuleWare code(v1.9) for instance 'U_0' of 'mux' … … 502 508 dac_cs => dac_cs, 503 509 mosi => mosi, 504 sclk => sclk ,510 sclk => sclk1, 505 511 sensor_array => sensor_array, 506 512 sensor_cs => sensor_cs, … … 547 553 config_busy => config_busy, 548 554 denable => denable, 549 dwrite_enable => dwrite_enable 555 dwrite_enable => dwrite_enable, 556 sclk_enable => sclk_enable 550 557 ); 551 558 -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd
r246 r260 65 65 66 66 denable : out std_logic := '0'; -- default domino wave off 67 dwrite_enable : out std_logic := '0' -- default DWRITE low. 67 dwrite_enable : out std_logic := '0'; -- default DWRITE low. 68 sclk_enable : out std_logic := '1' -- default DWRITE HIGH. 68 69 ); 69 70 … … 521 522 when CMD_DWRITE_STOP => 522 523 dwrite_enable <= '0'; 524 state_read_data <= RD_WAIT; 525 when CMD_SCLK_ON => 526 sclk_enable <= '1'; 527 state_read_data <= RD_WAIT; 528 when CMD_SCLK_OFF => 529 sclk_enable <= '0'; 523 530 state_read_data <= RD_WAIT; 524 531 when CMD_DENABLE => -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd.bak
r246 r260 49 49 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 50 50 data_valid : IN std_logic; 51 data_valid_ack : OUT std_logic := '0'; 51 52 busy : OUT std_logic := '1'; 52 53 write_header_flag, write_end_flag : IN std_logic; … … 64 65 65 66 denable : out std_logic := '0'; -- default domino wave off 66 dwrite_enable : out std_logic := '0' -- default DWRITE low. 67 dwrite_enable : out std_logic := '0'; -- default DWRITE low. 68 sclk_enable : out std_logic := '1' -- default DWRITE HIGH. 67 69 ); 68 70 … … 74 76 75 77 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, 76 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, 78 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 77 79 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA); 78 80 type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, … … 349 351 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8); 350 352 state_init <= WRITE_REG; 353 next_state <= TIMEOUT; 354 when TIMEOUT => 355 par_addr <= W5300_RTR; 356 par_data <= X"07D0"; -- 0x07D0 = 200ms 357 state_init <= WRITE_REG; 358 next_state <= RETRY; 359 when RETRY => 360 par_addr <= W5300_RCR; 361 par_data <= X"0008"; 362 state_init <= WRITE_REG; 351 363 next_state <= SI; 352 364 … … 431 443 s_trigger <= '0'; 432 444 end if; 433 if (chk_recv_cntr = 10 ) then445 if (chk_recv_cntr = 1000) then 434 446 chk_recv_cntr <= 0; 435 447 state_read_data <= RD_1; … … 437 449 busy <= '1'; 438 450 else 451 busy <= '0'; 452 data_valid_ack <= '0'; 439 453 chk_recv_cntr <= chk_recv_cntr + 1; 440 454 if (data_valid = '1') then 455 data_valid_ack <= '1'; 441 456 local_write_length <= write_length; 442 457 local_ram_start_addr <= ram_start_addr; … … 552 567 next_state <= CONFIG; 553 568 else 554 569 -- busy <= '0'; 555 570 next_state <= MAIN; 556 571 end if; … … 726 741 state_write <= WR_08; 727 742 when others => 728 743 -- busy <= '0'; 729 744 state_init <= next_state_tmp; 730 745 state_write <= WR_START; -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf
r252 r260 244 244 DESIGN @f@a@d_main 245 245 VIEW struct.bd 246 GRAPHIC 5478,0 126 0 247 DESIGN @f@a@d_main 248 VIEW struct.bd 249 GRAPHIC 5472,0 127 0 250 DESIGN @f@a@d_main 251 VIEW struct.bd 252 GRAPHIC 1981,0 128 0 253 DESIGN @f@a@d_main 254 VIEW struct.bd 255 GRAPHIC 8414,0 129 0 256 DESIGN @f@a@d_main 257 VIEW struct.bd 258 GRAPHIC 2468,0 130 0 259 DESIGN @f@a@d_main 260 VIEW struct.bd 261 GRAPHIC 2492,0 131 0 262 DESIGN @f@a@d_main 263 VIEW struct.bd 264 GRAPHIC 2486,0 132 0 265 DESIGN @f@a@d_main 266 VIEW struct.bd 267 GRAPHIC 2474,0 133 0 268 DESIGN @f@a@d_main 269 VIEW struct.bd 270 GRAPHIC 2498,0 134 0 271 DESIGN @f@a@d_main 272 VIEW struct.bd 273 GRAPHIC 2504,0 135 0 274 DESIGN @f@a@d_main 275 VIEW struct.bd 276 GRAPHIC 2480,0 136 0 277 DESIGN @f@a@d_main 278 VIEW struct.bd 279 GRAPHIC 320,0 137 0 280 DESIGN @f@a@d_main 281 VIEW struct.bd 282 NO_GRAPHIC 138 283 DESIGN @f@a@d_main 284 VIEW struct.bd 285 GRAPHIC 6276,0 140 0 286 DESIGN @f@a@d_main 287 VIEW struct.bd 288 GRAPHIC 3888,0 141 0 289 DESIGN @f@a@d_main 290 VIEW struct.bd 291 NO_GRAPHIC 143 246 GRAPHIC 8730,0 126 0 247 DESIGN @f@a@d_main 248 VIEW struct.bd 249 GRAPHIC 8746,0 127 0 250 DESIGN @f@a@d_main 251 VIEW struct.bd 252 GRAPHIC 5478,0 128 0 253 DESIGN @f@a@d_main 254 VIEW struct.bd 255 GRAPHIC 5472,0 129 0 256 DESIGN @f@a@d_main 257 VIEW struct.bd 258 GRAPHIC 1981,0 130 0 259 DESIGN @f@a@d_main 260 VIEW struct.bd 261 GRAPHIC 8414,0 131 0 262 DESIGN @f@a@d_main 263 VIEW struct.bd 264 GRAPHIC 2468,0 132 0 265 DESIGN @f@a@d_main 266 VIEW struct.bd 267 GRAPHIC 2492,0 133 0 268 DESIGN @f@a@d_main 269 VIEW struct.bd 270 GRAPHIC 2486,0 134 0 271 DESIGN @f@a@d_main 272 VIEW struct.bd 273 GRAPHIC 2474,0 135 0 274 DESIGN @f@a@d_main 275 VIEW struct.bd 276 GRAPHIC 2498,0 136 0 277 DESIGN @f@a@d_main 278 VIEW struct.bd 279 GRAPHIC 2504,0 137 0 280 DESIGN @f@a@d_main 281 VIEW struct.bd 282 GRAPHIC 2480,0 138 0 283 DESIGN @f@a@d_main 284 VIEW struct.bd 285 GRAPHIC 320,0 139 0 286 DESIGN @f@a@d_main 287 VIEW struct.bd 288 NO_GRAPHIC 140 289 DESIGN @f@a@d_main 290 VIEW struct.bd 291 GRAPHIC 6276,0 142 0 292 DESIGN @f@a@d_main 293 VIEW struct.bd 294 GRAPHIC 3888,0 143 0 295 DESIGN @f@a@d_main 296 VIEW struct.bd 297 NO_GRAPHIC 145 292 298 LIBRARY FACT_FAD_lib 293 299 DESIGN adc_buffer 294 300 VIEW beha 295 GRAPHIC 5678,0 14 50296 DESIGN @f@a@d_main 297 VIEW struct.bd 298 NO_GRAPHIC 15 2299 DESIGN @f@a@d_main 300 VIEW struct.bd 301 GRAPHIC 4194,0 15 40301 GRAPHIC 5678,0 147 0 302 DESIGN @f@a@d_main 303 VIEW struct.bd 304 NO_GRAPHIC 154 305 DESIGN @f@a@d_main 306 VIEW struct.bd 307 GRAPHIC 4194,0 156 0 302 308 DESIGN clock_generator 303 309 VIEW symbol.sb 304 GRAPHIC 168,0 15 60310 GRAPHIC 168,0 158 0 305 311 DESIGN clock_generator 306 312 VIEW symbol.sb 307 GRAPHIC 126,0 15 70313 GRAPHIC 126,0 159 0 308 314 DESIGN clock_generator 309 315 VIEW symbol.sb 310 GRAPHIC 131,0 1 580316 GRAPHIC 131,0 160 0 311 317 DESIGN clock_generator 312 318 VIEW symbol.sb 313 GRAPHIC 121,0 1 590314 DESIGN @f@a@d_main 315 VIEW struct.bd 316 GRAPHIC 5072,0 16 20317 DESIGN control_unit 318 VIEW symbol.sb 319 GRAPHIC 130,0 16 40320 DESIGN control_unit 321 VIEW symbol.sb 322 GRAPHIC 135,0 16 50323 DESIGN control_unit 324 VIEW symbol.sb 325 GRAPHIC 170,0 16 60326 DESIGN control_unit 327 VIEW symbol.sb 328 GRAPHIC 175,0 16 70329 DESIGN control_unit 330 VIEW symbol.sb 331 GRAPHIC 160,0 1 680332 DESIGN control_unit 333 VIEW symbol.sb 334 GRAPHIC 145,0 1 690335 DESIGN control_unit 336 VIEW symbol.sb 337 GRAPHIC 140,0 17 00338 DESIGN control_unit 339 VIEW symbol.sb 340 GRAPHIC 180,0 17 10341 DESIGN control_unit 342 VIEW symbol.sb 343 GRAPHIC 350,0 17 20344 DESIGN control_unit 345 VIEW symbol.sb 346 GRAPHIC 165,0 17 30347 DESIGN control_unit 348 VIEW symbol.sb 349 GRAPHIC 521,0 17 40350 DESIGN control_unit 351 VIEW symbol.sb 352 GRAPHIC 526,0 17 50353 DESIGN control_unit 354 VIEW symbol.sb 355 GRAPHIC 155,0 17 60356 DESIGN control_unit 357 VIEW symbol.sb 358 GRAPHIC 150,0 17 70359 DESIGN @f@a@d_main 360 VIEW struct.bd 361 GRAPHIC 8277,0 18 00319 GRAPHIC 121,0 161 0 320 DESIGN @f@a@d_main 321 VIEW struct.bd 322 GRAPHIC 5072,0 164 0 323 DESIGN control_unit 324 VIEW symbol.sb 325 GRAPHIC 130,0 166 0 326 DESIGN control_unit 327 VIEW symbol.sb 328 GRAPHIC 135,0 167 0 329 DESIGN control_unit 330 VIEW symbol.sb 331 GRAPHIC 170,0 168 0 332 DESIGN control_unit 333 VIEW symbol.sb 334 GRAPHIC 175,0 169 0 335 DESIGN control_unit 336 VIEW symbol.sb 337 GRAPHIC 160,0 170 0 338 DESIGN control_unit 339 VIEW symbol.sb 340 GRAPHIC 145,0 171 0 341 DESIGN control_unit 342 VIEW symbol.sb 343 GRAPHIC 140,0 172 0 344 DESIGN control_unit 345 VIEW symbol.sb 346 GRAPHIC 180,0 173 0 347 DESIGN control_unit 348 VIEW symbol.sb 349 GRAPHIC 350,0 174 0 350 DESIGN control_unit 351 VIEW symbol.sb 352 GRAPHIC 165,0 175 0 353 DESIGN control_unit 354 VIEW symbol.sb 355 GRAPHIC 521,0 176 0 356 DESIGN control_unit 357 VIEW symbol.sb 358 GRAPHIC 526,0 177 0 359 DESIGN control_unit 360 VIEW symbol.sb 361 GRAPHIC 155,0 178 0 362 DESIGN control_unit 363 VIEW symbol.sb 364 GRAPHIC 150,0 179 0 365 DESIGN @f@a@d_main 366 VIEW struct.bd 367 GRAPHIC 8277,0 182 0 362 368 DESIGN data@r@a@m_64b_16b_width14_5 363 369 VIEW data@r@a@m_64b_16b_width14_5_a 364 GRAPHIC 48,0 18 20370 GRAPHIC 48,0 184 0 365 371 DESIGN data@r@a@m_64b_16b_width14_5 366 372 VIEW data@r@a@m_64b_16b_width14_5_a 367 GRAPHIC 53,0 18 30373 GRAPHIC 53,0 185 0 368 374 DESIGN data@r@a@m_64b_16b_width14_5 369 375 VIEW data@r@a@m_64b_16b_width14_5_a 370 GRAPHIC 58,0 18 40376 GRAPHIC 58,0 186 0 371 377 DESIGN data@r@a@m_64b_16b_width14_5 372 378 VIEW data@r@a@m_64b_16b_width14_5_a 373 GRAPHIC 63,0 18 50379 GRAPHIC 63,0 187 0 374 380 DESIGN data@r@a@m_64b_16b_width14_5 375 381 VIEW data@r@a@m_64b_16b_width14_5_a 376 GRAPHIC 68,0 18 60382 GRAPHIC 68,0 188 0 377 383 DESIGN data@r@a@m_64b_16b_width14_5 378 384 VIEW data@r@a@m_64b_16b_width14_5_a 379 GRAPHIC 73,0 18 70385 GRAPHIC 73,0 189 0 380 386 DESIGN data@r@a@m_64b_16b_width14_5 381 387 VIEW data@r@a@m_64b_16b_width14_5_a 382 GRAPHIC 78,0 1 880383 DESIGN @f@a@d_main 384 VIEW struct.bd 385 GRAPHIC 1399,0 19 10386 DESIGN data_generator 387 VIEW symbol.sb 388 GRAPHIC 14,0 19 21389 DESIGN data_generator 390 VIEW @behavioral 391 GRAPHIC 48,0 19 60392 DESIGN data_generator 393 VIEW @behavioral 394 GRAPHIC 53,0 19 70395 DESIGN data_generator 396 VIEW @behavioral 397 GRAPHIC 58,0 1980398 DESIGN data_generator 399 VIEW @behavioral 400 GRAPHIC 73,0 1990401 DESIGN data_generator 402 VIEW @behavioral 403 GRAPHIC 78,0 20 00404 DESIGN data_generator 405 VIEW @behavioral 406 GRAPHIC 402,0 20 10407 DESIGN data_generator 408 VIEW @behavioral 409 GRAPHIC 407,0 20 20410 DESIGN data_generator 411 VIEW @behavioral 412 GRAPHIC 1122,0 20 30413 DESIGN data_generator 414 VIEW @behavioral 415 GRAPHIC 963,0 20 40416 DESIGN data_generator 417 VIEW @behavioral 418 GRAPHIC 1127,0 20 50419 DESIGN data_generator 420 VIEW @behavioral 421 GRAPHIC 1048,0 20 60422 DESIGN data_generator 423 VIEW @behavioral 424 GRAPHIC 958,0 20 70425 DESIGN data_generator 426 VIEW @behavioral 427 GRAPHIC 1053,0 2 080428 DESIGN data_generator 429 VIEW @behavioral 430 GRAPHIC 1201,0 2 090431 DESIGN data_generator 432 VIEW @behavioral 433 GRAPHIC 1196,0 21 00434 DESIGN data_generator 435 VIEW @behavioral 436 GRAPHIC 1206,0 21 10437 DESIGN data_generator 438 VIEW @behavioral 439 GRAPHIC 473,0 21 20440 DESIGN data_generator 441 VIEW @behavioral 442 GRAPHIC 412,0 21 30443 DESIGN data_generator 444 VIEW @behavioral 445 GRAPHIC 1085,0 21 40446 DESIGN data_generator 447 VIEW @behavioral 448 GRAPHIC 1090,0 21 50449 DESIGN data_generator 450 VIEW @behavioral 451 GRAPHIC 1240,0 21 60452 DESIGN data_generator 453 VIEW @behavioral 454 GRAPHIC 526,0 21 70455 DESIGN data_generator 456 VIEW @behavioral 457 GRAPHIC 88,0 2 180458 DESIGN data_generator 459 VIEW @behavioral 460 GRAPHIC 285,0 2 190461 DESIGN data_generator 462 VIEW @behavioral 463 GRAPHIC 93,0 22 00464 DESIGN data_generator 465 VIEW @behavioral 466 GRAPHIC 98,0 22 10467 DESIGN data_generator 468 VIEW @behavioral 469 GRAPHIC 1018,0 22 20470 DESIGN data_generator 471 VIEW @behavioral 472 GRAPHIC 1164,0 22 30473 DESIGN data_generator 474 VIEW @behavioral 475 GRAPHIC 1159,0 22 40476 DESIGN data_generator 477 VIEW @behavioral 478 GRAPHIC 898,0 22 50479 DESIGN data_generator 480 VIEW @behavioral 481 GRAPHIC 637,0 22 60482 DESIGN data_generator 483 VIEW @behavioral 484 GRAPHIC 642,0 22 70485 DESIGN data_generator 486 VIEW @behavioral 487 GRAPHIC 676,0 2 280488 DESIGN data_generator 489 VIEW @behavioral 490 GRAPHIC 845,0 2 290491 DESIGN data_generator 492 VIEW @behavioral 493 GRAPHIC 681,0 23 00494 DESIGN data_generator 495 VIEW @behavioral 496 GRAPHIC 801,0 23 10497 DESIGN data_generator 498 VIEW @behavioral 499 GRAPHIC 806,0 23 20500 DESIGN data_generator 501 VIEW @behavioral 502 GRAPHIC 811,0 23 30503 DESIGN @f@a@d_main 504 VIEW struct.bd 505 GRAPHIC 4903,0 23 60506 DESIGN @f@a@d_main 507 VIEW struct.bd 508 NO_GRAPHIC 2 49509 DESIGN @f@a@d_main 510 VIEW struct.bd 511 GRAPHIC 2311,0 25 10512 DESIGN memory_manager 513 VIEW symbol.sb 514 GRAPHIC 14,0 25 21515 DESIGN memory_manager 516 VIEW beha 517 GRAPHIC 138,0 25 70518 DESIGN memory_manager 519 VIEW beha 520 GRAPHIC 194,0 2 580521 DESIGN memory_manager 522 VIEW beha 523 GRAPHIC 349,0 2 590524 DESIGN memory_manager 525 VIEW beha 526 GRAPHIC 569,0 26 00527 DESIGN memory_manager 528 VIEW beha 529 GRAPHIC 224,0 26 10530 DESIGN memory_manager 531 VIEW beha 532 GRAPHIC 254,0 26 20533 DESIGN memory_manager 534 VIEW beha 535 GRAPHIC 804,0 26 30536 DESIGN memory_manager 537 VIEW beha 538 GRAPHIC 433,0 26 40539 DESIGN memory_manager 540 VIEW beha 541 GRAPHIC 622,0 26 50542 DESIGN memory_manager 543 VIEW beha 544 GRAPHIC 289,0 26 60545 DESIGN memory_manager 546 VIEW beha 547 GRAPHIC 309,0 26 70548 DESIGN memory_manager 549 VIEW beha 550 GRAPHIC 284,0 2 680551 DESIGN memory_manager 552 VIEW beha 553 GRAPHIC 294,0 2 690554 DESIGN memory_manager 555 VIEW beha 556 GRAPHIC 304,0 27 00557 DESIGN memory_manager 558 VIEW beha 559 GRAPHIC 299,0 27 10560 DESIGN memory_manager 561 VIEW beha 562 GRAPHIC 379,0 27 20563 DESIGN memory_manager 564 VIEW beha 565 GRAPHIC 915,0 27 30566 DESIGN memory_manager 567 VIEW beha 568 GRAPHIC 51,0 27 40569 DESIGN @f@a@d_main 570 VIEW struct.bd 571 GRAPHIC 5793,0 27 70388 GRAPHIC 78,0 190 0 389 DESIGN @f@a@d_main 390 VIEW struct.bd 391 GRAPHIC 1399,0 193 0 392 DESIGN data_generator 393 VIEW symbol.sb 394 GRAPHIC 14,0 194 1 395 DESIGN data_generator 396 VIEW @behavioral 397 GRAPHIC 48,0 198 0 398 DESIGN data_generator 399 VIEW @behavioral 400 GRAPHIC 53,0 199 0 401 DESIGN data_generator 402 VIEW @behavioral 403 GRAPHIC 58,0 200 0 404 DESIGN data_generator 405 VIEW @behavioral 406 GRAPHIC 73,0 201 0 407 DESIGN data_generator 408 VIEW @behavioral 409 GRAPHIC 78,0 202 0 410 DESIGN data_generator 411 VIEW @behavioral 412 GRAPHIC 402,0 203 0 413 DESIGN data_generator 414 VIEW @behavioral 415 GRAPHIC 407,0 204 0 416 DESIGN data_generator 417 VIEW @behavioral 418 GRAPHIC 1122,0 205 0 419 DESIGN data_generator 420 VIEW @behavioral 421 GRAPHIC 963,0 206 0 422 DESIGN data_generator 423 VIEW @behavioral 424 GRAPHIC 1127,0 207 0 425 DESIGN data_generator 426 VIEW @behavioral 427 GRAPHIC 1048,0 208 0 428 DESIGN data_generator 429 VIEW @behavioral 430 GRAPHIC 958,0 209 0 431 DESIGN data_generator 432 VIEW @behavioral 433 GRAPHIC 1053,0 210 0 434 DESIGN data_generator 435 VIEW @behavioral 436 GRAPHIC 1201,0 211 0 437 DESIGN data_generator 438 VIEW @behavioral 439 GRAPHIC 1196,0 212 0 440 DESIGN data_generator 441 VIEW @behavioral 442 GRAPHIC 1206,0 213 0 443 DESIGN data_generator 444 VIEW @behavioral 445 GRAPHIC 473,0 214 0 446 DESIGN data_generator 447 VIEW @behavioral 448 GRAPHIC 412,0 215 0 449 DESIGN data_generator 450 VIEW @behavioral 451 GRAPHIC 1085,0 216 0 452 DESIGN data_generator 453 VIEW @behavioral 454 GRAPHIC 1090,0 217 0 455 DESIGN data_generator 456 VIEW @behavioral 457 GRAPHIC 1240,0 218 0 458 DESIGN data_generator 459 VIEW @behavioral 460 GRAPHIC 526,0 219 0 461 DESIGN data_generator 462 VIEW @behavioral 463 GRAPHIC 88,0 220 0 464 DESIGN data_generator 465 VIEW @behavioral 466 GRAPHIC 285,0 221 0 467 DESIGN data_generator 468 VIEW @behavioral 469 GRAPHIC 93,0 222 0 470 DESIGN data_generator 471 VIEW @behavioral 472 GRAPHIC 98,0 223 0 473 DESIGN data_generator 474 VIEW @behavioral 475 GRAPHIC 1018,0 224 0 476 DESIGN data_generator 477 VIEW @behavioral 478 GRAPHIC 1164,0 225 0 479 DESIGN data_generator 480 VIEW @behavioral 481 GRAPHIC 1159,0 226 0 482 DESIGN data_generator 483 VIEW @behavioral 484 GRAPHIC 898,0 227 0 485 DESIGN data_generator 486 VIEW @behavioral 487 GRAPHIC 637,0 228 0 488 DESIGN data_generator 489 VIEW @behavioral 490 GRAPHIC 642,0 229 0 491 DESIGN data_generator 492 VIEW @behavioral 493 GRAPHIC 676,0 230 0 494 DESIGN data_generator 495 VIEW @behavioral 496 GRAPHIC 845,0 231 0 497 DESIGN data_generator 498 VIEW @behavioral 499 GRAPHIC 681,0 232 0 500 DESIGN data_generator 501 VIEW @behavioral 502 GRAPHIC 801,0 233 0 503 DESIGN data_generator 504 VIEW @behavioral 505 GRAPHIC 806,0 234 0 506 DESIGN data_generator 507 VIEW @behavioral 508 GRAPHIC 811,0 235 0 509 DESIGN @f@a@d_main 510 VIEW struct.bd 511 GRAPHIC 4903,0 238 0 512 DESIGN @f@a@d_main 513 VIEW struct.bd 514 NO_GRAPHIC 251 515 DESIGN @f@a@d_main 516 VIEW struct.bd 517 GRAPHIC 2311,0 253 0 518 DESIGN memory_manager 519 VIEW symbol.sb 520 GRAPHIC 14,0 254 1 521 DESIGN memory_manager 522 VIEW beha 523 GRAPHIC 138,0 259 0 524 DESIGN memory_manager 525 VIEW beha 526 GRAPHIC 194,0 260 0 527 DESIGN memory_manager 528 VIEW beha 529 GRAPHIC 349,0 261 0 530 DESIGN memory_manager 531 VIEW beha 532 GRAPHIC 569,0 262 0 533 DESIGN memory_manager 534 VIEW beha 535 GRAPHIC 224,0 263 0 536 DESIGN memory_manager 537 VIEW beha 538 GRAPHIC 254,0 264 0 539 DESIGN memory_manager 540 VIEW beha 541 GRAPHIC 804,0 265 0 542 DESIGN memory_manager 543 VIEW beha 544 GRAPHIC 433,0 266 0 545 DESIGN memory_manager 546 VIEW beha 547 GRAPHIC 622,0 267 0 548 DESIGN memory_manager 549 VIEW beha 550 GRAPHIC 289,0 268 0 551 DESIGN memory_manager 552 VIEW beha 553 GRAPHIC 309,0 269 0 554 DESIGN memory_manager 555 VIEW beha 556 GRAPHIC 284,0 270 0 557 DESIGN memory_manager 558 VIEW beha 559 GRAPHIC 294,0 271 0 560 DESIGN memory_manager 561 VIEW beha 562 GRAPHIC 304,0 272 0 563 DESIGN memory_manager 564 VIEW beha 565 GRAPHIC 299,0 273 0 566 DESIGN memory_manager 567 VIEW beha 568 GRAPHIC 379,0 274 0 569 DESIGN memory_manager 570 VIEW beha 571 GRAPHIC 915,0 275 0 572 DESIGN memory_manager 573 VIEW beha 574 GRAPHIC 51,0 276 0 575 DESIGN @f@a@d_main 576 VIEW struct.bd 577 GRAPHIC 5793,0 279 0 572 578 DESIGN spi_interface 573 579 VIEW symbol.sb 574 GRAPHIC 1121,0 2 790580 GRAPHIC 1121,0 281 0 575 581 DESIGN spi_interface 576 582 VIEW symbol.sb 577 GRAPHIC 326,0 28 00583 GRAPHIC 326,0 282 0 578 584 DESIGN spi_interface 579 585 VIEW symbol.sb 580 GRAPHIC 197,0 28 10586 GRAPHIC 197,0 283 0 581 587 DESIGN spi_interface 582 588 VIEW symbol.sb 583 GRAPHIC 321,0 28 20589 GRAPHIC 321,0 284 0 584 590 DESIGN spi_interface 585 591 VIEW symbol.sb 586 GRAPHIC 1198,0 28 30592 GRAPHIC 1198,0 285 0 587 593 DESIGN spi_interface 588 594 VIEW symbol.sb 589 GRAPHIC 1017,0 28 40595 GRAPHIC 1017,0 286 0 590 596 DESIGN spi_interface 591 597 VIEW symbol.sb 592 GRAPHIC 1229,0 28 50598 GRAPHIC 1229,0 287 0 593 599 DESIGN spi_interface 594 600 VIEW symbol.sb 595 GRAPHIC 126,0 28 60601 GRAPHIC 126,0 288 0 596 602 DESIGN spi_interface 597 603 VIEW symbol.sb 598 GRAPHIC 819,0 28 70604 GRAPHIC 819,0 289 0 599 605 DESIGN spi_interface 600 606 VIEW symbol.sb 601 GRAPHIC 1022,0 2 880607 GRAPHIC 1022,0 290 0 602 608 DESIGN spi_interface 603 609 VIEW symbol.sb 604 GRAPHIC 824,0 2 890610 GRAPHIC 824,0 291 0 605 611 DESIGN spi_interface 606 612 VIEW symbol.sb 607 GRAPHIC 1283,0 29 00608 DESIGN @f@a@d_main 609 VIEW struct.bd 610 GRAPHIC 1768,0 29 30613 GRAPHIC 1283,0 292 0 614 DESIGN @f@a@d_main 615 VIEW struct.bd 616 GRAPHIC 1768,0 295 0 611 617 DESIGN trigger_counter 612 618 VIEW beha 613 GRAPHIC 48,0 29 50619 GRAPHIC 48,0 297 0 614 620 DESIGN trigger_counter 615 621 VIEW beha 616 GRAPHIC 53,0 29 60622 GRAPHIC 53,0 298 0 617 623 DESIGN trigger_counter 618 624 VIEW beha 619 GRAPHIC 148,0 297 0 620 DESIGN @f@a@d_main 621 VIEW struct.bd 622 GRAPHIC 1606,0 300 0 623 DESIGN w5300_modul 624 VIEW symbol.sb 625 GRAPHIC 14,0 301 1 626 DESIGN w5300_modul 627 VIEW @behavioral 628 GRAPHIC 48,0 305 0 629 DESIGN w5300_modul 630 VIEW @behavioral 631 GRAPHIC 53,0 306 0 632 DESIGN w5300_modul 633 VIEW @behavioral 634 GRAPHIC 58,0 307 0 635 DESIGN w5300_modul 636 VIEW @behavioral 637 GRAPHIC 63,0 308 0 638 DESIGN w5300_modul 639 VIEW @behavioral 640 GRAPHIC 68,0 309 0 641 DESIGN w5300_modul 642 VIEW @behavioral 643 GRAPHIC 73,0 310 0 644 DESIGN w5300_modul 645 VIEW @behavioral 646 GRAPHIC 491,0 311 0 647 DESIGN w5300_modul 648 VIEW @behavioral 649 GRAPHIC 83,0 312 0 650 DESIGN w5300_modul 651 VIEW @behavioral 652 GRAPHIC 88,0 313 0 653 DESIGN w5300_modul 654 VIEW @behavioral 655 GRAPHIC 93,0 314 0 656 DESIGN w5300_modul 657 VIEW @behavioral 658 GRAPHIC 98,0 315 0 659 DESIGN w5300_modul 660 VIEW @behavioral 661 GRAPHIC 103,0 316 0 662 DESIGN w5300_modul 663 VIEW @behavioral 664 GRAPHIC 108,0 317 0 665 DESIGN w5300_modul 666 VIEW @behavioral 667 GRAPHIC 113,0 318 0 668 DESIGN w5300_modul 669 VIEW @behavioral 670 GRAPHIC 885,0 319 0 671 DESIGN w5300_modul 672 VIEW @behavioral 673 GRAPHIC 118,0 320 0 674 DESIGN w5300_modul 675 VIEW @behavioral 676 GRAPHIC 353,0 321 0 677 DESIGN w5300_modul 678 VIEW @behavioral 679 GRAPHIC 348,0 322 0 680 DESIGN w5300_modul 681 VIEW @behavioral 682 GRAPHIC 385,0 323 0 683 DESIGN w5300_modul 684 VIEW @behavioral 685 GRAPHIC 521,0 324 0 686 DESIGN w5300_modul 687 VIEW @behavioral 688 GRAPHIC 576,0 325 0 689 DESIGN w5300_modul 690 VIEW @behavioral 691 GRAPHIC 566,0 326 0 692 DESIGN w5300_modul 693 VIEW @behavioral 694 GRAPHIC 551,0 327 0 695 DESIGN w5300_modul 696 VIEW @behavioral 697 GRAPHIC 561,0 328 0 698 DESIGN w5300_modul 699 VIEW @behavioral 700 GRAPHIC 571,0 329 0 701 DESIGN w5300_modul 702 VIEW @behavioral 703 GRAPHIC 640,0 330 0 704 DESIGN w5300_modul 705 VIEW @behavioral 706 GRAPHIC 556,0 331 0 707 DESIGN w5300_modul 708 VIEW @behavioral 709 GRAPHIC 670,0 332 0 710 DESIGN w5300_modul 711 VIEW @behavioral 712 GRAPHIC 723,0 333 0 625 GRAPHIC 148,0 299 0 626 DESIGN @f@a@d_main 627 VIEW struct.bd 628 GRAPHIC 1606,0 302 0 629 DESIGN w5300_modul 630 VIEW symbol.sb 631 GRAPHIC 14,0 303 1 632 DESIGN w5300_modul 633 VIEW @behavioral 634 GRAPHIC 48,0 307 0 635 DESIGN w5300_modul 636 VIEW @behavioral 637 GRAPHIC 53,0 308 0 638 DESIGN w5300_modul 639 VIEW @behavioral 640 GRAPHIC 58,0 309 0 641 DESIGN w5300_modul 642 VIEW @behavioral 643 GRAPHIC 63,0 310 0 644 DESIGN w5300_modul 645 VIEW @behavioral 646 GRAPHIC 68,0 311 0 647 DESIGN w5300_modul 648 VIEW @behavioral 649 GRAPHIC 73,0 312 0 650 DESIGN w5300_modul 651 VIEW @behavioral 652 GRAPHIC 491,0 313 0 653 DESIGN w5300_modul 654 VIEW @behavioral 655 GRAPHIC 83,0 314 0 656 DESIGN w5300_modul 657 VIEW @behavioral 658 GRAPHIC 88,0 315 0 659 DESIGN w5300_modul 660 VIEW @behavioral 661 GRAPHIC 93,0 316 0 662 DESIGN w5300_modul 663 VIEW @behavioral 664 GRAPHIC 98,0 317 0 665 DESIGN w5300_modul 666 VIEW @behavioral 667 GRAPHIC 103,0 318 0 668 DESIGN w5300_modul 669 VIEW @behavioral 670 GRAPHIC 108,0 319 0 671 DESIGN w5300_modul 672 VIEW @behavioral 673 GRAPHIC 113,0 320 0 674 DESIGN w5300_modul 675 VIEW @behavioral 676 GRAPHIC 885,0 321 0 677 DESIGN w5300_modul 678 VIEW @behavioral 679 GRAPHIC 118,0 322 0 680 DESIGN w5300_modul 681 VIEW @behavioral 682 GRAPHIC 353,0 323 0 683 DESIGN w5300_modul 684 VIEW @behavioral 685 GRAPHIC 348,0 324 0 686 DESIGN w5300_modul 687 VIEW @behavioral 688 GRAPHIC 385,0 325 0 689 DESIGN w5300_modul 690 VIEW @behavioral 691 GRAPHIC 521,0 326 0 692 DESIGN w5300_modul 693 VIEW @behavioral 694 GRAPHIC 576,0 327 0 695 DESIGN w5300_modul 696 VIEW @behavioral 697 GRAPHIC 566,0 328 0 698 DESIGN w5300_modul 699 VIEW @behavioral 700 GRAPHIC 551,0 329 0 701 DESIGN w5300_modul 702 VIEW @behavioral 703 GRAPHIC 561,0 330 0 704 DESIGN w5300_modul 705 VIEW @behavioral 706 GRAPHIC 571,0 331 0 707 DESIGN w5300_modul 708 VIEW @behavioral 709 GRAPHIC 640,0 332 0 710 DESIGN w5300_modul 711 VIEW @behavioral 712 GRAPHIC 556,0 333 0 713 DESIGN w5300_modul 714 VIEW @behavioral 715 GRAPHIC 670,0 334 0 716 DESIGN w5300_modul 717 VIEW @behavioral 718 GRAPHIC 723,0 335 0 719 DESIGN w5300_modul 720 VIEW @behavioral 721 GRAPHIC 917,0 336 0 713 722 LIBRARY FACT_FAD_lib 714 723 DESIGN @f@a@d_main 715 724 VIEW struct.bd 716 NO_GRAPHIC 336 717 DESIGN @f@a@d_main 718 VIEW struct.bd 719 GRAPHIC 5678,0 339 0 720 DESIGN @f@a@d_main 721 VIEW struct.bd 722 GRAPHIC 4194,0 340 0 723 DESIGN @f@a@d_main 724 VIEW struct.bd 725 GRAPHIC 5072,0 341 0 726 DESIGN @f@a@d_main 727 VIEW struct.bd 728 GRAPHIC 8277,0 342 0 729 DESIGN @f@a@d_main 730 VIEW struct.bd 731 GRAPHIC 1399,0 343 0 732 DESIGN @f@a@d_main 733 VIEW struct.bd 734 GRAPHIC 4903,0 344 0 735 DESIGN @f@a@d_main 736 VIEW struct.bd 737 GRAPHIC 2311,0 345 0 738 DESIGN @f@a@d_main 739 VIEW struct.bd 740 GRAPHIC 5793,0 346 0 741 DESIGN @f@a@d_main 742 VIEW struct.bd 743 GRAPHIC 1768,0 347 0 744 DESIGN @f@a@d_main 745 VIEW struct.bd 746 GRAPHIC 1606,0 348 0 747 DESIGN @f@a@d_main 748 VIEW struct.bd 749 NO_GRAPHIC 351 750 DESIGN @f@a@d_main 751 VIEW struct.bd 752 GRAPHIC 6529,0 353 0 753 DESIGN @f@a@d_main 754 VIEW struct.bd 755 GRAPHIC 8562,0 356 0 756 DESIGN @f@a@d_main 757 VIEW struct.bd 758 NO_GRAPHIC 367 759 DESIGN @f@a@d_main 760 VIEW struct.bd 761 GRAPHIC 5678,0 369 0 762 DESIGN @f@a@d_main 763 VIEW struct.bd 764 GRAPHIC 5646,0 371 0 765 DESIGN @f@a@d_main 766 VIEW struct.bd 767 GRAPHIC 4272,0 372 0 768 DESIGN @f@a@d_main 769 VIEW struct.bd 770 GRAPHIC 2786,0 373 0 771 DESIGN @f@a@d_main 772 VIEW struct.bd 773 GRAPHIC 5626,0 374 0 774 DESIGN @f@a@d_main 775 VIEW struct.bd 776 GRAPHIC 5634,0 375 0 777 DESIGN @f@a@d_main 778 VIEW struct.bd 779 GRAPHIC 4194,0 377 0 780 DESIGN @f@a@d_main 781 VIEW struct.bd 782 GRAPHIC 4042,0 379 0 783 DESIGN @f@a@d_main 784 VIEW struct.bd 785 GRAPHIC 6072,0 380 0 786 DESIGN @f@a@d_main 787 VIEW struct.bd 788 GRAPHIC 3984,0 381 0 789 DESIGN @f@a@d_main 790 VIEW struct.bd 791 GRAPHIC 3888,0 382 0 792 DESIGN @f@a@d_main 793 VIEW struct.bd 794 GRAPHIC 5072,0 384 0 795 DESIGN @f@a@d_main 796 VIEW struct.bd 797 GRAPHIC 5582,0 386 0 798 DESIGN @f@a@d_main 799 VIEW struct.bd 800 GRAPHIC 5090,0 387 0 801 DESIGN @f@a@d_main 802 VIEW struct.bd 803 GRAPHIC 5130,0 388 0 804 DESIGN @f@a@d_main 805 VIEW struct.bd 806 GRAPHIC 5184,0 389 0 807 DESIGN @f@a@d_main 808 VIEW struct.bd 809 GRAPHIC 5122,0 390 0 810 DESIGN @f@a@d_main 811 VIEW struct.bd 812 GRAPHIC 5106,0 391 0 813 DESIGN @f@a@d_main 814 VIEW struct.bd 815 GRAPHIC 5098,0 392 0 816 DESIGN @f@a@d_main 817 VIEW struct.bd 818 GRAPHIC 5190,0 393 0 819 DESIGN @f@a@d_main 820 VIEW struct.bd 821 GRAPHIC 6002,0 394 0 822 DESIGN @f@a@d_main 823 VIEW struct.bd 824 GRAPHIC 5146,0 395 0 825 DESIGN @f@a@d_main 826 VIEW struct.bd 827 GRAPHIC 8510,0 396 0 828 DESIGN @f@a@d_main 829 VIEW struct.bd 830 GRAPHIC 8518,0 397 0 831 DESIGN @f@a@d_main 832 VIEW struct.bd 833 GRAPHIC 5138,0 398 0 834 DESIGN @f@a@d_main 835 VIEW struct.bd 836 GRAPHIC 5114,0 399 0 837 DESIGN @f@a@d_main 838 VIEW struct.bd 839 GRAPHIC 8277,0 401 0 840 DESIGN @f@a@d_main 841 VIEW struct.bd 842 GRAPHIC 5602,0 403 0 843 DESIGN @f@a@d_main 844 VIEW struct.bd 845 GRAPHIC 334,0 404 0 846 DESIGN @f@a@d_main 847 VIEW struct.bd 848 GRAPHIC 328,0 405 0 849 DESIGN @f@a@d_main 850 VIEW struct.bd 851 GRAPHIC 322,0 406 0 852 DESIGN @f@a@d_main 853 VIEW struct.bd 854 GRAPHIC 4240,0 407 0 855 DESIGN @f@a@d_main 856 VIEW struct.bd 857 GRAPHIC 364,0 408 0 858 DESIGN @f@a@d_main 859 VIEW struct.bd 860 GRAPHIC 370,0 409 0 861 DESIGN @f@a@d_main 862 VIEW struct.bd 863 GRAPHIC 1399,0 411 0 864 DESIGN @f@a@d_main 865 VIEW struct.bd 866 GRAPHIC 1406,0 412 1 867 DESIGN @f@a@d_main 868 VIEW struct.bd 869 GRAPHIC 5602,0 416 0 870 DESIGN @f@a@d_main 871 VIEW struct.bd 872 GRAPHIC 334,0 417 0 873 DESIGN @f@a@d_main 874 VIEW struct.bd 875 GRAPHIC 328,0 418 0 876 DESIGN @f@a@d_main 877 VIEW struct.bd 878 GRAPHIC 322,0 419 0 879 DESIGN @f@a@d_main 880 VIEW struct.bd 881 GRAPHIC 2299,0 420 0 882 DESIGN @f@a@d_main 883 VIEW struct.bd 884 GRAPHIC 2576,0 421 0 885 DESIGN @f@a@d_main 886 VIEW struct.bd 887 GRAPHIC 2582,0 422 0 888 DESIGN @f@a@d_main 889 VIEW struct.bd 890 GRAPHIC 2588,0 423 0 891 DESIGN @f@a@d_main 892 VIEW struct.bd 893 GRAPHIC 5184,0 424 0 894 DESIGN @f@a@d_main 895 VIEW struct.bd 896 GRAPHIC 5745,0 425 0 897 DESIGN @f@a@d_main 898 VIEW struct.bd 899 GRAPHIC 2594,0 426 0 900 DESIGN @f@a@d_main 901 VIEW struct.bd 902 GRAPHIC 5190,0 427 0 903 DESIGN @f@a@d_main 904 VIEW struct.bd 905 GRAPHIC 5404,0 428 0 906 DESIGN @f@a@d_main 907 VIEW struct.bd 908 GRAPHIC 6018,0 429 0 909 DESIGN @f@a@d_main 910 VIEW struct.bd 911 GRAPHIC 6002,0 430 0 912 DESIGN @f@a@d_main 913 VIEW struct.bd 914 GRAPHIC 6008,0 431 0 915 DESIGN @f@a@d_main 916 VIEW struct.bd 917 GRAPHIC 5138,0 432 0 918 DESIGN @f@a@d_main 919 VIEW struct.bd 920 GRAPHIC 2600,0 433 0 921 DESIGN @f@a@d_main 922 VIEW struct.bd 923 GRAPHIC 5480,0 434 0 924 DESIGN @f@a@d_main 925 VIEW struct.bd 926 GRAPHIC 5474,0 435 0 927 DESIGN @f@a@d_main 928 VIEW struct.bd 929 GRAPHIC 6064,0 436 0 930 DESIGN @f@a@d_main 931 VIEW struct.bd 932 GRAPHIC 2642,0 437 0 933 DESIGN @f@a@d_main 934 VIEW struct.bd 935 GRAPHIC 1411,0 438 0 936 DESIGN @f@a@d_main 937 VIEW struct.bd 938 GRAPHIC 1682,0 439 0 939 DESIGN @f@a@d_main 940 VIEW struct.bd 941 GRAPHIC 1983,0 440 0 942 DESIGN @f@a@d_main 943 VIEW struct.bd 944 GRAPHIC 1425,0 441 0 945 DESIGN @f@a@d_main 946 VIEW struct.bd 947 GRAPHIC 5281,0 442 0 948 DESIGN @f@a@d_main 949 VIEW struct.bd 950 GRAPHIC 5950,0 443 0 951 DESIGN @f@a@d_main 952 VIEW struct.bd 953 GRAPHIC 5962,0 444 0 954 DESIGN @f@a@d_main 955 VIEW struct.bd 956 GRAPHIC 5626,0 445 0 957 DESIGN @f@a@d_main 958 VIEW struct.bd 959 GRAPHIC 2778,0 446 0 960 DESIGN @f@a@d_main 961 VIEW struct.bd 962 GRAPHIC 5634,0 447 0 963 DESIGN @f@a@d_main 964 VIEW struct.bd 965 GRAPHIC 8577,0 448 0 966 DESIGN @f@a@d_main 967 VIEW struct.bd 968 GRAPHIC 6540,0 449 0 969 DESIGN @f@a@d_main 970 VIEW struct.bd 971 GRAPHIC 4401,0 450 0 972 DESIGN @f@a@d_main 973 VIEW struct.bd 974 GRAPHIC 4419,0 451 0 975 DESIGN @f@a@d_main 976 VIEW struct.bd 977 GRAPHIC 4743,0 452 0 978 DESIGN @f@a@d_main 979 VIEW struct.bd 980 GRAPHIC 4407,0 453 0 981 DESIGN @f@a@d_main 982 VIEW struct.bd 983 GRAPHIC 4903,0 455 0 984 DESIGN @f@a@d_main 985 VIEW struct.bd 986 GRAPHIC 4757,0 457 0 987 DESIGN @f@a@d_main 988 VIEW struct.bd 989 GRAPHIC 4401,0 458 0 990 DESIGN @f@a@d_main 991 VIEW struct.bd 992 GRAPHIC 4419,0 459 0 993 DESIGN @f@a@d_main 994 VIEW struct.bd 995 GRAPHIC 4671,0 460 0 996 DESIGN @f@a@d_main 997 VIEW struct.bd 998 GRAPHIC 4679,0 461 0 999 DESIGN @f@a@d_main 1000 VIEW struct.bd 1001 GRAPHIC 4687,0 462 0 1002 DESIGN @f@a@d_main 1003 VIEW struct.bd 1004 GRAPHIC 4695,0 463 0 1005 DESIGN @f@a@d_main 1006 VIEW struct.bd 1007 GRAPHIC 4407,0 464 0 1008 DESIGN @f@a@d_main 1009 VIEW struct.bd 1010 GRAPHIC 4743,0 465 0 1011 DESIGN @f@a@d_main 1012 VIEW struct.bd 1013 GRAPHIC 4948,0 466 0 1014 DESIGN @f@a@d_main 1015 VIEW struct.bd 1016 GRAPHIC 4962,0 467 0 1017 DESIGN @f@a@d_main 1018 VIEW struct.bd 1019 GRAPHIC 2311,0 469 0 1020 DESIGN @f@a@d_main 1021 VIEW struct.bd 1022 GRAPHIC 2318,0 470 1 1023 DESIGN @f@a@d_main 1024 VIEW struct.bd 1025 GRAPHIC 6082,0 475 0 1026 DESIGN @f@a@d_main 1027 VIEW struct.bd 1028 GRAPHIC 2588,0 476 0 1029 DESIGN @f@a@d_main 1030 VIEW struct.bd 1031 GRAPHIC 2582,0 477 0 1032 DESIGN @f@a@d_main 1033 VIEW struct.bd 1034 GRAPHIC 5168,0 478 0 1035 DESIGN @f@a@d_main 1036 VIEW struct.bd 1037 GRAPHIC 2576,0 479 0 1038 DESIGN @f@a@d_main 1039 VIEW struct.bd 1040 GRAPHIC 2594,0 480 0 1041 DESIGN @f@a@d_main 1042 VIEW struct.bd 1043 GRAPHIC 6018,0 481 0 1044 DESIGN @f@a@d_main 1045 VIEW struct.bd 1046 GRAPHIC 2600,0 482 0 1047 DESIGN @f@a@d_main 1048 VIEW struct.bd 1049 GRAPHIC 2642,0 483 0 1050 DESIGN @f@a@d_main 1051 VIEW struct.bd 1052 GRAPHIC 2488,0 484 0 1053 DESIGN @f@a@d_main 1054 VIEW struct.bd 1055 GRAPHIC 2482,0 485 0 1056 DESIGN @f@a@d_main 1057 VIEW struct.bd 1058 GRAPHIC 2494,0 486 0 1059 DESIGN @f@a@d_main 1060 VIEW struct.bd 1061 GRAPHIC 2476,0 487 0 1062 DESIGN @f@a@d_main 1063 VIEW struct.bd 1064 GRAPHIC 2506,0 488 0 1065 DESIGN @f@a@d_main 1066 VIEW struct.bd 1067 GRAPHIC 2500,0 489 0 1068 DESIGN @f@a@d_main 1069 VIEW struct.bd 1070 GRAPHIC 2470,0 490 0 1071 DESIGN @f@a@d_main 1072 VIEW struct.bd 1073 GRAPHIC 8416,0 491 0 1074 DESIGN @f@a@d_main 1075 VIEW struct.bd 1076 GRAPHIC 2299,0 492 0 1077 DESIGN @f@a@d_main 1078 VIEW struct.bd 1079 GRAPHIC 5793,0 494 0 1080 DESIGN @f@a@d_main 1081 VIEW struct.bd 1082 GRAPHIC 5805,0 496 0 1083 DESIGN @f@a@d_main 1084 VIEW struct.bd 1085 GRAPHIC 5745,0 497 0 1086 DESIGN @f@a@d_main 1087 VIEW struct.bd 1088 GRAPHIC 5146,0 498 0 1089 DESIGN @f@a@d_main 1090 VIEW struct.bd 1091 GRAPHIC 5404,0 499 0 1092 DESIGN @f@a@d_main 1093 VIEW struct.bd 1094 GRAPHIC 6008,0 500 0 1095 DESIGN @f@a@d_main 1096 VIEW struct.bd 1097 GRAPHIC 5829,0 501 0 1098 DESIGN @f@a@d_main 1099 VIEW struct.bd 1100 GRAPHIC 6160,0 502 0 1101 DESIGN @f@a@d_main 1102 VIEW struct.bd 1103 GRAPHIC 5813,0 503 0 1104 DESIGN @f@a@d_main 1105 VIEW struct.bd 1106 GRAPHIC 5480,0 504 0 1107 DESIGN @f@a@d_main 1108 VIEW struct.bd 1109 GRAPHIC 5837,0 505 0 1110 DESIGN @f@a@d_main 1111 VIEW struct.bd 1112 GRAPHIC 5474,0 506 0 1113 DESIGN @f@a@d_main 1114 VIEW struct.bd 1115 GRAPHIC 5821,0 507 0 1116 DESIGN @f@a@d_main 1117 VIEW struct.bd 1118 GRAPHIC 1768,0 509 0 1119 DESIGN @f@a@d_main 1120 VIEW struct.bd 1121 GRAPHIC 1983,0 511 0 1122 DESIGN @f@a@d_main 1123 VIEW struct.bd 1124 GRAPHIC 2876,0 512 0 1125 DESIGN @f@a@d_main 1126 VIEW struct.bd 1127 GRAPHIC 6276,0 513 0 1128 DESIGN @f@a@d_main 1129 VIEW struct.bd 1130 GRAPHIC 1606,0 515 0 1131 DESIGN @f@a@d_main 1132 VIEW struct.bd 1133 GRAPHIC 1613,0 516 1 1134 DESIGN @f@a@d_main 1135 VIEW struct.bd 1136 GRAPHIC 3888,0 520 0 1137 DESIGN @f@a@d_main 1138 VIEW struct.bd 1139 GRAPHIC 376,0 521 0 1140 DESIGN @f@a@d_main 1141 VIEW struct.bd 1142 GRAPHIC 384,0 522 0 1143 DESIGN @f@a@d_main 1144 VIEW struct.bd 1145 GRAPHIC 392,0 523 0 1146 DESIGN @f@a@d_main 1147 VIEW struct.bd 1148 GRAPHIC 400,0 524 0 1149 DESIGN @f@a@d_main 1150 VIEW struct.bd 1151 GRAPHIC 408,0 525 0 1152 DESIGN @f@a@d_main 1153 VIEW struct.bd 1154 GRAPHIC 5222,0 526 0 1155 DESIGN @f@a@d_main 1156 VIEW struct.bd 1157 GRAPHIC 424,0 527 0 1158 DESIGN @f@a@d_main 1159 VIEW struct.bd 1160 GRAPHIC 432,0 528 0 1161 DESIGN @f@a@d_main 1162 VIEW struct.bd 1163 GRAPHIC 2482,0 529 0 1164 DESIGN @f@a@d_main 1165 VIEW struct.bd 1166 GRAPHIC 2488,0 530 0 1167 DESIGN @f@a@d_main 1168 VIEW struct.bd 1169 GRAPHIC 370,0 531 0 1170 DESIGN @f@a@d_main 1171 VIEW struct.bd 1172 GRAPHIC 364,0 532 0 1173 DESIGN @f@a@d_main 1174 VIEW struct.bd 1175 GRAPHIC 2476,0 533 0 1176 DESIGN @f@a@d_main 1177 VIEW struct.bd 1178 GRAPHIC 8416,0 534 0 1179 DESIGN @f@a@d_main 1180 VIEW struct.bd 1181 GRAPHIC 2470,0 535 0 1182 DESIGN @f@a@d_main 1183 VIEW struct.bd 1184 GRAPHIC 2506,0 536 0 1185 DESIGN @f@a@d_main 1186 VIEW struct.bd 1187 GRAPHIC 2500,0 537 0 1188 DESIGN @f@a@d_main 1189 VIEW struct.bd 1190 GRAPHIC 2494,0 538 0 1191 DESIGN @f@a@d_main 1192 VIEW struct.bd 1193 GRAPHIC 5281,0 539 0 1194 DESIGN @f@a@d_main 1195 VIEW struct.bd 1196 GRAPHIC 5950,0 540 0 1197 DESIGN @f@a@d_main 1198 VIEW struct.bd 1199 GRAPHIC 5962,0 541 0 1200 DESIGN @f@a@d_main 1201 VIEW struct.bd 1202 GRAPHIC 5090,0 542 0 1203 DESIGN @f@a@d_main 1204 VIEW struct.bd 1205 GRAPHIC 5114,0 543 0 1206 DESIGN @f@a@d_main 1207 VIEW struct.bd 1208 GRAPHIC 5122,0 544 0 1209 DESIGN @f@a@d_main 1210 VIEW struct.bd 1211 GRAPHIC 5130,0 545 0 1212 DESIGN @f@a@d_main 1213 VIEW struct.bd 1214 GRAPHIC 5106,0 546 0 1215 DESIGN @f@a@d_main 1216 VIEW struct.bd 1217 GRAPHIC 6362,0 547 0 1218 DESIGN @f@a@d_main 1219 VIEW struct.bd 1220 GRAPHIC 6452,0 548 0 1221 DESIGN @f@a@d_main 1222 VIEW struct.bd 1223 GRAPHIC 6276,0 552 0 1224 DESIGN @f@a@d_main 1225 VIEW struct.bd 1226 GRAPHIC 3888,0 553 0 1227 DESIGN @f@a@d_main 1228 VIEW struct.bd 1229 NO_GRAPHIC 555 725 NO_GRAPHIC 339 726 DESIGN @f@a@d_main 727 VIEW struct.bd 728 GRAPHIC 5678,0 342 0 729 DESIGN @f@a@d_main 730 VIEW struct.bd 731 GRAPHIC 4194,0 343 0 732 DESIGN @f@a@d_main 733 VIEW struct.bd 734 GRAPHIC 5072,0 344 0 735 DESIGN @f@a@d_main 736 VIEW struct.bd 737 GRAPHIC 8277,0 345 0 738 DESIGN @f@a@d_main 739 VIEW struct.bd 740 GRAPHIC 1399,0 346 0 741 DESIGN @f@a@d_main 742 VIEW struct.bd 743 GRAPHIC 4903,0 347 0 744 DESIGN @f@a@d_main 745 VIEW struct.bd 746 GRAPHIC 2311,0 348 0 747 DESIGN @f@a@d_main 748 VIEW struct.bd 749 GRAPHIC 5793,0 349 0 750 DESIGN @f@a@d_main 751 VIEW struct.bd 752 GRAPHIC 1768,0 350 0 753 DESIGN @f@a@d_main 754 VIEW struct.bd 755 GRAPHIC 1606,0 351 0 756 DESIGN @f@a@d_main 757 VIEW struct.bd 758 NO_GRAPHIC 354 759 DESIGN @f@a@d_main 760 VIEW struct.bd 761 GRAPHIC 6529,0 356 0 762 DESIGN @f@a@d_main 763 VIEW struct.bd 764 GRAPHIC 8721,0 359 0 765 DESIGN @f@a@d_main 766 VIEW struct.bd 767 GRAPHIC 8562,0 362 0 768 DESIGN @f@a@d_main 769 VIEW struct.bd 770 NO_GRAPHIC 373 771 DESIGN @f@a@d_main 772 VIEW struct.bd 773 GRAPHIC 5678,0 375 0 774 DESIGN @f@a@d_main 775 VIEW struct.bd 776 GRAPHIC 5646,0 377 0 777 DESIGN @f@a@d_main 778 VIEW struct.bd 779 GRAPHIC 4272,0 378 0 780 DESIGN @f@a@d_main 781 VIEW struct.bd 782 GRAPHIC 2786,0 379 0 783 DESIGN @f@a@d_main 784 VIEW struct.bd 785 GRAPHIC 5626,0 380 0 786 DESIGN @f@a@d_main 787 VIEW struct.bd 788 GRAPHIC 5634,0 381 0 789 DESIGN @f@a@d_main 790 VIEW struct.bd 791 GRAPHIC 4194,0 383 0 792 DESIGN @f@a@d_main 793 VIEW struct.bd 794 GRAPHIC 4042,0 385 0 795 DESIGN @f@a@d_main 796 VIEW struct.bd 797 GRAPHIC 6072,0 386 0 798 DESIGN @f@a@d_main 799 VIEW struct.bd 800 GRAPHIC 3984,0 387 0 801 DESIGN @f@a@d_main 802 VIEW struct.bd 803 GRAPHIC 3888,0 388 0 804 DESIGN @f@a@d_main 805 VIEW struct.bd 806 GRAPHIC 5072,0 390 0 807 DESIGN @f@a@d_main 808 VIEW struct.bd 809 GRAPHIC 5582,0 392 0 810 DESIGN @f@a@d_main 811 VIEW struct.bd 812 GRAPHIC 5090,0 393 0 813 DESIGN @f@a@d_main 814 VIEW struct.bd 815 GRAPHIC 5130,0 394 0 816 DESIGN @f@a@d_main 817 VIEW struct.bd 818 GRAPHIC 5184,0 395 0 819 DESIGN @f@a@d_main 820 VIEW struct.bd 821 GRAPHIC 5122,0 396 0 822 DESIGN @f@a@d_main 823 VIEW struct.bd 824 GRAPHIC 5106,0 397 0 825 DESIGN @f@a@d_main 826 VIEW struct.bd 827 GRAPHIC 5098,0 398 0 828 DESIGN @f@a@d_main 829 VIEW struct.bd 830 GRAPHIC 5190,0 399 0 831 DESIGN @f@a@d_main 832 VIEW struct.bd 833 GRAPHIC 6002,0 400 0 834 DESIGN @f@a@d_main 835 VIEW struct.bd 836 GRAPHIC 5146,0 401 0 837 DESIGN @f@a@d_main 838 VIEW struct.bd 839 GRAPHIC 8510,0 402 0 840 DESIGN @f@a@d_main 841 VIEW struct.bd 842 GRAPHIC 8518,0 403 0 843 DESIGN @f@a@d_main 844 VIEW struct.bd 845 GRAPHIC 5138,0 404 0 846 DESIGN @f@a@d_main 847 VIEW struct.bd 848 GRAPHIC 5114,0 405 0 849 DESIGN @f@a@d_main 850 VIEW struct.bd 851 GRAPHIC 8277,0 407 0 852 DESIGN @f@a@d_main 853 VIEW struct.bd 854 GRAPHIC 5602,0 409 0 855 DESIGN @f@a@d_main 856 VIEW struct.bd 857 GRAPHIC 334,0 410 0 858 DESIGN @f@a@d_main 859 VIEW struct.bd 860 GRAPHIC 328,0 411 0 861 DESIGN @f@a@d_main 862 VIEW struct.bd 863 GRAPHIC 322,0 412 0 864 DESIGN @f@a@d_main 865 VIEW struct.bd 866 GRAPHIC 4240,0 413 0 867 DESIGN @f@a@d_main 868 VIEW struct.bd 869 GRAPHIC 364,0 414 0 870 DESIGN @f@a@d_main 871 VIEW struct.bd 872 GRAPHIC 370,0 415 0 873 DESIGN @f@a@d_main 874 VIEW struct.bd 875 GRAPHIC 1399,0 417 0 876 DESIGN @f@a@d_main 877 VIEW struct.bd 878 GRAPHIC 1406,0 418 1 879 DESIGN @f@a@d_main 880 VIEW struct.bd 881 GRAPHIC 5602,0 422 0 882 DESIGN @f@a@d_main 883 VIEW struct.bd 884 GRAPHIC 334,0 423 0 885 DESIGN @f@a@d_main 886 VIEW struct.bd 887 GRAPHIC 328,0 424 0 888 DESIGN @f@a@d_main 889 VIEW struct.bd 890 GRAPHIC 322,0 425 0 891 DESIGN @f@a@d_main 892 VIEW struct.bd 893 GRAPHIC 2299,0 426 0 894 DESIGN @f@a@d_main 895 VIEW struct.bd 896 GRAPHIC 2576,0 427 0 897 DESIGN @f@a@d_main 898 VIEW struct.bd 899 GRAPHIC 2582,0 428 0 900 DESIGN @f@a@d_main 901 VIEW struct.bd 902 GRAPHIC 2588,0 429 0 903 DESIGN @f@a@d_main 904 VIEW struct.bd 905 GRAPHIC 5184,0 430 0 906 DESIGN @f@a@d_main 907 VIEW struct.bd 908 GRAPHIC 5745,0 431 0 909 DESIGN @f@a@d_main 910 VIEW struct.bd 911 GRAPHIC 2594,0 432 0 912 DESIGN @f@a@d_main 913 VIEW struct.bd 914 GRAPHIC 5190,0 433 0 915 DESIGN @f@a@d_main 916 VIEW struct.bd 917 GRAPHIC 5404,0 434 0 918 DESIGN @f@a@d_main 919 VIEW struct.bd 920 GRAPHIC 6018,0 435 0 921 DESIGN @f@a@d_main 922 VIEW struct.bd 923 GRAPHIC 6002,0 436 0 924 DESIGN @f@a@d_main 925 VIEW struct.bd 926 GRAPHIC 6008,0 437 0 927 DESIGN @f@a@d_main 928 VIEW struct.bd 929 GRAPHIC 5138,0 438 0 930 DESIGN @f@a@d_main 931 VIEW struct.bd 932 GRAPHIC 2600,0 439 0 933 DESIGN @f@a@d_main 934 VIEW struct.bd 935 GRAPHIC 5480,0 440 0 936 DESIGN @f@a@d_main 937 VIEW struct.bd 938 GRAPHIC 5474,0 441 0 939 DESIGN @f@a@d_main 940 VIEW struct.bd 941 GRAPHIC 6064,0 442 0 942 DESIGN @f@a@d_main 943 VIEW struct.bd 944 GRAPHIC 2642,0 443 0 945 DESIGN @f@a@d_main 946 VIEW struct.bd 947 GRAPHIC 1411,0 444 0 948 DESIGN @f@a@d_main 949 VIEW struct.bd 950 GRAPHIC 1682,0 445 0 951 DESIGN @f@a@d_main 952 VIEW struct.bd 953 GRAPHIC 1983,0 446 0 954 DESIGN @f@a@d_main 955 VIEW struct.bd 956 GRAPHIC 1425,0 447 0 957 DESIGN @f@a@d_main 958 VIEW struct.bd 959 GRAPHIC 5281,0 448 0 960 DESIGN @f@a@d_main 961 VIEW struct.bd 962 GRAPHIC 5950,0 449 0 963 DESIGN @f@a@d_main 964 VIEW struct.bd 965 GRAPHIC 5962,0 450 0 966 DESIGN @f@a@d_main 967 VIEW struct.bd 968 GRAPHIC 5626,0 451 0 969 DESIGN @f@a@d_main 970 VIEW struct.bd 971 GRAPHIC 2778,0 452 0 972 DESIGN @f@a@d_main 973 VIEW struct.bd 974 GRAPHIC 5634,0 453 0 975 DESIGN @f@a@d_main 976 VIEW struct.bd 977 GRAPHIC 8577,0 454 0 978 DESIGN @f@a@d_main 979 VIEW struct.bd 980 GRAPHIC 6540,0 455 0 981 DESIGN @f@a@d_main 982 VIEW struct.bd 983 GRAPHIC 4401,0 456 0 984 DESIGN @f@a@d_main 985 VIEW struct.bd 986 GRAPHIC 4419,0 457 0 987 DESIGN @f@a@d_main 988 VIEW struct.bd 989 GRAPHIC 4743,0 458 0 990 DESIGN @f@a@d_main 991 VIEW struct.bd 992 GRAPHIC 4407,0 459 0 993 DESIGN @f@a@d_main 994 VIEW struct.bd 995 GRAPHIC 4903,0 461 0 996 DESIGN @f@a@d_main 997 VIEW struct.bd 998 GRAPHIC 4757,0 463 0 999 DESIGN @f@a@d_main 1000 VIEW struct.bd 1001 GRAPHIC 4401,0 464 0 1002 DESIGN @f@a@d_main 1003 VIEW struct.bd 1004 GRAPHIC 4419,0 465 0 1005 DESIGN @f@a@d_main 1006 VIEW struct.bd 1007 GRAPHIC 4671,0 466 0 1008 DESIGN @f@a@d_main 1009 VIEW struct.bd 1010 GRAPHIC 4679,0 467 0 1011 DESIGN @f@a@d_main 1012 VIEW struct.bd 1013 GRAPHIC 4687,0 468 0 1014 DESIGN @f@a@d_main 1015 VIEW struct.bd 1016 GRAPHIC 4695,0 469 0 1017 DESIGN @f@a@d_main 1018 VIEW struct.bd 1019 GRAPHIC 4407,0 470 0 1020 DESIGN @f@a@d_main 1021 VIEW struct.bd 1022 GRAPHIC 4743,0 471 0 1023 DESIGN @f@a@d_main 1024 VIEW struct.bd 1025 GRAPHIC 4948,0 472 0 1026 DESIGN @f@a@d_main 1027 VIEW struct.bd 1028 GRAPHIC 4962,0 473 0 1029 DESIGN @f@a@d_main 1030 VIEW struct.bd 1031 GRAPHIC 2311,0 475 0 1032 DESIGN @f@a@d_main 1033 VIEW struct.bd 1034 GRAPHIC 2318,0 476 1 1035 DESIGN @f@a@d_main 1036 VIEW struct.bd 1037 GRAPHIC 6082,0 481 0 1038 DESIGN @f@a@d_main 1039 VIEW struct.bd 1040 GRAPHIC 2588,0 482 0 1041 DESIGN @f@a@d_main 1042 VIEW struct.bd 1043 GRAPHIC 2582,0 483 0 1044 DESIGN @f@a@d_main 1045 VIEW struct.bd 1046 GRAPHIC 5168,0 484 0 1047 DESIGN @f@a@d_main 1048 VIEW struct.bd 1049 GRAPHIC 2576,0 485 0 1050 DESIGN @f@a@d_main 1051 VIEW struct.bd 1052 GRAPHIC 2594,0 486 0 1053 DESIGN @f@a@d_main 1054 VIEW struct.bd 1055 GRAPHIC 6018,0 487 0 1056 DESIGN @f@a@d_main 1057 VIEW struct.bd 1058 GRAPHIC 2600,0 488 0 1059 DESIGN @f@a@d_main 1060 VIEW struct.bd 1061 GRAPHIC 2642,0 489 0 1062 DESIGN @f@a@d_main 1063 VIEW struct.bd 1064 GRAPHIC 2488,0 490 0 1065 DESIGN @f@a@d_main 1066 VIEW struct.bd 1067 GRAPHIC 2482,0 491 0 1068 DESIGN @f@a@d_main 1069 VIEW struct.bd 1070 GRAPHIC 2494,0 492 0 1071 DESIGN @f@a@d_main 1072 VIEW struct.bd 1073 GRAPHIC 2476,0 493 0 1074 DESIGN @f@a@d_main 1075 VIEW struct.bd 1076 GRAPHIC 2506,0 494 0 1077 DESIGN @f@a@d_main 1078 VIEW struct.bd 1079 GRAPHIC 2500,0 495 0 1080 DESIGN @f@a@d_main 1081 VIEW struct.bd 1082 GRAPHIC 2470,0 496 0 1083 DESIGN @f@a@d_main 1084 VIEW struct.bd 1085 GRAPHIC 8416,0 497 0 1086 DESIGN @f@a@d_main 1087 VIEW struct.bd 1088 GRAPHIC 2299,0 498 0 1089 DESIGN @f@a@d_main 1090 VIEW struct.bd 1091 GRAPHIC 5793,0 500 0 1092 DESIGN @f@a@d_main 1093 VIEW struct.bd 1094 GRAPHIC 5805,0 502 0 1095 DESIGN @f@a@d_main 1096 VIEW struct.bd 1097 GRAPHIC 5745,0 503 0 1098 DESIGN @f@a@d_main 1099 VIEW struct.bd 1100 GRAPHIC 5146,0 504 0 1101 DESIGN @f@a@d_main 1102 VIEW struct.bd 1103 GRAPHIC 5404,0 505 0 1104 DESIGN @f@a@d_main 1105 VIEW struct.bd 1106 GRAPHIC 6008,0 506 0 1107 DESIGN @f@a@d_main 1108 VIEW struct.bd 1109 GRAPHIC 5829,0 507 0 1110 DESIGN @f@a@d_main 1111 VIEW struct.bd 1112 GRAPHIC 6160,0 508 0 1113 DESIGN @f@a@d_main 1114 VIEW struct.bd 1115 GRAPHIC 8732,0 509 0 1116 DESIGN @f@a@d_main 1117 VIEW struct.bd 1118 GRAPHIC 5480,0 510 0 1119 DESIGN @f@a@d_main 1120 VIEW struct.bd 1121 GRAPHIC 5837,0 511 0 1122 DESIGN @f@a@d_main 1123 VIEW struct.bd 1124 GRAPHIC 5474,0 512 0 1125 DESIGN @f@a@d_main 1126 VIEW struct.bd 1127 GRAPHIC 5821,0 513 0 1128 DESIGN @f@a@d_main 1129 VIEW struct.bd 1130 GRAPHIC 1768,0 515 0 1131 DESIGN @f@a@d_main 1132 VIEW struct.bd 1133 GRAPHIC 1983,0 517 0 1134 DESIGN @f@a@d_main 1135 VIEW struct.bd 1136 GRAPHIC 2876,0 518 0 1137 DESIGN @f@a@d_main 1138 VIEW struct.bd 1139 GRAPHIC 6276,0 519 0 1140 DESIGN @f@a@d_main 1141 VIEW struct.bd 1142 GRAPHIC 1606,0 521 0 1143 DESIGN @f@a@d_main 1144 VIEW struct.bd 1145 GRAPHIC 1613,0 522 1 1146 DESIGN @f@a@d_main 1147 VIEW struct.bd 1148 GRAPHIC 3888,0 526 0 1149 DESIGN @f@a@d_main 1150 VIEW struct.bd 1151 GRAPHIC 376,0 527 0 1152 DESIGN @f@a@d_main 1153 VIEW struct.bd 1154 GRAPHIC 384,0 528 0 1155 DESIGN @f@a@d_main 1156 VIEW struct.bd 1157 GRAPHIC 392,0 529 0 1158 DESIGN @f@a@d_main 1159 VIEW struct.bd 1160 GRAPHIC 400,0 530 0 1161 DESIGN @f@a@d_main 1162 VIEW struct.bd 1163 GRAPHIC 408,0 531 0 1164 DESIGN @f@a@d_main 1165 VIEW struct.bd 1166 GRAPHIC 5222,0 532 0 1167 DESIGN @f@a@d_main 1168 VIEW struct.bd 1169 GRAPHIC 424,0 533 0 1170 DESIGN @f@a@d_main 1171 VIEW struct.bd 1172 GRAPHIC 432,0 534 0 1173 DESIGN @f@a@d_main 1174 VIEW struct.bd 1175 GRAPHIC 2482,0 535 0 1176 DESIGN @f@a@d_main 1177 VIEW struct.bd 1178 GRAPHIC 2488,0 536 0 1179 DESIGN @f@a@d_main 1180 VIEW struct.bd 1181 GRAPHIC 370,0 537 0 1182 DESIGN @f@a@d_main 1183 VIEW struct.bd 1184 GRAPHIC 364,0 538 0 1185 DESIGN @f@a@d_main 1186 VIEW struct.bd 1187 GRAPHIC 2476,0 539 0 1188 DESIGN @f@a@d_main 1189 VIEW struct.bd 1190 GRAPHIC 8416,0 540 0 1191 DESIGN @f@a@d_main 1192 VIEW struct.bd 1193 GRAPHIC 2470,0 541 0 1194 DESIGN @f@a@d_main 1195 VIEW struct.bd 1196 GRAPHIC 2506,0 542 0 1197 DESIGN @f@a@d_main 1198 VIEW struct.bd 1199 GRAPHIC 2500,0 543 0 1200 DESIGN @f@a@d_main 1201 VIEW struct.bd 1202 GRAPHIC 2494,0 544 0 1203 DESIGN @f@a@d_main 1204 VIEW struct.bd 1205 GRAPHIC 5281,0 545 0 1206 DESIGN @f@a@d_main 1207 VIEW struct.bd 1208 GRAPHIC 5950,0 546 0 1209 DESIGN @f@a@d_main 1210 VIEW struct.bd 1211 GRAPHIC 5962,0 547 0 1212 DESIGN @f@a@d_main 1213 VIEW struct.bd 1214 GRAPHIC 5090,0 548 0 1215 DESIGN @f@a@d_main 1216 VIEW struct.bd 1217 GRAPHIC 5114,0 549 0 1218 DESIGN @f@a@d_main 1219 VIEW struct.bd 1220 GRAPHIC 5122,0 550 0 1221 DESIGN @f@a@d_main 1222 VIEW struct.bd 1223 GRAPHIC 5130,0 551 0 1224 DESIGN @f@a@d_main 1225 VIEW struct.bd 1226 GRAPHIC 5106,0 552 0 1227 DESIGN @f@a@d_main 1228 VIEW struct.bd 1229 GRAPHIC 6362,0 553 0 1230 DESIGN @f@a@d_main 1231 VIEW struct.bd 1232 GRAPHIC 6452,0 554 0 1233 DESIGN @f@a@d_main 1234 VIEW struct.bd 1235 GRAPHIC 8752,0 555 0 1236 DESIGN @f@a@d_main 1237 VIEW struct.bd 1238 GRAPHIC 6276,0 559 0 1239 DESIGN @f@a@d_main 1240 VIEW struct.bd 1241 GRAPHIC 3888,0 560 0 1242 DESIGN @f@a@d_main 1243 VIEW struct.bd 1244 NO_GRAPHIC 562 -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd
r252 r260 161 161 uid 8562,0 162 162 ) 163 (Instance 164 name "U_1" 165 duLibraryName "moduleware" 166 duName "and" 167 elements [ 168 ] 169 mwi 1 170 uid 8721,0 171 ) 163 172 ] 164 173 libraryRefs [ … … 216 225 (vvPair 217 226 variable "date" 218 value " 12.07.2010"227 value "21.07.2010" 219 228 ) 220 229 (vvPair 221 230 variable "day" 222 value "M o"231 value "Mi" 223 232 ) 224 233 (vvPair 225 234 variable "day_long" 226 value "M ontag"235 value "Mittwoch" 227 236 ) 228 237 (vvPair 229 238 variable "dd" 230 value " 12"239 value "21" 231 240 ) 232 241 (vvPair … … 256 265 (vvPair 257 266 variable "host" 258 value " TU-CC4900F8C7D2"267 value "E5B-LABOR6" 259 268 ) 260 269 (vvPair … … 368 377 (vvPair 369 378 variable "time" 370 value "1 4:21:30"379 value "11:39:48" 371 380 ) 372 381 (vvPair … … 459 468 font "Courier New,8,0" 460 469 ) 461 xt "-85000,8 6600,-41500,87400"470 xt "-85000,88200,-41500,89000" 462 471 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\" 463 472 " … … 3638 3647 ) 3639 3648 ) 3649 *97 (CptPort 3650 uid 8748,0 3651 ps "OnEdgeStrategy" 3652 shape (Triangle 3653 uid 8749,0 3654 ro 90 3655 va (VaSet 3656 vasetType 1 3657 fg "0,65535,0" 3658 ) 3659 xt "148000,76625,148750,77375" 3660 ) 3661 tg (CPTG 3662 uid 8750,0 3663 ps "CptPortTextPlaceStrategy" 3664 stg "RightVerticalLayoutStrategy" 3665 f (Text 3666 uid 8751,0 3667 va (VaSet 3668 ) 3669 xt "142300,76500,147000,77500" 3670 st "sclk_enable" 3671 ju 2 3672 blo "147000,77300" 3673 ) 3674 ) 3675 thePort (LogicalPort 3676 m 1 3677 decl (Decl 3678 n "sclk_enable" 3679 t "std_logic" 3680 eolc "-- default DWRITE HIGH." 3681 posAdd 0 3682 o 30 3683 suid 35,0 3684 i "'1'" 3685 ) 3686 ) 3687 ) 3640 3688 ] 3641 3689 shape (Rectangle … … 3655 3703 stg "VerticalLayoutStrategy" 3656 3704 textVec [ 3657 *9 7(Text3705 *98 (Text 3658 3706 uid 1609,0 3659 3707 va (VaSet … … 3665 3713 tm "BdLibraryNameMgr" 3666 3714 ) 3667 *9 8(Text3715 *99 (Text 3668 3716 uid 1610,0 3669 3717 va (VaSet … … 3675 3723 tm "CptNameMgr" 3676 3724 ) 3677 * 99(Text3725 *100 (Text 3678 3726 uid 1611,0 3679 3727 va (VaSet … … 3728 3776 archFileType "UNKNOWN" 3729 3777 ) 3730 *10 0(Net3778 *101 (Net 3731 3779 uid 1680,0 3732 3780 decl (Decl … … 3747 3795 ) 3748 3796 ) 3749 *10 1(SaComponent3797 *102 (SaComponent 3750 3798 uid 1768,0 3751 3799 optionalChildren [ 3752 *10 2(CptPort3800 *103 (CptPort 3753 3801 uid 1760,0 3754 3802 ps "OnEdgeStrategy" … … 3790 3838 ) 3791 3839 ) 3792 *10 3(CptPort3840 *104 (CptPort 3793 3841 uid 1764,0 3794 3842 ps "OnEdgeStrategy" … … 3827 3875 ) 3828 3876 ) 3829 *10 4(CptPort3877 *105 (CptPort 3830 3878 uid 6207,0 3831 3879 ps "OnEdgeStrategy" … … 3879 3927 stg "VerticalLayoutStrategy" 3880 3928 textVec [ 3881 *10 5(Text3929 *106 (Text 3882 3930 uid 1771,0 3883 3931 va (VaSet … … 3889 3937 tm "BdLibraryNameMgr" 3890 3938 ) 3891 *10 6(Text3939 *107 (Text 3892 3940 uid 1772,0 3893 3941 va (VaSet … … 3899 3947 tm "CptNameMgr" 3900 3948 ) 3901 *10 7(Text3949 *108 (Text 3902 3950 uid 1773,0 3903 3951 va (VaSet … … 3947 3995 archFileType "UNKNOWN" 3948 3996 ) 3949 *10 8(Net3997 *109 (Net 3950 3998 uid 1981,0 3951 3999 lang 2 … … 3964 4012 font "Courier New,8,0" 3965 4013 ) 3966 xt "-85000, 79400,-52500,80200"4014 xt "-85000,81000,-52500,81800" 3967 4015 st "SIGNAL trigger_id : std_logic_vector(47 downto 0) 3968 4016 " 3969 4017 ) 3970 4018 ) 3971 *1 09(Net4019 *110 (Net 3972 4020 uid 2297,0 3973 4021 decl (Decl … … 3990 4038 ) 3991 4039 ) 3992 *11 0(SaComponent4040 *111 (SaComponent 3993 4041 uid 2311,0 3994 4042 optionalChildren [ 3995 *11 1(CptPort4043 *112 (CptPort 3996 4044 uid 2307,0 3997 4045 ps "OnEdgeStrategy" … … 4034 4082 ) 4035 4083 ) 4036 *11 2(CptPort4084 *113 (CptPort 4037 4085 uid 2351,0 4038 4086 ps "OnEdgeStrategy" … … 4070 4118 ) 4071 4119 ) 4072 *11 3(CptPort4120 *114 (CptPort 4073 4121 uid 2361,0 4074 4122 ps "OnEdgeStrategy" … … 4108 4156 ) 4109 4157 ) 4110 *11 4(CptPort4158 *115 (CptPort 4111 4159 uid 2365,0 4112 4160 ps "OnEdgeStrategy" … … 4144 4192 ) 4145 4193 ) 4146 *11 5(CptPort4194 *116 (CptPort 4147 4195 uid 2369,0 4148 4196 ps "OnEdgeStrategy" … … 4182 4230 ) 4183 4231 ) 4184 *11 6(CptPort4232 *117 (CptPort 4185 4233 uid 2373,0 4186 4234 ps "OnEdgeStrategy" … … 4218 4266 ) 4219 4267 ) 4220 *11 7(CptPort4268 *118 (CptPort 4221 4269 uid 2377,0 4222 4270 ps "OnEdgeStrategy" … … 4257 4305 ) 4258 4306 ) 4259 *11 8(CptPort4307 *119 (CptPort 4260 4308 uid 2381,0 4261 4309 ps "OnEdgeStrategy" … … 4294 4342 ) 4295 4343 ) 4296 *1 19(CptPort4344 *120 (CptPort 4297 4345 uid 2385,0 4298 4346 ps "OnEdgeStrategy" … … 4334 4382 ) 4335 4383 ) 4336 *12 0(CptPort4384 *121 (CptPort 4337 4385 uid 2389,0 4338 4386 ps "OnEdgeStrategy" … … 4375 4423 ) 4376 4424 ) 4377 *12 1(CptPort4425 *122 (CptPort 4378 4426 uid 2393,0 4379 4427 ps "OnEdgeStrategy" … … 4414 4462 ) 4415 4463 ) 4416 *12 2(CptPort4464 *123 (CptPort 4417 4465 uid 2397,0 4418 4466 ps "OnEdgeStrategy" … … 4453 4501 ) 4454 4502 ) 4455 *12 3(CptPort4503 *124 (CptPort 4456 4504 uid 2401,0 4457 4505 ps "OnEdgeStrategy" … … 4492 4540 ) 4493 4541 ) 4494 *12 4(CptPort4542 *125 (CptPort 4495 4543 uid 2405,0 4496 4544 ps "OnEdgeStrategy" … … 4532 4580 ) 4533 4581 ) 4534 *12 5(CptPort4582 *126 (CptPort 4535 4583 uid 2454,0 4536 4584 ps "OnEdgeStrategy" … … 4568 4616 ) 4569 4617 ) 4570 *12 6(CptPort4618 *127 (CptPort 4571 4619 uid 2628,0 4572 4620 ps "OnEdgeStrategy" … … 4607 4655 ) 4608 4656 ) 4609 *12 7(CptPort4657 *128 (CptPort 4610 4658 uid 5991,0 4611 4659 ps "OnEdgeStrategy" … … 4645 4693 ) 4646 4694 ) 4647 *12 8(CptPort4695 *129 (CptPort 4648 4696 uid 8410,0 4649 4697 ps "OnEdgeStrategy" … … 4699 4747 stg "VerticalLayoutStrategy" 4700 4748 textVec [ 4701 *1 29(Text4749 *130 (Text 4702 4750 uid 2314,0 4703 4751 va (VaSet … … 4709 4757 tm "BdLibraryNameMgr" 4710 4758 ) 4711 *13 0(Text4759 *131 (Text 4712 4760 uid 2315,0 4713 4761 va (VaSet … … 4719 4767 tm "CptNameMgr" 4720 4768 ) 4721 *13 1(Text4769 *132 (Text 4722 4770 uid 2316,0 4723 4771 va (VaSet … … 4778 4826 archFileType "UNKNOWN" 4779 4827 ) 4780 *13 2(Net4828 *133 (Net 4781 4829 uid 2468,0 4782 4830 lang 2 … … 4792 4840 font "Courier New,8,0" 4793 4841 ) 4794 xt "-85000,8 1000,-62500,81800"4842 xt "-85000,82600,-62500,83400" 4795 4843 st "SIGNAL wiz_busy : std_logic 4796 4844 " 4797 4845 ) 4798 4846 ) 4799 *13 3(Net4847 *134 (Net 4800 4848 uid 2474,0 4801 4849 lang 2 … … 4812 4860 font "Courier New,8,0" 4813 4861 ) 4814 xt "-85000,8 3400,-41500,84200"4862 xt "-85000,85000,-41500,85800" 4815 4863 st "SIGNAL wiz_write_ea : std_logic := '0' 4816 4864 " 4817 4865 ) 4818 4866 ) 4819 *13 4(Net4867 *135 (Net 4820 4868 uid 2480,0 4821 4869 lang 2 … … 4833 4881 font "Courier New,8,0" 4834 4882 ) 4835 xt "-85000,8 5800,-35500,86600"4883 xt "-85000,87400,-35500,88200" 4836 4884 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') 4837 4885 " 4838 4886 ) 4839 4887 ) 4840 *13 5(Net4888 *136 (Net 4841 4889 uid 2486,0 4842 4890 lang 2 … … 4855 4903 font "Courier New,8,0" 4856 4904 ) 4857 xt "-85000,8 2600,-35500,83400"4905 xt "-85000,84200,-35500,85000" 4858 4906 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') 4859 4907 " 4860 4908 ) 4861 4909 ) 4862 *13 6(Net4910 *137 (Net 4863 4911 uid 2492,0 4864 4912 lang 2 … … 4876 4924 font "Courier New,8,0" 4877 4925 ) 4878 xt "-85000,8 1800,-35500,82600"4926 xt "-85000,83400,-35500,84200" 4879 4927 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') 4880 4928 " 4881 4929 ) 4882 4930 ) 4883 *13 7(Net4931 *138 (Net 4884 4932 uid 2498,0 4885 4933 lang 2 … … 4896 4944 font "Courier New,8,0" 4897 4945 ) 4898 xt "-85000,8 4200,-41500,85000"4946 xt "-85000,85800,-41500,86600" 4899 4947 st "SIGNAL wiz_write_end : std_logic := '0' 4900 4948 " 4901 4949 ) 4902 4950 ) 4903 *13 8(Net4951 *139 (Net 4904 4952 uid 2504,0 4905 4953 lang 2 … … 4916 4964 font "Courier New,8,0" 4917 4965 ) 4918 xt "-85000,8 5000,-41500,85800"4966 xt "-85000,86600,-41500,87400" 4919 4967 st "SIGNAL wiz_write_header : std_logic := '0' 4920 4968 " 4921 4969 ) 4922 4970 ) 4923 *1 39(Net4971 *140 (Net 4924 4972 uid 2574,0 4925 4973 decl (Decl … … 4939 4987 ) 4940 4988 ) 4941 *14 0(Net4989 *141 (Net 4942 4990 uid 2580,0 4943 4991 decl (Decl … … 4958 5006 ) 4959 5007 ) 4960 *14 1(Net5008 *142 (Net 4961 5009 uid 2586,0 4962 5010 decl (Decl … … 4977 5025 ) 4978 5026 ) 4979 *14 2(Net5027 *143 (Net 4980 5028 uid 2592,0 4981 5029 decl (Decl … … 4995 5043 ) 4996 5044 ) 4997 *14 3(Net5045 *144 (Net 4998 5046 uid 2598,0 4999 5047 decl (Decl … … 5013 5061 ) 5014 5062 ) 5015 *14 4(Net5063 *145 (Net 5016 5064 uid 2640,0 5017 5065 decl (Decl … … 5032 5080 ) 5033 5081 ) 5034 *14 5(Net5082 *146 (Net 5035 5083 uid 2776,0 5036 5084 decl (Decl … … 5051 5099 ) 5052 5100 ) 5053 *14 6(PortIoOut5101 *147 (PortIoOut 5054 5102 uid 2798,0 5055 5103 shape (CompositeShape … … 5096 5144 ) 5097 5145 ) 5098 *14 7(PortIoIn5146 *148 (PortIoIn 5099 5147 uid 2804,0 5100 5148 shape (CompositeShape … … 5141 5189 ) 5142 5190 ) 5143 *14 8(Net5191 *149 (Net 5144 5192 uid 2924,0 5145 5193 decl (Decl … … 5159 5207 ) 5160 5208 ) 5161 *1 49(PortIoIn5209 *150 (PortIoIn 5162 5210 uid 2950,0 5163 5211 shape (CompositeShape … … 5204 5252 ) 5205 5253 ) 5206 *15 0(PortIoIn5254 *151 (PortIoIn 5207 5255 uid 2956,0 5208 5256 shape (CompositeShape … … 5249 5297 ) 5250 5298 ) 5251 *15 1(Grouping5299 *152 (Grouping 5252 5300 uid 3137,0 5253 5301 optionalChildren [ 5254 *15 2(CommentText5302 *153 (CommentText 5255 5303 uid 3139,0 5256 5304 shape (Rectangle … … 5283 5331 titleBlock 1 5284 5332 ) 5285 *15 3(CommentText5333 *154 (CommentText 5286 5334 uid 3142,0 5287 5335 shape (Rectangle … … 5314 5362 titleBlock 1 5315 5363 ) 5316 *15 4(CommentText5364 *155 (CommentText 5317 5365 uid 3145,0 5318 5366 shape (Rectangle … … 5345 5393 titleBlock 1 5346 5394 ) 5347 *15 5(CommentText5395 *156 (CommentText 5348 5396 uid 3148,0 5349 5397 shape (Rectangle … … 5376 5424 titleBlock 1 5377 5425 ) 5378 *15 6(CommentText5426 *157 (CommentText 5379 5427 uid 3151,0 5380 5428 shape (Rectangle … … 5406 5454 titleBlock 1 5407 5455 ) 5408 *15 7(CommentText5456 *158 (CommentText 5409 5457 uid 3154,0 5410 5458 shape (Rectangle … … 5437 5485 titleBlock 1 5438 5486 ) 5439 *15 8(CommentText5487 *159 (CommentText 5440 5488 uid 3157,0 5441 5489 shape (Rectangle … … 5469 5517 titleBlock 1 5470 5518 ) 5471 *1 59(CommentText5519 *160 (CommentText 5472 5520 uid 3160,0 5473 5521 shape (Rectangle … … 5500 5548 titleBlock 1 5501 5549 ) 5502 *16 0(CommentText5550 *161 (CommentText 5503 5551 uid 3163,0 5504 5552 shape (Rectangle … … 5531 5579 titleBlock 1 5532 5580 ) 5533 *16 1(CommentText5581 *162 (CommentText 5534 5582 uid 3166,0 5535 5583 shape (Rectangle … … 5575 5623 oxt "14000,66000,55000,71000" 5576 5624 ) 5577 *16 2(Net5625 *163 (Net 5578 5626 uid 3894,0 5579 5627 decl (Decl … … 5593 5641 ) 5594 5642 ) 5595 *16 3(PortIoOut5643 *164 (PortIoOut 5596 5644 uid 3978,0 5597 5645 shape (CompositeShape … … 5638 5686 ) 5639 5687 ) 5640 *16 4(Net5688 *165 (Net 5641 5689 uid 4068,0 5642 5690 decl (Decl … … 5656 5704 ) 5657 5705 ) 5658 *16 5(SaComponent5706 *166 (SaComponent 5659 5707 uid 4194,0 5660 5708 optionalChildren [ 5661 *16 6(CptPort5709 *167 (CptPort 5662 5710 uid 4178,0 5663 5711 ps "OnEdgeStrategy" … … 5696 5744 ) 5697 5745 ) 5698 *16 7(CptPort5746 *168 (CptPort 5699 5747 uid 4182,0 5700 5748 ps "OnEdgeStrategy" … … 5733 5781 ) 5734 5782 ) 5735 *16 8(CptPort5783 *169 (CptPort 5736 5784 uid 4186,0 5737 5785 ps "OnEdgeStrategy" … … 5770 5818 ) 5771 5819 ) 5772 *1 69(CptPort5820 *170 (CptPort 5773 5821 uid 4190,0 5774 5822 ps "OnEdgeStrategy" … … 5822 5870 stg "VerticalLayoutStrategy" 5823 5871 textVec [ 5824 *17 0(Text5872 *171 (Text 5825 5873 uid 4197,0 5826 5874 va (VaSet … … 5832 5880 tm "BdLibraryNameMgr" 5833 5881 ) 5834 *17 1(Text5882 *172 (Text 5835 5883 uid 4198,0 5836 5884 va (VaSet … … 5842 5890 tm "CptNameMgr" 5843 5891 ) 5844 *17 2(Text5892 *173 (Text 5845 5893 uid 4199,0 5846 5894 va (VaSet … … 5889 5937 archFileType "UNKNOWN" 5890 5938 ) 5891 *17 3(Net5939 *174 (Net 5892 5940 uid 4204,0 5893 5941 decl (Decl … … 5907 5955 ) 5908 5956 ) 5909 *17 4(PortIoOut5957 *175 (PortIoOut 5910 5958 uid 4220,0 5911 5959 shape (CompositeShape … … 5952 6000 ) 5953 6001 ) 5954 *17 5(Net6002 *176 (Net 5955 6003 uid 4232,0 5956 6004 decl (Decl … … 5970 6018 ) 5971 6019 ) 5972 *17 6(Net6020 *177 (Net 5973 6021 uid 4260,0 5974 6022 decl (Decl … … 5989 6037 ) 5990 6038 ) 5991 *17 7(Net6039 *178 (Net 5992 6040 uid 4270,0 5993 6041 decl (Decl … … 6007 6055 ) 6008 6056 ) 6009 *17 8(PortIoIn6057 *179 (PortIoIn 6010 6058 uid 4307,0 6011 6059 shape (CompositeShape … … 6052 6100 ) 6053 6101 ) 6054 *1 79(Net6102 *180 (Net 6055 6103 uid 4399,0 6056 6104 decl (Decl … … 6071 6119 ) 6072 6120 ) 6073 *18 0(Net6121 *181 (Net 6074 6122 uid 4405,0 6075 6123 decl (Decl … … 6089 6137 ) 6090 6138 ) 6091 *18 1(Net6139 *182 (Net 6092 6140 uid 4417,0 6093 6141 decl (Decl … … 6108 6156 ) 6109 6157 ) 6110 *18 2(Net6158 *183 (Net 6111 6159 uid 4535,0 6112 6160 decl (Decl … … 6128 6176 ) 6129 6177 ) 6130 *18 3(Net6178 *184 (Net 6131 6179 uid 4543,0 6132 6180 decl (Decl … … 6147 6195 ) 6148 6196 ) 6149 *18 4(PortIoOut6197 *185 (PortIoOut 6150 6198 uid 4551,0 6151 6199 shape (CompositeShape … … 6192 6240 ) 6193 6241 ) 6194 *18 5(PortIoOut6242 *186 (PortIoOut 6195 6243 uid 4557,0 6196 6244 shape (CompositeShape … … 6237 6285 ) 6238 6286 ) 6239 *18 6(Net6287 *187 (Net 6240 6288 uid 4669,0 6241 6289 decl (Decl … … 6255 6303 ) 6256 6304 ) 6257 *18 7(Net6305 *188 (Net 6258 6306 uid 4677,0 6259 6307 decl (Decl … … 6273 6321 ) 6274 6322 ) 6275 *18 8(Net6323 *189 (Net 6276 6324 uid 4685,0 6277 6325 decl (Decl … … 6291 6339 ) 6292 6340 ) 6293 *1 89(Net6341 *190 (Net 6294 6342 uid 4693,0 6295 6343 decl (Decl … … 6309 6357 ) 6310 6358 ) 6311 *19 0(PortIoIn6359 *191 (PortIoIn 6312 6360 uid 4701,0 6313 6361 shape (CompositeShape … … 6354 6402 ) 6355 6403 ) 6356 *19 1(PortIoIn6404 *192 (PortIoIn 6357 6405 uid 4707,0 6358 6406 shape (CompositeShape … … 6399 6447 ) 6400 6448 ) 6401 *19 2(PortIoIn6449 *193 (PortIoIn 6402 6450 uid 4713,0 6403 6451 shape (CompositeShape … … 6444 6492 ) 6445 6493 ) 6446 *19 3(PortIoIn6494 *194 (PortIoIn 6447 6495 uid 4719,0 6448 6496 shape (CompositeShape … … 6489 6537 ) 6490 6538 ) 6491 *19 4(Net6539 *195 (Net 6492 6540 uid 4741,0 6493 6541 decl (Decl … … 6507 6555 ) 6508 6556 ) 6509 *19 5(SaComponent6557 *196 (SaComponent 6510 6558 uid 4903,0 6511 6559 optionalChildren [ 6512 *19 6(CptPort6560 *197 (CptPort 6513 6561 uid 4867,0 6514 6562 ps "OnEdgeStrategy" … … 6543 6591 ) 6544 6592 ) 6545 *19 7(CptPort6593 *198 (CptPort 6546 6594 uid 4871,0 6547 6595 ps "OnEdgeStrategy" … … 6577 6625 ) 6578 6626 ) 6579 *19 8(CptPort6627 *199 (CptPort 6580 6628 uid 4875,0 6581 6629 ps "OnEdgeStrategy" … … 6611 6659 ) 6612 6660 ) 6613 * 199(CptPort6661 *200 (CptPort 6614 6662 uid 4879,0 6615 6663 ps "OnEdgeStrategy" … … 6644 6692 ) 6645 6693 ) 6646 *20 0(CptPort6694 *201 (CptPort 6647 6695 uid 4883,0 6648 6696 ps "OnEdgeStrategy" … … 6677 6725 ) 6678 6726 ) 6679 *20 1(CptPort6727 *202 (CptPort 6680 6728 uid 4887,0 6681 6729 ps "OnEdgeStrategy" … … 6710 6758 ) 6711 6759 ) 6712 *20 2(CptPort6760 *203 (CptPort 6713 6761 uid 4891,0 6714 6762 ps "OnEdgeStrategy" … … 6743 6791 ) 6744 6792 ) 6745 *20 3(CptPort6793 *204 (CptPort 6746 6794 uid 4895,0 6747 6795 ps "OnEdgeStrategy" … … 6778 6826 ) 6779 6827 ) 6780 *20 4(CptPort6828 *205 (CptPort 6781 6829 uid 4899,0 6782 6830 ps "OnEdgeStrategy" … … 6814 6862 ) 6815 6863 ) 6816 *20 5(CptPort6864 *206 (CptPort 6817 6865 uid 4938,0 6818 6866 ps "OnEdgeStrategy" … … 6849 6897 ) 6850 6898 ) 6851 *20 6(CptPort6899 *207 (CptPort 6852 6900 uid 4942,0 6853 6901 ps "OnEdgeStrategy" … … 6901 6949 stg "VerticalLayoutStrategy" 6902 6950 textVec [ 6903 *20 7(Text6951 *208 (Text 6904 6952 uid 4906,0 6905 6953 va (VaSet … … 6911 6959 tm "BdLibraryNameMgr" 6912 6960 ) 6913 *20 8(Text6961 *209 (Text 6914 6962 uid 4907,0 6915 6963 va (VaSet … … 6921 6969 tm "CptNameMgr" 6922 6970 ) 6923 *2 09(Text6971 *210 (Text 6924 6972 uid 4908,0 6925 6973 va (VaSet … … 6968 7016 archFileType "UNKNOWN" 6969 7017 ) 6970 *21 0(Net7018 *211 (Net 6971 7019 uid 4946,0 6972 7020 decl (Decl … … 6987 7035 ) 6988 7036 ) 6989 *21 1(PortIoOut7037 *212 (PortIoOut 6990 7038 uid 4954,0 6991 7039 shape (CompositeShape … … 7032 7080 ) 7033 7081 ) 7034 *21 2(Net7082 *213 (Net 7035 7083 uid 4960,0 7036 7084 decl (Decl … … 7051 7099 ) 7052 7100 ) 7053 *21 3(PortIoOut7101 *214 (PortIoOut 7054 7102 uid 4968,0 7055 7103 shape (CompositeShape … … 7096 7144 ) 7097 7145 ) 7098 *21 4(SaComponent7146 *215 (SaComponent 7099 7147 uid 5072,0 7100 7148 optionalChildren [ 7101 *21 5(CptPort7149 *216 (CptPort 7102 7150 uid 5028,0 7103 7151 ps "OnEdgeStrategy" … … 7133 7181 ) 7134 7182 ) 7135 *21 6(CptPort7183 *217 (CptPort 7136 7184 uid 5032,0 7137 7185 ps "OnEdgeStrategy" … … 7169 7217 ) 7170 7218 ) 7171 *21 7(CptPort7219 *218 (CptPort 7172 7220 uid 5036,0 7173 7221 ps "OnEdgeStrategy" … … 7205 7253 ) 7206 7254 ) 7207 *21 8(CptPort7255 *219 (CptPort 7208 7256 uid 5040,0 7209 7257 ps "OnEdgeStrategy" … … 7241 7289 ) 7242 7290 ) 7243 *2 19(CptPort7291 *220 (CptPort 7244 7292 uid 5044,0 7245 7293 ps "OnEdgeStrategy" … … 7278 7326 ) 7279 7327 ) 7280 *22 0(CptPort7328 *221 (CptPort 7281 7329 uid 5048,0 7282 7330 ps "OnEdgeStrategy" … … 7313 7361 ) 7314 7362 ) 7315 *22 1(CptPort7363 *222 (CptPort 7316 7364 uid 5052,0 7317 7365 ps "OnEdgeStrategy" … … 7348 7396 ) 7349 7397 ) 7350 *22 2(CptPort7398 *223 (CptPort 7351 7399 uid 5056,0 7352 7400 ps "OnEdgeStrategy" … … 7383 7431 ) 7384 7432 ) 7385 *22 3(CptPort7433 *224 (CptPort 7386 7434 uid 5060,0 7387 7435 ps "OnEdgeStrategy" … … 7418 7466 ) 7419 7467 ) 7420 *22 4(CptPort7468 *225 (CptPort 7421 7469 uid 5064,0 7422 7470 ps "OnEdgeStrategy" … … 7452 7500 ) 7453 7501 ) 7454 *22 5(CptPort7502 *226 (CptPort 7455 7503 uid 5068,0 7456 7504 ps "OnEdgeStrategy" … … 7487 7535 ) 7488 7536 ) 7489 *22 6(CptPort7537 *227 (CptPort 7490 7538 uid 5995,0 7491 7539 ps "OnEdgeStrategy" … … 7523 7571 ) 7524 7572 ) 7525 *22 7(CptPort7573 *228 (CptPort 7526 7574 uid 8500,0 7527 7575 ps "OnEdgeStrategy" … … 7560 7608 ) 7561 7609 ) 7562 *22 8(CptPort7610 *229 (CptPort 7563 7611 uid 8504,0 7564 7612 ps "OnEdgeStrategy" … … 7613 7661 stg "VerticalLayoutStrategy" 7614 7662 textVec [ 7615 *2 29(Text7663 *230 (Text 7616 7664 uid 5075,0 7617 7665 va (VaSet … … 7623 7671 tm "BdLibraryNameMgr" 7624 7672 ) 7625 *23 0(Text7673 *231 (Text 7626 7674 uid 5076,0 7627 7675 va (VaSet … … 7633 7681 tm "CptNameMgr" 7634 7682 ) 7635 *23 1(Text7683 *232 (Text 7636 7684 uid 5077,0 7637 7685 va (VaSet … … 7679 7727 archFileType "UNKNOWN" 7680 7728 ) 7681 *23 2(Net7729 *233 (Net 7682 7730 uid 5088,0 7683 7731 decl (Decl … … 7698 7746 ) 7699 7747 ) 7700 *23 3(Net7748 *234 (Net 7701 7749 uid 5096,0 7702 7750 decl (Decl … … 7716 7764 ) 7717 7765 ) 7718 *23 4(Net7766 *235 (Net 7719 7767 uid 5104,0 7720 7768 decl (Decl … … 7734 7782 ) 7735 7783 ) 7736 *23 5(Net7784 *236 (Net 7737 7785 uid 5112,0 7738 7786 decl (Decl … … 7753 7801 ) 7754 7802 ) 7755 *23 6(Net7803 *237 (Net 7756 7804 uid 5120,0 7757 7805 decl (Decl … … 7771 7819 ) 7772 7820 ) 7773 *23 7(Net7821 *238 (Net 7774 7822 uid 5128,0 7775 7823 decl (Decl … … 7789 7837 ) 7790 7838 ) 7791 *23 8(Net7839 *239 (Net 7792 7840 uid 5144,0 7793 7841 decl (Decl … … 7807 7855 ) 7808 7856 ) 7809 *2 39(Net7857 *240 (Net 7810 7858 uid 5194,0 7811 7859 decl (Decl … … 7825 7873 ) 7826 7874 ) 7827 *24 0(Net7875 *241 (Net 7828 7876 uid 5196,0 7829 7877 decl (Decl … … 7843 7891 ) 7844 7892 ) 7845 *24 1(Net7893 *242 (Net 7846 7894 uid 5220,0 7847 7895 decl (Decl … … 7864 7912 ) 7865 7913 ) 7866 *24 2(Net7914 *243 (Net 7867 7915 uid 5279,0 7868 7916 decl (Decl … … 7883 7931 ) 7884 7932 ) 7885 *24 3(Net7933 *244 (Net 7886 7934 uid 5472,0 7887 7935 decl (Decl … … 7896 7944 font "Courier New,8,0" 7897 7945 ) 7898 xt "-85000, 78600,-62500,79400"7946 xt "-85000,80200,-62500,81000" 7899 7947 st "SIGNAL sensor_ready : std_logic 7900 7948 " 7901 7949 ) 7902 7950 ) 7903 *24 4(Net7951 *245 (Net 7904 7952 uid 5478,0 7905 7953 decl (Decl … … 7914 7962 font "Courier New,8,0" 7915 7963 ) 7916 xt "-85000,7 7800,-58500,78600"7964 xt "-85000,79400,-58500,80200" 7917 7965 st "SIGNAL sensor_array : sensor_array_type 7918 7966 " 7919 7967 ) 7920 7968 ) 7921 *24 5(Net7969 *246 (Net 7922 7970 uid 5588,0 7923 7971 decl (Decl … … 7937 7985 ) 7938 7986 ) 7939 *24 6(Net7987 *247 (Net 7940 7988 uid 5632,0 7941 7989 lang 10 … … 7957 8005 ) 7958 8006 ) 7959 *24 7(Net8007 *248 (Net 7960 8008 uid 5640,0 7961 8009 decl (Decl … … 7975 8023 ) 7976 8024 ) 7977 *24 8(SaComponent8025 *249 (SaComponent 7978 8026 uid 5678,0 7979 8027 optionalChildren [ 7980 *2 49(CptPort8028 *250 (CptPort 7981 8029 uid 5658,0 7982 8030 ps "OnEdgeStrategy" … … 8013 8061 ) 8014 8062 ) 8015 *25 0(CptPort8063 *251 (CptPort 8016 8064 uid 5662,0 8017 8065 ps "OnEdgeStrategy" … … 8050 8098 ) 8051 8099 ) 8052 *25 1(CptPort8100 *252 (CptPort 8053 8101 uid 5666,0 8054 8102 ps "OnEdgeStrategy" … … 8089 8137 ) 8090 8138 ) 8091 *25 2(CptPort8139 *253 (CptPort 8092 8140 uid 5670,0 8093 8141 ps "OnEdgeStrategy" … … 8125 8173 ) 8126 8174 ) 8127 *25 3(CptPort8175 *254 (CptPort 8128 8176 uid 5674,0 8129 8177 ps "OnEdgeStrategy" … … 8178 8226 stg "VerticalLayoutStrategy" 8179 8227 textVec [ 8180 *25 4(Text8228 *255 (Text 8181 8229 uid 5681,0 8182 8230 va (VaSet … … 8188 8236 tm "BdLibraryNameMgr" 8189 8237 ) 8190 *25 5(Text8238 *256 (Text 8191 8239 uid 5682,0 8192 8240 va (VaSet … … 8198 8246 tm "CptNameMgr" 8199 8247 ) 8200 *25 6(Text8248 *257 (Text 8201 8249 uid 5683,0 8202 8250 va (VaSet … … 8247 8295 archFileType "UNKNOWN" 8248 8296 ) 8249 *25 7(Net8297 *258 (Net 8250 8298 uid 5743,0 8251 8299 decl (Decl … … 8266 8314 ) 8267 8315 ) 8268 *25 8(SaComponent8316 *259 (SaComponent 8269 8317 uid 5793,0 8270 8318 optionalChildren [ 8271 *2 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(Rectangle … … 10459 10507 ) 10460 10508 ) 10461 *34 1(CommentText10509 *342 (CommentText 10462 10510 uid 8556,0 10463 10511 shape (Rectangle … … 10491 10539 ) 10492 10540 ) 10493 *34 2(CommentText10541 *343 (CommentText 10494 10542 uid 8559,0 10495 10543 shape (Rectangle … … 10542 10590 stg "VerticalLayoutStrategy" 10543 10591 textVec [ 10544 *34 3(Text10592 *344 (Text 10545 10593 uid 8565,0 10546 10594 va (VaSet … … 10552 10600 blo "-30650,102900" 10553 10601 ) 10554 *34 4(Text10602 *345 (Text 10555 10603 uid 8566,0 10556 10604 va (VaSet … … 10561 10609 blo "-30650,103900" 10562 10610 ) 10563 *34 5(Text10611 *346 (Text 10564 10612 uid 8567,0 10565 10613 va (VaSet … … 10607 10655 ) 10608 10656 ) 10609 *34 6(Net10657 *347 (Net 10610 10658 uid 8583,0 10611 10659 decl (Decl … … 10627 10675 ) 10628 10676 ) 10629 *347 (Wire 10677 *348 (MWC 10678 uid 8721,0 10679 optionalChildren [ 10680 *349 (CptPort 10681 uid 8693,0 10682 optionalChildren [ 10683 *350 (Line 10684 uid 8697,0 10685 layer 5 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va (VaSet 10802 vasetType 3 10803 ) 10804 xt "-8000,111000,-7000,111000" 10805 pts [ 10806 "-7000,111000" 10807 "-8000,111000" 10808 ] 10809 ) 10810 ] 10811 ps "OnEdgeStrategy" 10812 shape (Triangle 10813 uid 8705,0 10814 ro 270 10815 va (VaSet 10816 vasetType 1 10817 isHidden 1 10818 fg "0,65535,65535" 10819 ) 10820 xt "-7000,110625,-6250,111375" 10821 ) 10822 tg (CPTG 10823 uid 8706,0 10824 ps "CptPortTextPlaceStrategy" 10825 stg "RightVerticalLayoutStrategy" 10826 f (Text 10827 uid 8707,0 10828 sl 0 10829 va (VaSet 10830 isHidden 1 10831 font "arial,8,0" 10832 ) 10833 xt "-11250,340700,-9450,341700" 10834 st "din1" 10835 ju 2 10836 blo "-9450,341500" 10837 ) 10838 ) 10839 thePort (LogicalPort 10840 decl (Decl 10841 n "din1" 10842 t "std_logic" 10843 o 85 10844 suid 3,0 10845 ) 10846 ) 10847 ) 10848 *356 (CommentGraphic 10849 uid 8709,0 10850 optionalChildren [ 10851 *357 (Property 10852 uid 8711,0 10853 pclass "_MW_GEOM_" 10854 pname "expand" 10855 ptn "String" 10856 ) 10857 ] 10858 shape (PolyLine2D 10859 pts [ 10860 "-8000,110000" 10861 "-8000,110000" 10862 ] 10863 uid 8710,0 10864 layer 0 10865 sl 0 10866 va (VaSet 10867 vasetType 1 10868 transparent 1 10869 fg "49152,49152,49152" 10870 ) 10871 xt "-8000,110000,-8000,110000" 10872 ) 10873 oxt "11000,6000,11000,6000" 10874 ) 10875 *358 (CommentGraphic 10876 uid 8712,0 10877 optionalChildren [ 10878 *359 (Property 10879 uid 8714,0 10880 pclass "_MW_GEOM_" 10881 pname "expand" 10882 ptn "String" 10883 ) 10884 ] 10885 shape (PolyLine2D 10886 pts [ 10887 "-8000,114000" 10888 "-8000,114000" 10889 ] 10890 uid 8713,0 10891 layer 0 10892 sl 0 10893 va (VaSet 10894 vasetType 1 10895 transparent 1 10896 fg "49152,49152,49152" 10897 ) 10898 xt "-8000,114000,-8000,114000" 10899 ) 10900 oxt "11000,10000,11000,10000" 10901 ) 10902 *360 (Grouping 10903 uid 8715,0 10904 optionalChildren [ 10905 *361 (CommentGraphic 10906 uid 8717,0 10907 shape (PolyLine2D 10908 pts [ 10909 "-10000,110000" 10910 "-8000,110000" 10911 "-8000,114000" 10912 "-10000,114000" 10913 ] 10914 uid 8718,0 10915 layer 0 10916 sl 0 10917 va (VaSet 10918 vasetType 1 10919 fg "0,65535,65535" 10920 lineColor "26368,26368,26368" 10921 ) 10922 xt "-10000,110000,-8000,114000" 10923 ) 10924 oxt "9000,6000,11000,10000" 10925 ) 10926 *362 (CommentGraphic 10927 uid 8719,0 10928 shape (Arc2D 10929 pts [ 10930 "-10000,114000" 10931 "-12000,112000" 10932 "-10000,110000" 10933 ] 10934 uid 8720,0 10935 layer 0 10936 sl 0 10937 va (VaSet 10938 vasetType 1 10939 fg "0,65535,65535" 10940 lineColor "26368,26368,26368" 10941 ) 10942 xt "-12000,110000,-10000,114000" 10943 ) 10944 oxt "7000,6000,9000,10000" 10945 ) 10946 ] 10947 shape (GroupingShape 10948 uid 8716,0 10949 sl 0 10950 va (VaSet 10951 vasetType 1 10952 fg "65535,65535,65535" 10953 lineStyle 2 10954 lineWidth 2 10955 ) 10956 xt "-12000,110000,-8000,114000" 10957 ) 10958 oxt "7000,6000,11000,10000" 10959 ) 10960 ] 10961 shape (Rectangle 10962 uid 8722,0 10963 va (VaSet 10964 vasetType 1 10965 transparent 1 10966 fg "65535,65535,65535" 10967 lineWidth -1 10968 ) 10969 xt "-13000,110000,-7000,114000" 10970 fos 1 10971 ) 10972 showPorts 0 10973 oxt "6000,6000,12000,10000" 10974 ttg (MlTextGroup 10975 uid 8723,0 10976 ps "CenterOffsetStrategy" 10977 stg "VerticalLayoutStrategy" 10978 textVec [ 10979 *363 (Text 10980 uid 8724,0 10981 va (VaSet 10982 isHidden 1 10983 font "arial,8,0" 10984 ) 10985 xt "-11500,112500,-6700,113500" 10986 st "moduleware" 10987 blo "-11500,113300" 10988 ) 10989 *364 (Text 10990 uid 8725,0 10991 va (VaSet 10992 font "arial,8,0" 10993 ) 10994 xt "-11500,113500,-9900,114500" 10995 st "and" 10996 blo "-11500,114300" 10997 ) 10998 *365 (Text 10999 uid 8726,0 11000 va (VaSet 11001 font "arial,8,0" 11002 ) 11003 xt "-11500,114500,-9700,115500" 11004 st "U_1" 11005 blo "-11500,115300" 11006 tm "InstanceNameMgr" 11007 ) 11008 ] 11009 ) 11010 ga (GenericAssociation 11011 uid 8727,0 11012 ps "EdgeToEdgeStrategy" 11013 matrix (Matrix 11014 uid 8728,0 11015 text (MLText 11016 uid 8729,0 11017 va (VaSet 11018 font "arial,8,0" 11019 ) 11020 xt "-28000,101000,-28000,101000" 11021 ) 11022 header "" 11023 ) 11024 elements [ 11025 ] 11026 ) 11027 sed 1 11028 awe 1 11029 portVis (PortSigDisplay 11030 sN 0 11031 sTC 0 11032 selT 0 11033 ) 11034 prms (Property 11035 pclass "params" 11036 pname "params" 11037 ptn "String" 11038 ) 11039 de 1 11040 visOptions (mwParamsVisibilityOptions 11041 ) 11042 ) 11043 *366 (Net 11044 uid 8730,0 11045 decl (Decl 11046 n "sclk1" 11047 t "std_logic" 11048 o 85 11049 suid 191,0 11050 ) 11051 declText (MLText 11052 uid 8731,0 11053 va (VaSet 11054 font "Courier New,8,0" 11055 ) 11056 xt "-85000,77800,-62500,78600" 11057 st "SIGNAL sclk1 : std_logic 11058 " 11059 ) 11060 ) 11061 *367 (Net 11062 uid 8746,0 11063 decl (Decl 11064 n "sclk_enable" 11065 t "std_logic" 11066 o 86 11067 suid 194,0 11068 ) 11069 declText (MLText 11070 uid 8747,0 11071 va (VaSet 11072 font "Courier New,8,0" 11073 ) 11074 xt "-85000,78600,-62500,79400" 11075 st "SIGNAL sclk_enable : std_logic 11076 " 11077 ) 11078 ) 11079 *368 (Wire 10630 11080 uid 322,0 10631 11081 shape (OrthoPolyLine … … 10643 11093 ) 10644 11094 start &26 10645 end &31 511095 end &316 10646 11096 sat 32 10647 11097 eat 32 … … 10666 11116 on &2 10667 11117 ) 10668 *3 48(Wire11118 *369 (Wire 10669 11119 uid 328,0 10670 11120 shape (OrthoPolyLine … … 10682 11132 ) 10683 11133 start &25 10684 end &31 411134 end &315 10685 11135 sat 32 10686 11136 eat 32 … … 10705 11155 on &3 10706 11156 ) 10707 *3 49(Wire11157 *370 (Wire 10708 11158 uid 334,0 10709 11159 shape (OrthoPolyLine … … 10721 11171 ) 10722 11172 start &24 10723 end &31 311173 end &314 10724 11174 sat 32 10725 11175 eat 32 … … 10744 11194 on &4 10745 11195 ) 10746 *3 50(Wire11196 *371 (Wire 10747 11197 uid 364,0 10748 11198 shape (OrthoPolyLine … … 10761 11211 ) 10762 11212 start &79 10763 end &31 711213 end &318 10764 11214 sat 32 10765 11215 eat 32 … … 10784 11234 on &5 10785 11235 ) 10786 *3 51(Wire11236 *372 (Wire 10787 11237 uid 370,0 10788 11238 shape (OrthoPolyLine … … 10801 11251 ) 10802 11252 start &78 10803 end &31 811253 end &319 10804 11254 sat 32 10805 11255 eat 32 … … 10824 11274 on &6 10825 11275 ) 10826 *3 52(Wire11276 *373 (Wire 10827 11277 uid 376,0 10828 11278 shape (OrthoPolyLine … … 10862 11312 on &7 10863 11313 ) 10864 *3 53(Wire11314 *374 (Wire 10865 11315 uid 384,0 10866 11316 shape (OrthoPolyLine … … 10902 11352 on &8 10903 11353 ) 10904 *3 54(Wire11354 *375 (Wire 10905 11355 uid 392,0 10906 11356 shape (OrthoPolyLine … … 10942 11392 on &9 10943 11393 ) 10944 *3 55(Wire11394 *376 (Wire 10945 11395 uid 400,0 10946 11396 shape (OrthoPolyLine … … 10980 11430 on &10 10981 11431 ) 10982 *3 56(Wire11432 *377 (Wire 10983 11433 uid 408,0 10984 11434 shape (OrthoPolyLine … … 11018 11468 on &11 11019 11469 ) 11020 *3 57(Wire11470 *378 (Wire 11021 11471 uid 424,0 11022 11472 shape (OrthoPolyLine … … 11056 11506 on &12 11057 11507 ) 11058 *3 58(Wire11508 *379 (Wire 11059 11509 uid 432,0 11060 11510 shape (OrthoPolyLine … … 11094 11544 on &13 11095 11545 ) 11096 *3 59(Wire11546 *380 (Wire 11097 11547 uid 1411,0 11098 11548 shape (OrthoPolyLine … … 11108 11558 ] 11109 11559 ) 11110 start &1 4911560 start &150 11111 11561 end &28 11112 11562 sat 32 … … 11133 11583 on &64 11134 11584 ) 11135 *3 60(Wire11585 *381 (Wire 11136 11586 uid 1425,0 11137 11587 optionalChildren [ 11138 *3 61(BdJunction11588 *382 (BdJunction 11139 11589 uid 4391,0 11140 11590 ps "OnConnectorStrategy" … … 11186 11636 on &65 11187 11637 ) 11188 *3 62(Wire11638 *383 (Wire 11189 11639 uid 1682,0 11190 11640 shape (OrthoPolyLine … … 11200 11650 ] 11201 11651 ) 11202 start &15 011652 start &151 11203 11653 end &31 11204 11654 sat 32 … … 11223 11673 ) 11224 11674 ) 11225 on &10 011226 ) 11227 *3 63(Wire11675 on &101 11676 ) 11677 *384 (Wire 11228 11678 uid 1983,0 11229 11679 shape (OrthoPolyLine … … 11241 11691 ] 11242 11692 ) 11243 start &10 211693 start &103 11244 11694 end &29 11245 11695 sat 32 … … 11262 11712 ) 11263 11713 ) 11264 on &10 811265 ) 11266 *3 64(Wire11714 on &109 11715 ) 11716 *385 (Wire 11267 11717 uid 2299,0 11268 11718 shape (OrthoPolyLine … … 11280 11730 ] 11281 11731 ) 11282 start &11 111732 start &112 11283 11733 end &27 11284 11734 sat 32 … … 11302 11752 ) 11303 11753 ) 11304 on &1 0911305 ) 11306 *3 65(Wire11754 on &110 11755 ) 11756 *386 (Wire 11307 11757 uid 2470,0 11308 11758 shape (OrthoPolyLine … … 11318 11768 ] 11319 11769 ) 11320 start &11 811770 start &119 11321 11771 end &81 11322 11772 sat 32 … … 11339 11789 ) 11340 11790 ) 11341 on &13 211342 ) 11343 *3 66(Wire11791 on &133 11792 ) 11793 *387 (Wire 11344 11794 uid 2476,0 11345 11795 shape (OrthoPolyLine … … 11355 11805 ] 11356 11806 ) 11357 start &12 111807 start &122 11358 11808 end &80 11359 11809 sat 32 … … 11376 11826 ) 11377 11827 ) 11378 on &13 311379 ) 11380 *3 67(Wire11828 on &134 11829 ) 11830 *388 (Wire 11381 11831 uid 2482,0 11382 11832 shape (OrthoPolyLine … … 11393 11843 ] 11394 11844 ) 11395 start &12 411845 start &125 11396 11846 end &76 11397 11847 sat 32 … … 11415 11865 ) 11416 11866 ) 11417 on &13 411418 ) 11419 *3 68(Wire11867 on &135 11868 ) 11869 *389 (Wire 11420 11870 uid 2488,0 11421 11871 shape (OrthoPolyLine … … 11432 11882 ] 11433 11883 ) 11434 start &12 011884 start &121 11435 11885 end &77 11436 11886 sat 32 … … 11454 11904 ) 11455 11905 ) 11456 on &13 511457 ) 11458 *3 69(Wire11906 on &136 11907 ) 11908 *390 (Wire 11459 11909 uid 2494,0 11460 11910 shape (OrthoPolyLine … … 11471 11921 ] 11472 11922 ) 11473 start &1 1911923 start &120 11474 11924 end &82 11475 11925 sat 32 … … 11493 11943 ) 11494 11944 ) 11495 on &13 611496 ) 11497 *3 70(Wire11945 on &137 11946 ) 11947 *391 (Wire 11498 11948 uid 2500,0 11499 11949 shape (OrthoPolyLine … … 11509 11959 ] 11510 11960 ) 11511 start &12 211961 start &123 11512 11962 end &83 11513 11963 sat 32 … … 11530 11980 ) 11531 11981 ) 11532 on &13 711533 ) 11534 *3 71(Wire11982 on &138 11983 ) 11984 *392 (Wire 11535 11985 uid 2506,0 11536 11986 shape (OrthoPolyLine … … 11546 11996 ] 11547 11997 ) 11548 start &12 311998 start &124 11549 11999 end &84 11550 12000 sat 32 … … 11567 12017 ) 11568 12018 ) 11569 on &13 811570 ) 11571 *3 72(Wire12019 on &139 12020 ) 12021 *393 (Wire 11572 12022 uid 2576,0 11573 12023 shape (OrthoPolyLine … … 11585 12035 ) 11586 12036 start &32 11587 end &11 512037 end &116 11588 12038 sat 32 11589 12039 eat 32 … … 11605 12055 ) 11606 12056 ) 11607 on &1 3911608 ) 11609 *3 73(Wire12057 on &140 12058 ) 12059 *394 (Wire 11610 12060 uid 2582,0 11611 12061 shape (OrthoPolyLine … … 11623 12073 ) 11624 12074 start &33 11625 end &11 612075 end &117 11626 12076 sat 32 11627 12077 eat 32 … … 11643 12093 ) 11644 12094 ) 11645 on &14 011646 ) 11647 *3 74(Wire12095 on &141 12096 ) 12097 *395 (Wire 11648 12098 uid 2588,0 11649 12099 shape (OrthoPolyLine … … 11661 12111 ) 11662 12112 start &53 11663 end &11 412113 end &115 11664 12114 ss 0 11665 12115 sat 32 … … 11682 12132 ) 11683 12133 ) 11684 on &14 111685 ) 11686 *3 75(Wire12134 on &142 12135 ) 12136 *396 (Wire 11687 12137 uid 2594,0 11688 12138 shape (OrthoPolyLine … … 11700 12150 ) 11701 12151 start &49 11702 end &11 312152 end &114 11703 12153 sat 32 11704 12154 eat 32 … … 11720 12170 ) 11721 12171 ) 11722 on &14 211723 ) 11724 *3 76(Wire12172 on &143 12173 ) 12174 *397 (Wire 11725 12175 uid 2600,0 11726 12176 shape (OrthoPolyLine … … 11738 12188 ) 11739 12189 start &34 11740 end &11 712190 end &118 11741 12191 sat 32 11742 12192 eat 32 … … 11758 12208 ) 11759 12209 ) 11760 on &14 311761 ) 11762 *3 77(Wire12210 on &144 12211 ) 12212 *398 (Wire 11763 12213 uid 2642,0 11764 12214 shape (OrthoPolyLine … … 11777 12227 ) 11778 12228 start &36 11779 end &12 612229 end &127 11780 12230 sat 32 11781 12231 eat 32 … … 11798 12248 ) 11799 12249 ) 11800 on &14 411801 ) 11802 *3 78(Wire12250 on &145 12251 ) 12252 *399 (Wire 11803 12253 uid 2778,0 11804 12254 shape (OrthoPolyLine … … 11814 12264 ) 11815 12265 start &37 11816 end &14 612266 end &147 11817 12267 sat 32 11818 12268 eat 32 … … 11836 12286 ) 11837 12287 ) 11838 on &14 511839 ) 11840 * 379(Wire12288 on &146 12289 ) 12290 *400 (Wire 11841 12291 uid 2786,0 11842 12292 shape (OrthoPolyLine … … 11852 12302 ] 11853 12303 ) 11854 start &14 711855 end &25 212304 start &148 12305 end &253 11856 12306 sat 32 11857 12307 eat 32 … … 11876 12326 ) 11877 12327 ) 11878 on &17 611879 ) 11880 * 380(Wire12328 on &177 12329 ) 12330 *401 (Wire 11881 12331 uid 2876,0 11882 12332 shape (OrthoPolyLine … … 11892 12342 ] 11893 12343 ) 11894 start &3 6111895 end &10 312344 start &382 12345 end &104 11896 12346 es 0 11897 12347 sat 32 … … 11916 12366 on &65 11917 12367 ) 11918 * 381(Wire12368 *402 (Wire 11919 12369 uid 3888,0 11920 12370 optionalChildren [ 11921 * 382(BdJunction12371 *403 (BdJunction 11922 12372 uid 4230,0 11923 12373 ps "OnConnectorStrategy" … … 11931 12381 ) 11932 12382 ) 11933 * 383(BdJunction12383 *404 (BdJunction 11934 12384 uid 4244,0 11935 12385 ps "OnConnectorStrategy" … … 11958 12408 ] 11959 12409 ) 11960 start &16 612410 start &167 11961 12411 end &68 11962 12412 sat 32 … … 11980 12430 ) 11981 12431 ) 11982 on &16 411983 ) 11984 * 384(Wire12432 on &165 12433 ) 12434 *405 (Wire 11985 12435 uid 3984,0 11986 12436 shape (OrthoPolyLine … … 11998 12448 ] 11999 12449 ) 12000 start &16 312001 end &16 812450 start &164 12451 end &169 12002 12452 sat 32 12003 12453 eat 32 … … 12021 12471 ) 12022 12472 ) 12023 on &16 212024 ) 12025 * 385(Wire12473 on &163 12474 ) 12475 *406 (Wire 12026 12476 uid 4042,0 12027 12477 shape (OrthoPolyLine … … 12037 12487 ) 12038 12488 start &1 12039 end &1 6912489 end &170 12040 12490 sat 32 12041 12491 eat 32 … … 12059 12509 ) 12060 12510 ) 12061 on &17 512062 ) 12063 * 386(Wire12511 on &176 12512 ) 12513 *407 (Wire 12064 12514 uid 4226,0 12065 12515 shape (OrthoPolyLine … … 12076 12526 ] 12077 12527 ) 12078 start &17 412079 end & 38212528 start &175 12529 end &403 12080 12530 sat 32 12081 12531 eat 32 … … 12099 12549 ) 12100 12550 ) 12101 on &16 412102 ) 12103 * 387(Wire12551 on &165 12552 ) 12553 *408 (Wire 12104 12554 uid 4240,0 12105 12555 shape (OrthoPolyLine … … 12116 12566 ] 12117 12567 ) 12118 start &31 612119 end & 38312568 start &317 12569 end &404 12120 12570 sat 32 12121 12571 eat 32 … … 12138 12588 ) 12139 12589 ) 12140 on &16 412141 ) 12142 * 388(Wire12590 on &165 12591 ) 12592 *409 (Wire 12143 12593 uid 4272,0 12144 12594 shape (OrthoPolyLine … … 12153 12603 ] 12154 12604 ) 12155 start &17 812156 end &2 4912605 start &179 12606 end &250 12157 12607 sat 32 12158 12608 eat 32 … … 12176 12626 ) 12177 12627 ) 12178 on &17 712179 ) 12180 * 389(Wire12628 on &178 12629 ) 12630 *410 (Wire 12181 12631 uid 4401,0 12182 12632 shape (OrthoPolyLine … … 12192 12642 ) 12193 12643 start &40 12194 end &19 712644 end &198 12195 12645 sat 32 12196 12646 eat 32 … … 12212 12662 ) 12213 12663 ) 12214 on &1 7912215 ) 12216 * 390(Wire12664 on &180 12665 ) 12666 *411 (Wire 12217 12667 uid 4407,0 12218 12668 shape (OrthoPolyLine … … 12228 12678 ) 12229 12679 start &44 12230 end &20 312680 end &204 12231 12681 sat 32 12232 12682 eat 32 … … 12248 12698 ) 12249 12699 ) 12250 on &18 012251 ) 12252 * 391(Wire12700 on &181 12701 ) 12702 *412 (Wire 12253 12703 uid 4419,0 12254 12704 shape (OrthoPolyLine … … 12264 12714 ) 12265 12715 start &42 12266 end &19 812716 end &199 12267 12717 sat 32 12268 12718 eat 32 … … 12284 12734 ) 12285 12735 ) 12286 on &18 112287 ) 12288 * 392(Wire12736 on &182 12737 ) 12738 *413 (Wire 12289 12739 uid 4537,0 12290 12740 shape (OrthoPolyLine … … 12300 12750 ] 12301 12751 ) 12302 start &32 812303 end &18 412752 start &329 12753 end &185 12304 12754 sat 32 12305 12755 eat 32 … … 12324 12774 ) 12325 12775 ) 12326 on &18 212327 ) 12328 * 393(Wire12776 on &183 12777 ) 12778 *414 (Wire 12329 12779 uid 4545,0 12330 12780 shape (OrthoPolyLine … … 12339 12789 ] 12340 12790 ) 12341 start &29 312342 end &18 512791 start &294 12792 end &186 12343 12793 sat 32 12344 12794 eat 32 … … 12361 12811 ) 12362 12812 ) 12363 on &18 312364 ) 12365 * 394(Wire12813 on &184 12814 ) 12815 *415 (Wire 12366 12816 uid 4671,0 12367 12817 shape (OrthoPolyLine … … 12376 12826 ] 12377 12827 ) 12378 start &19 012379 end & 19912828 start &191 12829 end &200 12380 12830 sat 32 12381 12831 eat 32 … … 12399 12849 ) 12400 12850 ) 12401 on &18 612402 ) 12403 * 395(Wire12851 on &187 12852 ) 12853 *416 (Wire 12404 12854 uid 4679,0 12405 12855 shape (OrthoPolyLine … … 12414 12864 ] 12415 12865 ) 12416 start &19 112417 end &20 012866 start &192 12867 end &201 12418 12868 sat 32 12419 12869 eat 32 … … 12437 12887 ) 12438 12888 ) 12439 on &18 712440 ) 12441 * 396(Wire12889 on &188 12890 ) 12891 *417 (Wire 12442 12892 uid 4687,0 12443 12893 shape (OrthoPolyLine … … 12452 12902 ] 12453 12903 ) 12454 start &19 212455 end &20 112904 start &193 12905 end &202 12456 12906 sat 32 12457 12907 eat 32 … … 12475 12925 ) 12476 12926 ) 12477 on &18 812478 ) 12479 * 397(Wire12927 on &189 12928 ) 12929 *418 (Wire 12480 12930 uid 4695,0 12481 12931 shape (OrthoPolyLine … … 12490 12940 ] 12491 12941 ) 12492 start &19 312493 end &20 212942 start &194 12943 end &203 12494 12944 sat 32 12495 12945 eat 32 … … 12513 12963 ) 12514 12964 ) 12515 on &1 8912516 ) 12517 * 398(Wire12965 on &190 12966 ) 12967 *419 (Wire 12518 12968 uid 4743,0 12519 12969 shape (OrthoPolyLine … … 12528 12978 ] 12529 12979 ) 12530 start &20 412980 start &205 12531 12981 end &43 12532 12982 sat 32 … … 12549 12999 ) 12550 13000 ) 12551 on &19 412552 ) 12553 * 399(Wire13001 on &195 13002 ) 13003 *420 (Wire 12554 13004 uid 4757,0 12555 13005 optionalChildren [ 12556 *4 00(BdJunction13006 *421 (BdJunction 12557 13007 uid 6076,0 12558 13008 ps "OnConnectorStrategy" … … 12581 13031 ] 12582 13032 ) 12583 start &19 612584 end *4 01(BdJunction13033 start &197 13034 end *422 (BdJunction 12585 13035 uid 6080,0 12586 13036 ps "OnConnectorStrategy" … … 12614 13064 ) 12615 13065 ) 12616 on &17 312617 ) 12618 *4 02(Wire13066 on &174 13067 ) 13068 *423 (Wire 12619 13069 uid 4948,0 12620 13070 shape (OrthoPolyLine … … 12629 13079 ] 12630 13080 ) 12631 start &20 512632 end &21 113081 start &206 13082 end &212 12633 13083 sat 32 12634 13084 eat 32 … … 12652 13102 ) 12653 13103 ) 12654 on &21 012655 ) 12656 *4 03(Wire13104 on &211 13105 ) 13106 *424 (Wire 12657 13107 uid 4962,0 12658 13108 shape (OrthoPolyLine … … 12667 13117 ] 12668 13118 ) 12669 start &20 612670 end &21 313119 start &207 13120 end &214 12671 13121 sat 32 12672 13122 eat 32 … … 12690 13140 ) 12691 13141 ) 12692 on &21 212693 ) 12694 *4 04(Wire13142 on &213 13143 ) 13144 *425 (Wire 12695 13145 uid 5090,0 12696 13146 shape (OrthoPolyLine … … 12709 13159 ) 12710 13160 start &87 12711 end &21 613161 end &217 12712 13162 sat 32 12713 13163 eat 32 … … 12729 13179 ) 12730 13180 ) 12731 on &23 212732 ) 12733 *4 05(Wire13181 on &233 13182 ) 13183 *426 (Wire 12734 13184 uid 5098,0 12735 13185 shape (OrthoPolyLine … … 12744 13194 ] 12745 13195 ) 12746 start &21 713196 start &218 12747 13197 sat 32 12748 13198 eat 16 … … 12763 13213 ) 12764 13214 ) 12765 on &23 312766 ) 12767 *4 06(Wire13215 on &234 13216 ) 13217 *427 (Wire 12768 13218 uid 5106,0 12769 13219 shape (OrthoPolyLine … … 12780 13230 ] 12781 13231 ) 12782 start &21 813232 start &219 12783 13233 end &88 12784 13234 sat 32 … … 12800 13250 ) 12801 13251 ) 12802 on &23 412803 ) 12804 *4 07(Wire13252 on &235 13253 ) 13254 *428 (Wire 12805 13255 uid 5114,0 12806 13256 shape (OrthoPolyLine … … 12818 13268 ] 12819 13269 ) 12820 start &2 1913270 start &220 12821 13271 end &89 12822 13272 sat 32 … … 12839 13289 ) 12840 13290 ) 12841 on &23 512842 ) 12843 *4 08(Wire13291 on &236 13292 ) 13293 *429 (Wire 12844 13294 uid 5122,0 12845 13295 shape (OrthoPolyLine … … 12857 13307 ) 12858 13308 start &91 12859 end &22 113309 end &222 12860 13310 sat 32 12861 13311 eat 32 … … 12876 13326 ) 12877 13327 ) 12878 on &23 612879 ) 12880 *4 09(Wire13328 on &237 13329 ) 13330 *430 (Wire 12881 13331 uid 5130,0 12882 13332 shape (OrthoPolyLine … … 12894 13344 ) 12895 13345 start &93 12896 end &22 313346 end &224 12897 13347 sat 32 12898 13348 eat 32 … … 12913 13363 ) 12914 13364 ) 12915 on &23 712916 ) 12917 *4 10(Wire13365 on &238 13366 ) 13367 *431 (Wire 12918 13368 uid 5138,0 12919 13369 optionalChildren [ 12920 *4 11(BdJunction13370 *432 (BdJunction 12921 13371 uid 5400,0 12922 13372 ps "OnConnectorStrategy" … … 12944 13394 ] 12945 13395 ) 12946 start &22 013396 start &221 12947 13397 end &35 12948 13398 ss 0 … … 12966 13416 ) 12967 13417 ) 12968 on &14 812969 ) 12970 *4 12(Wire13418 on &149 13419 ) 13420 *433 (Wire 12971 13421 uid 5146,0 12972 13422 shape (OrthoPolyLine … … 12981 13431 ] 12982 13432 ) 12983 start &22 212984 end &26 013433 start &223 13434 end &261 12985 13435 es 0 12986 13436 sat 32 … … 13002 13452 ) 13003 13453 ) 13004 on &23 813005 ) 13006 *4 13(Wire13454 on &239 13455 ) 13456 *434 (Wire 13007 13457 uid 5168,0 13008 13458 shape (OrthoPolyLine … … 13017 13467 ] 13018 13468 ) 13019 start &4 1113020 end &12 513469 start &432 13470 end &126 13021 13471 sat 32 13022 13472 eat 32 … … 13038 13488 ) 13039 13489 ) 13040 on &14 813041 ) 13042 *4 14(Wire13490 on &149 13491 ) 13492 *435 (Wire 13043 13493 uid 5184,0 13044 13494 shape (OrthoPolyLine … … 13055 13505 ] 13056 13506 ) 13057 start &22 413507 start &225 13058 13508 end &47 13059 13509 sat 32 … … 13075 13525 ) 13076 13526 ) 13077 on &2 3913078 ) 13079 *4 15(Wire13527 on &240 13528 ) 13529 *436 (Wire 13080 13530 uid 5190,0 13081 13531 shape (OrthoPolyLine … … 13092 13542 ] 13093 13543 ) 13094 start &22 513544 start &226 13095 13545 end &46 13096 13546 sat 32 … … 13112 13562 ) 13113 13563 ) 13114 on &24 013115 ) 13116 *4 16(Wire13564 on &241 13565 ) 13566 *437 (Wire 13117 13567 uid 5222,0 13118 13568 shape (OrthoPolyLine … … 13152 13602 ) 13153 13603 ) 13154 on &24 113155 ) 13156 *4 17(Wire13604 on &242 13605 ) 13606 *438 (Wire 13157 13607 uid 5281,0 13158 13608 shape (OrthoPolyLine … … 13190 13640 ) 13191 13641 ) 13192 on &24 213193 ) 13194 *4 18(Wire13642 on &243 13643 ) 13644 *439 (Wire 13195 13645 uid 5404,0 13196 13646 shape (OrthoPolyLine … … 13207 13657 ] 13208 13658 ) 13209 start &26 113659 start &262 13210 13660 end &50 13211 13661 sat 32 … … 13227 13677 ) 13228 13678 ) 13229 on &24 513230 ) 13231 *4 19(Wire13679 on &246 13680 ) 13681 *440 (Wire 13232 13682 uid 5474,0 13233 13683 shape (OrthoPolyLine … … 13244 13694 ] 13245 13695 ) 13246 start &26 413696 start &265 13247 13697 end &52 13248 13698 sat 32 … … 13264 13714 ) 13265 13715 ) 13266 on &24 313267 ) 13268 *4 20(Wire13716 on &244 13717 ) 13718 *441 (Wire 13269 13719 uid 5480,0 13270 13720 shape (OrthoPolyLine … … 13281 13731 ] 13282 13732 ) 13283 start &26 313733 start &264 13284 13734 end &51 13285 13735 sat 32 … … 13301 13751 ) 13302 13752 ) 13303 on &24 413304 ) 13305 *4 21(Wire13753 on &245 13754 ) 13755 *442 (Wire 13306 13756 uid 5582,0 13307 13757 shape (OrthoPolyLine … … 13317 13767 ] 13318 13768 ) 13319 end &21 513769 end &216 13320 13770 sat 16 13321 13771 eat 32 … … 13336 13786 ) 13337 13787 ) 13338 on &16 413339 ) 13340 *4 22(Wire13788 on &165 13789 ) 13790 *443 (Wire 13341 13791 uid 5602,0 13342 13792 optionalChildren [ 13343 &4 0113344 *4 23(BdJunction13793 &422 13794 *444 (BdJunction 13345 13795 uid 6086,0 13346 13796 ps "OnConnectorStrategy" … … 13372 13822 ) 13373 13823 start &23 13374 end &31 213824 end &313 13375 13825 sat 32 13376 13826 eat 32 … … 13393 13843 ) 13394 13844 ) 13395 on &17 313396 ) 13397 *4 24(Wire13845 on &174 13846 ) 13847 *445 (Wire 13398 13848 uid 5626,0 13399 13849 shape (OrthoPolyLine … … 13409 13859 ) 13410 13860 start &45 13411 end &25 013861 end &251 13412 13862 sat 32 13413 13863 eat 32 … … 13429 13879 ) 13430 13880 ) 13431 on &24 713432 ) 13433 *4 25(Wire13881 on &248 13882 ) 13883 *446 (Wire 13434 13884 uid 5634,0 13435 13885 shape (OrthoPolyLine … … 13446 13896 ) 13447 13897 start &38 13448 end &25 113898 end &252 13449 13899 sat 32 13450 13900 eat 32 … … 13467 13917 ) 13468 13918 ) 13469 on &24 613470 ) 13471 *4 26(Wire13919 on &247 13920 ) 13921 *447 (Wire 13472 13922 uid 5646,0 13473 13923 shape (OrthoPolyLine … … 13483 13933 ] 13484 13934 ) 13485 end &25 313935 end &254 13486 13936 sat 16 13487 13937 eat 32 … … 13503 13953 ) 13504 13954 ) 13505 on &16 213506 ) 13507 *4 27(Wire13955 on &163 13956 ) 13957 *448 (Wire 13508 13958 uid 5745,0 13509 13959 shape (OrthoPolyLine … … 13521 13971 ) 13522 13972 start &54 13523 end &26 213973 end &263 13524 13974 sat 32 13525 13975 eat 32 … … 13541 13991 ) 13542 13992 ) 13543 on &25 713544 ) 13545 *4 28(Wire13993 on &258 13994 ) 13995 *449 (Wire 13546 13996 uid 5805,0 13547 13997 shape (OrthoPolyLine … … 13556 14006 ] 13557 14007 ) 13558 end &26 714008 end &268 13559 14009 sat 16 13560 14010 eat 32 … … 13575 14025 ) 13576 14026 ) 13577 on &16 413578 ) 13579 *4 29(Wire14027 on &165 14028 ) 14029 *450 (Wire 13580 14030 uid 5813,0 13581 14031 shape (OrthoPolyLine … … 13584 14034 vasetType 3 13585 14035 ) 13586 xt " 12000,107000,20250,107000"14036 xt "-18000,112000,-13000,112000" 13587 14037 pts [ 13588 " 20250,107000"13589 " 12000,107000"13590 ] 13591 ) 13592 start & 25913593 end &27 814038 "-13000,112000" 14039 "-18000,112000" 14040 ] 14041 ) 14042 start &349 14043 end &279 13594 14044 sat 32 13595 14045 eat 32 … … 13607 14057 isHidden 1 13608 14058 ) 13609 xt " 13000,106000,14700,107000"14059 xt "-17000,111000,-15300,112000" 13610 14060 st "sclk" 13611 blo " 13000,106800"14061 blo "-17000,111800" 13612 14062 tm "WireNameMgr" 13613 14063 ) 13614 14064 ) 13615 on &27 413616 ) 13617 *4 30(Wire14065 on &275 14066 ) 14067 *451 (Wire 13618 14068 uid 5821,0 13619 14069 shape (OrthoPolyLine … … 13628 14078 ] 13629 14079 ) 13630 start &27 013631 end &2 7914080 start &271 14081 end &280 13632 14082 sat 32 13633 14083 eat 32 … … 13651 14101 ) 13652 14102 ) 13653 on &27 513654 ) 13655 *4 31(Wire14103 on &276 14104 ) 14105 *452 (Wire 13656 14106 uid 5829,0 13657 14107 shape (OrthoPolyLine … … 13666 14116 ] 13667 14117 ) 13668 start &26 513669 end &28 014118 start &266 14119 end &281 13670 14120 sat 32 13671 14121 eat 32 … … 13689 14139 ) 13690 14140 ) 13691 on &27 613692 ) 13693 *4 32(Wire14141 on &277 14142 ) 14143 *453 (Wire 13694 14144 uid 5837,0 13695 14145 shape (OrthoPolyLine … … 13705 14155 ] 13706 14156 ) 13707 start &26 613708 end &28 114157 start &267 14158 end &282 13709 14159 sat 32 13710 14160 eat 32 … … 13729 14179 ) 13730 14180 ) 13731 on &27 713732 ) 13733 *4 33(Wire14181 on &278 14182 ) 14183 *454 (Wire 13734 14184 uid 5950,0 13735 14185 shape (OrthoPolyLine … … 13767 14217 ) 13768 14218 ) 13769 on &28 213770 ) 13771 *4 34(Wire14219 on &283 14220 ) 14221 *455 (Wire 13772 14222 uid 5962,0 13773 14223 shape (OrthoPolyLine … … 13805 14255 ) 13806 14256 ) 13807 on &28 313808 ) 13809 *4 35(Wire14257 on &284 14258 ) 14259 *456 (Wire 13810 14260 uid 6002,0 13811 14261 shape (OrthoPolyLine … … 13822 14272 ] 13823 14273 ) 13824 start &22 614274 start &227 13825 14275 end &57 13826 14276 sat 32 … … 13843 14293 ) 13844 14294 ) 13845 on &28 513846 ) 13847 *4 36(Wire14295 on &286 14296 ) 14297 *457 (Wire 13848 14298 uid 6008,0 13849 14299 shape (OrthoPolyLine … … 13860 14310 ] 13861 14311 ) 13862 start &26 814312 start &269 13863 14313 end &59 13864 14314 sat 32 … … 13881 14331 ) 13882 14332 ) 13883 on &28 413884 ) 13885 *4 37(Wire14333 on &285 14334 ) 14335 *458 (Wire 13886 14336 uid 6018,0 13887 14337 shape (OrthoPolyLine … … 13899 14349 ) 13900 14350 start &58 13901 end &12 714351 end &128 13902 14352 sat 32 13903 14353 eat 32 … … 13919 14369 ) 13920 14370 ) 13921 on &28 613922 ) 13923 *4 38(Wire14371 on &287 14372 ) 14373 *459 (Wire 13924 14374 uid 6064,0 13925 14375 shape (OrthoPolyLine … … 13954 14404 ) 13955 14405 ) 13956 on &23 813957 ) 13958 *4 39(Wire14406 on &239 14407 ) 14408 *460 (Wire 13959 14409 uid 6072,0 13960 14410 shape (OrthoPolyLine … … 13971 14421 ] 13972 14422 ) 13973 start &16 713974 end &4 0014423 start &168 14424 end &421 13975 14425 sat 32 13976 14426 eat 32 … … 13993 14443 ) 13994 14444 ) 13995 on &17 313996 ) 13997 *4 40(Wire14445 on &174 14446 ) 14447 *461 (Wire 13998 14448 uid 6082,0 13999 14449 shape (OrthoPolyLine … … 14010 14460 ] 14011 14461 ) 14012 start &11 214013 end &4 2314462 start &113 14463 end &444 14014 14464 sat 32 14015 14465 eat 32 … … 14032 14482 ) 14033 14483 ) 14034 on &17 314035 ) 14036 *4 41(Wire14484 on &174 14485 ) 14486 *462 (Wire 14037 14487 uid 6160,0 14038 14488 shape (OrthoPolyLine … … 14047 14497 ] 14048 14498 ) 14049 start &2 6914050 end &28 814499 start &270 14500 end &289 14051 14501 sat 32 14052 14502 eat 32 … … 14070 14520 ) 14071 14521 ) 14072 on &28 714073 ) 14074 *4 42(Wire14522 on &288 14523 ) 14524 *463 (Wire 14075 14525 uid 6276,0 14076 14526 shape (OrthoPolyLine … … 14085 14535 ] 14086 14536 ) 14087 end &10 414537 end &105 14088 14538 sat 16 14089 14539 eat 32 … … 14104 14554 ) 14105 14555 ) 14106 on &16 214107 ) 14108 *4 43(Wire14556 on &163 14557 ) 14558 *464 (Wire 14109 14559 uid 6362,0 14110 14560 shape (OrthoPolyLine … … 14120 14570 ) 14121 14571 start &94 14122 end &29 014572 end &291 14123 14573 sat 32 14124 14574 eat 32 … … 14142 14592 ) 14143 14593 ) 14144 on &2 8914145 ) 14146 *4 44(Wire14594 on &290 14595 ) 14596 *465 (Wire 14147 14597 uid 6452,0 14148 14598 shape (OrthoPolyLine … … 14179 14629 ) 14180 14630 ) 14181 on &29 114182 ) 14183 *4 45(Wire14631 on &292 14632 ) 14633 *466 (Wire 14184 14634 uid 6540,0 14185 14635 shape (OrthoPolyLine … … 14194 14644 ] 14195 14645 ) 14196 start &29 614646 start &297 14197 14647 end &41 14198 14648 sat 32 … … 14216 14666 ) 14217 14667 ) 14218 on &31 014219 ) 14220 *4 46(Wire14668 on &311 14669 ) 14670 *467 (Wire 14221 14671 uid 6548,0 14222 14672 shape (OrthoPolyLine … … 14231 14681 ] 14232 14682 ) 14233 start &29 814683 start &299 14234 14684 sat 32 14235 14685 eat 16 … … 14252 14702 ) 14253 14703 ) 14254 on &29 114255 ) 14256 *4 47(Wire14704 on &292 14705 ) 14706 *468 (Wire 14257 14707 uid 8416,0 14258 14708 shape (OrthoPolyLine … … 14267 14717 ] 14268 14718 ) 14269 start &12 814719 start &129 14270 14720 end &96 14271 14721 sat 32 … … 14288 14738 ) 14289 14739 ) 14290 on &32 214291 ) 14292 *4 48(Wire14740 on &323 14741 ) 14742 *469 (Wire 14293 14743 uid 8510,0 14294 14744 shape (OrthoPolyLine … … 14304 14754 ] 14305 14755 ) 14306 start &22 714756 start &228 14307 14757 sat 32 14308 14758 eat 16 … … 14325 14775 ) 14326 14776 ) 14327 on &32 314328 ) 14329 *4 49(Wire14777 on &324 14778 ) 14779 *470 (Wire 14330 14780 uid 8518,0 14331 14781 shape (OrthoPolyLine … … 14340 14790 ] 14341 14791 ) 14342 start &22 814792 start &229 14343 14793 sat 32 14344 14794 eat 16 … … 14360 14810 ) 14361 14811 ) 14362 on &32 414363 ) 14364 *4 50(Wire14812 on &325 14813 ) 14814 *471 (Wire 14365 14815 uid 8577,0 14366 14816 shape (OrthoPolyLine … … 14397 14847 ) 14398 14848 ) 14399 on &34 614400 ) 14401 *4 51(Wire14849 on &347 14850 ) 14851 *472 (Wire 14402 14852 uid 8587,0 14403 14853 shape (OrthoPolyLine … … 14413 14863 ] 14414 14864 ) 14415 end &32 614865 end &327 14416 14866 sat 16 14417 14867 eat 32 … … 14435 14885 ) 14436 14886 ) 14437 on &34 614438 ) 14439 *4 52(Wire14887 on &347 14888 ) 14889 *473 (Wire 14440 14890 uid 8595,0 14441 14891 shape (OrthoPolyLine … … 14451 14901 ] 14452 14902 ) 14453 end &33 114903 end &332 14454 14904 sat 16 14455 14905 eat 32 … … 14473 14923 ) 14474 14924 ) 14475 on &32 314476 ) 14477 *4 53(Wire14925 on &324 14926 ) 14927 *474 (Wire 14478 14928 uid 8603,0 14479 14929 shape (OrthoPolyLine … … 14489 14939 ] 14490 14940 ) 14491 end &33 314941 end &334 14492 14942 sat 16 14493 14943 eat 32 … … 14510 14960 ) 14511 14961 ) 14512 on &324 14962 on &325 14963 ) 14964 *475 (Wire 14965 uid 8732,0 14966 shape (OrthoPolyLine 14967 uid 8733,0 14968 va (VaSet 14969 vasetType 3 14970 ) 14971 xt "-7000,107000,20250,111000" 14972 pts [ 14973 "20250,107000" 14974 "-1000,107000" 14975 "-1000,111000" 14976 "-7000,111000" 14977 ] 14978 ) 14979 start &260 14980 end &354 14981 sat 32 14982 eat 32 14983 st 0 14984 sf 1 14985 si 0 14986 tg (WTG 14987 uid 8734,0 14988 ps "ConnStartEndStrategy" 14989 stg "STSignalDisplayStrategy" 14990 f (Text 14991 uid 8735,0 14992 va (VaSet 14993 ) 14994 xt "17250,106000,19350,107000" 14995 st "sclk1" 14996 blo "17250,106800" 14997 tm "WireNameMgr" 14998 ) 14999 ) 15000 on &366 15001 ) 15002 *476 (Wire 15003 uid 8738,0 15004 shape (OrthoPolyLine 15005 uid 8739,0 15006 va (VaSet 15007 vasetType 3 15008 ) 15009 xt "-7000,113000,4000,113000" 15010 pts [ 15011 "4000,113000" 15012 "-7000,113000" 15013 ] 15014 ) 15015 end &352 15016 sat 16 15017 eat 32 15018 stc 0 15019 st 0 15020 sf 1 15021 si 0 15022 tg (WTG 15023 uid 8742,0 15024 ps "ConnStartEndStrategy" 15025 stg "STSignalDisplayStrategy" 15026 f (Text 15027 uid 8743,0 15028 va (VaSet 15029 ) 15030 xt "-5000,112000,-300,113000" 15031 st "sclk_enable" 15032 blo "-5000,112800" 15033 tm "WireNameMgr" 15034 ) 15035 ) 15036 on &367 15037 ) 15038 *477 (Wire 15039 uid 8752,0 15040 shape (OrthoPolyLine 15041 uid 8753,0 15042 va (VaSet 15043 vasetType 3 15044 ) 15045 xt "148750,77000,156000,77000" 15046 pts [ 15047 "148750,77000" 15048 "156000,77000" 15049 ] 15050 ) 15051 start &97 15052 sat 32 15053 eat 16 15054 st 0 15055 sf 1 15056 si 0 15057 tg (WTG 15058 uid 8756,0 15059 ps "ConnStartEndStrategy" 15060 stg "STSignalDisplayStrategy" 15061 f (Text 15062 uid 8757,0 15063 va (VaSet 15064 ) 15065 xt "150000,76000,154700,77000" 15066 st "sclk_enable" 15067 blo "150000,76800" 15068 tm "WireNameMgr" 15069 ) 15070 ) 15071 on &367 14513 15072 ) 14514 15073 ] … … 14524 15083 color "26368,26368,26368" 14525 15084 ) 14526 packageList *4 54(PackageList15085 packageList *478 (PackageList 14527 15086 uid 41,0 14528 15087 stg "VerticalLayoutStrategy" 14529 15088 textVec [ 14530 *4 55(Text15089 *479 (Text 14531 15090 uid 42,0 14532 15091 va (VaSet … … 14537 15096 blo "-87000,1800" 14538 15097 ) 14539 *4 56(MLText15098 *480 (MLText 14540 15099 uid 43,0 14541 15100 va (VaSet … … 14562 15121 stg "VerticalLayoutStrategy" 14563 15122 textVec [ 14564 *4 57(Text15123 *481 (Text 14565 15124 uid 45,0 14566 15125 va (VaSet … … 14572 15131 blo "20000,800" 14573 15132 ) 14574 *4 58(Text15133 *482 (Text 14575 15134 uid 46,0 14576 15135 va (VaSet … … 14582 15141 blo "20000,1800" 14583 15142 ) 14584 *4 59(MLText15143 *483 (MLText 14585 15144 uid 47,0 14586 15145 va (VaSet … … 14592 15151 tm "BdCompilerDirectivesTextMgr" 14593 15152 ) 14594 *4 60(Text15153 *484 (Text 14595 15154 uid 48,0 14596 15155 va (VaSet … … 14602 15161 blo "20000,4800" 14603 15162 ) 14604 *4 61(MLText15163 *485 (MLText 14605 15164 uid 49,0 14606 15165 va (VaSet … … 14610 15169 tm "BdCompilerDirectivesTextMgr" 14611 15170 ) 14612 *4 62(Text15171 *486 (Text 14613 15172 uid 50,0 14614 15173 va (VaSet … … 14620 15179 blo "20000,5800" 14621 15180 ) 14622 *4 63(MLText15181 *487 (MLText 14623 15182 uid 51,0 14624 15183 va (VaSet … … 14632 15191 ) 14633 15192 windowSize "0,0,1281,1024" 14634 viewArea " -73966,37109,33461,125703"14635 cachedDiagramExtent "-100999,0,162300,3 01700"15193 viewArea "58743,41963,165915,130347" 15194 cachedDiagramExtent "-100999,0,162300,343294" 14636 15195 pageSetupInfo (PageSetupInfo 14637 15196 ptrCmd "eDocPrintPro,winspool," … … 14658 15217 hasePageBreakOrigin 1 14659 15218 pageBreakOrigin "-73000,0" 14660 lastUid 8 614,015219 lastUid 8761,0 14661 15220 defaultCommentText (CommentText 14662 15221 shape (Rectangle … … 14720 15279 stg "VerticalLayoutStrategy" 14721 15280 textVec [ 14722 *4 64(Text15281 *488 (Text 14723 15282 va (VaSet 14724 15283 font "Arial,8,1" … … 14729 15288 tm "BdLibraryNameMgr" 14730 15289 ) 14731 *4 65(Text15290 *489 (Text 14732 15291 va (VaSet 14733 15292 font "Arial,8,1" … … 14738 15297 tm "BlkNameMgr" 14739 15298 ) 14740 *4 66(Text15299 *490 (Text 14741 15300 va (VaSet 14742 15301 font "Arial,8,1" … … 14789 15348 stg "VerticalLayoutStrategy" 14790 15349 textVec [ 14791 *4 67(Text15350 *491 (Text 14792 15351 va (VaSet 14793 15352 font "Arial,8,1" … … 14797 15356 blo "550,4300" 14798 15357 ) 14799 *4 68(Text15358 *492 (Text 14800 15359 va (VaSet 14801 15360 font "Arial,8,1" … … 14805 15364 blo "550,5300" 14806 15365 ) 14807 *4 69(Text15366 *493 (Text 14808 15367 va (VaSet 14809 15368 font "Arial,8,1" … … 14854 15413 stg "VerticalLayoutStrategy" 14855 15414 textVec [ 14856 *4 70(Text15415 *494 (Text 14857 15416 va (VaSet 14858 15417 font "Arial,8,1" … … 14863 15422 tm "BdLibraryNameMgr" 14864 15423 ) 14865 *4 71(Text15424 *495 (Text 14866 15425 va (VaSet 14867 15426 font "Arial,8,1" … … 14872 15431 tm "CptNameMgr" 14873 15432 ) 14874 *4 72(Text15433 *496 (Text 14875 15434 va (VaSet 14876 15435 font "Arial,8,1" … … 14926 15485 stg "VerticalLayoutStrategy" 14927 15486 textVec [ 14928 *4 73(Text15487 *497 (Text 14929 15488 va (VaSet 14930 15489 font "Arial,8,1" … … 14934 15493 blo "500,4300" 14935 15494 ) 14936 *4 74(Text15495 *498 (Text 14937 15496 va (VaSet 14938 15497 font "Arial,8,1" … … 14942 15501 blo "500,5300" 14943 15502 ) 14944 *4 75(Text15503 *499 (Text 14945 15504 va (VaSet 14946 15505 font "Arial,8,1" … … 14987 15546 stg "VerticalLayoutStrategy" 14988 15547 textVec [ 14989 * 476(Text15548 *500 (Text 14990 15549 va (VaSet 14991 15550 font "Arial,8,1" … … 14995 15554 blo "50,4300" 14996 15555 ) 14997 * 477(Text15556 *501 (Text 14998 15557 va (VaSet 14999 15558 font "Arial,8,1" … … 15003 15562 blo "50,5300" 15004 15563 ) 15005 * 478(Text15564 *502 (Text 15006 15565 va (VaSet 15007 15566 font "Arial,8,1" … … 15044 15603 stg "VerticalLayoutStrategy" 15045 15604 textVec [ 15046 * 479(Text15605 *503 (Text 15047 15606 va (VaSet 15048 15607 font "Arial,8,1" … … 15053 15612 tm "HdlTextNameMgr" 15054 15613 ) 15055 * 480(Text15614 *504 (Text 15056 15615 va (VaSet 15057 15616 font "Arial,8,1" … … 15456 16015 stg "VerticalLayoutStrategy" 15457 16016 textVec [ 15458 * 481(Text16017 *505 (Text 15459 16018 va (VaSet 15460 16019 font "Arial,8,1" … … 15464 16023 blo "14100,20800" 15465 16024 ) 15466 * 482(MLText16025 *506 (MLText 15467 16026 va (VaSet 15468 16027 ) … … 15516 16075 stg "VerticalLayoutStrategy" 15517 16076 textVec [ 15518 * 483(Text16077 *507 (Text 15519 16078 va (VaSet 15520 16079 font "Arial,8,1" … … 15524 16083 blo "14100,20800" 15525 16084 ) 15526 * 484(MLText16085 *508 (MLText 15527 16086 va (VaSet 15528 16087 ) … … 15649 16208 font "Arial,8,1" 15650 16209 ) 15651 xt "-87000,8 7400,-82300,88400"16210 xt "-87000,89000,-82300,90000" 15652 16211 st "Post User:" 15653 blo "-87000,8 8200"16212 blo "-87000,89800" 15654 16213 ) 15655 16214 postUserText (MLText … … 15664 16223 commonDM (CommonDM 15665 16224 ldm (LogicalDM 15666 suid 19 0,016225 suid 194,0 15667 16226 usingSuid 1 15668 emptyRow * 485(LEmptyRow16227 emptyRow *509 (LEmptyRow 15669 16228 ) 15670 16229 uid 54,0 15671 16230 optionalChildren [ 15672 * 486(RefLabelRowHdr15673 ) 15674 * 487(TitleRowHdr15675 ) 15676 * 488(FilterRowHdr15677 ) 15678 * 489(RefLabelColHdr16231 *510 (RefLabelRowHdr 16232 ) 16233 *511 (TitleRowHdr 16234 ) 16235 *512 (FilterRowHdr 16236 ) 16237 *513 (RefLabelColHdr 15679 16238 tm "RefLabelColHdrMgr" 15680 16239 ) 15681 * 490(RowExpandColHdr16240 *514 (RowExpandColHdr 15682 16241 tm "RowExpandColHdrMgr" 15683 16242 ) 15684 * 491(GroupColHdr16243 *515 (GroupColHdr 15685 16244 tm "GroupColHdrMgr" 15686 16245 ) 15687 * 492(NameColHdr16246 *516 (NameColHdr 15688 16247 tm "BlockDiagramNameColHdrMgr" 15689 16248 ) 15690 * 493(ModeColHdr16249 *517 (ModeColHdr 15691 16250 tm "BlockDiagramModeColHdrMgr" 15692 16251 ) 15693 * 494(TypeColHdr16252 *518 (TypeColHdr 15694 16253 tm "BlockDiagramTypeColHdrMgr" 15695 16254 ) 15696 * 495(BoundsColHdr16255 *519 (BoundsColHdr 15697 16256 tm "BlockDiagramBoundsColHdrMgr" 15698 16257 ) 15699 * 496(InitColHdr16258 *520 (InitColHdr 15700 16259 tm "BlockDiagramInitColHdrMgr" 15701 16260 ) 15702 * 497(EolColHdr16261 *521 (EolColHdr 15703 16262 tm "BlockDiagramEolColHdrMgr" 15704 16263 ) 15705 * 498(LeafLogPort16264 *522 (LeafLogPort 15706 16265 port (LogicalPort 15707 16266 m 4 … … 15717 16276 uid 516,0 15718 16277 ) 15719 * 499(LeafLogPort16278 *523 (LeafLogPort 15720 16279 port (LogicalPort 15721 16280 m 4 … … 15730 16289 uid 518,0 15731 16290 ) 15732 *5 00(LeafLogPort16291 *524 (LeafLogPort 15733 16292 port (LogicalPort 15734 16293 m 4 … … 15743 16302 uid 520,0 15744 16303 ) 15745 *5 01(LeafLogPort16304 *525 (LeafLogPort 15746 16305 port (LogicalPort 15747 16306 m 4 … … 15756 16315 uid 530,0 15757 16316 ) 15758 *5 02(LeafLogPort16317 *526 (LeafLogPort 15759 16318 port (LogicalPort 15760 16319 m 4 … … 15769 16328 uid 532,0 15770 16329 ) 15771 *5 03(LeafLogPort16330 *527 (LeafLogPort 15772 16331 port (LogicalPort 15773 16332 m 1 … … 15782 16341 uid 534,0 15783 16342 ) 15784 *5 04(LeafLogPort16343 *528 (LeafLogPort 15785 16344 port (LogicalPort 15786 16345 m 1 … … 15795 16354 uid 536,0 15796 16355 ) 15797 *5 05(LeafLogPort16356 *529 (LeafLogPort 15798 16357 port (LogicalPort 15799 16358 m 2 … … 15808 16367 uid 538,0 15809 16368 ) 15810 *5 06(LeafLogPort16369 *530 (LeafLogPort 15811 16370 port (LogicalPort 15812 16371 m 1 … … 15821 16380 uid 540,0 15822 16381 ) 15823 *5 07(LeafLogPort16382 *531 (LeafLogPort 15824 16383 port (LogicalPort 15825 16384 m 1 … … 15834 16393 uid 542,0 15835 16394 ) 15836 *5 08(LeafLogPort16395 *532 (LeafLogPort 15837 16396 port (LogicalPort 15838 16397 m 1 … … 15847 16406 uid 546,0 15848 16407 ) 15849 *5 09(LeafLogPort16408 *533 (LeafLogPort 15850 16409 port (LogicalPort 15851 16410 decl (Decl … … 15858 16417 uid 548,0 15859 16418 ) 15860 *5 10(LeafLogPort16419 *534 (LeafLogPort 15861 16420 port (LogicalPort 15862 16421 decl (Decl … … 15872 16431 uid 1455,0 15873 16432 ) 15874 *5 11(LeafLogPort16433 *535 (LeafLogPort 15875 16434 port (LogicalPort 15876 16435 decl (Decl … … 15885 16444 uid 1457,0 15886 16445 ) 15887 *5 12(LeafLogPort16446 *536 (LeafLogPort 15888 16447 port (LogicalPort 15889 16448 decl (Decl … … 15897 16456 uid 1694,0 15898 16457 ) 15899 *5 13(LeafLogPort16458 *537 (LeafLogPort 15900 16459 port (LogicalPort 15901 16460 lang 2 … … 15913 16472 uid 1993,0 15914 16473 ) 15915 *5 14(LeafLogPort16474 *538 (LeafLogPort 15916 16475 port (LogicalPort 15917 16476 m 4 … … 15928 16487 uid 2305,0 15929 16488 ) 15930 *5 15(LeafLogPort16489 *539 (LeafLogPort 15931 16490 port (LogicalPort 15932 16491 lang 2 … … 15941 16500 uid 2510,0 15942 16501 ) 15943 *5 16(LeafLogPort16502 *540 (LeafLogPort 15944 16503 port (LogicalPort 15945 16504 lang 2 … … 15955 16514 uid 2512,0 15956 16515 ) 15957 *5 17(LeafLogPort16516 *541 (LeafLogPort 15958 16517 port (LogicalPort 15959 16518 lang 2 … … 15970 16529 uid 2514,0 15971 16530 ) 15972 *5 18(LeafLogPort16531 *542 (LeafLogPort 15973 16532 port (LogicalPort 15974 16533 lang 2 … … 15986 16545 uid 2516,0 15987 16546 ) 15988 *5 19(LeafLogPort16547 *543 (LeafLogPort 15989 16548 port (LogicalPort 15990 16549 lang 2 … … 16001 16560 uid 2518,0 16002 16561 ) 16003 *5 20(LeafLogPort16562 *544 (LeafLogPort 16004 16563 port (LogicalPort 16005 16564 lang 2 … … 16015 16574 uid 2520,0 16016 16575 ) 16017 *5 21(LeafLogPort16576 *545 (LeafLogPort 16018 16577 port (LogicalPort 16019 16578 lang 2 … … 16029 16588 uid 2522,0 16030 16589 ) 16031 *5 22(LeafLogPort16590 *546 (LeafLogPort 16032 16591 port (LogicalPort 16033 16592 m 4 … … 16041 16600 uid 2604,0 16042 16601 ) 16043 *5 23(LeafLogPort16602 *547 (LeafLogPort 16044 16603 port (LogicalPort 16045 16604 m 4 … … 16054 16613 uid 2606,0 16055 16614 ) 16056 *5 24(LeafLogPort16615 *548 (LeafLogPort 16057 16616 port (LogicalPort 16058 16617 m 4 … … 16067 16626 uid 2608,0 16068 16627 ) 16069 *5 25(LeafLogPort16628 *549 (LeafLogPort 16070 16629 port (LogicalPort 16071 16630 m 4 … … 16079 16638 uid 2610,0 16080 16639 ) 16081 *5 26(LeafLogPort16640 *550 (LeafLogPort 16082 16641 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litem &520 17385 17980 pos 6 17386 17981 dimension 50 17387 17982 uid 80,0 17388 17983 ) 17389 * 678(MRCItem17390 litem & 49717984 *706 (MRCItem 17985 litem &521 17391 17986 pos 7 17392 17987 dimension 80 … … 17408 18003 genericsCommonDM (CommonDM 17409 18004 ldm (LogicalDM 17410 emptyRow * 679(LEmptyRow18005 emptyRow *707 (LEmptyRow 17411 18006 ) 17412 18007 uid 83,0 17413 18008 optionalChildren [ 17414 * 680(RefLabelRowHdr17415 ) 17416 * 681(TitleRowHdr17417 ) 17418 * 682(FilterRowHdr17419 ) 17420 * 683(RefLabelColHdr18009 *708 (RefLabelRowHdr 18010 ) 18011 *709 (TitleRowHdr 18012 ) 18013 *710 (FilterRowHdr 18014 ) 18015 *711 (RefLabelColHdr 17421 18016 tm "RefLabelColHdrMgr" 17422 18017 ) 17423 * 684(RowExpandColHdr18018 *712 (RowExpandColHdr 17424 18019 tm "RowExpandColHdrMgr" 17425 18020 ) 17426 * 685(GroupColHdr18021 *713 (GroupColHdr 17427 18022 tm "GroupColHdrMgr" 17428 18023 ) 17429 * 686(NameColHdr18024 *714 (NameColHdr 17430 18025 tm "GenericNameColHdrMgr" 17431 18026 ) 17432 * 687(TypeColHdr18027 *715 (TypeColHdr 17433 18028 tm "GenericTypeColHdrMgr" 17434 18029 ) 17435 * 688(InitColHdr18030 *716 (InitColHdr 17436 18031 tm "GenericValueColHdrMgr" 17437 18032 ) 17438 * 689(PragmaColHdr18033 *717 (PragmaColHdr 17439 18034 tm "GenericPragmaColHdrMgr" 17440 18035 ) 17441 * 690(EolColHdr18036 *718 (EolColHdr 17442 18037 tm "GenericEolColHdrMgr" 17443 18038 ) 17444 * 691(LogGeneric18039 *719 (LogGeneric 17445 18040 generic (GiElement 17446 18041 name "RAMADDRWIDTH64b" … … 17457 18052 uid 95,0 17458 18053 optionalChildren [ 17459 * 692(Sheet18054 *720 (Sheet 17460 18055 sheetRow (SheetRow 17461 18056 headerVa (MVa … … 17474 18069 font "Tahoma,10,0" 17475 18070 ) 17476 emptyMRCItem * 693(MRCItem17477 litem & 67918071 emptyMRCItem *721 (MRCItem 18072 litem &707 17478 18073 pos 1 17479 18074 dimension 20 … … 17481 18076 uid 97,0 17482 18077 optionalChildren [ 17483 * 694(MRCItem17484 litem & 68018078 *722 (MRCItem 18079 litem &708 17485 18080 pos 0 17486 18081 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FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak
r252 r260 152 152 uid 8277,0 153 153 ) 154 (Instance 155 name "U_0" 156 duLibraryName "moduleware" 157 duName "mux" 158 elements [ 159 ] 160 mwi 1 161 uid 8562,0 162 ) 154 163 ] 155 164 libraryRefs [ … … 359 368 (vvPair 360 369 variable "time" 361 value "1 1:42:03"370 value "14:21:30" 362 371 ) 363 372 (vvPair … … 450 459 font "Courier New,8,0" 451 460 ) 452 xt "-85000,84200,-41500,85000" 453 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\"" 461 xt "-85000,86600,-41500,87400" 462 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\" 463 " 454 464 ) 455 465 ) … … 469 479 ) 470 480 xt "-85000,47400,-45000,48200" 471 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 481 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 482 " 472 483 ) 473 484 ) … … 487 498 ) 488 499 xt "-85000,61800,-52500,62600" 489 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0)" 500 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0) 501 " 490 502 ) 491 503 ) … … 504 516 font "Courier New,8,0" 505 517 ) 506 xt "-85000,69000,-45000,69800" 507 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)" 518 xt "-85000,71400,-45000,72200" 519 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) 520 " 508 521 ) 509 522 ) … … 522 535 font "Courier New,8,0" 523 536 ) 524 xt "-85000,69800,-52500,70600" 525 st "SIGNAL ram_data : std_logic_vector(15 downto 0)" 537 xt "-85000,72200,-52500,73000" 538 st "SIGNAL ram_data : std_logic_vector(15 downto 0) 539 " 526 540 ) 527 541 ) … … 541 555 ) 542 556 xt "-85000,39800,-45000,40600" 543 st "wiz_reset : std_logic := '1'" 557 st "wiz_reset : std_logic := '1' 558 " 544 559 ) 545 560 ) … … 559 574 ) 560 575 xt "-85000,37400,-56500,38200" 561 st "wiz_addr : std_logic_vector(9 DOWNTO 0)" 576 st "wiz_addr : std_logic_vector(9 DOWNTO 0) 577 " 562 578 ) 563 579 ) … … 577 593 ) 578 594 xt "-85000,42200,-56000,43000" 579 st "wiz_data : std_logic_vector(15 DOWNTO 0)" 595 st "wiz_data : std_logic_vector(15 DOWNTO 0) 596 " 580 597 ) 581 598 ) … … 595 612 ) 596 613 xt "-85000,38200,-45000,39000" 597 st "wiz_cs : std_logic := '1'" 614 st "wiz_cs : std_logic := '1' 615 " 598 616 ) 599 617 ) … … 613 631 ) 614 632 xt "-85000,40600,-45000,41400" 615 st "wiz_wr : std_logic := '1'" 633 st "wiz_wr : std_logic := '1' 634 " 616 635 ) 617 636 ) … … 631 650 ) 632 651 xt "-85000,39000,-45000,39800" 633 st "wiz_rd : std_logic := '1'" 652 st "wiz_rd : std_logic := '1' 653 " 634 654 ) 635 655 ) … … 648 668 ) 649 669 xt "-85000,26200,-66500,27000" 650 st "wiz_int : std_logic" 670 st "wiz_int : std_logic 671 " 651 672 ) 652 673 ) … … 2473 2494 ) 2474 2495 xt "-85000,23800,-56500,24600" 2475 st "board_id : std_logic_vector(3 downto 0)" 2496 st "board_id : std_logic_vector(3 downto 0) 2497 " 2476 2498 ) 2477 2499 ) … … 2492 2514 ) 2493 2515 xt "-85000,25400,-66500,26200" 2494 st "trigger : std_logic" 2516 st "trigger : std_logic 2517 " 2495 2518 ) 2496 2519 ) … … 3720 3743 ) 3721 3744 xt "-85000,24600,-56500,25400" 3722 st "crate_id : std_logic_vector(1 downto 0)" 3745 st "crate_id : std_logic_vector(1 downto 0) 3746 " 3723 3747 ) 3724 3748 ) … … 3940 3964 font "Courier New,8,0" 3941 3965 ) 3942 xt "-85000,77000,-52500,77800" 3943 st "SIGNAL trigger_id : std_logic_vector(47 downto 0)" 3966 xt "-85000,79400,-52500,80200" 3967 st "SIGNAL trigger_id : std_logic_vector(47 downto 0) 3968 " 3944 3969 ) 3945 3970 ) … … 3960 3985 font "Courier New,8,0" 3961 3986 ) 3962 xt "-85000,70600,-45000,71400" 3963 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 3987 xt "-85000,73000,-45000,73800" 3988 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 3989 " 3964 3990 ) 3965 3991 ) … … 4766 4792 font "Courier New,8,0" 4767 4793 ) 4768 xt "-85000,78600,-62500,79400" 4769 st "SIGNAL wiz_busy : std_logic" 4794 xt "-85000,81000,-62500,81800" 4795 st "SIGNAL wiz_busy : std_logic 4796 " 4770 4797 ) 4771 4798 ) … … 4785 4812 font "Courier New,8,0" 4786 4813 ) 4787 xt "-85000,81000,-41500,81800" 4788 st "SIGNAL wiz_write_ea : std_logic := '0'" 4814 xt "-85000,83400,-41500,84200" 4815 st "SIGNAL wiz_write_ea : std_logic := '0' 4816 " 4789 4817 ) 4790 4818 ) … … 4805 4833 font "Courier New,8,0" 4806 4834 ) 4807 xt "-85000,83400,-35500,84200" 4808 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0')" 4835 xt "-85000,85800,-35500,86600" 4836 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') 4837 " 4809 4838 ) 4810 4839 ) … … 4826 4855 font "Courier New,8,0" 4827 4856 ) 4828 xt "-85000,80200,-35500,81000" 4829 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')" 4857 xt "-85000,82600,-35500,83400" 4858 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') 4859 " 4830 4860 ) 4831 4861 ) … … 4846 4876 font "Courier New,8,0" 4847 4877 ) 4848 xt "-85000,79400,-35500,80200" 4849 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0')" 4878 xt "-85000,81800,-35500,82600" 4879 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') 4880 " 4850 4881 ) 4851 4882 ) … … 4865 4896 font "Courier New,8,0" 4866 4897 ) 4867 xt "-85000,81800,-41500,82600" 4868 st "SIGNAL wiz_write_end : std_logic := '0'" 4898 xt "-85000,84200,-41500,85000" 4899 st "SIGNAL wiz_write_end : std_logic := '0' 4900 " 4869 4901 ) 4870 4902 ) … … 4884 4916 font "Courier New,8,0" 4885 4917 ) 4886 xt "-85000,82600,-41500,83400" 4887 st "SIGNAL wiz_write_header : std_logic := '0'" 4918 xt "-85000,85000,-41500,85800" 4919 st "SIGNAL wiz_write_header : std_logic := '0' 4920 " 4888 4921 ) 4889 4922 ) … … 4901 4934 font "Courier New,8,0" 4902 4935 ) 4903 xt "-85000,71400,-62500,72200" 4904 st "SIGNAL ram_write_ea : std_logic" 4936 xt "-85000,73800,-62500,74600" 4937 st "SIGNAL ram_write_ea : std_logic 4938 " 4905 4939 ) 4906 4940 ) … … 4919 4953 font "Courier New,8,0" 4920 4954 ) 4921 xt "-85000,72200,-41500,73000" 4922 st "SIGNAL ram_write_ready : std_logic := '0'" 4955 xt "-85000,74600,-41500,75400" 4956 st "SIGNAL ram_write_ready : std_logic := '0' 4957 " 4923 4958 ) 4924 4959 ) … … 4938 4973 ) 4939 4974 xt "-85000,54600,-41500,55400" 4940 st "SIGNAL config_start : std_logic := '0'" 4975 st "SIGNAL config_start : std_logic := '0' 4976 " 4941 4977 ) 4942 4978 ) … … 4955 4991 ) 4956 4992 xt "-85000,52200,-62500,53000" 4957 st "SIGNAL config_ready : std_logic" 4993 st "SIGNAL config_ready : std_logic 4994 " 4958 4995 ) 4959 4996 ) … … 4971 5008 font "Courier New,8,0" 4972 5009 ) 4973 xt "-85000,73800,-61000,74600" 4974 st "SIGNAL roi_max : roi_max_type" 5010 xt "-85000,76200,-61000,77000" 5011 st "SIGNAL roi_max : roi_max_type 5012 " 4975 5013 ) 4976 5014 ) … … 4989 5027 font "Courier New,8,0" 4990 5028 ) 4991 xt "-85000,68200,-52500,69000" 4992 st "SIGNAL package_length : std_logic_vector(15 downto 0)" 5029 xt "-85000,70600,-52500,71400" 5030 st "SIGNAL package_length : std_logic_vector(15 downto 0) 5031 " 4993 5032 ) 4994 5033 ) … … 5008 5047 ) 5009 5048 xt "-85000,30200,-45000,31000" 5010 st "adc_oeb : std_logic := '1'" 5049 st "adc_oeb : std_logic := '1' 5050 " 5011 5051 ) 5012 5052 ) … … 5114 5154 font "Courier New,8,0" 5115 5155 ) 5116 xt "-85000,73000,-60000,73800" 5117 st "SIGNAL roi_array : roi_array_type" 5156 xt "-85000,75400,-60000,76200" 5157 st "SIGNAL roi_array : roi_array_type 5158 " 5118 5159 ) 5119 5160 ) … … 5548 5589 ) 5549 5590 xt "-85000,27000,-66500,27800" 5550 st "CLK_25_PS : std_logic" 5591 st "CLK_25_PS : std_logic 5592 " 5551 5593 ) 5552 5594 ) … … 5610 5652 ) 5611 5653 xt "-85000,27800,-66500,28600" 5612 st "CLK_50 : std_logic" 5654 st "CLK_50 : std_logic 5655 " 5613 5656 ) 5614 5657 ) … … 5860 5903 ) 5861 5904 xt "-85000,45000,-62500,45800" 5862 st "SIGNAL CLK_25 : std_logic" 5905 st "SIGNAL CLK_25 : std_logic 5906 " 5863 5907 ) 5864 5908 ) … … 5922 5966 ) 5923 5967 xt "-85000,18200,-66500,19000" 5924 st "CLK : std_logic" 5968 st "CLK : std_logic 5969 " 5925 5970 ) 5926 5971 ) … … 5940 5985 ) 5941 5986 xt "-85000,23000,-56500,23800" 5942 st "adc_otr_array : std_logic_vector(3 DOWNTO 0)" 5987 st "adc_otr_array : std_logic_vector(3 DOWNTO 0) 5988 " 5943 5989 ) 5944 5990 ) … … 5957 6003 ) 5958 6004 xt "-85000,22200,-61000,23000" 5959 st "adc_data_array : adc_data_array_type" 6005 st "adc_data_array : adc_data_array_type 6006 " 5960 6007 ) 5961 6008 ) … … 6019 6066 font "Courier New,8,0" 6020 6067 ) 6021 xt "-85000,62600,-41500,63400" 6022 st "SIGNAL drs_clk_en : std_logic := '0'" 6068 xt "-85000,65000,-41500,65800" 6069 st "SIGNAL drs_clk_en : std_logic := '0' 6070 " 6023 6071 ) 6024 6072 ) … … 6036 6084 font "Courier New,8,0" 6037 6085 ) 6038 xt "-85000,65000,-56500,65800" 6039 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type" 6086 xt "-85000,67400,-56500,68200" 6087 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type 6088 " 6040 6089 ) 6041 6090 ) … … 6054 6103 font "Courier New,8,0" 6055 6104 ) 6056 xt "-85000,63400,-41500,64200" 6057 st "SIGNAL drs_read_s_cell : std_logic := '0'" 6105 xt "-85000,65800,-41500,66600" 6106 st "SIGNAL drs_read_s_cell : std_logic := '0' 6107 " 6058 6108 ) 6059 6109 ) … … 6074 6124 ) 6075 6125 xt "-85000,32600,-39000,33400" 6076 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 6126 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6127 " 6077 6128 ) 6078 6129 ) … … 6092 6143 ) 6093 6144 xt "-85000,33400,-45000,34200" 6094 st "drs_dwrite : std_logic := '1'" 6145 st "drs_dwrite : std_logic := '1' 6146 " 6095 6147 ) 6096 6148 ) … … 6108 6160 sl 0 6109 6161 ro 90 6110 xt "- 28000,56625,-26500,57375"6162 xt "-39000,99625,-37500,100375" 6111 6163 ) 6112 6164 (Line … … 6114 6166 sl 0 6115 6167 ro 90 6116 xt "- 26500,57000,-26000,57000"6168 xt "-37500,100000,-37000,100000" 6117 6169 pts [ 6118 "- 26000,57000"6119 "- 26500,57000"6170 "-37000,100000" 6171 "-37500,100000" 6120 6172 ] 6121 6173 ) … … 6132 6184 va (VaSet 6133 6185 ) 6134 xt "- 34900,56500,-29000,57500"6186 xt "-45900,99500,-40000,100500" 6135 6187 st "drs_channel_id" 6136 6188 ju 2 6137 blo "- 29000,57300"6189 blo "-40000,100300" 6138 6190 tm "WireNameMgr" 6139 6191 ) … … 6199 6251 ) 6200 6252 xt "-85000,19000,-66500,19800" 6201 st "SROUT_in_0 : std_logic" 6253 st "SROUT_in_0 : std_logic 6254 " 6202 6255 ) 6203 6256 ) … … 6216 6269 ) 6217 6270 xt "-85000,19800,-66500,20600" 6218 st "SROUT_in_1 : std_logic" 6271 st "SROUT_in_1 : std_logic 6272 " 6219 6273 ) 6220 6274 ) … … 6233 6287 ) 6234 6288 xt "-85000,20600,-66500,21400" 6235 st "SROUT_in_2 : std_logic" 6289 st "SROUT_in_2 : std_logic 6290 " 6236 6291 ) 6237 6292 ) … … 6250 6305 ) 6251 6306 xt "-85000,21400,-66500,22200" 6252 st "SROUT_in_3 : std_logic" 6307 st "SROUT_in_3 : std_logic 6308 " 6253 6309 ) 6254 6310 ) … … 6446 6502 font "Courier New,8,0" 6447 6503 ) 6448 xt "-85000,64200,-62500,65000" 6449 st "SIGNAL drs_read_s_cell_ready : std_logic" 6504 xt "-85000,66600,-62500,67400" 6505 st "SIGNAL drs_read_s_cell_ready : std_logic 6506 " 6450 6507 ) 6451 6508 ) … … 6926 6983 ) 6927 6984 xt "-85000,28600,-45000,29400" 6928 st "RSRLOAD : std_logic := '0'" 6985 st "RSRLOAD : std_logic := '0' 6986 " 6929 6987 ) 6930 6988 ) … … 6989 7047 ) 6990 7048 xt "-85000,29400,-45000,30200" 6991 st "SRCLK : std_logic := '0'" 7049 st "SRCLK : std_logic := '0' 7050 " 6992 7051 ) 6993 7052 ) … … 7214 7273 t "std_logic_vector" 7215 7274 b "(15 DOWNTO 0)" 7216 o 1 27275 o 14 7217 7276 suid 5,0 7218 7277 ) … … 7249 7308 n "roi_array" 7250 7309 t "roi_array_type" 7251 o 1 17310 o 13 7252 7311 suid 6,0 7253 7312 ) … … 7464 7523 ) 7465 7524 ) 7525 *227 (CptPort 7526 uid 8500,0 7527 ps "OnEdgeStrategy" 7528 shape (Triangle 7529 uid 8501,0 7530 ro 90 7531 va (VaSet 7532 vasetType 1 7533 fg "0,65535,0" 7534 ) 7535 xt "92000,109625,92750,110375" 7536 ) 7537 tg (CPTG 7538 uid 8502,0 7539 ps "CptPortTextPlaceStrategy" 7540 stg "RightVerticalLayoutStrategy" 7541 f (Text 7542 uid 8503,0 7543 va (VaSet 7544 ) 7545 xt "83800,109500,91000,110500" 7546 st "drs_address : (3:0)" 7547 ju 2 7548 blo "91000,110300" 7549 ) 7550 ) 7551 thePort (LogicalPort 7552 m 1 7553 decl (Decl 7554 n "drs_address" 7555 t "std_logic_vector" 7556 b "(3 DOWNTO 0)" 7557 o 11 7558 suid 13,0 7559 ) 7560 ) 7561 ) 7562 *228 (CptPort 7563 uid 8504,0 7564 ps "OnEdgeStrategy" 7565 shape (Triangle 7566 uid 8505,0 7567 ro 90 7568 va (VaSet 7569 vasetType 1 7570 fg "0,65535,0" 7571 ) 7572 xt "92000,110625,92750,111375" 7573 ) 7574 tg (CPTG 7575 uid 8506,0 7576 ps "CptPortTextPlaceStrategy" 7577 stg "RightVerticalLayoutStrategy" 7578 f (Text 7579 uid 8507,0 7580 va (VaSet 7581 ) 7582 xt "83800,110500,91000,111500" 7583 st "drs_address_mode" 7584 ju 2 7585 blo "91000,111300" 7586 ) 7587 ) 7588 thePort (LogicalPort 7589 m 1 7590 decl (Decl 7591 n "drs_address_mode" 7592 t "std_logic" 7593 o 12 7594 suid 14,0 7595 ) 7596 ) 7597 ) 7466 7598 ] 7467 7599 shape (Rectangle … … 7481 7613 stg "VerticalLayoutStrategy" 7482 7614 textVec [ 7483 *22 7(Text7615 *229 (Text 7484 7616 uid 5075,0 7485 7617 va (VaSet … … 7491 7623 tm "BdLibraryNameMgr" 7492 7624 ) 7493 *2 28(Text7625 *230 (Text 7494 7626 uid 5076,0 7495 7627 va (VaSet … … 7501 7633 tm "CptNameMgr" 7502 7634 ) 7503 *2 29(Text7635 *231 (Text 7504 7636 uid 5077,0 7505 7637 va (VaSet … … 7547 7679 archFileType "UNKNOWN" 7548 7680 ) 7549 *23 0(Net7681 *232 (Net 7550 7682 uid 5088,0 7551 7683 decl (Decl … … 7562 7694 ) 7563 7695 xt "-85000,48200,-53000,49000" 7564 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0)" 7565 ) 7566 ) 7567 *231 (Net 7696 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0) 7697 " 7698 ) 7699 ) 7700 *233 (Net 7568 7701 uid 5096,0 7569 7702 decl (Decl … … 7579 7712 ) 7580 7713 xt "-85000,50600,-62500,51400" 7581 st "SIGNAL config_data_valid : std_logic" 7582 ) 7583 ) 7584 *232 (Net 7714 st "SIGNAL config_data_valid : std_logic 7715 " 7716 ) 7717 ) 7718 *234 (Net 7585 7719 uid 5104,0 7586 7720 decl (Decl … … 7596 7730 ) 7597 7731 xt "-85000,49000,-62500,49800" 7598 st "SIGNAL config_busy : std_logic" 7599 ) 7600 ) 7601 *233 (Net 7732 st "SIGNAL config_busy : std_logic 7733 " 7734 ) 7735 ) 7736 *235 (Net 7602 7737 uid 5112,0 7603 7738 decl (Decl … … 7614 7749 ) 7615 7750 xt "-85000,49800,-52500,50600" 7616 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0)" 7617 ) 7618 ) 7619 *234 (Net 7751 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0) 7752 " 7753 ) 7754 ) 7755 *236 (Net 7620 7756 uid 5120,0 7621 7757 decl (Decl … … 7631 7767 ) 7632 7768 xt "-85000,60200,-62500,61000" 7633 st "SIGNAL config_wr_en : std_logic" 7634 ) 7635 ) 7636 *235 (Net 7769 st "SIGNAL config_wr_en : std_logic 7770 " 7771 ) 7772 ) 7773 *237 (Net 7637 7774 uid 5128,0 7638 7775 decl (Decl … … 7648 7785 ) 7649 7786 xt "-85000,51400,-62500,52200" 7650 st "SIGNAL config_rd_en : std_logic" 7651 ) 7652 ) 7653 *236 (Net 7787 st "SIGNAL config_rd_en : std_logic 7788 " 7789 ) 7790 ) 7791 *238 (Net 7654 7792 uid 5144,0 7655 7793 decl (Decl … … 7665 7803 ) 7666 7804 xt "-85000,61000,-60000,61800" 7667 st "SIGNAL dac_array : dac_array_type" 7668 ) 7669 ) 7670 *237 (Net 7805 st "SIGNAL dac_array : dac_array_type 7806 " 7807 ) 7808 ) 7809 *239 (Net 7671 7810 uid 5194,0 7672 7811 decl (Decl … … 7682 7821 ) 7683 7822 xt "-85000,55400,-62500,56200" 7684 st "SIGNAL config_start_cm : std_logic" 7685 ) 7686 ) 7687 *238 (Net 7823 st "SIGNAL config_start_cm : std_logic 7824 " 7825 ) 7826 ) 7827 *240 (Net 7688 7828 uid 5196,0 7689 7829 decl (Decl … … 7699 7839 ) 7700 7840 xt "-85000,53000,-62500,53800" 7701 st "SIGNAL config_ready_cm : std_logic" 7702 ) 7703 ) 7704 *239 (Net 7841 st "SIGNAL config_ready_cm : std_logic 7842 " 7843 ) 7844 ) 7845 *241 (Net 7705 7846 uid 5220,0 7706 7847 decl (Decl … … 7719 7860 ) 7720 7861 xt "-85000,34200,-39000,35000" 7721 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 7722 ) 7723 ) 7724 *240 (Net 7862 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 7863 " 7864 ) 7865 ) 7866 *242 (Net 7725 7867 uid 5279,0 7726 7868 decl (Decl … … 7736 7878 font "Courier New,8,0" 7737 7879 ) 7738 xt "-85000,74600,-41500,75400" 7739 st "SIGNAL s_trigger : std_logic := '0'" 7740 ) 7741 ) 7742 *241 (Net 7880 xt "-85000,77000,-41500,77800" 7881 st "SIGNAL s_trigger : std_logic := '0' 7882 " 7883 ) 7884 ) 7885 *243 (Net 7743 7886 uid 5472,0 7744 7887 decl (Decl … … 7753 7896 font "Courier New,8,0" 7754 7897 ) 7755 xt "-85000,76200,-62500,77000" 7756 st "SIGNAL sensor_ready : std_logic" 7757 ) 7758 ) 7759 *242 (Net 7898 xt "-85000,78600,-62500,79400" 7899 st "SIGNAL sensor_ready : std_logic 7900 " 7901 ) 7902 ) 7903 *244 (Net 7760 7904 uid 5478,0 7761 7905 decl (Decl … … 7770 7914 font "Courier New,8,0" 7771 7915 ) 7772 xt "-85000,75400,-58500,76200" 7773 st "SIGNAL sensor_array : sensor_array_type" 7774 ) 7775 ) 7776 *243 (Net 7916 xt "-85000,77800,-58500,78600" 7917 st "SIGNAL sensor_array : sensor_array_type 7918 " 7919 ) 7920 ) 7921 *245 (Net 7777 7922 uid 5588,0 7778 7923 decl (Decl … … 7788 7933 ) 7789 7934 xt "-85000,53800,-62500,54600" 7790 st "SIGNAL config_ready_spi : std_logic" 7791 ) 7792 ) 7793 *244 (Net 7935 st "SIGNAL config_ready_spi : std_logic 7936 " 7937 ) 7938 ) 7939 *246 (Net 7794 7940 uid 5632,0 7795 7941 lang 10 … … 7807 7953 ) 7808 7954 xt "-85000,46600,-53000,47400" 7809 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0)" 7810 ) 7811 ) 7812 *245 (Net 7955 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0) 7956 " 7957 ) 7958 ) 7959 *247 (Net 7813 7960 uid 5640,0 7814 7961 decl (Decl … … 7824 7971 ) 7825 7972 xt "-85000,45800,-57500,46600" 7826 st "SIGNAL adc_data_array_int : adc_data_array_type" 7827 ) 7828 ) 7829 *246 (SaComponent 7973 st "SIGNAL adc_data_array_int : adc_data_array_type 7974 " 7975 ) 7976 ) 7977 *248 (SaComponent 7830 7978 uid 5678,0 7831 7979 optionalChildren [ 7832 *24 7(CptPort7980 *249 (CptPort 7833 7981 uid 5658,0 7834 7982 ps "OnEdgeStrategy" … … 7865 8013 ) 7866 8014 ) 7867 *2 48(CptPort8015 *250 (CptPort 7868 8016 uid 5662,0 7869 8017 ps "OnEdgeStrategy" … … 7902 8050 ) 7903 8051 ) 7904 *2 49(CptPort8052 *251 (CptPort 7905 8053 uid 5666,0 7906 8054 ps "OnEdgeStrategy" … … 7941 8089 ) 7942 8090 ) 7943 *25 0(CptPort8091 *252 (CptPort 7944 8092 uid 5670,0 7945 8093 ps "OnEdgeStrategy" … … 7977 8125 ) 7978 8126 ) 7979 *25 1(CptPort8127 *253 (CptPort 7980 8128 uid 5674,0 7981 8129 ps "OnEdgeStrategy" … … 8030 8178 stg "VerticalLayoutStrategy" 8031 8179 textVec [ 8032 *25 2(Text8180 *254 (Text 8033 8181 uid 5681,0 8034 8182 va (VaSet … … 8040 8188 tm "BdLibraryNameMgr" 8041 8189 ) 8042 *25 3(Text8190 *255 (Text 8043 8191 uid 5682,0 8044 8192 va (VaSet … … 8050 8198 tm "CptNameMgr" 8051 8199 ) 8052 *25 4(Text8200 *256 (Text 8053 8201 uid 5683,0 8054 8202 va (VaSet … … 8099 8247 archFileType "UNKNOWN" 8100 8248 ) 8101 *25 5(Net8249 *257 (Net 8102 8250 uid 5743,0 8103 8251 decl (Decl … … 8114 8262 ) 8115 8263 xt "-85000,56200,-41500,57000" 8116 st "SIGNAL config_start_spi : std_logic := '0'" 8117 ) 8118 ) 8119 *256 (SaComponent 8264 st "SIGNAL config_start_spi : std_logic := '0' 8265 " 8266 ) 8267 ) 8268 *258 (SaComponent 8120 8269 uid 5793,0 8121 8270 optionalChildren [ 8122 *25 7(CptPort8271 *259 (CptPort 8123 8272 uid 5753,0 8124 8273 ps "OnEdgeStrategy" … … 8155 8304 ) 8156 8305 ) 8157 *2 58(CptPort8306 *260 (CptPort 8158 8307 uid 5761,0 8159 8308 ps "OnEdgeStrategy" … … 8190 8339 ) 8191 8340 ) 8192 *2 59(CptPort8341 *261 (CptPort 8193 8342 uid 5765,0 8194 8343 ps "OnEdgeStrategy" … … 8226 8375 ) 8227 8376 ) 8228 *26 0(CptPort8377 *262 (CptPort 8229 8378 uid 5769,0 8230 8379 ps "OnEdgeStrategy" … … 8261 8410 ) 8262 8411 ) 8263 *26 1(CptPort8412 *263 (CptPort 8264 8413 uid 5773,0 8265 8414 ps "OnEdgeStrategy" … … 8297 8446 ) 8298 8447 ) 8299 *26 2(CptPort8448 *264 (CptPort 8300 8449 uid 5777,0 8301 8450 ps "OnEdgeStrategy" … … 8333 8482 ) 8334 8483 ) 8335 *26 3(CptPort8484 *265 (CptPort 8336 8485 uid 5781,0 8337 8486 ps "OnEdgeStrategy" … … 8368 8517 ) 8369 8518 ) 8370 *26 4(CptPort8519 *266 (CptPort 8371 8520 uid 5785,0 8372 8521 ps "OnEdgeStrategy" … … 8404 8553 ) 8405 8554 ) 8406 *26 5(CptPort8555 *267 (CptPort 8407 8556 uid 5789,0 8408 8557 ps "OnEdgeStrategy" … … 8440 8589 ) 8441 8590 ) 8442 *26 6(CptPort8591 *268 (CptPort 8443 8592 uid 5986,0 8444 8593 ps "OnEdgeStrategy" … … 8477 8626 ) 8478 8627 ) 8479 *26 7(CptPort8628 *269 (CptPort 8480 8629 uid 6154,0 8481 8630 ps "OnEdgeStrategy" … … 8513 8662 ) 8514 8663 ) 8515 *2 68(CptPort8664 *270 (CptPort 8516 8665 uid 6317,0 8517 8666 ps "OnEdgeStrategy" … … 8567 8716 stg "VerticalLayoutStrategy" 8568 8717 textVec [ 8569 *2 69(Text8718 *271 (Text 8570 8719 uid 5796,0 8571 8720 va (VaSet … … 8577 8726 tm "BdLibraryNameMgr" 8578 8727 ) 8579 *27 0(Text8728 *272 (Text 8580 8729 uid 5797,0 8581 8730 va (VaSet … … 8587 8736 tm "CptNameMgr" 8588 8737 ) 8589 *27 1(Text8738 *273 (Text 8590 8739 uid 5798,0 8591 8740 va (VaSet … … 8633 8782 archFileType "UNKNOWN" 8634 8783 ) 8635 *27 2(Net8784 *274 (Net 8636 8785 uid 5811,0 8637 8786 decl (Decl … … 8647 8796 ) 8648 8797 xt "-85000,35800,-66500,36600" 8649 st "sclk : std_logic" 8650 ) 8651 ) 8652 *273 (Net 8798 st "sclk : std_logic 8799 " 8800 ) 8801 ) 8802 *275 (Net 8653 8803 uid 5819,0 8654 8804 decl (Decl … … 8666 8816 ) 8667 8817 xt "-85000,41400,-66500,42200" 8668 st "sio : std_logic" 8669 ) 8670 ) 8671 *274 (Net 8818 st "sio : std_logic 8819 " 8820 ) 8821 ) 8822 *276 (Net 8672 8823 uid 5827,0 8673 8824 decl (Decl … … 8683 8834 ) 8684 8835 xt "-85000,31000,-66500,31800" 8685 st "dac_cs : std_logic" 8686 ) 8687 ) 8688 *275 (Net 8836 st "dac_cs : std_logic 8837 " 8838 ) 8839 ) 8840 *277 (Net 8689 8841 uid 5835,0 8690 8842 decl (Decl … … 8701 8853 ) 8702 8854 xt "-85000,36600,-56500,37400" 8703 st "sensor_cs : std_logic_vector(3 DOWNTO 0)" 8704 ) 8705 ) 8706 *276 (PortIoOut 8855 st "sensor_cs : std_logic_vector(3 DOWNTO 0) 8856 " 8857 ) 8858 ) 8859 *278 (PortIoOut 8707 8860 uid 5843,0 8708 8861 shape (CompositeShape … … 8749 8902 ) 8750 8903 ) 8751 *27 7(PortIoInOut8904 *279 (PortIoInOut 8752 8905 uid 5849,0 8753 8906 shape (CompositeShape … … 8794 8947 ) 8795 8948 ) 8796 *2 78(PortIoOut8949 *280 (PortIoOut 8797 8950 uid 5855,0 8798 8951 shape (CompositeShape … … 8839 8992 ) 8840 8993 ) 8841 *2 79(PortIoOut8994 *281 (PortIoOut 8842 8995 uid 5861,0 8843 8996 shape (CompositeShape … … 8884 9037 ) 8885 9038 ) 8886 *28 0(Net9039 *282 (Net 8887 9040 uid 5948,0 8888 9041 decl (Decl … … 8898 9051 font "Courier New,8,0" 8899 9052 ) 8900 xt "-85000,67400,-41500,68200" 8901 st "SIGNAL new_config : std_logic := '0'" 8902 ) 8903 ) 8904 *281 (Net 9053 xt "-85000,69800,-41500,70600" 9054 st "SIGNAL new_config : std_logic := '0' 9055 " 9056 ) 9057 ) 9058 *283 (Net 8905 9059 uid 5960,0 8906 9060 decl (Decl … … 8916 9070 ) 8917 9071 xt "-85000,57000,-62500,57800" 8918 st "SIGNAL config_started : std_logic" 8919 ) 8920 ) 8921 *282 (Net 9072 st "SIGNAL config_started : std_logic 9073 " 9074 ) 9075 ) 9076 *284 (Net 8922 9077 uid 6012,0 8923 9078 decl (Decl … … 8934 9089 ) 8935 9090 xt "-85000,59400,-41500,60200" 8936 st "SIGNAL config_started_spi : std_logic := '0'" 8937 ) 8938 ) 8939 *283 (Net 9091 st "SIGNAL config_started_spi : std_logic := '0' 9092 " 9093 ) 9094 ) 9095 *285 (Net 8940 9096 uid 6014,0 8941 9097 decl (Decl … … 8952 9108 ) 8953 9109 xt "-85000,57800,-41500,58600" 8954 st "SIGNAL config_started_cu : std_logic := '0'" 8955 ) 8956 ) 8957 *284 (Net 9110 st "SIGNAL config_started_cu : std_logic := '0' 9111 " 9112 ) 9113 ) 9114 *286 (Net 8958 9115 uid 6016,0 8959 9116 decl (Decl … … 8969 9126 ) 8970 9127 xt "-85000,58600,-62500,59400" 8971 st "SIGNAL config_started_mm : std_logic" 8972 ) 8973 ) 8974 *285 (Net 9128 st "SIGNAL config_started_mm : std_logic 9129 " 9130 ) 9131 ) 9132 *287 (Net 8975 9133 uid 6158,0 8976 9134 decl (Decl … … 8987 9145 ) 8988 9146 xt "-85000,35000,-45000,35800" 8989 st "mosi : std_logic := '0'" 8990 ) 8991 ) 8992 *286 (PortIoOut 9147 st "mosi : std_logic := '0' 9148 " 9149 ) 9150 ) 9151 *288 (PortIoOut 8993 9152 uid 6166,0 8994 9153 shape (CompositeShape … … 9035 9194 ) 9036 9195 ) 9037 *28 7(Net9196 *289 (Net 9038 9197 uid 6360,0 9039 9198 decl (Decl … … 9052 9211 ) 9053 9212 xt "-85000,31800,-31500,32600" 9054 st "denable : std_logic := '0' -- default domino wave off" 9055 ) 9056 ) 9057 *288 (PortIoOut 9213 st "denable : std_logic := '0' -- default domino wave off 9214 " 9215 ) 9216 ) 9217 *290 (PortIoOut 9058 9218 uid 6368,0 9059 9219 shape (CompositeShape … … 9099 9259 ) 9100 9260 ) 9101 *2 89(Net9261 *291 (Net 9102 9262 uid 6450,0 9103 9263 decl (Decl … … 9113 9273 font "Courier New,8,0" 9114 9274 ) 9115 xt "-85000,66600,-41500,67400" 9116 st "SIGNAL dwrite_enable : std_logic := '1'" 9117 ) 9118 ) 9119 *290 (MWC 9275 xt "-85000,69000,-41500,69800" 9276 st "SIGNAL dwrite_enable : std_logic := '1' 9277 " 9278 ) 9279 ) 9280 *292 (MWC 9120 9281 uid 6529,0 9121 9282 optionalChildren [ 9122 *29 1(CptPort9283 *293 (CptPort 9123 9284 uid 6501,0 9124 9285 optionalChildren [ 9125 *29 2(Line9286 *294 (Line 9126 9287 uid 6505,0 9127 9288 layer 5 … … 9136 9297 ] 9137 9298 ) 9138 *29 3(Property9299 *295 (Property 9139 9300 uid 6506,0 9140 9301 pclass "_MW_GEOM_" … … 9181 9342 ) 9182 9343 ) 9183 *29 4(CptPort9344 *296 (CptPort 9184 9345 uid 6507,0 9185 9346 optionalChildren [ 9186 *29 5(Line9347 *297 (Line 9187 9348 uid 6511,0 9188 9349 layer 5 … … 9236 9397 ) 9237 9398 ) 9238 *29 6(CptPort9399 *298 (CptPort 9239 9400 uid 6512,0 9240 9401 optionalChildren [ 9241 *29 7(Line9402 *299 (Line 9242 9403 uid 6516,0 9243 9404 layer 5 … … 9291 9452 ) 9292 9453 ) 9293 * 298(CommentGraphic9454 *300 (CommentGraphic 9294 9455 uid 6517,0 9295 9456 optionalChildren [ 9296 * 299(Property9457 *301 (Property 9297 9458 uid 6519,0 9298 9459 pclass "_MW_GEOM_" … … 9318 9479 oxt "11000,10000,11000,10000" 9319 9480 ) 9320 *30 0(CommentGraphic9481 *302 (CommentGraphic 9321 9482 uid 6520,0 9322 9483 optionalChildren [ 9323 *30 1(Property9484 *303 (Property 9324 9485 uid 6522,0 9325 9486 pclass "_MW_GEOM_" … … 9345 9506 oxt "11000,6000,11000,6000" 9346 9507 ) 9347 *30 2(Grouping9508 *304 (Grouping 9348 9509 uid 6523,0 9349 9510 optionalChildren [ 9350 *30 3(CommentGraphic9511 *305 (CommentGraphic 9351 9512 uid 6525,0 9352 9513 shape (PolyLine2D … … 9369 9530 oxt "9000,6000,11000,10000" 9370 9531 ) 9371 *30 4(CommentGraphic9532 *306 (CommentGraphic 9372 9533 uid 6527,0 9373 9534 shape (Arc2D … … 9422 9583 stg "VerticalLayoutStrategy" 9423 9584 textVec [ 9424 *30 5(Text9585 *307 (Text 9425 9586 uid 6532,0 9426 9587 va (VaSet … … 9432 9593 blo "3500,59300" 9433 9594 ) 9434 *30 6(Text9595 *308 (Text 9435 9596 uid 6533,0 9436 9597 va (VaSet … … 9441 9602 blo "3500,60300" 9442 9603 ) 9443 *30 7(Text9604 *309 (Text 9444 9605 uid 6534,0 9445 9606 va (VaSet … … 9486 9647 ) 9487 9648 ) 9488 *3 08(Net9649 *310 (Net 9489 9650 uid 6544,0 9490 9651 decl (Decl … … 9500 9661 font "Courier New,8,0" 9501 9662 ) 9502 xt "-85000,65800,-41500,66600" 9503 st "SIGNAL dwrite : std_logic := '1'" 9504 ) 9505 ) 9506 *309 (SaComponent 9663 xt "-85000,68200,-41500,69000" 9664 st "SIGNAL dwrite : std_logic := '1' 9665 " 9666 ) 9667 ) 9668 *311 (SaComponent 9507 9669 uid 8277,0 9508 9670 optionalChildren [ 9509 *31 0(CptPort9671 *312 (CptPort 9510 9672 uid 8246,0 9511 9673 ps "OnEdgeStrategy" … … 9544 9706 ) 9545 9707 ) 9546 *31 1(CptPort9708 *313 (CptPort 9547 9709 uid 8250,0 9548 9710 ps "OnEdgeStrategy" … … 9582 9744 ) 9583 9745 ) 9584 *31 2(CptPort9746 *314 (CptPort 9585 9747 uid 8254,0 9586 9748 ps "OnEdgeStrategy" … … 9620 9782 ) 9621 9783 ) 9622 *31 3(CptPort9784 *315 (CptPort 9623 9785 uid 8258,0 9624 9786 ps "OnEdgeStrategy" … … 9658 9820 ) 9659 9821 ) 9660 *31 4(CptPort9822 *316 (CptPort 9661 9823 uid 8262,0 9662 9824 ps "OnEdgeStrategy" … … 9696 9858 ) 9697 9859 ) 9698 *31 5(CptPort9860 *317 (CptPort 9699 9861 uid 8266,0 9700 9862 ps "OnEdgeStrategy" … … 9735 9897 ) 9736 9898 ) 9737 *31 6(CptPort9899 *318 (CptPort 9738 9900 uid 8270,0 9739 9901 ps "OnEdgeStrategy" … … 9792 9954 stg "VerticalLayoutStrategy" 9793 9955 textVec [ 9794 *31 7(Text9956 *319 (Text 9795 9957 uid 8280,0 9796 9958 va (VaSet … … 9802 9964 tm "BdLibraryNameMgr" 9803 9965 ) 9804 *3 18(Text9966 *320 (Text 9805 9967 uid 8281,0 9806 9968 va (VaSet … … 9812 9974 tm "CptNameMgr" 9813 9975 ) 9814 *3 19(Text9976 *321 (Text 9815 9977 uid 8282,0 9816 9978 va (VaSet … … 9860 10022 archFileType "UNKNOWN" 9861 10023 ) 9862 *32 0(Net10024 *322 (Net 9863 10025 uid 8414,0 9864 10026 lang 2 … … 9874 10036 font "Courier New,8,0" 9875 10037 ) 9876 xt "-85000,77800,-62500,78600" 9877 st "SIGNAL wiz_ack : std_logic" 9878 ) 9879 ) 9880 *321 (Wire 10038 xt "-85000,80200,-62500,81000" 10039 st "SIGNAL wiz_ack : std_logic 10040 " 10041 ) 10042 ) 10043 *323 (Net 10044 uid 8508,0 10045 decl (Decl 10046 n "drs_address" 10047 t "std_logic_vector" 10048 b "(3 DOWNTO 0)" 10049 o 82 10050 suid 184,0 10051 i "(others => '0')" 10052 ) 10053 declText (MLText 10054 uid 8509,0 10055 va (VaSet 10056 font "Courier New,8,0" 10057 ) 10058 xt "-85000,62600,-35500,63400" 10059 st "SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0') 10060 " 10061 ) 10062 ) 10063 *324 (Net 10064 uid 8516,0 10065 decl (Decl 10066 n "drs_address_mode" 10067 t "std_logic" 10068 o 83 10069 suid 185,0 10070 ) 10071 declText (MLText 10072 uid 8517,0 10073 va (VaSet 10074 font "Courier New,8,0" 10075 ) 10076 xt "-85000,63400,-62500,64200" 10077 st "SIGNAL drs_address_mode : std_logic 10078 " 10079 ) 10080 ) 10081 *325 (MWC 10082 uid 8562,0 10083 optionalChildren [ 10084 *326 (CptPort 10085 uid 8524,0 10086 optionalChildren [ 10087 *327 (Line 10088 uid 8528,0 10089 layer 5 10090 sl 0 10091 va (VaSet 10092 vasetType 3 10093 lineWidth 2 10094 ) 10095 xt "-29999,101000,-29000,101000" 10096 pts [ 10097 "-29000,101000" 10098 "-29999,101000" 10099 ] 10100 ) 10101 ] 10102 ps "OnEdgeStrategy" 10103 shape (Triangle 10104 uid 8525,0 10105 ro 270 10106 va (VaSet 10107 vasetType 1 10108 isHidden 1 10109 fg "0,65535,65535" 10110 ) 10111 xt "-29000,100625,-28250,101375" 10112 ) 10113 tg (CPTG 10114 uid 8526,0 10115 ps "CptPortTextPlaceStrategy" 10116 stg "RightVerticalLayoutStrategy" 10117 f (Text 10118 uid 8527,0 10119 sl 0 10120 va (VaSet 10121 isHidden 1 10122 font "arial,8,0" 10123 ) 10124 xt "-98971,288551,-97171,289551" 10125 st "din0" 10126 ju 2 10127 blo "-97171,289351" 10128 ) 10129 s (Text 10130 uid 8571,0 10131 sl 0 10132 va (VaSet 10133 font "arial,8,0" 10134 ) 10135 xt "-97171,289551,-97171,289551" 10136 ju 2 10137 blo "-97171,289551" 10138 ) 10139 ) 10140 thePort (LogicalPort 10141 decl (Decl 10142 n "din0" 10143 t "std_logic_vector" 10144 b "(3 DOWNTO 0)" 10145 o 84 10146 suid 1,0 10147 i "(others => '0')" 10148 ) 10149 ) 10150 ) 10151 *328 (CptPort 10152 uid 8529,0 10153 optionalChildren [ 10154 *329 (Line 10155 uid 8533,0 10156 layer 5 10157 sl 0 10158 va (VaSet 10159 vasetType 3 10160 lineWidth 2 10161 ) 10162 xt "-33000,100000,-31999,100000" 10163 pts [ 10164 "-33000,100000" 10165 "-31999,100000" 10166 ] 10167 ) 10168 *330 (Property 10169 uid 8534,0 10170 pclass "_MW_GEOM_" 10171 pname "fixed" 10172 ptn "String" 10173 ) 10174 ] 10175 ps "OnEdgeStrategy" 10176 shape (Triangle 10177 uid 8530,0 10178 ro 270 10179 va (VaSet 10180 vasetType 1 10181 isHidden 1 10182 fg "0,65535,65535" 10183 ) 10184 xt "-33750,99625,-33000,100375" 10185 ) 10186 tg (CPTG 10187 uid 8531,0 10188 ps "CptPortTextPlaceStrategy" 10189 stg "VerticalLayoutStrategy" 10190 f (Text 10191 uid 8532,0 10192 sl 0 10193 va (VaSet 10194 isHidden 1 10195 font "arial,8,0" 10196 ) 10197 xt "-100999,287527,-99199,288527" 10198 st "dout" 10199 blo "-100999,288327" 10200 ) 10201 s (Text 10202 uid 8572,0 10203 sl 0 10204 va (VaSet 10205 font "arial,8,0" 10206 ) 10207 xt "-100999,288527,-100999,288527" 10208 blo "-100999,288527" 10209 ) 10210 ) 10211 thePort (LogicalPort 10212 m 1 10213 decl (Decl 10214 n "dout" 10215 t "std_logic_vector" 10216 b "(3 DOWNTO 0)" 10217 o 19 10218 suid 2,0 10219 i "(others => '0')" 10220 ) 10221 ) 10222 ) 10223 *331 (CptPort 10224 uid 8535,0 10225 optionalChildren [ 10226 *332 (Line 10227 uid 8539,0 10228 layer 5 10229 sl 0 10230 va (VaSet 10231 vasetType 3 10232 lineWidth 2 10233 ) 10234 xt "-29999,99000,-29000,99000" 10235 pts [ 10236 "-29000,99000" 10237 "-29999,99000" 10238 ] 10239 ) 10240 ] 10241 ps "OnEdgeStrategy" 10242 shape (Triangle 10243 uid 8536,0 10244 ro 270 10245 va (VaSet 10246 vasetType 1 10247 isHidden 1 10248 fg "0,65535,65535" 10249 ) 10250 xt "-29000,98625,-28250,99375" 10251 ) 10252 tg (CPTG 10253 uid 8537,0 10254 ps "CptPortTextPlaceStrategy" 10255 stg "RightVerticalLayoutStrategy" 10256 f (Text 10257 uid 8538,0 10258 sl 0 10259 va (VaSet 10260 isHidden 1 10261 font "arial,8,0" 10262 ) 10263 xt "-98971,286503,-97171,287503" 10264 st "din1" 10265 ju 2 10266 blo "-97171,287303" 10267 ) 10268 s (Text 10269 uid 8573,0 10270 sl 0 10271 va (VaSet 10272 font "arial,8,0" 10273 ) 10274 xt "-97171,287503,-97171,287503" 10275 ju 2 10276 blo "-97171,287503" 10277 ) 10278 ) 10279 thePort (LogicalPort 10280 decl (Decl 10281 n "din1" 10282 t "std_logic_vector" 10283 b "(3 DOWNTO 0)" 10284 o 82 10285 suid 3,0 10286 i "(others => '0')" 10287 ) 10288 ) 10289 ) 10290 *333 (CptPort 10291 uid 8540,0 10292 optionalChildren [ 10293 *334 (Line 10294 uid 8544,0 10295 layer 5 10296 sl 0 10297 va (VaSet 10298 vasetType 3 10299 ) 10300 xt "-31000,101333,-31000,103000" 10301 pts [ 10302 "-31000,103000" 10303 "-31000,101333" 10304 ] 10305 ) 10306 ] 10307 ps "OnEdgeStrategy" 10308 shape (Triangle 10309 uid 8541,0 10310 va (VaSet 10311 vasetType 1 10312 isHidden 1 10313 fg "0,65535,65535" 10314 ) 10315 xt "-31375,103000,-30625,103750" 10316 ) 10317 tg (CPTG 10318 uid 8542,0 10319 ps "CptPortTextPlaceStrategy" 10320 stg "VerticalLayoutStrategy" 10321 f (Text 10322 uid 8543,0 10323 sl 0 10324 ro 270 10325 va (VaSet 10326 isHidden 1 10327 font "arial,8,0" 10328 ) 10329 xt "-99473,289183,-98473,290583" 10330 st "sel" 10331 blo "-98673,290583" 10332 ) 10333 s (Text 10334 uid 8574,0 10335 sl 0 10336 ro 270 10337 va (VaSet 10338 font "arial,8,0" 10339 ) 10340 xt "-98473,290583,-98473,290583" 10341 blo "-98473,290583" 10342 ) 10343 ) 10344 thePort (LogicalPort 10345 decl (Decl 10346 n "sel" 10347 t "std_logic" 10348 o 83 10349 suid 4,0 10350 ) 10351 ) 10352 ) 10353 *335 (CommentGraphic 10354 uid 8545,0 10355 shape (CustomPolygon 10356 pts [ 10357 "-30000,102000" 10358 "-32000,100666" 10359 "-32000,99334" 10360 "-30000,98000" 10361 "-30000,102000" 10362 ] 10363 uid 8546,0 10364 layer 0 10365 sl 0 10366 va (VaSet 10367 vasetType 1 10368 fg "0,65535,65535" 10369 bg "0,65535,65535" 10370 lineColor "26368,26368,26368" 10371 ) 10372 xt "-32000,98000,-30000,102000" 10373 ) 10374 oxt "7000,7000,9000,11000" 10375 ) 10376 *336 (CommentGraphic 10377 uid 8547,0 10378 optionalChildren [ 10379 *337 (Property 10380 uid 8549,0 10381 pclass "_MW_GEOM_" 10382 pname "expand" 10383 ptn "String" 10384 ) 10385 ] 10386 shape (PolyLine2D 10387 pts [ 10388 "-30000,98000" 10389 "-30000,98000" 10390 ] 10391 uid 8548,0 10392 layer 0 10393 sl 0 10394 va (VaSet 10395 vasetType 1 10396 transparent 1 10397 fg "49152,49152,49152" 10398 ) 10399 xt "-30000,98000,-30000,98000" 10400 ) 10401 oxt "9000,7000,9000,7000" 10402 ) 10403 *338 (CommentGraphic 10404 uid 8550,0 10405 optionalChildren [ 10406 *339 (Property 10407 uid 8552,0 10408 pclass "_MW_GEOM_" 10409 pname "expand" 10410 ptn "String" 10411 ) 10412 ] 10413 shape (PolyLine2D 10414 pts [ 10415 "-30000,102000" 10416 "-30000,102000" 10417 ] 10418 uid 8551,0 10419 layer 0 10420 sl 0 10421 va (VaSet 10422 vasetType 1 10423 transparent 1 10424 fg "49152,49152,49152" 10425 ) 10426 xt "-30000,102000,-30000,102000" 10427 ) 10428 oxt "9000,11000,9000,11000" 10429 ) 10430 *340 (CommentText 10431 uid 8553,0 10432 shape (Rectangle 10433 uid 8554,0 10434 sl 0 10435 va (VaSet 10436 vasetType 1 10437 transparent 1 10438 fg "65535,65535,65535" 10439 lineColor "65535,65535,65535" 10440 lineWidth -1 10441 ) 10442 xt "-32000,100000,-30000,101506" 10443 ) 10444 oxt "7000,9000,9000,10506" 10445 text (MLText 10446 uid 8555,0 10447 sl 0 10448 va (VaSet 10449 font "arial,8,0" 10450 ) 10451 xt "-31800,100200,-30600,101200" 10452 st " 10453 Lo 10454 " 10455 tm "CommentText" 10456 wrapOption 3 10457 visibleHeight 1506 10458 visibleWidth 2000 10459 ) 10460 ) 10461 *341 (CommentText 10462 uid 8556,0 10463 shape (Rectangle 10464 uid 8557,0 10465 layer 8 10466 sl 0 10467 va (VaSet 10468 vasetType 1 10469 transparent 1 10470 fg "65535,65535,65535" 10471 lineColor "65535,65535,65535" 10472 lineWidth -1 10473 ) 10474 xt "-32000,98000,-30002,99556" 10475 ) 10476 oxt "7000,7000,8998,8556" 10477 text (MLText 10478 uid 8558,0 10479 sl 0 10480 va (VaSet 10481 font "arial,8,0" 10482 ) 10483 xt "-31800,98200,-30600,99200" 10484 st " 10485 Hi 10486 " 10487 tm "CommentText" 10488 wrapOption 3 10489 visibleHeight 1556 10490 visibleWidth 1998 10491 ) 10492 ) 10493 *342 (CommentText 10494 uid 8559,0 10495 shape (Rectangle 10496 uid 8560,0 10497 layer 0 10498 sl 0 10499 va (VaSet 10500 vasetType 1 10501 transparent 1 10502 fg "65535,65535,65535" 10503 lineColor "65535,65535,65535" 10504 lineWidth -1 10505 ) 10506 xt "-32111,99517,-30111,100517" 10507 ) 10508 oxt "6889,8517,8889,9517" 10509 text (MLText 10510 uid 8561,0 10511 sl 0 10512 va (VaSet 10513 font "arial,8,0" 10514 ) 10515 xt "-31911,99717,-30211,100717" 10516 st " 10517 mux 10518 " 10519 tm "CommentText" 10520 wrapOption 3 10521 visibleHeight 1000 10522 visibleWidth 2000 10523 ) 10524 ) 10525 ] 10526 shape (Rectangle 10527 uid 8563,0 10528 va (VaSet 10529 vasetType 1 10530 transparent 1 10531 fg "65535,65535,65535" 10532 lineWidth -1 10533 ) 10534 xt "-33000,97000,-29000,103000" 10535 fos 1 10536 ) 10537 showPorts 0 10538 oxt "6000,6000,10000,12000" 10539 ttg (MlTextGroup 10540 uid 8564,0 10541 ps "CenterOffsetStrategy" 10542 stg "VerticalLayoutStrategy" 10543 textVec [ 10544 *343 (Text 10545 uid 8565,0 10546 va (VaSet 10547 isHidden 1 10548 font "arial,8,0" 10549 ) 10550 xt "-30650,102100,-25850,103100" 10551 st "moduleware" 10552 blo "-30650,102900" 10553 ) 10554 *344 (Text 10555 uid 8566,0 10556 va (VaSet 10557 font "arial,8,0" 10558 ) 10559 xt "-30650,103100,-28950,104100" 10560 st "mux" 10561 blo "-30650,103900" 10562 ) 10563 *345 (Text 10564 uid 8567,0 10565 va (VaSet 10566 font "arial,8,0" 10567 ) 10568 xt "-30650,104100,-28850,105100" 10569 st "U_0" 10570 blo "-30650,104900" 10571 tm "InstanceNameMgr" 10572 ) 10573 ] 10574 ) 10575 ga (GenericAssociation 10576 uid 8568,0 10577 ps "EdgeToEdgeStrategy" 10578 matrix (Matrix 10579 uid 8569,0 10580 text (MLText 10581 uid 8570,0 10582 va (VaSet 10583 font "arial,8,0" 10584 ) 10585 xt "-36000,79400,-36000,79400" 10586 ) 10587 header "" 10588 ) 10589 elements [ 10590 ] 10591 ) 10592 sed 1 10593 awe 1 10594 portVis (PortSigDisplay 10595 disp 1 10596 sN 0 10597 sTC 0 10598 selT 0 10599 ) 10600 prms (Property 10601 pclass "params" 10602 pname "params" 10603 ptn "String" 10604 ) 10605 de 1 10606 visOptions (mwParamsVisibilityOptions 10607 ) 10608 ) 10609 *346 (Net 10610 uid 8583,0 10611 decl (Decl 10612 n "drs_channel_internal" 10613 t "std_logic_vector" 10614 b "(3 DOWNTO 0)" 10615 o 84 10616 suid 187,0 10617 i "(others => '0')" 10618 ) 10619 declText (MLText 10620 uid 8584,0 10621 va (VaSet 10622 font "Courier New,8,0" 10623 ) 10624 xt "-85000,64200,-35500,65000" 10625 st "SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0') 10626 " 10627 ) 10628 ) 10629 *347 (Wire 9881 10630 uid 322,0 9882 10631 shape (OrthoPolyLine … … 9894 10643 ) 9895 10644 start &26 9896 end &31 310645 end &315 9897 10646 sat 32 9898 10647 eat 32 … … 9917 10666 on &2 9918 10667 ) 9919 *3 22(Wire10668 *348 (Wire 9920 10669 uid 328,0 9921 10670 shape (OrthoPolyLine … … 9933 10682 ) 9934 10683 start &25 9935 end &31 210684 end &314 9936 10685 sat 32 9937 10686 eat 32 … … 9956 10705 on &3 9957 10706 ) 9958 *3 23(Wire10707 *349 (Wire 9959 10708 uid 334,0 9960 10709 shape (OrthoPolyLine … … 9972 10721 ) 9973 10722 start &24 9974 end &31 110723 end &313 9975 10724 sat 32 9976 10725 eat 32 … … 9995 10744 on &4 9996 10745 ) 9997 *3 24(Wire10746 *350 (Wire 9998 10747 uid 364,0 9999 10748 shape (OrthoPolyLine … … 10012 10761 ) 10013 10762 start &79 10014 end &31 510763 end &317 10015 10764 sat 32 10016 10765 eat 32 … … 10035 10784 on &5 10036 10785 ) 10037 *3 25(Wire10786 *351 (Wire 10038 10787 uid 370,0 10039 10788 shape (OrthoPolyLine … … 10052 10801 ) 10053 10802 start &78 10054 end &31 610803 end &318 10055 10804 sat 32 10056 10805 eat 32 … … 10075 10824 on &6 10076 10825 ) 10077 *3 26(Wire10826 *352 (Wire 10078 10827 uid 376,0 10079 10828 shape (OrthoPolyLine … … 10113 10862 on &7 10114 10863 ) 10115 *3 27(Wire10864 *353 (Wire 10116 10865 uid 384,0 10117 10866 shape (OrthoPolyLine … … 10153 10902 on &8 10154 10903 ) 10155 *3 28(Wire10904 *354 (Wire 10156 10905 uid 392,0 10157 10906 shape (OrthoPolyLine … … 10193 10942 on &9 10194 10943 ) 10195 *3 29(Wire10944 *355 (Wire 10196 10945 uid 400,0 10197 10946 shape (OrthoPolyLine … … 10231 10980 on &10 10232 10981 ) 10233 *3 30(Wire10982 *356 (Wire 10234 10983 uid 408,0 10235 10984 shape (OrthoPolyLine … … 10269 11018 on &11 10270 11019 ) 10271 *3 31(Wire11020 *357 (Wire 10272 11021 uid 424,0 10273 11022 shape (OrthoPolyLine … … 10307 11056 on &12 10308 11057 ) 10309 *3 32(Wire11058 *358 (Wire 10310 11059 uid 432,0 10311 11060 shape (OrthoPolyLine … … 10345 11094 on &13 10346 11095 ) 10347 *3 33(Wire11096 *359 (Wire 10348 11097 uid 1411,0 10349 11098 shape (OrthoPolyLine … … 10384 11133 on &64 10385 11134 ) 10386 *3 34(Wire11135 *360 (Wire 10387 11136 uid 1425,0 10388 11137 optionalChildren [ 10389 *3 35(BdJunction11138 *361 (BdJunction 10390 11139 uid 4391,0 10391 11140 ps "OnConnectorStrategy" … … 10437 11186 on &65 10438 11187 ) 10439 *3 36(Wire11188 *362 (Wire 10440 11189 uid 1682,0 10441 11190 shape (OrthoPolyLine … … 10476 11225 on &100 10477 11226 ) 10478 *3 37(Wire11227 *363 (Wire 10479 11228 uid 1983,0 10480 11229 shape (OrthoPolyLine … … 10515 11264 on &108 10516 11265 ) 10517 *3 38(Wire11266 *364 (Wire 10518 11267 uid 2299,0 10519 11268 shape (OrthoPolyLine … … 10555 11304 on &109 10556 11305 ) 10557 *3 39(Wire11306 *365 (Wire 10558 11307 uid 2470,0 10559 11308 shape (OrthoPolyLine … … 10592 11341 on &132 10593 11342 ) 10594 *3 40(Wire11343 *366 (Wire 10595 11344 uid 2476,0 10596 11345 shape (OrthoPolyLine … … 10629 11378 on &133 10630 11379 ) 10631 *3 41(Wire11380 *367 (Wire 10632 11381 uid 2482,0 10633 11382 shape (OrthoPolyLine … … 10668 11417 on &134 10669 11418 ) 10670 *3 42(Wire11419 *368 (Wire 10671 11420 uid 2488,0 10672 11421 shape (OrthoPolyLine … … 10707 11456 on &135 10708 11457 ) 10709 *3 43(Wire11458 *369 (Wire 10710 11459 uid 2494,0 10711 11460 shape (OrthoPolyLine … … 10746 11495 on &136 10747 11496 ) 10748 *3 44(Wire11497 *370 (Wire 10749 11498 uid 2500,0 10750 11499 shape (OrthoPolyLine … … 10783 11532 on &137 10784 11533 ) 10785 *3 45(Wire11534 *371 (Wire 10786 11535 uid 2506,0 10787 11536 shape (OrthoPolyLine … … 10820 11569 on &138 10821 11570 ) 10822 *3 46(Wire11571 *372 (Wire 10823 11572 uid 2576,0 10824 11573 shape (OrthoPolyLine … … 10858 11607 on &139 10859 11608 ) 10860 *3 47(Wire11609 *373 (Wire 10861 11610 uid 2582,0 10862 11611 shape (OrthoPolyLine … … 10896 11645 on &140 10897 11646 ) 10898 *3 48(Wire11647 *374 (Wire 10899 11648 uid 2588,0 10900 11649 shape (OrthoPolyLine … … 10935 11684 on &141 10936 11685 ) 10937 *3 49(Wire11686 *375 (Wire 10938 11687 uid 2594,0 10939 11688 shape (OrthoPolyLine … … 10973 11722 on &142 10974 11723 ) 10975 *3 50(Wire11724 *376 (Wire 10976 11725 uid 2600,0 10977 11726 shape (OrthoPolyLine … … 11011 11760 on &143 11012 11761 ) 11013 *3 51(Wire11762 *377 (Wire 11014 11763 uid 2642,0 11015 11764 shape (OrthoPolyLine … … 11051 11800 on &144 11052 11801 ) 11053 *3 52(Wire11802 *378 (Wire 11054 11803 uid 2778,0 11055 11804 shape (OrthoPolyLine … … 11089 11838 on &145 11090 11839 ) 11091 *3 53(Wire11840 *379 (Wire 11092 11841 uid 2786,0 11093 11842 shape (OrthoPolyLine … … 11104 11853 ) 11105 11854 start &147 11106 end &25 011855 end &252 11107 11856 sat 32 11108 11857 eat 32 … … 11129 11878 on &176 11130 11879 ) 11131 *3 54(Wire11880 *380 (Wire 11132 11881 uid 2876,0 11133 11882 shape (OrthoPolyLine … … 11143 11892 ] 11144 11893 ) 11145 start &3 3511894 start &361 11146 11895 end &103 11147 11896 es 0 … … 11167 11916 on &65 11168 11917 ) 11169 *3 55(Wire11918 *381 (Wire 11170 11919 uid 3888,0 11171 11920 optionalChildren [ 11172 *3 56(BdJunction11921 *382 (BdJunction 11173 11922 uid 4230,0 11174 11923 ps "OnConnectorStrategy" … … 11182 11931 ) 11183 11932 ) 11184 *3 57(BdJunction11933 *383 (BdJunction 11185 11934 uid 4244,0 11186 11935 ps "OnConnectorStrategy" … … 11233 11982 on &164 11234 11983 ) 11235 *3 58(Wire11984 *384 (Wire 11236 11985 uid 3984,0 11237 11986 shape (OrthoPolyLine … … 11274 12023 on &162 11275 12024 ) 11276 *3 59(Wire12025 *385 (Wire 11277 12026 uid 4042,0 11278 12027 shape (OrthoPolyLine … … 11312 12061 on &175 11313 12062 ) 11314 *3 60(Wire12063 *386 (Wire 11315 12064 uid 4226,0 11316 12065 shape (OrthoPolyLine … … 11328 12077 ) 11329 12078 start &174 11330 end &3 5612079 end &382 11331 12080 sat 32 11332 12081 eat 32 … … 11352 12101 on &164 11353 12102 ) 11354 *3 61(Wire12103 *387 (Wire 11355 12104 uid 4240,0 11356 12105 shape (OrthoPolyLine … … 11367 12116 ] 11368 12117 ) 11369 start &31 411370 end &3 5712118 start &316 12119 end &383 11371 12120 sat 32 11372 12121 eat 32 … … 11391 12140 on &164 11392 12141 ) 11393 *3 62(Wire12142 *388 (Wire 11394 12143 uid 4272,0 11395 12144 shape (OrthoPolyLine … … 11405 12154 ) 11406 12155 start &178 11407 end &24 712156 end &249 11408 12157 sat 32 11409 12158 eat 32 … … 11429 12178 on &177 11430 12179 ) 11431 *3 63(Wire12180 *389 (Wire 11432 12181 uid 4401,0 11433 12182 shape (OrthoPolyLine … … 11465 12214 on &179 11466 12215 ) 11467 *3 64(Wire12216 *390 (Wire 11468 12217 uid 4407,0 11469 12218 shape (OrthoPolyLine … … 11501 12250 on &180 11502 12251 ) 11503 *3 65(Wire12252 *391 (Wire 11504 12253 uid 4419,0 11505 12254 shape (OrthoPolyLine … … 11537 12286 on &181 11538 12287 ) 11539 *3 66(Wire12288 *392 (Wire 11540 12289 uid 4537,0 11541 12290 shape (OrthoPolyLine … … 11545 12294 lineWidth 2 11546 12295 ) 11547 xt "- 26000,57000,18250,57000"12296 xt "-37000,100000,-33000,100000" 11548 12297 pts [ 11549 " 18250,57000"11550 "- 26000,57000"11551 ] 11552 ) 11553 start &3 912298 "-33000,100000" 12299 "-37000,100000" 12300 ] 12301 ) 12302 start &328 11554 12303 end &184 11555 12304 sat 32 … … 11569 12318 isHidden 1 11570 12319 ) 11571 xt "- 20000,56000,-14100,57000"12320 xt "-71000,99000,-65100,100000" 11572 12321 st "drs_channel_id" 11573 blo "- 20000,56800"12322 blo "-71000,99800" 11574 12323 tm "WireNameMgr" 11575 12324 ) … … 11577 12326 on &182 11578 12327 ) 11579 *3 67(Wire12328 *393 (Wire 11580 12329 uid 4545,0 11581 12330 shape (OrthoPolyLine … … 11590 12339 ] 11591 12340 ) 11592 start &29 112341 start &293 11593 12342 end &185 11594 12343 sat 32 … … 11614 12363 on &183 11615 12364 ) 11616 *3 68(Wire12365 *394 (Wire 11617 12366 uid 4671,0 11618 12367 shape (OrthoPolyLine … … 11652 12401 on &186 11653 12402 ) 11654 *3 69(Wire12403 *395 (Wire 11655 12404 uid 4679,0 11656 12405 shape (OrthoPolyLine … … 11690 12439 on &187 11691 12440 ) 11692 *3 70(Wire12441 *396 (Wire 11693 12442 uid 4687,0 11694 12443 shape (OrthoPolyLine … … 11728 12477 on &188 11729 12478 ) 11730 *3 71(Wire12479 *397 (Wire 11731 12480 uid 4695,0 11732 12481 shape (OrthoPolyLine … … 11766 12515 on &189 11767 12516 ) 11768 *3 72(Wire12517 *398 (Wire 11769 12518 uid 4743,0 11770 12519 shape (OrthoPolyLine … … 11802 12551 on &194 11803 12552 ) 11804 *3 73(Wire12553 *399 (Wire 11805 12554 uid 4757,0 11806 12555 optionalChildren [ 11807 * 374(BdJunction12556 *400 (BdJunction 11808 12557 uid 6076,0 11809 12558 ps "OnConnectorStrategy" … … 11833 12582 ) 11834 12583 start &196 11835 end * 375(BdJunction12584 end *401 (BdJunction 11836 12585 uid 6080,0 11837 12586 ps "OnConnectorStrategy" … … 11867 12616 on &173 11868 12617 ) 11869 * 376(Wire12618 *402 (Wire 11870 12619 uid 4948,0 11871 12620 shape (OrthoPolyLine … … 11905 12654 on &210 11906 12655 ) 11907 * 377(Wire12656 *403 (Wire 11908 12657 uid 4962,0 11909 12658 shape (OrthoPolyLine … … 11943 12692 on &212 11944 12693 ) 11945 * 378(Wire12694 *404 (Wire 11946 12695 uid 5090,0 11947 12696 shape (OrthoPolyLine … … 11980 12729 ) 11981 12730 ) 11982 on &23 011983 ) 11984 * 379(Wire12731 on &232 12732 ) 12733 *405 (Wire 11985 12734 uid 5098,0 11986 12735 shape (OrthoPolyLine … … 12014 12763 ) 12015 12764 ) 12016 on &23 112017 ) 12018 * 380(Wire12765 on &233 12766 ) 12767 *406 (Wire 12019 12768 uid 5106,0 12020 12769 shape (OrthoPolyLine … … 12051 12800 ) 12052 12801 ) 12053 on &23 212054 ) 12055 * 381(Wire12802 on &234 12803 ) 12804 *407 (Wire 12056 12805 uid 5114,0 12057 12806 shape (OrthoPolyLine … … 12090 12839 ) 12091 12840 ) 12092 on &23 312093 ) 12094 * 382(Wire12841 on &235 12842 ) 12843 *408 (Wire 12095 12844 uid 5122,0 12096 12845 shape (OrthoPolyLine … … 12127 12876 ) 12128 12877 ) 12129 on &23 412130 ) 12131 * 383(Wire12878 on &236 12879 ) 12880 *409 (Wire 12132 12881 uid 5130,0 12133 12882 shape (OrthoPolyLine … … 12164 12913 ) 12165 12914 ) 12166 on &23 512167 ) 12168 * 384(Wire12915 on &237 12916 ) 12917 *410 (Wire 12169 12918 uid 5138,0 12170 12919 optionalChildren [ 12171 * 385(BdJunction12920 *411 (BdJunction 12172 12921 uid 5400,0 12173 12922 ps "OnConnectorStrategy" … … 12219 12968 on &148 12220 12969 ) 12221 * 386(Wire12970 *412 (Wire 12222 12971 uid 5146,0 12223 12972 shape (OrthoPolyLine … … 12233 12982 ) 12234 12983 start &222 12235 end &2 5812984 end &260 12236 12985 es 0 12237 12986 sat 32 … … 12253 13002 ) 12254 13003 ) 12255 on &23 612256 ) 12257 * 387(Wire13004 on &238 13005 ) 13006 *413 (Wire 12258 13007 uid 5168,0 12259 13008 shape (OrthoPolyLine … … 12268 13017 ] 12269 13018 ) 12270 start & 38513019 start &411 12271 13020 end &125 12272 13021 sat 32 … … 12291 13040 on &148 12292 13041 ) 12293 * 388(Wire13042 *414 (Wire 12294 13043 uid 5184,0 12295 13044 shape (OrthoPolyLine … … 12326 13075 ) 12327 13076 ) 12328 on &23 712329 ) 12330 * 389(Wire13077 on &239 13078 ) 13079 *415 (Wire 12331 13080 uid 5190,0 12332 13081 shape (OrthoPolyLine … … 12363 13112 ) 12364 13113 ) 12365 on &2 3812366 ) 12367 * 390(Wire13114 on &240 13115 ) 13116 *416 (Wire 12368 13117 uid 5222,0 12369 13118 shape (OrthoPolyLine … … 12403 13152 ) 12404 13153 ) 12405 on &2 3912406 ) 12407 * 391(Wire13154 on &241 13155 ) 13156 *417 (Wire 12408 13157 uid 5281,0 12409 13158 shape (OrthoPolyLine … … 12441 13190 ) 12442 13191 ) 12443 on &24 012444 ) 12445 * 392(Wire13192 on &242 13193 ) 13194 *418 (Wire 12446 13195 uid 5404,0 12447 13196 shape (OrthoPolyLine … … 12458 13207 ] 12459 13208 ) 12460 start &2 5913209 start &261 12461 13210 end &50 12462 13211 sat 32 … … 12478 13227 ) 12479 13228 ) 12480 on &24 312481 ) 12482 * 393(Wire13229 on &245 13230 ) 13231 *419 (Wire 12483 13232 uid 5474,0 12484 13233 shape (OrthoPolyLine … … 12495 13244 ] 12496 13245 ) 12497 start &26 213246 start &264 12498 13247 end &52 12499 13248 sat 32 … … 12515 13264 ) 12516 13265 ) 12517 on &24 112518 ) 12519 * 394(Wire13266 on &243 13267 ) 13268 *420 (Wire 12520 13269 uid 5480,0 12521 13270 shape (OrthoPolyLine … … 12532 13281 ] 12533 13282 ) 12534 start &26 113283 start &263 12535 13284 end &51 12536 13285 sat 32 … … 12552 13301 ) 12553 13302 ) 12554 on &24 212555 ) 12556 * 395(Wire13303 on &244 13304 ) 13305 *421 (Wire 12557 13306 uid 5582,0 12558 13307 shape (OrthoPolyLine … … 12589 13338 on &164 12590 13339 ) 12591 * 396(Wire13340 *422 (Wire 12592 13341 uid 5602,0 12593 13342 optionalChildren [ 12594 & 37512595 * 397(BdJunction13343 &401 13344 *423 (BdJunction 12596 13345 uid 6086,0 12597 13346 ps "OnConnectorStrategy" … … 12623 13372 ) 12624 13373 start &23 12625 end &31 013374 end &312 12626 13375 sat 32 12627 13376 eat 32 … … 12646 13395 on &173 12647 13396 ) 12648 * 398(Wire13397 *424 (Wire 12649 13398 uid 5626,0 12650 13399 shape (OrthoPolyLine … … 12660 13409 ) 12661 13410 start &45 12662 end &2 4813411 end &250 12663 13412 sat 32 12664 13413 eat 32 … … 12680 13429 ) 12681 13430 ) 12682 on &24 512683 ) 12684 * 399(Wire13431 on &247 13432 ) 13433 *425 (Wire 12685 13434 uid 5634,0 12686 13435 shape (OrthoPolyLine … … 12697 13446 ) 12698 13447 start &38 12699 end &2 4913448 end &251 12700 13449 sat 32 12701 13450 eat 32 … … 12718 13467 ) 12719 13468 ) 12720 on &24 412721 ) 12722 *4 00(Wire13469 on &246 13470 ) 13471 *426 (Wire 12723 13472 uid 5646,0 12724 13473 shape (OrthoPolyLine … … 12734 13483 ] 12735 13484 ) 12736 end &25 113485 end &253 12737 13486 sat 16 12738 13487 eat 32 … … 12756 13505 on &162 12757 13506 ) 12758 *4 01(Wire13507 *427 (Wire 12759 13508 uid 5745,0 12760 13509 shape (OrthoPolyLine … … 12772 13521 ) 12773 13522 start &54 12774 end &26 013523 end &262 12775 13524 sat 32 12776 13525 eat 32 … … 12792 13541 ) 12793 13542 ) 12794 on &25 512795 ) 12796 *4 02(Wire13543 on &257 13544 ) 13545 *428 (Wire 12797 13546 uid 5805,0 12798 13547 shape (OrthoPolyLine … … 12807 13556 ] 12808 13557 ) 12809 end &26 513558 end &267 12810 13559 sat 16 12811 13560 eat 32 … … 12828 13577 on &164 12829 13578 ) 12830 *4 03(Wire13579 *429 (Wire 12831 13580 uid 5813,0 12832 13581 shape (OrthoPolyLine … … 12841 13590 ] 12842 13591 ) 12843 start &25 712844 end &27 613592 start &259 13593 end &278 12845 13594 sat 32 12846 13595 eat 32 … … 12864 13613 ) 12865 13614 ) 12866 on &27 212867 ) 12868 *4 04(Wire13615 on &274 13616 ) 13617 *430 (Wire 12869 13618 uid 5821,0 12870 13619 shape (OrthoPolyLine … … 12879 13628 ] 12880 13629 ) 12881 start &2 6812882 end &27 713630 start &270 13631 end &279 12883 13632 sat 32 12884 13633 eat 32 … … 12902 13651 ) 12903 13652 ) 12904 on &27 312905 ) 12906 *4 05(Wire13653 on &275 13654 ) 13655 *431 (Wire 12907 13656 uid 5829,0 12908 13657 shape (OrthoPolyLine … … 12917 13666 ] 12918 13667 ) 12919 start &26 312920 end &2 7813668 start &265 13669 end &280 12921 13670 sat 32 12922 13671 eat 32 … … 12940 13689 ) 12941 13690 ) 12942 on &27 412943 ) 12944 *4 06(Wire13691 on &276 13692 ) 13693 *432 (Wire 12945 13694 uid 5837,0 12946 13695 shape (OrthoPolyLine … … 12956 13705 ] 12957 13706 ) 12958 start &26 412959 end &2 7913707 start &266 13708 end &281 12960 13709 sat 32 12961 13710 eat 32 … … 12980 13729 ) 12981 13730 ) 12982 on &27 512983 ) 12984 *4 07(Wire13731 on &277 13732 ) 13733 *433 (Wire 12985 13734 uid 5950,0 12986 13735 shape (OrthoPolyLine … … 13018 13767 ) 13019 13768 ) 13020 on &28 013021 ) 13022 *4 08(Wire13769 on &282 13770 ) 13771 *434 (Wire 13023 13772 uid 5962,0 13024 13773 shape (OrthoPolyLine … … 13056 13805 ) 13057 13806 ) 13058 on &28 113059 ) 13060 *4 09(Wire13807 on &283 13808 ) 13809 *435 (Wire 13061 13810 uid 6002,0 13062 13811 shape (OrthoPolyLine … … 13094 13843 ) 13095 13844 ) 13096 on &28 313097 ) 13098 *4 10(Wire13845 on &285 13846 ) 13847 *436 (Wire 13099 13848 uid 6008,0 13100 13849 shape (OrthoPolyLine … … 13111 13860 ] 13112 13861 ) 13113 start &26 613862 start &268 13114 13863 end &59 13115 13864 sat 32 … … 13132 13881 ) 13133 13882 ) 13134 on &28 213135 ) 13136 *4 11(Wire13883 on &284 13884 ) 13885 *437 (Wire 13137 13886 uid 6018,0 13138 13887 shape (OrthoPolyLine … … 13170 13919 ) 13171 13920 ) 13172 on &28 413173 ) 13174 *4 12(Wire13921 on &286 13922 ) 13923 *438 (Wire 13175 13924 uid 6064,0 13176 13925 shape (OrthoPolyLine … … 13205 13954 ) 13206 13955 ) 13207 on &23 613208 ) 13209 *4 13(Wire13956 on &238 13957 ) 13958 *439 (Wire 13210 13959 uid 6072,0 13211 13960 shape (OrthoPolyLine … … 13223 13972 ) 13224 13973 start &167 13225 end & 37413974 end &400 13226 13975 sat 32 13227 13976 eat 32 … … 13246 13995 on &173 13247 13996 ) 13248 *4 14(Wire13997 *440 (Wire 13249 13998 uid 6082,0 13250 13999 shape (OrthoPolyLine … … 13262 14011 ) 13263 14012 start &112 13264 end & 39714013 end &423 13265 14014 sat 32 13266 14015 eat 32 … … 13285 14034 on &173 13286 14035 ) 13287 *4 15(Wire14036 *441 (Wire 13288 14037 uid 6160,0 13289 14038 shape (OrthoPolyLine … … 13298 14047 ] 13299 14048 ) 13300 start &26 713301 end &28 614049 start &269 14050 end &288 13302 14051 sat 32 13303 14052 eat 32 … … 13321 14070 ) 13322 14071 ) 13323 on &28 513324 ) 13325 *4 16(Wire14072 on &287 14073 ) 14074 *442 (Wire 13326 14075 uid 6276,0 13327 14076 shape (OrthoPolyLine … … 13357 14106 on &162 13358 14107 ) 13359 *4 17(Wire14108 *443 (Wire 13360 14109 uid 6362,0 13361 14110 shape (OrthoPolyLine … … 13371 14120 ) 13372 14121 start &94 13373 end &2 8814122 end &290 13374 14123 sat 32 13375 14124 eat 32 … … 13393 14142 ) 13394 14143 ) 13395 on &28 713396 ) 13397 *4 18(Wire14144 on &289 14145 ) 14146 *444 (Wire 13398 14147 uid 6452,0 13399 14148 shape (OrthoPolyLine … … 13430 14179 ) 13431 14180 ) 13432 on &2 8913433 ) 13434 *4 19(Wire14181 on &291 14182 ) 14183 *445 (Wire 13435 14184 uid 6540,0 13436 14185 shape (OrthoPolyLine … … 13445 14194 ] 13446 14195 ) 13447 start &29 414196 start &296 13448 14197 end &41 13449 14198 sat 32 … … 13467 14216 ) 13468 14217 ) 13469 on &3 0813470 ) 13471 *4 20(Wire14218 on &310 14219 ) 14220 *446 (Wire 13472 14221 uid 6548,0 13473 14222 shape (OrthoPolyLine … … 13482 14231 ] 13483 14232 ) 13484 start &29 614233 start &298 13485 14234 sat 32 13486 14235 eat 16 … … 13503 14252 ) 13504 14253 ) 13505 on &2 8913506 ) 13507 *4 21(Wire14254 on &291 14255 ) 14256 *447 (Wire 13508 14257 uid 8416,0 13509 14258 shape (OrthoPolyLine … … 13539 14288 ) 13540 14289 ) 13541 on &320 14290 on &322 14291 ) 14292 *448 (Wire 14293 uid 8510,0 14294 shape (OrthoPolyLine 14295 uid 8511,0 14296 va (VaSet 14297 vasetType 3 14298 lineWidth 2 14299 ) 14300 xt "92750,110000,102000,110000" 14301 pts [ 14302 "92750,110000" 14303 "102000,110000" 14304 ] 14305 ) 14306 start &227 14307 sat 32 14308 eat 16 14309 sty 1 14310 st 0 14311 sf 1 14312 si 0 14313 tg (WTG 14314 uid 8514,0 14315 ps "ConnStartEndStrategy" 14316 stg "STSignalDisplayStrategy" 14317 f (Text 14318 uid 8515,0 14319 va (VaSet 14320 ) 14321 xt "94000,109000,101200,110000" 14322 st "drs_address : (3:0)" 14323 blo "94000,109800" 14324 tm "WireNameMgr" 14325 ) 14326 ) 14327 on &323 14328 ) 14329 *449 (Wire 14330 uid 8518,0 14331 shape (OrthoPolyLine 14332 uid 8519,0 14333 va (VaSet 14334 vasetType 3 14335 ) 14336 xt "92750,111000,102000,111000" 14337 pts [ 14338 "92750,111000" 14339 "102000,111000" 14340 ] 14341 ) 14342 start &228 14343 sat 32 14344 eat 16 14345 st 0 14346 sf 1 14347 si 0 14348 tg (WTG 14349 uid 8522,0 14350 ps "ConnStartEndStrategy" 14351 stg "STSignalDisplayStrategy" 14352 f (Text 14353 uid 8523,0 14354 va (VaSet 14355 ) 14356 xt "94000,110000,101200,111000" 14357 st "drs_address_mode" 14358 blo "94000,110800" 14359 tm "WireNameMgr" 14360 ) 14361 ) 14362 on &324 14363 ) 14364 *450 (Wire 14365 uid 8577,0 14366 shape (OrthoPolyLine 14367 uid 8578,0 14368 va (VaSet 14369 vasetType 3 14370 lineWidth 2 14371 ) 14372 xt "7000,57000,18250,57000" 14373 pts [ 14374 "18250,57000" 14375 "7000,57000" 14376 ] 14377 ) 14378 start &39 14379 sat 32 14380 eat 16 14381 sty 1 14382 st 0 14383 sf 1 14384 si 0 14385 tg (WTG 14386 uid 8581,0 14387 ps "ConnStartEndStrategy" 14388 stg "STSignalDisplayStrategy" 14389 f (Text 14390 uid 8582,0 14391 va (VaSet 14392 ) 14393 xt "8000,56000,18400,57000" 14394 st "drs_channel_internal : (3:0)" 14395 blo "8000,56800" 14396 tm "WireNameMgr" 14397 ) 14398 ) 14399 on &346 14400 ) 14401 *451 (Wire 14402 uid 8587,0 14403 shape (OrthoPolyLine 14404 uid 8588,0 14405 va (VaSet 14406 vasetType 3 14407 lineWidth 2 14408 ) 14409 xt "-29000,101000,-20000,101000" 14410 pts [ 14411 "-20000,101000" 14412 "-29000,101000" 14413 ] 14414 ) 14415 end &326 14416 sat 16 14417 eat 32 14418 sty 1 14419 stc 0 14420 st 0 14421 sf 1 14422 si 0 14423 tg (WTG 14424 uid 8591,0 14425 ps "ConnStartEndStrategy" 14426 stg "STSignalDisplayStrategy" 14427 f (Text 14428 uid 8592,0 14429 va (VaSet 14430 ) 14431 xt "-29000,100000,-20800,101000" 14432 st "drs_channel_internal" 14433 blo "-29000,100800" 14434 tm "WireNameMgr" 14435 ) 14436 ) 14437 on &346 14438 ) 14439 *452 (Wire 14440 uid 8595,0 14441 shape (OrthoPolyLine 14442 uid 8596,0 14443 va (VaSet 14444 vasetType 3 14445 lineWidth 2 14446 ) 14447 xt "-29000,99000,-20000,99000" 14448 pts [ 14449 "-20000,99000" 14450 "-29000,99000" 14451 ] 14452 ) 14453 end &331 14454 sat 16 14455 eat 32 14456 sty 1 14457 stc 0 14458 st 0 14459 sf 1 14460 si 0 14461 tg (WTG 14462 uid 8599,0 14463 ps "ConnStartEndStrategy" 14464 stg "VerticalLayoutStrategy" 14465 f (Text 14466 uid 8600,0 14467 va (VaSet 14468 ) 14469 xt "-29000,98000,-24000,99000" 14470 st "drs_address" 14471 blo "-29000,98800" 14472 tm "WireNameMgr" 14473 ) 14474 ) 14475 on &323 14476 ) 14477 *453 (Wire 14478 uid 8603,0 14479 shape (OrthoPolyLine 14480 uid 8604,0 14481 va (VaSet 14482 vasetType 3 14483 ) 14484 xt "-31000,103000,-20000,107000" 14485 pts [ 14486 "-20000,107000" 14487 "-31000,107000" 14488 "-31000,103000" 14489 ] 14490 ) 14491 end &333 14492 sat 16 14493 eat 32 14494 stc 0 14495 st 0 14496 sf 1 14497 si 0 14498 tg (WTG 14499 uid 8607,0 14500 ps "ConnStartEndStrategy" 14501 stg "VerticalLayoutStrategy" 14502 f (Text 14503 uid 8608,0 14504 va (VaSet 14505 ) 14506 xt "-29000,106000,-21800,107000" 14507 st "drs_address_mode" 14508 blo "-29000,106800" 14509 tm "WireNameMgr" 14510 ) 14511 ) 14512 on &324 13542 14513 ) 13543 14514 ] … … 13553 14524 color "26368,26368,26368" 13554 14525 ) 13555 packageList *4 22(PackageList14526 packageList *454 (PackageList 13556 14527 uid 41,0 13557 14528 stg "VerticalLayoutStrategy" 13558 14529 textVec [ 13559 *4 23(Text14530 *455 (Text 13560 14531 uid 42,0 13561 14532 va (VaSet … … 13566 14537 blo "-87000,1800" 13567 14538 ) 13568 *4 24(MLText14539 *456 (MLText 13569 14540 uid 43,0 13570 14541 va (VaSet … … 13591 14562 stg "VerticalLayoutStrategy" 13592 14563 textVec [ 13593 *4 25(Text14564 *457 (Text 13594 14565 uid 45,0 13595 14566 va (VaSet … … 13601 14572 blo "20000,800" 13602 14573 ) 13603 *4 26(Text14574 *458 (Text 13604 14575 uid 46,0 13605 14576 va (VaSet … … 13611 14582 blo "20000,1800" 13612 14583 ) 13613 *4 27(MLText14584 *459 (MLText 13614 14585 uid 47,0 13615 14586 va (VaSet … … 13621 14592 tm "BdCompilerDirectivesTextMgr" 13622 14593 ) 13623 *4 28(Text14594 *460 (Text 13624 14595 uid 48,0 13625 14596 va (VaSet … … 13631 14602 blo "20000,4800" 13632 14603 ) 13633 *4 29(MLText14604 *461 (MLText 13634 14605 uid 49,0 13635 14606 va (VaSet … … 13639 14610 tm "BdCompilerDirectivesTextMgr" 13640 14611 ) 13641 *4 30(Text14612 *462 (Text 13642 14613 uid 50,0 13643 14614 va (VaSet … … 13649 14620 blo "20000,5800" 13650 14621 ) 13651 *4 31(MLText14622 *463 (MLText 13652 14623 uid 51,0 13653 14624 va (VaSet … … 13661 14632 ) 13662 14633 windowSize "0,0,1281,1024" 13663 viewArea "- 62364,34906,23843,105999"13664 cachedDiagramExtent "- 87000,0,162300,301700"14634 viewArea "-73966,37109,33461,125703" 14635 cachedDiagramExtent "-100999,0,162300,301700" 13665 14636 pageSetupInfo (PageSetupInfo 13666 14637 ptrCmd "eDocPrintPro,winspool," … … 13687 14658 hasePageBreakOrigin 1 13688 14659 pageBreakOrigin "-73000,0" 13689 lastUid 8 460,014660 lastUid 8614,0 13690 14661 defaultCommentText (CommentText 13691 14662 shape (Rectangle … … 13749 14720 stg "VerticalLayoutStrategy" 13750 14721 textVec [ 13751 *4 32(Text14722 *464 (Text 13752 14723 va (VaSet 13753 14724 font "Arial,8,1" … … 13758 14729 tm "BdLibraryNameMgr" 13759 14730 ) 13760 *4 33(Text14731 *465 (Text 13761 14732 va (VaSet 13762 14733 font "Arial,8,1" … … 13767 14738 tm "BlkNameMgr" 13768 14739 ) 13769 *4 34(Text14740 *466 (Text 13770 14741 va (VaSet 13771 14742 font "Arial,8,1" … … 13818 14789 stg "VerticalLayoutStrategy" 13819 14790 textVec [ 13820 *4 35(Text14791 *467 (Text 13821 14792 va (VaSet 13822 14793 font "Arial,8,1" … … 13826 14797 blo "550,4300" 13827 14798 ) 13828 *4 36(Text14799 *468 (Text 13829 14800 va (VaSet 13830 14801 font "Arial,8,1" … … 13834 14805 blo "550,5300" 13835 14806 ) 13836 *4 37(Text14807 *469 (Text 13837 14808 va (VaSet 13838 14809 font "Arial,8,1" … … 13883 14854 stg "VerticalLayoutStrategy" 13884 14855 textVec [ 13885 *4 38(Text14856 *470 (Text 13886 14857 va (VaSet 13887 14858 font "Arial,8,1" … … 13892 14863 tm "BdLibraryNameMgr" 13893 14864 ) 13894 *4 39(Text14865 *471 (Text 13895 14866 va (VaSet 13896 14867 font "Arial,8,1" … … 13901 14872 tm "CptNameMgr" 13902 14873 ) 13903 *4 40(Text14874 *472 (Text 13904 14875 va (VaSet 13905 14876 font "Arial,8,1" … … 13955 14926 stg "VerticalLayoutStrategy" 13956 14927 textVec [ 13957 *4 41(Text14928 *473 (Text 13958 14929 va (VaSet 13959 14930 font "Arial,8,1" … … 13963 14934 blo "500,4300" 13964 14935 ) 13965 *4 42(Text14936 *474 (Text 13966 14937 va (VaSet 13967 14938 font "Arial,8,1" … … 13971 14942 blo "500,5300" 13972 14943 ) 13973 *4 43(Text14944 *475 (Text 13974 14945 va (VaSet 13975 14946 font "Arial,8,1" … … 14016 14987 stg "VerticalLayoutStrategy" 14017 14988 textVec [ 14018 *4 44(Text14989 *476 (Text 14019 14990 va (VaSet 14020 14991 font "Arial,8,1" … … 14024 14995 blo "50,4300" 14025 14996 ) 14026 *4 45(Text14997 *477 (Text 14027 14998 va (VaSet 14028 14999 font "Arial,8,1" … … 14032 15003 blo "50,5300" 14033 15004 ) 14034 *4 46(Text15005 *478 (Text 14035 15006 va (VaSet 14036 15007 font "Arial,8,1" … … 14073 15044 stg "VerticalLayoutStrategy" 14074 15045 textVec [ 14075 *4 47(Text15046 *479 (Text 14076 15047 va (VaSet 14077 15048 font "Arial,8,1" … … 14082 15053 tm "HdlTextNameMgr" 14083 15054 ) 14084 *4 48(Text15055 *480 (Text 14085 15056 va (VaSet 14086 15057 font "Arial,8,1" … … 14485 15456 stg "VerticalLayoutStrategy" 14486 15457 textVec [ 14487 *4 49(Text15458 *481 (Text 14488 15459 va (VaSet 14489 15460 font "Arial,8,1" … … 14493 15464 blo "14100,20800" 14494 15465 ) 14495 *4 50(MLText15466 *482 (MLText 14496 15467 va (VaSet 14497 15468 ) … … 14545 15516 stg "VerticalLayoutStrategy" 14546 15517 textVec [ 14547 *4 51(Text15518 *483 (Text 14548 15519 va (VaSet 14549 15520 font "Arial,8,1" … … 14553 15524 blo "14100,20800" 14554 15525 ) 14555 *4 52(MLText15526 *484 (MLText 14556 15527 va (VaSet 14557 15528 ) … … 14678 15649 font "Arial,8,1" 14679 15650 ) 14680 xt "-87000,8 5000,-82300,86000"15651 xt "-87000,87400,-82300,88400" 14681 15652 st "Post User:" 14682 blo "-87000,8 5800"15653 blo "-87000,88200" 14683 15654 ) 14684 15655 postUserText (MLText … … 14693 15664 commonDM (CommonDM 14694 15665 ldm (LogicalDM 14695 suid 1 83,015666 suid 190,0 14696 15667 usingSuid 1 14697 emptyRow *4 53(LEmptyRow15668 emptyRow *485 (LEmptyRow 14698 15669 ) 14699 15670 uid 54,0 14700 15671 optionalChildren [ 14701 *4 54(RefLabelRowHdr14702 ) 14703 *4 55(TitleRowHdr14704 ) 14705 *4 56(FilterRowHdr14706 ) 14707 *4 57(RefLabelColHdr15672 *486 (RefLabelRowHdr 15673 ) 15674 *487 (TitleRowHdr 15675 ) 15676 *488 (FilterRowHdr 15677 ) 15678 *489 (RefLabelColHdr 14708 15679 tm "RefLabelColHdrMgr" 14709 15680 ) 14710 *4 58(RowExpandColHdr15681 *490 (RowExpandColHdr 14711 15682 tm "RowExpandColHdrMgr" 14712 15683 ) 14713 *4 59(GroupColHdr15684 *491 (GroupColHdr 14714 15685 tm "GroupColHdrMgr" 14715 15686 ) 14716 *4 60(NameColHdr15687 *492 (NameColHdr 14717 15688 tm "BlockDiagramNameColHdrMgr" 14718 15689 ) 14719 *4 61(ModeColHdr15690 *493 (ModeColHdr 14720 15691 tm "BlockDiagramModeColHdrMgr" 14721 15692 ) 14722 *4 62(TypeColHdr15693 *494 (TypeColHdr 14723 15694 tm "BlockDiagramTypeColHdrMgr" 14724 15695 ) 14725 *4 63(BoundsColHdr15696 *495 (BoundsColHdr 14726 15697 tm "BlockDiagramBoundsColHdrMgr" 14727 15698 ) 14728 *4 64(InitColHdr15699 *496 (InitColHdr 14729 15700 tm "BlockDiagramInitColHdrMgr" 14730 15701 ) 14731 *4 65(EolColHdr15702 *497 (EolColHdr 14732 15703 tm "BlockDiagramEolColHdrMgr" 14733 15704 ) 14734 *4 66(LeafLogPort15705 *498 (LeafLogPort 14735 15706 port (LogicalPort 14736 15707 m 4 … … 14746 15717 uid 516,0 14747 15718 ) 14748 *4 67(LeafLogPort15719 *499 (LeafLogPort 14749 15720 port (LogicalPort 14750 15721 m 4 … … 14759 15730 uid 518,0 14760 15731 ) 14761 * 468(LeafLogPort15732 *500 (LeafLogPort 14762 15733 port (LogicalPort 14763 15734 m 4 … … 14772 15743 uid 520,0 14773 15744 ) 14774 * 469(LeafLogPort15745 *501 (LeafLogPort 14775 15746 port (LogicalPort 14776 15747 m 4 … … 14785 15756 uid 530,0 14786 15757 ) 14787 * 470(LeafLogPort15758 *502 (LeafLogPort 14788 15759 port (LogicalPort 14789 15760 m 4 … … 14798 15769 uid 532,0 14799 15770 ) 14800 * 471(LeafLogPort15771 *503 (LeafLogPort 14801 15772 port (LogicalPort 14802 15773 m 1 … … 14811 15782 uid 534,0 14812 15783 ) 14813 * 472(LeafLogPort15784 *504 (LeafLogPort 14814 15785 port (LogicalPort 14815 15786 m 1 … … 14824 15795 uid 536,0 14825 15796 ) 14826 * 473(LeafLogPort15797 *505 (LeafLogPort 14827 15798 port (LogicalPort 14828 15799 m 2 … … 14837 15808 uid 538,0 14838 15809 ) 14839 * 474(LeafLogPort15810 *506 (LeafLogPort 14840 15811 port (LogicalPort 14841 15812 m 1 … … 14850 15821 uid 540,0 14851 15822 ) 14852 * 475(LeafLogPort15823 *507 (LeafLogPort 14853 15824 port (LogicalPort 14854 15825 m 1 … … 14863 15834 uid 542,0 14864 15835 ) 14865 * 476(LeafLogPort15836 *508 (LeafLogPort 14866 15837 port (LogicalPort 14867 15838 m 1 … … 14876 15847 uid 546,0 14877 15848 ) 14878 * 477(LeafLogPort15849 *509 (LeafLogPort 14879 15850 port (LogicalPort 14880 15851 decl (Decl … … 14887 15858 uid 548,0 14888 15859 ) 14889 * 478(LeafLogPort15860 *510 (LeafLogPort 14890 15861 port (LogicalPort 14891 15862 decl (Decl … … 14901 15872 uid 1455,0 14902 15873 ) 14903 * 479(LeafLogPort15874 *511 (LeafLogPort 14904 15875 port (LogicalPort 14905 15876 decl (Decl … … 14914 15885 uid 1457,0 14915 15886 ) 14916 * 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FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/w5300_modul/symbol.sb
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89(RefLabelColHdr794 *88 (RefLabelRowHdr 795 ) 796 *89 (TitleRowHdr 797 ) 798 *90 (FilterRowHdr 799 ) 800 *91 (RefLabelColHdr 780 801 tm "RefLabelColHdrMgr" 781 802 ) 782 *9 0(RowExpandColHdr803 *92 (RowExpandColHdr 783 804 tm "RowExpandColHdrMgr" 784 805 ) 785 *9 1(GroupColHdr806 *93 (GroupColHdr 786 807 tm "GroupColHdrMgr" 787 808 ) 788 *9 2(NameColHdr809 *94 (NameColHdr 789 810 tm "GenericNameColHdrMgr" 790 811 ) 791 *9 3(TypeColHdr812 *95 (TypeColHdr 792 813 tm "GenericTypeColHdrMgr" 793 814 ) 794 *9 4(InitColHdr815 *96 (InitColHdr 795 816 tm "GenericValueColHdrMgr" 796 817 ) 797 *9 5(PragmaColHdr818 *97 (PragmaColHdr 798 819 tm "GenericPragmaColHdrMgr" 799 820 ) 800 *9 6(EolColHdr821 *98 (EolColHdr 801 822 tm "GenericEolColHdrMgr" 802 823 ) 803 *9 7(LogGeneric824 *99 (LogGeneric 804 825 generic (GiElement 805 826 name "RAM_ADDR_WIDTH" … … 807 828 value "14" 808 829 ) 809 uid 892,0830 uid 924,0 810 831 ) 811 832 ] … … 816 837 uid 216,0 817 838 optionalChildren [ 818 * 98(Sheet839 *100 (Sheet 819 840 sheetRow (SheetRow 820 841 headerVa (MVa … … 833 854 font "Tahoma,10,0" 834 855 ) 835 emptyMRCItem * 99(MRCItem836 litem &8 5856 emptyMRCItem *101 (MRCItem 857 litem &87 837 858 pos 3 838 859 dimension 20 … … 840 861 uid 218,0 841 862 optionalChildren [ 842 *10 0(MRCItem843 litem &8 6863 *102 (MRCItem 864 litem &88 844 865 pos 0 845 866 dimension 20 846 867 uid 219,0 847 868 ) 848 *10 1(MRCItem849 litem &8 7869 *103 (MRCItem 870 litem &89 850 871 pos 1 851 872 dimension 23 852 873 uid 220,0 853 874 ) 854 *10 2(MRCItem855 litem & 88875 *104 (MRCItem 876 litem &90 856 877 pos 2 857 878 hidden 1 … … 859 880 uid 221,0 860 881 ) 861 *10 3(MRCItem862 litem &9 7882 *105 (MRCItem 883 litem &99 863 884 pos 0 864 885 dimension 20 865 uid 893,0886 uid 925,0 866 887 ) 867 888 ] … … 876 897 uid 222,0 877 898 optionalChildren [ 878 *10 4(MRCItem879 litem & 89899 *106 (MRCItem 900 litem &91 880 901 pos 0 881 902 dimension 20 882 903 uid 223,0 883 904 ) 884 *10 5(MRCItem885 litem &9 1905 *107 (MRCItem 906 litem &93 886 907 pos 1 887 908 dimension 50 888 909 uid 224,0 889 910 ) 890 *10 6(MRCItem891 litem &9 2911 *108 (MRCItem 912 litem &94 892 913 pos 2 893 914 dimension 100 894 915 uid 225,0 895 916 ) 896 *10 7(MRCItem897 litem &9 3917 *109 (MRCItem 918 litem &95 898 919 pos 3 899 920 dimension 100 900 921 uid 226,0 901 922 ) 902 *1 08(MRCItem903 litem &9 4923 *110 (MRCItem 924 litem &96 904 925 pos 4 905 926 dimension 50 906 927 uid 227,0 907 928 ) 908 *1 09(MRCItem909 litem &9 5929 *111 (MRCItem 930 litem &97 910 931 pos 5 911 932 dimension 50 912 933 uid 228,0 913 934 ) 914 *11 0(MRCItem915 litem &9 6935 *112 (MRCItem 936 litem &98 916 937 pos 6 917 938 dimension 80 … … 936 957 (vvPair 937 958 variable "HDLDir" 938 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hdl"959 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" 939 960 ) 940 961 (vvPair 941 962 variable "HDSDir" 942 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds"963 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 943 964 ) 944 965 (vvPair 945 966 variable "SideDataDesignDir" 946 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb.info"967 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb.info" 947 968 ) 948 969 (vvPair 949 970 variable "SideDataUserDir" 950 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb.user"971 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb.user" 951 972 ) 952 973 (vvPair 953 974 variable "SourceDir" 954 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds"975 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 955 976 ) 956 977 (vvPair … … 968 989 (vvPair 969 990 variable "d" 970 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\w5300_modul"991 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\w5300_modul" 971 992 ) 972 993 (vvPair 973 994 variable "d_logical" 974 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\w5300_modul"995 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\w5300_modul" 975 996 ) 976 997 (vvPair 977 998 variable "date" 978 value " 02.07.2010"999 value "21.07.2010" 979 1000 ) 980 1001 (vvPair 981 1002 variable "day" 982 value " Fr"1003 value "Mi" 983 1004 ) 984 1005 (vvPair 985 1006 variable "day_long" 986 value " Freitag"1007 value "Mittwoch" 987 1008 ) 988 1009 (vvPair 989 1010 variable "dd" 990 value " 02"1011 value "21" 991 1012 ) 992 1013 (vvPair … … 1016 1037 (vvPair 1017 1038 variable "host" 1018 value " TU-CC4900F8C7D2"1039 value "E5B-LABOR6" 1019 1040 ) 1020 1041 (vvPair … … 1068 1089 (vvPair 1069 1090 variable "p" 1070 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb"1091 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb" 1071 1092 ) 1072 1093 (vvPair 1073 1094 variable "p_logical" 1074 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb"1095 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb" 1075 1096 ) 1076 1097 (vvPair … … 1128 1149 (vvPair 1129 1150 variable "time" 1130 value "1 0:38:02"1151 value "11:26:29" 1131 1152 ) 1132 1153 (vvPair … … 1159 1180 uid 173,0 1160 1181 optionalChildren [ 1161 *11 1(SymbolBody1182 *113 (SymbolBody 1162 1183 uid 8,0 1163 1184 optionalChildren [ 1164 *11 2(CptPort1185 *114 (CptPort 1165 1186 uid 48,0 1166 1187 ps "OnEdgeStrategy" … … 1208 1229 ) 1209 1230 ) 1210 *11 3(CptPort1231 *115 (CptPort 1211 1232 uid 53,0 1212 1233 ps "OnEdgeStrategy" … … 1257 1278 ) 1258 1279 ) 1259 *11 4(CptPort1280 *116 (CptPort 1260 1281 uid 58,0 1261 1282 ps "OnEdgeStrategy" … … 1306 1327 ) 1307 1328 ) 1308 *11 5(CptPort1329 *117 (CptPort 1309 1330 uid 63,0 1310 1331 ps "OnEdgeStrategy" … … 1355 1376 ) 1356 1377 ) 1357 *11 6(CptPort1378 *118 (CptPort 1358 1379 uid 68,0 1359 1380 ps "OnEdgeStrategy" … … 1404 1425 ) 1405 1426 ) 1406 *11 7(CptPort1427 *119 (CptPort 1407 1428 uid 73,0 1408 1429 ps "OnEdgeStrategy" … … 1453 1474 ) 1454 1475 ) 1455 *1 18(CptPort1476 *120 (CptPort 1456 1477 uid 83,0 1457 1478 ps "OnEdgeStrategy" … … 1502 1523 ) 1503 1524 ) 1504 *1 19(CptPort1525 *121 (CptPort 1505 1526 uid 88,0 1506 1527 ps "OnEdgeStrategy" … … 1548 1569 ) 1549 1570 ) 1550 *12 0(CptPort1571 *122 (CptPort 1551 1572 uid 93,0 1552 1573 ps "OnEdgeStrategy" … … 1595 1616 ) 1596 1617 ) 1597 *12 1(CptPort1618 *123 (CptPort 1598 1619 uid 98,0 1599 1620 ps "OnEdgeStrategy" … … 1642 1663 ) 1643 1664 ) 1644 *12 2(CptPort1665 *124 (CptPort 1645 1666 uid 103,0 1646 1667 ps "OnEdgeStrategy" … … 1689 1710 ) 1690 1711 ) 1691 *12 3(CptPort1712 *125 (CptPort 1692 1713 uid 108,0 1693 1714 ps "OnEdgeStrategy" … … 1738 1759 ) 1739 1760 ) 1740 *12 4(CptPort1761 *126 (CptPort 1741 1762 uid 113,0 1742 1763 ps "OnEdgeStrategy" … … 1784 1805 ) 1785 1806 ) 1786 *12 5(CptPort1807 *127 (CptPort 1787 1808 uid 118,0 1788 1809 ps "OnEdgeStrategy" … … 1833 1854 ) 1834 1855 ) 1835 *12 6(CommentText1856 *128 (CommentText 1836 1857 uid 299,0 1837 1858 ps "EdgeToEdgeStrategy" … … 1867 1888 excludeCommentLeader 1 1868 1889 ) 1869 *12 7(CptPort1890 *129 (CptPort 1870 1891 uid 348,0 1871 1892 ps "OnEdgeStrategy" … … 1911 1932 ) 1912 1933 ) 1913 *1 28(CptPort1934 *130 (CptPort 1914 1935 uid 353,0 1915 1936 ps "OnEdgeStrategy" … … 1955 1976 ) 1956 1977 ) 1957 *1 29(CptPort1978 *131 (CptPort 1958 1979 uid 385,0 1959 1980 ps "OnEdgeStrategy" … … 2000 2021 ) 2001 2022 ) 2002 *13 0(CptPort2023 *132 (CptPort 2003 2024 uid 491,0 2004 2025 ps "OnEdgeStrategy" … … 2049 2070 ) 2050 2071 ) 2051 *13 1(CptPort2072 *133 (CptPort 2052 2073 uid 521,0 2053 2074 ps "OnEdgeStrategy" … … 2096 2117 ) 2097 2118 ) 2098 *13 2(CptPort2119 *134 (CptPort 2099 2120 uid 551,0 2100 2121 ps "OnEdgeStrategy" … … 2143 2164 ) 2144 2165 ) 2145 *13 3(CptPort2166 *135 (CptPort 2146 2167 uid 556,0 2147 2168 ps "OnEdgeStrategy" … … 2187 2208 ) 2188 2209 ) 2189 *13 4(CptPort2210 *136 (CptPort 2190 2211 uid 561,0 2191 2212 ps "OnEdgeStrategy" … … 2235 2256 ) 2236 2257 ) 2237 *13 5(CptPort2258 *137 (CptPort 2238 2259 uid 566,0 2239 2260 ps "OnEdgeStrategy" … … 2279 2300 ) 2280 2301 ) 2281 *13 6(CptPort2302 *138 (CptPort 2282 2303 uid 571,0 2283 2304 ps "OnEdgeStrategy" … … 2326 2347 ) 2327 2348 ) 2328 *13 7(CptPort2349 *139 (CptPort 2329 2350 uid 576,0 2330 2351 ps "OnEdgeStrategy" … … 2373 2394 ) 2374 2395 ) 2375 *1 38(CptPort2396 *140 (CptPort 2376 2397 uid 640,0 2377 2398 ps "OnEdgeStrategy" … … 2420 2441 ) 2421 2442 ) 2422 *1 39(CptPort2443 *141 (CptPort 2423 2444 uid 670,0 2424 2445 ps "OnEdgeStrategy" … … 2469 2490 ) 2470 2491 ) 2471 *14 0(CptPort2492 *142 (CptPort 2472 2493 uid 723,0 2473 2494 ps "OnEdgeStrategy" … … 2501 2522 font "Courier New,8,0" 2502 2523 ) 2503 xt "2000,38400,4 7500,39200"2504 st "dwrite_enable : OUT std_logic := '0' -- default DWRITE low.2524 xt "2000,38400,48500,39200" 2525 st "dwrite_enable : OUT std_logic := '0' ; -- default DWRITE low. 2505 2526 " 2506 2527 ) … … 2519 2540 ) 2520 2541 ) 2521 *14 1(CptPort2542 *143 (CptPort 2522 2543 uid 885,0 2523 2544 ps "OnEdgeStrategy" … … 2566 2587 ) 2567 2588 ) 2589 *144 (CptPort 2590 uid 917,0 2591 ps "OnEdgeStrategy" 2592 shape (Triangle 2593 uid 918,0 2594 ro 90 2595 va (VaSet 2596 vasetType 1 2597 fg "0,65535,0" 2598 ) 2599 xt "77000,30625,77750,31375" 2600 ) 2601 tg (CPTG 2602 uid 919,0 2603 ps "CptPortTextPlaceStrategy" 2604 stg "RightVerticalLayoutStrategy" 2605 f (Text 2606 uid 920,0 2607 va (VaSet 2608 ) 2609 xt "71300,30500,76000,31500" 2610 st "sclk_enable" 2611 ju 2 2612 blo "76000,31300" 2613 tm "CptPortNameMgr" 2614 ) 2615 ) 2616 dt (MLText 2617 uid 921,0 2618 va (VaSet 2619 font "Courier New,8,0" 2620 ) 2621 xt "2000,39200,48000,40000" 2622 st "sclk_enable : OUT std_logic := '1' -- default DWRITE HIGH. 2623 " 2624 ) 2625 thePort (LogicalPort 2626 m 1 2627 decl (Decl 2628 n "sclk_enable" 2629 t "std_logic" 2630 eolc "-- default DWRITE HIGH." 2631 posAdd 0 2632 o 30 2633 suid 35,0 2634 i "'1'" 2635 ) 2636 ) 2637 ) 2568 2638 ] 2569 2639 shape (Rectangle … … 2575 2645 lineWidth 2 2576 2646 ) 2577 xt "43000,2000,77000,3 1000"2647 xt "43000,2000,77000,32000" 2578 2648 ) 2579 2649 oxt "43000,2000,56000,22000" … … 2601 2671 ) 2602 2672 ) 2603 gi *14 2(GenericInterface2673 gi *145 (GenericInterface 2604 2674 uid 13,0 2605 2675 ps "CenterOffsetStrategy" … … 2637 2707 ) 2638 2708 ) 2639 *14 3(Grouping2709 *146 (Grouping 2640 2710 uid 16,0 2641 2711 optionalChildren [ 2642 *14 4(CommentText2712 *147 (CommentText 2643 2713 uid 18,0 2644 2714 shape (Rectangle … … 2658 2728 bg "0,0,32768" 2659 2729 ) 2660 xt "47200,30000,56 700,31000"2730 xt "47200,30000,56500,31000" 2661 2731 st " 2662 2732 by %user on %dd %month %year … … 2671 2741 titleBlock 1 2672 2742 ) 2673 *14 5(CommentText2743 *148 (CommentText 2674 2744 uid 21,0 2675 2745 shape (Rectangle … … 2702 2772 titleBlock 1 2703 2773 ) 2704 *14 6(CommentText2774 *149 (CommentText 2705 2775 uid 24,0 2706 2776 shape (Rectangle … … 2733 2803 titleBlock 1 2734 2804 ) 2735 *1 47(CommentText2805 *150 (CommentText 2736 2806 uid 27,0 2737 2807 shape (Rectangle … … 2764 2834 titleBlock 1 2765 2835 ) 2766 *1 48(CommentText2836 *151 (CommentText 2767 2837 uid 30,0 2768 2838 shape (Rectangle … … 2794 2864 titleBlock 1 2795 2865 ) 2796 *1 49(CommentText2866 *152 (CommentText 2797 2867 uid 33,0 2798 2868 shape (Rectangle … … 2825 2895 titleBlock 1 2826 2896 ) 2827 *15 0(CommentText2897 *153 (CommentText 2828 2898 uid 36,0 2829 2899 shape (Rectangle … … 2856 2926 titleBlock 1 2857 2927 ) 2858 *15 1(CommentText2928 *154 (CommentText 2859 2929 uid 39,0 2860 2930 shape (Rectangle … … 2887 2957 titleBlock 1 2888 2958 ) 2889 *15 2(CommentText2959 *155 (CommentText 2890 2960 uid 42,0 2891 2961 shape (Rectangle … … 2918 2988 titleBlock 1 2919 2989 ) 2920 *15 3(CommentText2990 *156 (CommentText 2921 2991 uid 45,0 2922 2992 shape (Rectangle … … 2962 3032 oxt "14000,66000,55000,71000" 2963 3033 ) 2964 *15 4(CommentText3034 *157 (CommentText 2965 3035 uid 133,0 2966 3036 shape (Rectangle … … 3005 3075 color "26368,26368,26368" 3006 3076 ) 3007 packageList *15 5(PackageList3077 packageList *158 (PackageList 3008 3078 uid 170,0 3009 3079 stg "VerticalLayoutStrategy" 3010 3080 textVec [ 3011 *15 6(Text3081 *159 (Text 3012 3082 uid 171,0 3013 3083 va (VaSet … … 3018 3088 blo "0,1800" 3019 3089 ) 3020 *1 57(MLText3090 *160 (MLText 3021 3091 uid 172,0 3022 3092 va (VaSet … … 3119 3189 ) 3120 3190 ) 3121 gi *1 58(GenericInterface3191 gi *161 (GenericInterface 3122 3192 ps "CenterOffsetStrategy" 3123 3193 matrix (Matrix … … 3216 3286 ) 3217 3287 ) 3218 DeclarativeBlock *1 59(SymDeclBlock3288 DeclarativeBlock *162 (SymDeclBlock 3219 3289 uid 1,0 3220 3290 stg "SymDeclLayoutStrategy" … … 3242 3312 font "Arial,8,1" 3243 3313 ) 3244 xt "0, 39200,2400,40200"3314 xt "0,40000,2400,41000" 3245 3315 st "User:" 3246 blo "0,40 000"3316 blo "0,40800" 3247 3317 ) 3248 3318 internalLabel (Text … … 3261 3331 font "Courier New,8,0" 3262 3332 ) 3263 xt "2000,4 0200,2000,40200"3333 xt "2000,41000,2000,41000" 3264 3334 tm "SyDeclarativeTextMgr" 3265 3335 ) … … 3274 3344 ) 3275 3345 ) 3276 lastUid 893,03346 lastUid 925,0 3277 3347 activeModelName "Symbol:CDM" 3278 3348 )
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