Changeset 10081 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl

Timestamp:

01/05/11 17:19:13 (14 years ago)

Author:

neise

Message:

DRS write shift register & write config register

Location:

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl

Files:

• data_generator.vhd (modified) (7 diffs)
• data_generator.vhd.bak (modified) (8 diffs)
• drs_pulser_dummy.vhd (modified) (3 diffs)
• fad_board_struct.vhd (modified) (7 diffs)
• fad_definitions.vhd (modified) (1 diff)
• fad_definitions.vhd.bak (modified) (4 diffs)
• fad_main_struct.vhd (modified) (6 diffs)

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd

@@ -67 +67 @@
 
       drs_read_s_cell_ready : in std_logic;
-      drs_s_cell_array : in drs_s_cell_array_type
+      drs_s_cell_array : in drs_s_cell_array_type;
+      
+      drs_readout_started : out std_logic
       );
 end data_generator ;
@@ -73 +75 @@
 architecture Behavioral of data_generator is
 
-type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
+type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
                              WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
                              WRITE_END_FLAG, WRITE_DATA_STOP,
@@ -93 +95 @@
 signal roi_max_int : roi_max_type;
 
+signal sig_drs_readout_started : std_logic := '0';
+
 begin
   
+  drs_readout_started <= sig_drs_readout_started;
   
         generate_data : process (clk)
@@ -151 +156 @@
           if (drs_srin_write_ready = '1') then
             roi_max_int <= roi_max;
-            state_generate <= WRITE_DATA_IDLE;
-          end if;
+            state_generate <= CONFIG6;
+          end if;
+          when CONFIG6 =>
+            drs_channel_id <= DRS_WRITE_CONFIG_REG;
+            drs_srin_data <= "11111111";
+            drs_srin_write_8b <= '1';
+            if (drs_srin_write_ack = '1') then
+              drs_srin_write_8b <= '0';
+              state_generate <= CONFIG7;
+            end if;
+          when CONFIG7 =>
+            if (drs_srin_write_ready = '1') then
+              roi_max_int <= roi_max;
+              state_generate <= WRITE_DATA_IDLE;
+            end if;
         -- end configure DRS
 
@@ -161 +179 @@
 --          if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then
           if (ram_write_ea = '1' and trigger_flag = '1') then
+            sig_drs_readout_started <= '1'; -- is set to '0' in state WRITE_DAC1
             -- stop drs, dwrite low
             drs_dwrite <= '0';
@@ -193 +212 @@
 
         when WRITE_DAC1 =>
+          sig_drs_readout_started <= '0'; -- is set to '1' in state WRITE_DATA_IDLE
           data_out <= conv_std_logic_vector (dac_array (3), 16)
                     & conv_std_logic_vector (dac_array (2), 16)
@@ -256 +276 @@
                       & "000" & adc_otr(1) & adc_data_array(1)
                       & "000" & adc_otr(0) & adc_data_array(0);
---              data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) 
+ --             data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) 
 --                          & "00010" & conv_std_logic_vector (data_cntr, 11) 
 --                          & "00100" & conv_std_logic_vector (data_cntr, 11) 

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak

@@ -67 +67 @@
 
       drs_read_s_cell_ready : in std_logic;
-      drs_s_cell_array : in drs_s_cell_array_type
+      drs_s_cell_array : in drs_s_cell_array_type;
+      
+      drs_readout_started : out std_logic
       );
 end data_generator ;
@@ -73 +75 @@
 architecture Behavioral of data_generator is
 
-type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
+type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
                              WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
                              WRITE_END_FLAG, WRITE_DATA_STOP,
@@ -93 +95 @@
 signal roi_max_int : roi_max_type;
 
+signal sig_drs_readout_started : std_logic := '0';
+
 begin
   
+  drs_readout_started <= sig_drs_readout_started;
   
         generate_data : process (clk)
@@ -142 +147 @@
         when CONFIG4 =>
           drs_channel_id <= DRS_WRITE_SHIFT_REG;
-          drs_srin_data <= "10101010";
+          drs_srin_data <= "11111111";
           drs_srin_write_8b <= '1';
           if (drs_srin_write_ack = '1') then
@@ -151 +156 @@
           if (drs_srin_write_ready = '1') then
             roi_max_int <= roi_max;
-            state_generate <= WRITE_DATA_IDLE;
-          end if;
+            state_generate <= CONFIG6;
+          end if;
+          when CONFIG6 =>
+            drs_channel_id <= DRS_WRITE_CONFIG_REG;
+            drs_srin_data <= "11111111";
+            drs_srin_write_8b <= '1';
+            if (drs_srin_write_ack = '1') then
+              drs_srin_write_8b <= '0';
+              state_generate <= CONFIG7;
+            end if;
+          when CONFIG7 =>
+            if (drs_srin_write_ready = '1') then
+              roi_max_int <= roi_max;
+              state_generate <= WRITE_DATA_IDLE;
+            end if;
         -- end configure DRS
 
@@ -161 +179 @@
 --          if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then
           if (ram_write_ea = '1' and trigger_flag = '1') then
+            sig_drs_readout_started <= '1'; -- is set to '0' in state WRITE_DAC1
             -- stop drs, dwrite low
             drs_dwrite <= '0';
@@ -193 +212 @@
 
         when WRITE_DAC1 =>
+          sig_drs_readout_started <= '0'; -- is set to '1' in state WRITE_DATA_IDLE
           data_out <= conv_std_logic_vector (dac_array (3), 16)
                     & conv_std_logic_vector (dac_array (2), 16)
@@ -252 +272 @@
         when WRITE_ADC_DATA =>
           if (data_cntr < roi_max (channel_id)) then
-            data_out <= "000" & adc_otr(3) & adc_data_array(3)
-                      & "000" & adc_otr(2) & adc_data_array(2)
-                      & "000" & adc_otr(1) & adc_data_array(1)
-                      & "000" & adc_otr(0) & adc_data_array(0);
---              data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) 
---                          & "00010" & conv_std_logic_vector (data_cntr, 11) 
---                          & "00100" & conv_std_logic_vector (data_cntr, 11) 
---                          & "00110" & conv_std_logic_vector (data_cntr, 11) ;
+--            data_out <= "000" & adc_otr(3) & adc_data_array(3)
+--                      & "000" & adc_otr(2) & adc_data_array(2)
+--                      & "000" & adc_otr(1) & adc_data_array(1)
+--                      & "000" & adc_otr(0) & adc_data_array(0);
+              data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) 
+                          & "00010" & conv_std_logic_vector (data_cntr, 11) 
+                          & "00100" & conv_std_logic_vector (data_cntr, 11) 
+                          & "00110" & conv_std_logic_vector (data_cntr, 11) ;
             addr_cntr <= addr_cntr + 1;
             state_generate <= WRITE_ADC_DATA;

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd

@@ -61 +61 @@
             srin_write_ack <= '1';
             srin_cntr <= 0;
-            SRCLK_EN <= '1';
+            --SRCLK_EN <= '1';
             state_main <= SRIN_WRITE_8B;
           end if;
@@ -75 +75 @@
         
         when SRIN_WRITE_8B =>
+          SRCLK_EN <= '1';
           srin_out <= srin_data (7 - srin_cntr);
           if (srin_cntr = 7) then
-            SRCLK_EN <= '0';
+            --SRCLK_EN <= '0';
             state_main <= SRIN_WRITE_END;
           else
@@ -83 +84 @@
           end if;
         when SRIN_WRITE_END =>
-          srin_out <= '0';
+          SRCLK_EN <= '0';
+          srin_out <= '1';
           srin_write_ready <= '1';
           srin_write_ack <= '0';

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd

@@ -3 +3 @@
 -- Created:
 --          by - dneise.UNKNOWN (E5B-LABOR6)
---          at - 12:19:07 05.01.2011
+--          at - 17:46:34 05.01.2011
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
@@ -79 +79 @@
 -- Created:
 --          by - dneise.UNKNOWN (E5B-LABOR6)
---          at - 12:19:08 05.01.2011
+--          at - 17:46:35 05.01.2011
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
@@ -124 +124 @@
    -- status:
    SIGNAL shifting        : std_logic                    := '0';
+
+   -- Implicit buffer signal declarations
+   SIGNAL SRIN_internal : std_logic;
 
 
@@ -253 +256 @@
    -- HDL Embedded Text Block 9 eb3
    -- eb3 9                          
-   A0_T(0) <= CLK50_OUT;
-   A0_T(1)  <= CLK25_OUT;
+   A0_T(0) <= ready;
+   A0_T(1) <= shifting;
    A0_T(2) <= CLK25_PSOUT;
    A0_T(3) <= PS_DIR_IN;
@@ -262 +265 @@
    A0_T(7) <= DCM_locked;
    
-   A1_T(0) <= ready;
-   A1_T(1) <= shifting;
-   A1_T(2) <= PSDONE_extraOUT;
-   A1_T(3) <= PSCLK_OUT;
-   A1_T(4) <= LOCKED_extraOUT;
-   
-   A1_T(5) <= '0';
-   A1_T(6) <= '0';
-   A1_T(7) <= '0';
+   A1_T(0) <= SRIN_internal;
+   A1_T(1) <= PSDONE_extraOUT;
+   A1_T(2) <= PSCLK_OUT;
+   A1_T(3) <= LOCKED_extraOUT;
+   
+   A1_T(4) <= drs_channel_id(0);
+   A1_T(5) <= drs_channel_id(1);
+   A1_T(6) <= drs_channel_id(2);
+   A1_T(7) <= drs_channel_id(3);
 
 
@@ -311 +314 @@
          RSRLOAD         => RSRLOAD,
          SRCLK           => SRCLK,
-         SRIN_out        => SRIN,
+         SRIN_out        => SRIN_internal,
          adc_clk_en      => adc_clk_en,
          adc_oeb         => OE_ADC,
@@ -337 +340 @@
       );
 
+   -- Implicit buffered output assignments
+   SRIN <= SRIN_internal;
+
 END struct;

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd

@@ -140 +140 @@
 constant CMD_PS_RESET : std_logic_vector     := X"17";
 -- DRS Registers
+  constant DRS_CONFIG_REG : std_logic_vector := "1100";  
   constant DRS_WRITE_SHIFT_REG : std_logic_vector := "1101";  
-  
+  constant DRS_WRITE_CONFIG_REG : std_logic_vector := "1110";  
+  constant DRS_DISABLE_ALL_OUTS : std_logic_vector := "1111";  
   
 -- Declare functions and procedure

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd.bak

@@ -23 +23 @@
   
   -- @ ETH zurich
-    constant NETMASK : ip_type := (255, 255, 248, 0);
-    constant IP_ADDRESS : ip_type := (192, 33, 99, 225);
-    constant GATEWAY : ip_type := (192, 33, 96, 1);
+--    constant NETMASK : ip_type := (255, 255, 248, 0);
+--    constant IP_ADDRESS : ip_type := (192, 33, 99, 225);
+--    constant GATEWAY : ip_type := (192, 33, 96, 1);
 
   -- @ TU Dortmund
---  constant NETMASK : ip_type := (255, 255, 255, 0);
---  constant IP_ADDRESS : ip_type := (129, 217, 160, 119);
---  constant GATEWAY : ip_type := (129, 217, 160, 1);
+  constant NETMASK : ip_type := (255, 255, 255, 0);
+  constant IP_ADDRESS : ip_type := (129, 217, 160, 119);
+  constant GATEWAY : ip_type := (129, 217, 160, 1);
 
   constant FIRST_PORT : integer := 5000;
@@ -79 +79 @@
 
 -- 
-  constant W5300_TX_FIFO_SIZE : integer := (15360 / 2); -- Socket TX FIFO-Size in 16 Bit Words
+  constant W5300_TX_FIFO_SIZE_8B : integer := 15360; -- Socket TX FIFO-Size in Bytes
+  constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words
 
   constant LOG2_OF_RAM_SIZE_64B : integer := 15;
@@ -119 +120 @@
   constant CMD_READ : std_logic_vector        := X"0A";
   constant CMD_WRITE : std_logic_vector       := X"05";
+-- Config-RAM 
+  constant BADDR_ROI : std_logic_vector := X"00"; -- Baseaddress ROI-Values
+  constant BADDR_DAC : std_logic_vector := X"24"; -- Baseaddress DAC-Values
 
   constant CMD_DENABLE : std_logic_vector     := X"06";
@@ -135 +139 @@
 
 constant CMD_PS_RESET : std_logic_vector     := X"17";
-
+-- DRS Registers
+  constant DRS_WRITE_SHIFT_REG : std_logic_vector := "1101";  
   
   

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd

@@ -3 +3 @@
 -- Created:
 --          by - dneise.UNKNOWN (E5B-LABOR6)
---          at - 12:19:06 05.01.2011
+--          at - 17:46:33 05.01.2011
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
@@ -80 +80 @@
 -- Created:
 --          by - dneise.UNKNOWN (E5B-LABOR6)
---          at - 12:19:07 05.01.2011
+--          at - 17:46:34 05.01.2011
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
@@ -137 +137 @@
    SIGNAL drs_read_s_cell        : std_logic                                    := '0';
    SIGNAL drs_read_s_cell_ready  : std_logic;
+   SIGNAL drs_readout_started    : std_logic;
    SIGNAL drs_s_cell_array       : drs_s_cell_array_type;
    SIGNAL drs_srin_data          : std_logic_vector(7 DOWNTO 0)                 := (others => '0');
@@ -298 +299 @@
       drs_srin_write_ready  : IN     std_logic ;
       drs_read_s_cell_ready : IN     std_logic ;
-      drs_s_cell_array      : IN     drs_s_cell_array_type 
+      drs_s_cell_array      : IN     drs_s_cell_array_type ;
+      drs_readout_started   : OUT    std_logic 
    );
    END COMPONENT;
@@ -596 +598 @@
          drs_srin_write_ready  => srin_write_ready,
          drs_read_s_cell_ready => drs_read_s_cell_ready,
-         drs_s_cell_array      => drs_s_cell_array
+         drs_s_cell_array      => drs_s_cell_array,
+         drs_readout_started   => drs_readout_started
       );
    I_main_drs_pulser : drs_pulser
@@ -628 +631 @@
          amber           => amber,
          red             => red,
-         trigger         => trigger_out,
+         trigger         => drs_readout_started,
          socks_waiting   => socks_waiting,
          socks_connected => socks_connected