Changeset 10418
- Timestamp:
- 04/20/11 12:37:39 (14 years ago)
- Location:
- firmware/FTM
- Files:
-
- 5 added
- 9 edited
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FTM_central_control.vhd (modified) (7 diffs)
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FTM_top.vhd (modified) (13 diffs)
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FTM_top_tb.vhd (modified) (7 diffs)
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dna (added)
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dna/FTM_dna_gen.vhd (added)
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ethernet/dd_write_general_modul_beha.vhd (modified) (1 diff)
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fad_broadcast (added)
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fad_broadcast/FTM_fad_broadcast.vhd (added)
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fad_broadcast/FTM_fad_rs485_interface.vhd (added)
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ftm_board.ucf (modified) (1 diff)
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ftm_definitions.vhd (modified) (7 diffs)
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ftu_control/FTM_ftu_control.vhd (modified) (20 diffs)
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ftu_control/FTM_ftu_rs485_interpreter.vhd (modified) (3 diffs)
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trigger/kernel/trigger_generator/trigger_generator.vhd (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FTM/FTM_central_control.vhd
r10366 r10418 59 59 dd_send_ack : IN std_logic; 60 60 dd_send_ready : IN std_logic; 61 dd_block_ready_ftu : out std_logic := '0'; 62 dd_block_start_ack_ftu : in std_logic; 63 dd_block_start_ftu : out std_logic := '0'; 61 64 config_start_cc : out std_logic := '0'; 62 65 config_started_cc : in std_logic; 63 66 config_ready_cc : in std_logic; 64 67 config_trigger : out std_logic := '0'; 65 config_trigger_done : in std_logic 68 config_trigger_done : in std_logic; 69 dna_start : out std_logic := '0'; 70 dna_ready : in std_logic 66 71 ); 67 72 end FTM_central_control; … … 80 85 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111"; 81 86 82 type state_central_proc_type is (CP_INIT, 87 type state_central_proc_type is (CP_INIT, CP_INIT_DNA, 83 88 CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01, 84 89 CP_CONFIG_CC, CP_CONFIG_CC_01, … … 86 91 CP_CONFIG_SCALER, CP_CONFIG_SCALER_01, 87 92 CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01, 88 CP_IDLE, CP_PING, CP_ READ_RATES, CP_READ_RATES_01,93 CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01, 89 94 CP_SEND_START, CP_SEND_END); 90 95 signal state_central_proc : state_central_proc_type := CP_INIT; … … 97 102 case state_central_proc is 98 103 99 when CP_INIT => 104 when CP_INIT => -- wait for DCMs to lock 100 105 if (clk_ready = '1') then 106 state_central_proc <= CP_INIT_DNA; 107 end if; 108 109 when CP_INIT_DNA => -- get FPGA DNA 110 if (dna_ready = '1') then 101 111 state_central_proc <= CP_CONFIG; 102 end if; 103 112 dna_start <= '0'; 113 else 114 dna_start <= '1'; 115 state_central_proc <= CP_INIT_DNA; 116 end if; 117 104 118 when CP_CONFIG_START => 105 119 if (config_started_ack = '1') then … … 189 203 elsif (new_period_sig = '1') then 190 204 new_period_ack_sig <= '1'; 191 rates_ftu <= '1'; 192 state_central_proc <= CP_READ_RATES; 205 --rates_ftu <= '1'; 206 --state_central_proc <= CP_READ_RATES; 207 state_central_proc <= CP_START_RATES; 193 208 end if; 194 209 … … 202 217 end if; 203 218 219 when CP_START_RATES => 220 new_period_ack_sig <= '0'; 221 dd_block_start_ftu <= '1'; 222 dd_block_ready_ftu <= '0'; 223 if (dd_block_start_ack_ftu = '1') then 224 dd_block_start_ftu <= '0'; 225 rates_ftu <= '1'; 226 state_central_proc <= CP_READ_RATES; 227 end if; 228 204 229 when CP_READ_RATES => 205 230 new_period_ack_sig <= '0'; … … 211 236 when CP_READ_RATES_01 => 212 237 if (rates_ready_ftu = '1') then 238 dd_block_ready_ftu <= '1'; 213 239 state_central_proc <= CP_SEND_START; 214 240 end if; -
firmware/FTM/FTM_top.vhd
r10366 r10418 146 146 147 147 -- Bus 2: Trigger-ID to FAD boards 148 --Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable149 --Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable150 151 --Bus2_RxD_0 : in STD_LOGIC; -- crate 0152 --Bus2_TxD_0 : out STD_LOGIC;153 154 --Bus2_RxD_1 : in STD_LOGIC; -- crate 1155 --Bus2_TxD_1 : out STD_LOGIC;156 157 --Bus2_RxD_2 : in STD_LOGIC; -- crate 2158 --Bus2_TxD_2 : out STD_LOGIC;159 160 --Bus2_RxD_3 : in STD_LOGIC; -- crate 3161 --Bus2_TxD_3 : out STD_LOGIC;148 Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable 149 Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable 150 151 Bus2_RxD_0 : in STD_LOGIC; -- crate 0 152 Bus2_TxD_0 : out STD_LOGIC; 153 154 Bus2_RxD_1 : in STD_LOGIC; -- crate 1 155 Bus2_TxD_1 : out STD_LOGIC; 156 157 Bus2_RxD_2 : in STD_LOGIC; -- crate 2 158 Bus2_TxD_2 : out STD_LOGIC; 159 160 Bus2_RxD_3 : in STD_LOGIC; -- crate 3 161 Bus2_TxD_3 : out STD_LOGIC; 162 162 163 163 … … 326 326 signal dd_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); 327 327 signal dd_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0'); 328 signal dd_block_start_ sig: std_logic := '0';328 signal dd_block_start_ftu_sig : std_logic := '0'; 329 329 signal dd_block_start_ack_ftu_sig : std_logic := '0'; 330 signal dd_block_ready_ sig: std_logic := '0';330 signal dd_block_ready_ftu_sig : std_logic := '0'; 331 331 signal dd_busy_sig : std_logic; 332 332 signal dd_write_sig : std_logic := '0'; … … 361 361 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTM_clk_gen when DCMs have locked 362 362 363 signal trigger_ID_ready_sig : std_logic; -- initialized in trigger manager 364 signal trigger_ID_sig : std_logic_vector(55 downto 0); -- initialized in trigger manager 365 signal trigger_ID_read_sig : std_logic; -- initialized in FTM_fad_broadcast 366 363 367 signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up 364 368 365 369 signal trigger_signal_sig : std_logic := '0'; 366 370 signal TIM_signal_sig : std_logic := '0'; 371 372 --signals for FPGA DNA identifier 373 signal dna_sig : STD_LOGIC_VECTOR(63 downto 0); -- initialized in FTM_dna_gen 374 signal dna_start_sig : STD_LOGIC; -- initialized in FTM_central_control 375 signal dna_ready_sig : STD_LOGIC; -- initialized in FTM_dna_gen 367 376 368 377 signal led_sig : std_logic_vector(7 downto 0) := (others => '0'); … … 389 398 clk_250_ps : OUT STD_LOGIC; 390 399 ready : OUT STD_LOGIC 400 ); 401 end component; 402 403 component FTM_dna_gen 404 port( 405 clk : IN STD_LOGIC; 406 start : IN STD_LOGIC; 407 dna : OUT STD_LOGIC_VECTOR(63 downto 0); 408 ready : OUT STD_LOGIC 391 409 ); 392 410 end component; … … 498 516 dd_send_ack : IN std_logic; 499 517 dd_send_ready : IN std_logic; 518 dd_block_ready_ftu : out std_logic := '0'; 519 dd_block_start_ack_ftu : in std_logic; 520 dd_block_start_ftu : out std_logic := '0'; 500 521 config_start_cc : out std_logic := '0'; 501 522 config_started_cc : in std_logic; 502 523 config_ready_cc : in std_logic; 503 524 config_trigger : out std_logic; 504 config_trigger_done : in std_logic 525 config_trigger_done : in std_logic; 526 dna_start : out std_logic; 527 dna_ready : in std_logic 505 528 ); 506 529 end component; … … 532 555 ftu_active_cr2 : in std_logic_vector (15 downto 0); 533 556 ftu_active_cr3 : in std_logic_vector (15 downto 0); 557 ftu_error_calls : out std_logic_vector (15 DOWNTO 0) := (others => '0'); 558 ftu_error_data : out std_logic_vector ((FTU_RS485_BLOCK_WIDTH - 1) downto 0) := (others => '0'); 559 ftu_error_send : out std_logic := '0'; 560 ftu_error_send_ack : in std_logic; 561 ftu_error_send_ready : in std_logic; 534 562 static_RAM_busy : in std_logic; 535 563 static_RAM_started : in std_logic; … … 553 581 end component; 554 582 583 component FTM_fad_broadcast 584 port( 585 clk_50MHz : in std_logic; 586 rx_en : out STD_LOGIC; 587 tx_en : out STD_LOGIC; 588 rx_d_0 : in STD_LOGIC; 589 tx_d_0 : out STD_LOGIC; 590 rx_d_1 : in STD_LOGIC; 591 tx_d_1 : out STD_LOGIC; 592 rx_d_2 : in STD_LOGIC; 593 tx_d_2 : out STD_LOGIC; 594 rx_d_3 : in STD_LOGIC; 595 tx_d_3 : out STD_LOGIC; 596 enable_ID_sending : in std_logic; 597 TIM_source : in std_logic; 598 LP_settings : in std_logic_vector(3 downto 0); 599 trigger_ID_ready : in std_logic; 600 trigger_ID : in std_logic_vector(FAD_RS485_BLOCK_WIDTH - 1 downto 0); 601 trigger_ID_read : out std_logic 602 ); 603 end component; 604 555 605 component ethernet_modul 556 606 port( … … 674 724 ready => clk_ready_sig 675 725 ); 726 727 Inst_FTM_dna_gen : FTM_dna_gen 728 port map( 729 clk => clk_50M_sig, 730 start => dna_start_sig, 731 dna => dna_sig, 732 ready => dna_ready_sig 733 ); 676 734 677 735 --differential output buffer for trigger signal … … 730 788 active_FTU_list_3 => ftu_active_cr3_sig, 731 789 --control signals or information for other entities 732 trigger_ID_read => '0',790 trigger_ID_read => trigger_ID_read_sig, 733 791 trig_cnt_copy_read => trigger_counter_read_sig, 734 trigger_ID_ready => open,735 trigger_ID => open,792 trigger_ID_ready => trigger_ID_ready_sig, 793 trigger_ID => trigger_ID_sig, 736 794 trig_cnt_copy => trigger_counter_sig, --counter reading 737 795 trig_cnt_copy_valid => trigger_counter_valid_sig, --trigger counter reading is valid … … 795 853 dd_send_ack => dd_send_ack_sig, 796 854 dd_send_ready => dd_send_ready_sig, 855 dd_block_ready_ftu => dd_block_ready_ftu_sig, 856 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig, 857 dd_block_start_ftu => dd_block_start_ftu_sig, 797 858 config_start_cc => config_start_cc_sig, 798 859 config_started_cc => config_started_cc_sig, 799 860 config_ready_cc => config_ready_cc_sig, 800 861 config_trigger => config_trigger_sig, 801 config_trigger_done => config_trigger_done_sig 862 config_trigger_done => config_trigger_done_sig, 863 dna_start => dna_start_sig, 864 dna_ready => dna_ready_sig 802 865 ); 803 866 … … 828 891 ftu_active_cr2 => ftu_active_cr2_sig, 829 892 ftu_active_cr3 => ftu_active_cr3_sig, 893 ftu_error_calls => ftu_error_calls_sig, 894 ftu_error_data => ftu_error_data_sig, 895 ftu_error_send => ftu_error_send_sig, 896 ftu_error_send_ack => ftu_error_send_ack_sig, 897 ftu_error_send_ready=> ftu_error_send_ready_sig, 830 898 static_RAM_busy => sd_busy_sig, 831 899 static_RAM_started => sd_started_ftu_sig, … … 846 914 write_FTUlist_RAM => fl_write_sig, 847 915 addr_FTUlist_RAM => fl_addr_sig 916 ); 917 918 Inst_FTM_fad_broadcast : FTM_fad_broadcast 919 port map( 920 clk_50MHz => clk_50M_sig, 921 rx_en => Bus2_Rx_En, 922 tx_en => Bus2_Tx_En, 923 rx_d_0 => Bus2_RxD_0, 924 tx_d_0 => Bus2_TxD_0, 925 rx_d_1 => Bus2_RxD_1, 926 tx_d_1 => Bus2_TxD_1, 927 rx_d_2 => Bus2_RxD_2, 928 tx_d_2 => Bus2_TxD_2, 929 rx_d_3 => Bus2_RxD_3, 930 tx_d_3 => Bus2_TxD_3, 931 enable_ID_sending => '1', 932 TIM_source => general_settings_sig(0), 933 LP_settings => "0000", 934 trigger_ID_ready => trigger_ID_ready_sig, 935 trigger_ID => trigger_ID_sig, 936 trigger_ID_read => trigger_ID_read_sig 848 937 ); 849 938 … … 913 1002 coin_win_p => coin_win_p_sig, 914 1003 --new stuff 915 dd_block_ready_ftu => dd_block_ready_ sig,1004 dd_block_ready_ftu => dd_block_ready_ftu_sig, 916 1005 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig, 917 dd_block_start_ftu => dd_block_start_ sig,1006 dd_block_start_ftu => dd_block_start_ftu_sig, 918 1007 dd_send => dd_send_sig, 919 1008 dd_send_ack => dd_send_ack_sig, -
firmware/FTM/FTM_top_tb.vhd
r10366 r10418 145 145 146 146 -- Bus 2: Trigger-ID to FAD boards 147 --Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable148 --Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable149 150 --Bus2_RxD_0 : in STD_LOGIC; -- crate 0151 --Bus2_TxD_0 : out STD_LOGIC;152 153 --Bus2_RxD_1 : in STD_LOGIC; -- crate 1154 --Bus2_TxD_1 : out STD_LOGIC;155 156 --Bus2_RxD_2 : in STD_LOGIC; -- crate 2157 --Bus2_TxD_2 : out STD_LOGIC;158 159 --Bus2_RxD_3 : in STD_LOGIC; -- crate 3160 --Bus2_TxD_3 : out STD_LOGIC;147 Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable 148 Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable 149 150 Bus2_RxD_0 : in STD_LOGIC; -- crate 0 151 Bus2_TxD_0 : out STD_LOGIC; 152 153 Bus2_RxD_1 : in STD_LOGIC; -- crate 1 154 Bus2_TxD_1 : out STD_LOGIC; 155 156 Bus2_RxD_2 : in STD_LOGIC; -- crate 2 157 Bus2_TxD_2 : out STD_LOGIC; 158 159 Bus2_RxD_3 : in STD_LOGIC; -- crate 3 160 Bus2_TxD_3 : out STD_LOGIC; 161 161 162 162 … … 347 347 348 348 -- Clock period definitions 349 constant clk_period : TIME := 25 ns; -- 40 MHZ oscillator U47 350 constant baud_rate_period : TIME := 4 us; -- 250 kHz baud rate 349 constant clk_period : TIME := 25 ns; -- 40 MHZ oscillator U47 350 --constant baud_rate_period : TIME := 4 us; -- 250 kHz baud rate 351 constant baud_rate_period : TIME := 100 ns; -- 10 MHz baud rate 351 352 352 353 begin … … 394 395 Bus1_RxD_3 => Bus1_RxD_3_sig, 395 396 Bus1_TxD_3 => Bus1_TxD_3_sig, 396 --Bus2_Tx_En => Bus2_Tx_En_sig,397 --Bus2_Rx_En => Bus2_Rx_En_sig,398 --Bus2_RxD_0 => Bus2_RxD_0_sig,399 --Bus2_TxD_0 => Bus2_TxD_0_sig,400 --Bus2_RxD_1 => Bus2_RxD_1_sig,401 --Bus2_TxD_1 => Bus2_TxD_1_sig,402 --Bus2_RxD_2 => Bus2_RxD_2_sig,403 --Bus2_TxD_2 => Bus2_TxD_2_sig,404 --Bus2_RxD_3 => Bus2_RxD_3_sig,405 --Bus2_TxD_3 => Bus2_TxD_3_sig,397 Bus2_Tx_En => Bus2_Tx_En_sig, 398 Bus2_Rx_En => Bus2_Rx_En_sig, 399 Bus2_RxD_0 => Bus2_RxD_0_sig, 400 Bus2_TxD_0 => Bus2_TxD_0_sig, 401 Bus2_RxD_1 => Bus2_RxD_1_sig, 402 Bus2_TxD_1 => Bus2_TxD_1_sig, 403 Bus2_RxD_2 => Bus2_RxD_2_sig, 404 Bus2_TxD_2 => Bus2_TxD_2_sig, 405 Bus2_RxD_3 => Bus2_RxD_3_sig, 406 Bus2_TxD_3 => Bus2_TxD_3_sig, 406 407 -- Crate_Res0 => Crate_Res0_sig, 407 408 -- Crate_Res1 => Crate_Res1_sig, … … 453 454 wait for 100us; 454 455 Busy0_sig <= '0'; 455 wait for 1ms;456 Busy0_sig <= '1';457 wait for 500us;458 Busy0_sig <= '0';456 -- wait for 1ms; 457 -- Busy0_sig <= '1'; 458 -- wait for 500us; 459 -- Busy0_sig <= '0'; 459 460 wait; 460 461 end process busy_proc; … … 531 532 -- time of FTU answer 532 533 --------------------------------------------------------------------------- 533 wait for 2ms;534 wait for 1.24ms; 534 535 --------------------------------------------------------------------------- 535 536 -- data package of FTU answer (28 byte) … … 543 544 assign_rs485_0(X"01"); --FTM firmware ID 544 545 wait for 0ns; 545 assign_rs485_0(X"0 5"); --instruction546 assign_rs485_0(X"02"); --instruction 546 547 wait for 0us; 547 548 assign_rs485_0(X"00"); --data byte 01 548 549 wait for 0ns; 549 assign_rs485_0(X" 00"); --data byte 02550 assign_rs485_0(X"F0"); --data byte 02 550 551 wait for 0ns; 551 552 assign_rs485_0(X"00"); --data byte 03 … … 589 590 assign_rs485_0(X"00"); --CRC error counter (not used) 590 591 wait for 0ns; 591 --assign_rs485_0(X"9E"); --check sum for rates592 assign_rs485_0(X"A5"); --check sum for ping592 assign_rs485_0(X"98"); --check sum for rates 593 --assign_rs485_0(X"A5"); --check sum for ping 593 594 --------------------------------------------------------------------------- 594 595 -- don't forget final wait! -
firmware/FTM/ethernet/dd_write_general_modul_beha.vhd
r10256 r10418 118 118 when WGP_WRITE_READY => 119 119 if (dd_write_general = '0') then 120 dd_write_general_started <= '0'; 120 121 dd_write_general_ready <= '1'; 121 122 state_write_general_proc <= WGP_IDLE; -
firmware/FTM/ftm_board.ucf
r10366 r10418 217 217 218 218 # Bus 2: Trigger-ID to FAD boards 219 #NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #220 #NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #219 NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 220 NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 221 221 222 222 # crate 0 223 #NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #224 #NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #223 NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 224 NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 225 225 226 226 # crate 1 227 #NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #228 #NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #227 NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 228 NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 229 229 230 230 # crate 2 231 #NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #232 #NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #231 NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 232 NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 233 233 234 234 # crate 3 235 #NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #236 #NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #235 NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 236 NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 237 237 238 238 -
firmware/FTM/ftm_definitions.vhd
r10366 r10418 109 109 constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol 110 110 constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter "@" 111 112 --broadcast to FADs 113 constant FAD_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case 114 constant FAD_RS485_BLOCK_WIDTH : integer := 56; -- 7 byte trigger ID 111 115 112 116 --CRC setup … … 115 119 116 120 --DNA identifier for simulation 117 constant DNA_FOR_SIM : bit_vector := X"01710000 E0000501";121 constant DNA_FOR_SIM : bit_vector := X"01710000F0000501"; 118 122 119 123 -- Clock conditioner (LMK03000, National semiconductor) interface … … 215 219 constant FTU_LIST_RAM_OFFSET : integer := 16#009#; 216 220 constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12; 221 222 constant NO_OF_DD_RAM_REG : integer := 12; 217 223 218 224 -- Static data block … … 226 232 constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3) 227 233 constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block 228 234 229 235 -- dynamic data block 230 236 --constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"010"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block 231 constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E7"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block 232 constant DD_BLOCK_SIZE_GENERAL : integer := 7; -- dynamic block size without FTU data 237 constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E7"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block 238 constant DD_BLOCK_SIZE_GENERAL : integer := 7; -- dynamic block size without FTU data 239 constant DYNAMIC_RAM_ADDR_WIDTH : integer := 12; 233 240 234 241 -- addresses in static data block … … 280 287 -- !!! to be defined !!! 281 288 constant sd_block_default_array : sd_block_default_array_type := ( 282 --X"0080", -- SD_ADDR_general_settings -- general settings283 X"0060", -- SD_ADDR_general_settings -- general settings289 X"0080", -- SD_ADDR_general_settings -- general settings 290 --X"0010", -- SD_ADDR_general_settings -- general settings 284 291 X"0000", -- SD_ADDR_led -- on-board status LEDs 285 --X"0400", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency286 X"0001", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency292 X"03FF", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency 293 --X"0001", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency 287 294 --X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers 288 X"0 420", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers295 X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers 289 296 X"0004", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude 290 297 X"0005", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude … … 295 302 X"0000", -- SD_ADDR_trigger_delay -- trigger delay 296 303 X"0000", -- SD_ADDR_timemarker_delay -- timemarker delay 297 --X"0019", -- SD_ADDR_dead_time -- dead time, 8ns + 4x25ns = 108ns298 X"0000", -- SD_ADDR_dead_time -- dead time, 8ns + 4x25ns = 108ns304 X"0017", -- SD_ADDR_dead_time -- dead time, 8ns + 4x23ns = 100ns 305 --X"0000", -- SD_ADDR_dead_time -- dead time, 8ns + 4x25ns = 108ns 299 306 X"0003", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16 300 307 X"8000", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0 … … 334 341 --default values for active FTU lists 335 342 constant sd_block_default_ftu_active_list : sd_block_default_ftu_active_list_type := ( 336 X"000 0",343 X"0001", 337 344 X"0000", 338 345 X"0000", -
firmware/FTM/ftu_control/FTM_ftu_control.vhd
r10328 r10418 74 74 ftu_active_cr2 : in std_logic_vector (15 downto 0); 75 75 ftu_active_cr3 : in std_logic_vector (15 downto 0); 76 77 --error message interface to ethernet control 78 ftu_error_calls : out std_logic_vector (15 DOWNTO 0) := (others => '0'); 79 ftu_error_data : out std_logic_vector ((FTU_RS485_BLOCK_WIDTH - 1) downto 0) := (others => '0'); 80 ftu_error_send : out std_logic := '0'; 81 ftu_error_send_ack : in std_logic; 82 ftu_error_send_ready : in std_logic; 76 83 77 84 -- communication with static (config) RAM … … 146 153 signal FTU_enable_array_sig : FTU_enable_array_type; -- initialized in interpreter 147 154 signal FTU_rate_array_sig : FTU_rate_array_type; -- initialized in interpreter 155 signal FTU_overflow_sig : std_logic_vector(7 downto 0); -- initialized in interpreter 148 156 signal FTU_prescaling_sig : std_logic_vector(7 downto 0); -- initialized in interpreter 149 157 signal FTU_crc_error_cnt_sig : std_logic_vector(7 downto 0); -- initialized in interpreter … … 199 207 signal enable_crc_from_interpreter_sig : std_logic; 200 208 signal crc_data_from_FSM_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0'); 209 signal crc_data_from_FSM_sig_cp : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0'); 201 210 signal crc_sig : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0); 202 211 signal crc_sig_inv : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0); … … 211 220 signal FTU_list_reg_cnt : integer range 0 to NO_OF_FTU_LIST_REG := 0; 212 221 signal FTU_list_header_cnt : integer range 0 to FTU_LIST_RAM_OFFSET := 0; 213 222 signal DD_RAM_reg_cnt : integer range 0 to NO_OF_DD_RAM_REG := 0; 223 214 224 -- counter to define timeout and number of retries 215 225 signal timeout_cnt : integer range 0 to FTU_RS485_TIMEOUT := 0; 216 226 signal retry_cnt : integer range 0 to FTU_RS485_NO_OF_RETRY := 0; 227 228 --Zwischenrechnungen 229 signal FTU_cnt_offset_sig : integer range 0 to (NO_OF_DD_RAM_REG * NO_OF_FTUS_PER_CRATE) := 0; 230 signal crate_cnt_offset_sig : integer range 0 to (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG) := 0; 217 231 218 232 component FTM_ftu_rs485_interface … … 260 274 FTU_enable_array : OUT FTU_enable_array_type; 261 275 FTU_rate_array : OUT FTU_rate_array_type; 276 FTU_overflow : OUT std_logic_vector(7 downto 0); 262 277 FTU_prescaling : OUT std_logic_vector(7 downto 0); 263 278 FTU_crc_error_cnt : OUT std_logic_vector(7 downto 0); … … 285 300 type FTM_ftu_rs485_control_StateType is (INIT, IDLE, ACTIVE_LIST, READ_CONFIG, TRANSMIT_CONFIG, 286 301 PING, PING_END, FTU_LIST, 302 SEND_ERROR_1, SEND_ERROR_2, 287 303 RATES, RATES_1, RATES_2, RATES_3, 304 DD_RAM, DD_RAM_1, DD_RAM_2, DD_RAM_3, 288 305 READ_CONFIG_1, READ_CONFIG_2, READ_CONFIG_3, 289 306 TRANSMIT_CONFIG_1, TRANSMIT_CONFIG_2, TRANSMIT_CONFIG_3, … … 291 308 FTU_LIST_1, FTU_LIST_2, FTU_LIST_3); 292 309 signal FTM_ftu_rs485_control_State : FTM_ftu_rs485_control_StateType; 310 signal after_error_State : FTM_ftu_rs485_control_StateType; 293 311 294 312 begin 295 313 296 Inst_FTM_f TU_rs485_interface_0 : FTM_ftu_rs485_interface -- crate 0314 Inst_FTM_ftu_rs485_interface_0 : FTM_ftu_rs485_interface -- crate 0 297 315 port map( 298 316 clk => clk_50MHz, … … 311 329 ); 312 330 313 Inst_FTM_f TU_rs485_interface_1 : FTM_ftu_rs485_interface -- crate 1331 Inst_FTM_ftu_rs485_interface_1 : FTM_ftu_rs485_interface -- crate 1 314 332 port map( 315 333 clk => clk_50MHz, … … 328 346 ); 329 347 330 Inst_FTM_f TU_rs485_interface_2 : FTM_ftu_rs485_interface -- crate 2348 Inst_FTM_ftu_rs485_interface_2 : FTM_ftu_rs485_interface -- crate 2 331 349 port map( 332 350 clk => clk_50MHz, … … 345 363 ); 346 364 347 Inst_FTM_f TU_rs485_interface_3 : FTM_ftu_rs485_interface -- crate 3365 Inst_FTM_ftu_rs485_interface_3 : FTM_ftu_rs485_interface -- crate 3 348 366 port map( 349 367 clk => clk_50MHz, … … 387 405 FTU_enable_array => FTU_enable_array_sig, 388 406 FTU_rate_array => FTU_rate_array_sig, 407 FTU_overflow => FTU_overflow_sig, 389 408 FTU_prescaling => FTU_prescaling_sig, 390 409 FTU_crc_error_cnt => FTU_crc_error_cnt_sig, … … 602 621 when TRANSMIT_CONFIG_1 => -- wait one cycle for CRC calculation 603 622 enable_crc_from_FSM_sig <= '0'; 623 crc_data_from_FSM_sig_cp <= crc_data_from_FSM_sig; 604 624 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2; 605 625 … … 614 634 elsif (frame_cnt = 27) then 615 635 frame_cnt <= frame_cnt + 1; 636 ftu_error_data <= crc_sig & crc_data_from_FSM_sig_cp; 616 637 tx_data_sig <= crc_sig; 617 638 tx_start_sig <= '1'; … … 633 654 retry_cnt <= 0; 634 655 sel_crc_input_source_sig <= '0'; 635 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG; 656 if (retry_cnt = 0) then -- no errors 657 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG; 658 else -- send error message and move to next command; 659 ftu_error_calls <= conv_std_logic_vector((retry_cnt + 1), 16); 660 after_error_State <= TRANSMIT_CONFIG; 661 FTM_ftu_rs485_control_State <= SEND_ERROR_1; 662 end if; 636 663 else 637 664 if (timeout_cnt < FTU_RS485_TIMEOUT) then … … 649 676 else 650 677 retry_cnt <= 0; 651 FTU_command_cnt <= FTU_command_cnt; -- move to next command; 652 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG; 678 FTU_command_cnt <= FTU_command_cnt; -- send error message and move to next command 679 ftu_error_calls <= (others => '0'); 680 after_error_State <= TRANSMIT_CONFIG; 681 FTM_ftu_rs485_control_State <= SEND_ERROR_1; 653 682 end if; 654 683 end if; 655 684 end if; 656 685 686 when SEND_ERROR_1 => -- send an error message 687 ftu_error_send <= '1'; 688 if (ftu_error_send_ack = '1') then 689 ftu_error_send <= '0'; 690 FTM_ftu_rs485_control_State <= SEND_ERROR_2; 691 end if; 692 693 when SEND_ERROR_2 => 694 if (ftu_error_send_ready = '1') then 695 FTM_ftu_rs485_control_State <= after_error_state; 696 end if; 697 657 698 when PING => -- ping all FTUs 658 699 rec_reset_sig <= '0'; … … 759 800 write_FTUlist_RAM <= '1'; 760 801 addr_FTUlist_RAM <= conv_std_logic_vector(FTU_LIST_RAM_OFFSET + 761 (FTU_cnt - 1)* NO_OF_FTU_LIST_REG + 802 (crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_FTU_LIST_REG) + 803 ((FTU_cnt - 1) * NO_OF_FTU_LIST_REG) + 762 804 (FTU_list_reg_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH); 763 805 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then … … 871 913 when RATES_1 => -- wait one cycle for CRC calculation 872 914 enable_crc_from_FSM_sig <= '0'; 915 crc_data_from_FSM_sig_cp <= crc_data_from_FSM_sig; 873 916 FTM_ftu_rs485_control_State <= RATES_2; 874 917 … … 883 926 elsif (frame_cnt = 27) then 884 927 frame_cnt <= frame_cnt + 1; 928 ftu_error_data <= crc_sig & crc_data_from_FSM_sig_cp; 885 929 tx_data_sig <= crc_sig; 886 930 tx_start_sig <= '1'; … … 901 945 timeout_cnt <= 0; 902 946 sel_crc_input_source_sig <= '0'; 903 FTM_ftu_rs485_control_State <= RATES; 947 --FTM_ftu_rs485_control_State <= RATES; 948 if (retry_cnt = 0) then -- no errors 949 FTM_ftu_rs485_control_State <= DD_RAM; 950 else -- send error message and move to next command; 951 ftu_error_calls <= conv_std_logic_vector((retry_cnt + 1), 16); 952 after_error_State <= DD_RAM; 953 FTM_ftu_rs485_control_State <= SEND_ERROR_1; 954 end if; 904 955 else 905 956 if (timeout_cnt < FTU_RS485_TIMEOUT) then … … 916 967 FTM_ftu_rs485_control_State <= RATES; 917 968 else 918 retry_cnt <= 0;969 --retry_cnt <= 0; 919 970 FTU_cnt <= FTU_cnt; -- move on 920 FTM_ftu_rs485_control_State <= RATES; 971 ftu_error_calls <= (others => '0'); 972 after_error_State <= DD_RAM; 973 FTM_ftu_rs485_control_State <= SEND_ERROR_1; 921 974 end if; 922 975 end if; 976 end if; 977 978 when DD_RAM => -- write rates of actual FTU to DD RAM 979 rec_reset_sig <= '0'; 980 if (DD_RAM_reg_cnt < NO_OF_DD_RAM_REG) then 981 DD_RAM_reg_cnt <= DD_RAM_reg_cnt + 1; 982 FTU_cnt_offset_sig <= ((FTU_cnt - 1) * NO_OF_DD_RAM_REG); 983 crate_cnt_offset_sig <= (crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG); 984 FTM_ftu_rs485_control_State <= DD_RAM_1; 985 else 986 DD_RAM_reg_cnt <= 0; 987 retry_cnt <= 0; 988 FTM_ftu_rs485_control_State <= RATES; 989 end if; 990 991 when DD_RAM_1 => 992 if (dynamic_RAM_busy = '0') then 993 write_dynamic_RAM <= '1'; 994 addr_dynamic_RAM <= conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL + 995 crate_cnt_offset_sig + 996 --(crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG) + 997 --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) + 998 FTU_cnt_offset_sig + 999 (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH); 1000 if ( (retry_cnt < FTU_RS485_NO_OF_RETRY) 1001 and (FTU_cnt_offset_sig < (NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG)) 1002 and (crate_cnt_offset_sig < (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG)) ) then 1003 if ((DD_RAM_reg_cnt - 1) = 0) then 1004 data_dynamic_RAM <= FTU_rate_array_sig(0)(31 downto 16); 1005 elsif ((DD_RAM_reg_cnt - 1) = 1) then 1006 data_dynamic_RAM <= FTU_rate_array_sig(0)(15 downto 0); 1007 elsif ((DD_RAM_reg_cnt - 1) = 2) then 1008 data_dynamic_RAM <= FTU_rate_array_sig(1)(31 downto 16); 1009 elsif ((DD_RAM_reg_cnt - 1) = 3) then 1010 data_dynamic_RAM <= FTU_rate_array_sig(1)(15 downto 0); 1011 elsif ((DD_RAM_reg_cnt - 1) = 4) then 1012 data_dynamic_RAM <= FTU_rate_array_sig(2)(31 downto 16); 1013 elsif ((DD_RAM_reg_cnt - 1) = 5) then 1014 data_dynamic_RAM <= FTU_rate_array_sig(2)(15 downto 0); 1015 elsif ((DD_RAM_reg_cnt - 1) = 6) then 1016 data_dynamic_RAM <= FTU_rate_array_sig(3)(31 downto 16); 1017 elsif ((DD_RAM_reg_cnt - 1) = 7) then 1018 data_dynamic_RAM <= FTU_rate_array_sig(3)(15 downto 0); 1019 elsif ((DD_RAM_reg_cnt - 1) = 8) then 1020 data_dynamic_RAM <= FTU_rate_array_sig(4)(31 downto 16); 1021 elsif ((DD_RAM_reg_cnt - 1) = 9) then 1022 data_dynamic_RAM <= FTU_rate_array_sig(4)(15 downto 0); 1023 elsif ((DD_RAM_reg_cnt - 1) = 10) then 1024 data_dynamic_RAM <= "00000000" & FTU_overflow_sig; 1025 elsif ((DD_RAM_reg_cnt - 1) = 11) then 1026 data_dynamic_RAM <= "00000000" & FTU_crc_error_cnt_sig; 1027 -- elsif ((DD_RAM_reg_cnt - 1) = 10) then 1028 -- data_dynamic_RAM <= "0000" & conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL + 1029 -- --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) + 1030 -- FTU_cnt_offset_sig + 1031 -- (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH); 1032 -- elsif ((DD_RAM_reg_cnt - 1) = 11) then 1033 -- --data_dynamic_RAM <= "0000" & conv_std_logic_vector(FTU_cnt_offset_sig, DYNAMIC_RAM_ADDR_WIDTH); 1034 -- data_dynamic_RAM <= "0000" & conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL + 1035 -- --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) + 1036 -- FTU_cnt_offset_sig + 1037 -- (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH); 1038 end if; 1039 else 1040 data_dynamic_RAM <= (others => '0'); 1041 end if; 1042 FTM_ftu_rs485_control_State <= DD_RAM_2; 1043 end if; 1044 1045 when DD_RAM_2 => 1046 if (dynamic_RAM_started = '1') then 1047 write_dynamic_RAM <= '0'; 1048 FTM_ftu_rs485_control_State <= DD_RAM_3; 1049 end if; 1050 1051 when DD_RAM_3 => 1052 if (dynamic_RAM_ready = '1') then 1053 FTM_ftu_rs485_control_State <= DD_RAM; 923 1054 end if; 924 1055 -
firmware/FTM/ftu_control/FTM_ftu_rs485_interpreter.vhd
r10232 r10418 47 47 FTU_enable_array : OUT FTU_enable_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0')); 48 48 FTU_rate_array : OUT FTU_rate_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0')); 49 FTU_overflow : OUT std_logic_vector(7 downto 0) := (others => '0'); 49 50 FTU_prescaling : OUT std_logic_vector(7 downto 0) := (others => '0'); 50 51 FTU_crc_error_cnt : OUT std_logic_vector(7 downto 0) := (others => '0'); … … 144 145 data_block(199 downto 168) 145 146 ); 147 FTU_overflow <= data_block(207 downto 200); 146 148 FTU_crc_error_cnt <= data_block(215 downto 208); 147 149 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA; … … 165 167 elsif (data_block(39 downto 32) = "00000111") then -- read counter mode 166 168 FTU_prescaling <= data_block(47 downto 40); 169 FTU_overflow <= data_block(55 downto 48); 167 170 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA; 168 171 elsif (data_block(39 downto 32) = "00000101") then -- ping pong -
firmware/FTM/trigger/kernel/trigger_generator/trigger_generator.vhd
r10366 r10418 13 13 -- 14/03/2011 JGi 110314a Description 14 14 -- 13/04/2011 JGi 110413a Update trigger enable management 15 -- 15/04/2011 JGi 110415a Update LP1 "N-out-of-40" logic detection 16 -- in order to allow user to reset it by 17 -- disabling LP1 pulse as trigger source if the 18 -- N is never reached and system is locked 15 19 --======================================================================================= 16 20 -- Library Definition … … 332 336 general_settings(4) = '1' then 333 337 v_reg.wait_for_calib := '1'; 334 elsif i_reg.enable_trigger = '0' then 338 -- If trigger is processed or disabled by user, reset detection logic to avoid 339 -- remaining in locked state 340 elsif i_reg.enable_trigger = '0' or general_settings(4) = '0' then 335 341 v_reg.wait_for_calib := '0'; 336 342 end if;
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