Changeset 10072 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib
- Timestamp:
- 01/03/11 15:26:12 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 7 edited
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control_manager_beha.vhd (modified) (8 diffs)
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data_generator.vhd (modified) (10 diffs)
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data_generator.vhd.bak (modified) (3 diffs)
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drs_pulser_dummy.vhd (modified) (5 diffs)
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fad_definitions.vhd (modified) (3 diffs)
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memory_manager_beha.vhd (modified) (7 diffs)
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w5300_modul.vhd (modified) (19 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_manager_beha.vhd
r9912 r10072 32 32 config_data_valid : OUT std_logic := '0'; 33 33 config_busy : OUT std_logic := '0'; 34 -- -- 35 config_rw_ack, config_rw_ready : out std_logic := '0'; 36 -- -- 34 37 ram_addr : OUT std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0); 35 38 ram_data_in : OUT std_logic_vector (15 DOWNTO 0); 36 39 ram_write_en : OUT std_logic_vector (0 DOWNTO 0); 37 40 dac_array : OUT dac_array_type; 38 roi_array : OUT roi_array_type; 39 drs_address : OUT std_logic_vector (3 DOWNTO 0); 40 drs_address_mode : OUT std_logic 41 roi_array : OUT roi_array_type 41 42 ); 42 43 … … 47 48 ARCHITECTURE beha OF control_manager IS 48 49 49 type TYPE_CTRL_STATE is (CTRL_INIT, CTRL_IDLE, CTRL_WAIT_IDLE, CTRL_WRITE, 50 type TYPE_CTRL_STATE is (CTRL_INIT, CTRL_IDLE, CTRL_WAIT_IDLE, CTRL_WRITE, CTRL_WRITE_READY, 50 51 CTRL_LOAD_ADDR, CTRL_LOAD_WAIT, CTRL_LOAD_DATA, 51 52 CTRL_READ_ADDR, CTRL_READ_WAIT, CTRL_READ_DATA); … … 55 56 signal int_dac_array : dac_array_type := DEFAULT_DAC; 56 57 signal int_roi_array : roi_array_type := DEFAULT_ROI; 57 signal int_drs_address: std_logic_vector (3 DOWNTO 0) := DEFAULT_DRSADDR;58 signal int_drs_address_mode: std_logic := DEFAULT_DRSADDR_MODE;59 58 60 59 BEGIN … … 81 80 elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then 82 81 ram_data_in <= conv_std_logic_vector(int_dac_array(addr_cntr - NO_OF_ROI), 16); 83 elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then84 ram_data_in <= "0000" & "0000"85 & "000" & conv_std_logic_vector(int_drs_address_mode, 1)86 & int_drs_address;87 82 else 88 83 ram_write_en <= "0"; … … 91 86 92 87 when CTRL_IDLE => 93 --94 88 addr_cntr <= 0; 95 89 ram_write_en <= "0"; … … 103 97 if (config_wr_en = '1') then 104 98 config_busy <= '1'; 99 config_rw_ack <= '1'; 100 config_rw_ready <= '0'; 105 101 config_data <= (others => 'Z'); 106 102 ctrl_state <= CTRL_WRITE; … … 129 125 dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out); 130 126 ctrl_state <= CTRL_LOAD_ADDR; 131 elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then 132 drs_address <= ram_data_out(3 downto 0); 133 drs_address_mode <= ram_data_out(4); 134 ctrl_state <= CTRL_LOAD_ADDR; 135 else 127 else 136 128 addr_cntr <= 0; 137 129 config_started <= '0'; … … 144 136 ram_addr <= config_addr; 145 137 ram_write_en <= "1"; 146 ctrl_state <= CTRL_IDLE; 138 ctrl_state <= CTRL_WRITE_READY; 139 when CTRL_WRITE_READY => 140 config_rw_ack <= '0'; 141 config_rw_ready <= '1'; 142 if (config_wr_en = '0') then 143 ctrl_state <= CTRL_IDLE; 144 end if; 147 145 148 146 -- *** IMPORTANT *** -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r9912 r10072 25 25 ); 26 26 port( 27 -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 28 27 29 clk : in std_logic; 28 30 data_out : out std_logic_vector (63 downto 0); … … 32 34 ram_write_ea : in std_logic; 33 35 ram_write_ready : out std_logic := '0'; 36 -- -- 37 ram_write_ready_ack : IN std_logic; 38 -- -- 34 39 config_start_mm, config_start_cm, config_start_spi : out std_logic := '0'; 35 40 config_ready_mm, config_ready_cm, config_ready_spi : in std_logic; … … 45 50 trigger_id : in std_logic_vector (47 downto 0); 46 51 trigger : in std_logic; 47 s_trigger : in std_logic;52 -- s_trigger : in std_logic; 48 53 new_config : in std_logic; 49 54 config_started : out std_logic := '0'; … … 55 60 drs_dwrite : out std_logic := '1'; 56 61 drs_clk_en, drs_read_s_cell : out std_logic := '0'; 62 63 drs_srin_write_8b : out std_logic := '0'; 64 drs_srin_write_ack : in std_logic; 65 drs_srin_data : out std_logic_vector (7 downto 0) := (others => '0'); 66 drs_srin_write_ready : in std_logic; 67 57 68 drs_read_s_cell_ready : in std_logic; 58 69 drs_s_cell_array : in drs_s_cell_array_type … … 62 73 architecture Behavioral of data_generator is 63 74 64 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,75 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES, 65 76 WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT, 66 77 WRITE_END_FLAG, WRITE_DATA_STOP, … … 76 87 signal adc_wait_cnt : integer range 0 to 7 := 0; 77 88 78 signal trigger_flag : std_logic := '0'; 79 89 signal trigger_flag :std_logic := '0'; 90 signal ram_write_ea_flag : std_logic := '0'; 91 signal new_config_int : std_logic := '0'; 92 93 signal roi_max_int : roi_max_type; 80 94 81 95 begin … … 95 109 when CONFIG => 96 110 config_started <= '1'; 97 -- config config manager 98 config_start_cm <= '1'; 99 if (config_started_cm = '1') then 100 state_generate <= CONFIG1; 111 if (new_config = '0') then 112 config_started <= '0'; 113 -- config config manager 114 config_start_cm <= '1'; 115 if (config_started_cm = '1') then 116 config_start_cm <= '0'; 117 state_generate <= CONFIG1; 118 end if; 101 119 end if; 102 120 when CONFIG1 => 103 121 if (config_ready_cm = '1') then 104 config_started <= '0';105 config_start_cm <= '0';106 122 config_start_mm <= '1'; 107 123 end if; 108 124 if (config_started_mm = '1') then 125 config_start_mm <= '0'; 109 126 state_generate <= CONFIG2; 110 127 end if; 111 128 when CONFIG2 => 112 129 if (config_ready_mm = '1') then 113 config_start_mm <= '0';114 130 config_start_spi <= '1'; 115 131 end if; 116 132 if (config_started_spi = '1') then 133 config_start_spi <= '0'; 117 134 state_generate <= CONFIG3; 118 135 end if; 119 136 when CONFIG3 => 120 137 if (config_ready_spi = '1') then 121 config_start_spi <= '0'; 138 state_generate <= CONFIG4; 139 -- state_generate <= WRITE_DATA_IDLE; 140 end if; 141 -- configure DRS 142 when CONFIG4 => 143 drs_channel_id <= DRS_WRITE_SHIFT_REG; 144 drs_srin_data <= "10101010"; 145 drs_srin_write_8b <= '1'; 146 if (drs_srin_write_ack = '1') then 147 drs_srin_write_8b <= '0'; 148 state_generate <= CONFIG5; 149 end if; 150 when CONFIG5 => 151 if (drs_srin_write_ready = '1') then 152 roi_max_int <= roi_max; 122 153 state_generate <= WRITE_DATA_IDLE; 123 154 end if; 155 -- end configure DRS 124 156 125 157 when WRITE_DATA_IDLE => … … 127 159 state_generate <= CONFIG; 128 160 end if; 129 if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then 161 -- if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then 162 if (ram_write_ea = '1' and trigger_flag = '1') then 130 163 -- stop drs, dwrite low 131 164 drs_dwrite <= '0'; … … 248 281 when WRITE_EXTERNAL_TRIGGER => -- external trigger ID 249 282 addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH); 250 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); 283 -- data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); 284 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); 251 285 state_generate <= WRITE_INTERNAL_TRIGGER; 252 286 when WRITE_INTERNAL_TRIGGER => -- internal trigger ID … … 263 297 state_generate <= WRITE_DATA_END_WAIT; 264 298 when WRITE_DATA_END_WAIT => 265 state_generate <= WRITE_DATA_STOP; 299 -- -- 300 if (ram_write_ready_ack = '1') then 301 state_generate <= WRITE_DATA_STOP; 302 -- -- 303 ram_write_ready <= '0'; 304 -- -- 305 end if; 306 -- -- 266 307 when WRITE_DATA_STOP => 267 drs_dwrite <= '1'; 268 data_cntr <= 0; 269 addr_cntr <= 0; 270 channel_id <= 0; 271 ram_write_ready <= '0'; 272 state_generate <= WRITE_DATA_IDLE; 273 308 -- -- 309 if (ram_write_ready_ack = '0') then 310 -- -- 311 drs_dwrite <= '1'; 312 data_cntr <= 0; 313 addr_cntr <= 0; 314 channel_id <= 0; 315 state_generate <= WRITE_DATA_IDLE; 316 -- -- 317 end if; 318 -- -- 274 319 when others => 275 320 null; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak
r9912 r10072 76 76 signal adc_wait_cnt : integer range 0 to 7 := 0; 77 77 78 signal trigger_flag : std_logic := '0'; 79 78 80 79 81 begin … … 83 85 begin 84 86 if rising_edge (clk) then 87 trigger_flag <= trigger; 85 88 86 89 addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH); … … 124 127 state_generate <= CONFIG; 125 128 end if; 126 if (ram_write_ea = '1' and (trigger = '1' or s_trigger = '1')) then129 if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then 127 130 -- stop drs, dwrite low 128 131 drs_dwrite <= '0'; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd
r9912 r10072 23 23 stop_pos_valid : out std_logic := '0'; 24 24 25 start_srin_write_8b : in std_logic; 26 srin_write_ready : out std_logic := '0'; 27 srin_write_ack : out std_logic := '0'; 28 srin_data : in std_logic_vector (7 downto 0); 29 SRIN_out : out std_logic := '0'; 30 25 31 RSRLOAD : out std_logic := '0'; 26 32 SRCLK : out std_logic := '0' … … 31 37 ARCHITECTURE behavior of drs_pulser IS 32 38 33 type state_main_type is (MAIN, READ_STOP_POS, ENDLESS_MODE);39 type state_main_type is (MAIN, SRIN_WRITE_8B, SRIN_WRITE_END, READ_STOP_POS, ENDLESS_MODE); 34 40 signal state_main : state_main_type := MAIN; 35 41 signal stop_pos_cntr, wait_cntr : integer range 0 to 31 := 0; … … 37 43 signal stop_pos_int : drs_s_cell_array_type; 38 44 signal RSRLOAD_EN, SRCLK_EN : std_logic := '0'; 45 46 signal srin_cntr : integer range 0 to 7 := 1; 39 47 40 48 begin … … 49 57 case state_main is 50 58 when MAIN => 59 if (start_srin_write_8b = '1') then 60 srin_write_ready <= '0'; 61 srin_write_ack <= '1'; 62 srin_cntr <= 0; 63 SRCLK_EN <= '1'; 64 state_main <= SRIN_WRITE_8B; 65 end if; 51 66 if (start_read_stop_pos_mode = '1') then 52 67 RSRLOAD_EN <= '1'; … … 58 73 state_main <= ENDLESS_MODE; 59 74 end if; 75 76 when SRIN_WRITE_8B => 77 srin_out <= srin_data (7 - srin_cntr); 78 if (srin_cntr = 7) then 79 SRCLK_EN <= '0'; 80 state_main <= SRIN_WRITE_END; 81 else 82 srin_cntr <= srin_cntr + 1; 83 end if; 84 when SRIN_WRITE_END => 85 srin_out <= '0'; 86 srin_write_ready <= '1'; 87 srin_write_ack <= '0'; 88 state_main <= MAIN; 89 60 90 61 91 when ENDLESS_MODE => -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r9912 r10072 79 79 80 80 -- 81 constant W5300_TX_FIFO_SIZE : integer := (15360 / 2); -- Socket TX FIFO-Size in 16 Bit Words 81 constant W5300_TX_FIFO_SIZE_8B : integer := 15360; -- Socket TX FIFO-Size in Bytes 82 constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words 82 83 83 84 constant LOG2_OF_RAM_SIZE_64B : integer := 15; … … 119 120 constant CMD_READ : std_logic_vector := X"0A"; 120 121 constant CMD_WRITE : std_logic_vector := X"05"; 122 -- Config-RAM 123 constant BADDR_ROI : std_logic_vector := X"00"; -- Baseaddress ROI-Values 124 constant BADDR_DAC : std_logic_vector := X"24"; -- Baseaddress DAC-Values 121 125 122 126 constant CMD_DENABLE : std_logic_vector := X"06"; … … 135 139 136 140 constant CMD_PS_RESET : std_logic_vector := X"17"; 137 141 -- DRS Registers 142 constant DRS_WRITE_SHIFT_REG : std_logic_vector := "1101"; 138 143 139 144 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd
r9912 r10072 36 36 config_start : IN std_logic; 37 37 ram_write_ready : IN std_logic; 38 -- -- 39 ram_write_ready_ack : OUT std_logic := '0'; 40 -- -- 38 41 roi_array : IN roi_array_type; 39 42 ram_write_ea : OUT std_logic := '0'; … … 59 62 ARCHITECTURE beha OF memory_manager IS 60 63 61 type state_mm_type is (MM_CONFIG, MAX_ROI, MAX_ROI1, MAX_ROI2, FIFO_CALC, RAM_CALC, RAM_CALC1, RAM_CALC2, MM_MAIN, MM_MAIN1 );64 type state_mm_type is (MM_CONFIG, MAX_ROI, MAX_ROI1, MAX_ROI2, FIFO_CALC, RAM_CALC, RAM_CALC1, RAM_CALC2, MM_MAIN, MM_MAIN1, MM_MAIN2, MM_MAIN3, MM_MAIN4); 62 65 signal state_mm : state_mm_type := MM_CONFIG; 63 66 … … 93 96 signal write_start_addr : integer range 0 to (RAM_SIZE_16B - 1); 94 97 signal event_ready_flag : std_logic := '0'; 95 signal wiz_ack_flag 98 signal wiz_ack_flag, wiz_write_ea_flag: std_logic := '0'; 96 99 97 100 signal roi_index : integer range 0 to 45 := 0; … … 99 102 100 103 BEGIN 104 105 -- led <= conv_std_logic_vector (events_in_ram, 4) & "00" & wiz_ack & wiz_busy; 101 106 102 107 mm : process (clk) … … 207 212 roi_max(i) <= conv_std_logic_vector(roi_max_array(i), 11); 208 213 end loop; 214 215 event_ready_flag <= '0'; 216 wiz_ack_flag <= '0'; 217 wiz_write_ea_flag <= '0'; 209 218 state_mm <= MM_MAIN; 210 219 211 220 when MM_MAIN => 212 221 state_mm <= MM_MAIN1; 213 if ((ram_write_ready = '1') and (event_ready_flag = '0')) then214 ram_write_ea <= '0';215 events_in_ram <= events_in_ram + 1;216 if ((event_start_addr + event_size_ram_64b) < (RAM_SIZE_64B - event_size_ram_64b)) then217 event_start_addr <= event_start_addr + event_size_ram_64b;218 else219 event_start_addr <= 0;220 end if;221 event_ready_flag <= '1';222 end if;223 224 225 when MM_MAIN1 =>226 state_mm <= MM_MAIN;227 222 if (config_start = '1') then 228 223 config_ready <= '0'; … … 231 226 end if; 232 227 end if; 233 if (event_ready_flag = '1') then 228 229 when MM_MAIN1 => 230 state_mm <= MM_MAIN2; 231 if ((ram_write_ready = '1') and (event_ready_flag = '0')) then 232 ram_write_ea <= '0'; 233 -- -- 234 ram_write_ready_ack <= '1'; 235 -- -- 236 events_in_ram <= events_in_ram + 1; 237 if ((event_start_addr + event_size_ram_64b) < (RAM_SIZE_64B - event_size_ram_64b)) then 238 event_start_addr <= event_start_addr + event_size_ram_64b; 239 else 240 event_start_addr <= 0; 241 end if; 242 event_ready_flag <= '1'; 243 end if; 244 245 246 when MM_MAIN2 => 247 state_mm <= MM_MAIN3; 248 if ((event_ready_flag = '1') and (ram_write_ready = '0')) then 234 249 if (events_in_ram < max_events_ram) then 235 250 ram_write_ea <= '1'; 236 251 ram_start_addr <= conv_std_logic_vector(event_start_addr, RAM_ADDR_WIDTH_64B); 237 252 event_ready_flag <= '0'; 238 end if; 239 end if; 240 253 -- -- 254 ram_write_ready_ack <= '0'; 255 -- -- 256 end if; 257 end if; 258 259 when MM_MAIN3 => 260 state_mm <= MM_MAIN4; 261 if ((wiz_ack = '1') and (wiz_ack_flag = '0')) then 262 wiz_ack_flag <= '1'; 263 wiz_write_ea <= '0'; 264 package_index <= package_index + 1; 265 if (package_index = (number_of_packages - 1)) then 266 -- next address 267 if ((write_start_addr + fifo_package_size_ram (package_index)) < (RAM_SIZE_16B - event_size_ram)) then 268 write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); 269 else 270 write_start_addr <= 0; 271 end if; 272 else 273 write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); 274 end if; 275 end if; -- wiz_ack_int 276 277 when MM_MAIN4 => 278 state_mm <= MM_MAIN; 241 279 if ((events_in_ram > 0) and (wiz_busy = '0')) then 242 280 if (package_index < number_of_packages) then … … 264 302 end if; 265 303 266 if ((wiz_ack = '1') and (wiz_ack_flag = '0')) then 267 wiz_ack_flag <= '1'; 268 wiz_write_ea <= '0'; 269 package_index <= package_index + 1; 270 if (package_index = (number_of_packages - 1)) then 271 -- next address 272 if ((write_start_addr + fifo_package_size_ram (package_index)) < (RAM_SIZE_16B - event_size_ram)) then 273 write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); 274 else 275 write_start_addr <= 0; 276 end if; 277 else 278 write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); 279 end if; 280 end if; -- wiz_ack 281 304 282 305 end case; -- state_mm 283 306 end if; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r9912 r10072 60 60 config_wr_en : out std_logic := '0'; 61 61 config_rd_en : out std_logic := '0'; 62 -- -- 63 config_rw_ack, config_rw_ready : in std_logic; 64 -- -- 62 65 config_busy : in std_logic; 63 66 … … 82 85 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, 83 86 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 84 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA);85 type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_0 6, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,87 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA); 88 type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, 86 89 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3); 87 90 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); … … 120 123 signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0'); 121 124 signal chk_recv_cntr : integer range 0 to 10000 := 0; 125 126 -- -- 127 signal wait_cntr : integer range 0 to 10000 := 0; 128 -- -- 129 122 130 signal rx_packets_cnt : std_logic_vector (15 downto 0); 123 131 signal next_packet_data : std_logic := '0'; … … 133 141 signal local_fifo_channels : std_logic_vector (3 downto 0); 134 142 143 signal data_valid_int : std_logic := '0'; 144 145 -- only for debugging 146 --signal error_cnt : std_logic_vector (7 downto 0) := (others => '0'); 147 --signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0'); 148 149 135 150 begin 136 151 … … 138 153 RST_TIME <= X"00120"; 139 154 --synthesis translate_on 155 140 156 141 157 w5300_init_proc : process (clk, int) … … 220 236 -- reset W5300 221 237 when RESET => 238 busy <= '1'; 222 239 zaehler <= zaehler + 1; 223 240 wiz_reset <= '0'; 224 led <= X"FF";241 -- led <= X"FF"; 225 242 if (zaehler >= X"00064") then -- wait 2µs 226 243 wiz_reset <= '1'; … … 356 373 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8); 357 374 state_init <= WRITE_REG; 358 next_state <= TIMEOUT;359 when TIMEOUT =>360 par_addr <= W5300_RTR;361 par_data <= X"07D0"; -- 0x07D0 = 200ms362 state_init <= WRITE_REG;363 next_state <= RETRY;364 when RETRY =>365 par_addr <= W5300_RCR;366 par_data <= X"0008";367 state_init <= WRITE_REG;368 375 next_state <= SI; 376 -- when TIMEOUT => 377 -- par_addr <= W5300_RTR; 378 -- par_data <= X"07D0"; -- 0x07D0 = 200ms 379 -- state_init <= WRITE_REG; 380 -- next_state <= RETRY; 381 -- when RETRY => 382 -- par_addr <= W5300_RCR; 383 -- par_data <= X"0008"; 384 -- state_init <= WRITE_REG; 385 -- next_state <= SI; 386 -- 369 387 370 388 -- Socket Init … … 418 436 next_state <= EST1; 419 437 when EST1 => 420 led <= data_read (7 downto 0); 438 -- led <= data_read (7 downto 0); 439 -- led <= X"00"; 421 440 case data_read (7 downto 0) is 422 441 when X"17" => -- established … … 434 453 435 454 when CONFIG => 436 455 -- led <= X"F0"; 437 456 new_config <= '1'; 438 457 if (config_started = '1') then 439 led <= X"0F";458 -- led <= X"0F"; 440 459 new_config <= '0'; 441 busy <= '0';442 460 state_init <= MAIN; 443 461 end if; … … 448 466 ps_reset <= '0'; 449 467 if (trigger_stop = '1') then 450 s_trigger <= '0'; 451 end if; 468 s_trigger <= '0'; 469 end if; 470 data_valid_ack <= '0'; 471 state_init <= MAIN1; 472 data_valid_int <= data_valid; 473 when MAIN1 => 452 474 if (chk_recv_cntr = 1000) then 453 475 chk_recv_cntr <= 0; … … 456 478 busy <= '1'; 457 479 else 458 busy <= '0';459 data_valid_ack <= '0';460 480 chk_recv_cntr <= chk_recv_cntr + 1; 461 if (data_valid = '1') then 462 data_valid_ack <= '1'; 463 local_write_length <= write_length; 464 local_ram_start_addr <= ram_start_addr; 465 local_ram_addr <= (others => '0'); 466 local_write_header_flag <= write_header_flag; 467 local_write_end_flag <= write_end_flag; 468 local_fifo_channels <= fifo_channels; 469 next_state <= MAIN; 470 state_init <= WRITE_DATA; 471 busy <= '1'; 472 end if; 473 end if; 481 state_init <= MAIN2; 482 end if; 483 when MAIN2 => 484 busy <= '0'; 485 if (data_valid = '1') then 486 data_valid_int <= '0'; 487 busy <= '1'; 488 local_write_length <= write_length; 489 local_ram_start_addr <= ram_start_addr; 490 local_ram_addr <= (others => '0'); 491 local_write_header_flag <= write_header_flag; 492 local_write_end_flag <= write_end_flag; 493 local_fifo_channels <= fifo_channels; 494 -- data_valid_ack <= '1'; 495 -- next_state <= MAIN; 496 -- state_init <= WRITE_DATA; 497 state_init <= MAIN3; 498 else 499 state_init <= MAIN1; 500 end if; 501 when MAIN3 => 502 -- led <= local_ram_start_addr (7 downto 0); 503 data_valid_ack <= '1'; 504 next_state <= MAIN; 505 state_init <= WRITE_DATA; 506 474 507 475 508 -- read data from socket 0 … … 507 540 else 508 541 state_read_data <= RD_END; 509 -- if (new_config_flag = '1') then510 -- new_config_flag <= '0';511 -- state_init <= CONFIG;512 -- else513 -- busy <= '0';514 -- state_init <= MAIN;515 -- end if;516 542 end if; 517 543 when RD_6 => 518 led <= data_read (15 downto 8);544 -- led <= data_read (15 downto 8); 519 545 -- read command 520 546 if (next_packet_data = '0') then … … 523 549 trigger_stop <= '1'; 524 550 s_trigger <= '1'; 525 state_read_data <= RD_ WAIT;551 state_read_data <= RD_5; 526 552 when CMD_DWRITE_RUN => 527 553 dwrite_enable <= '1'; 528 state_read_data <= RD_ WAIT;554 state_read_data <= RD_5; 529 555 when CMD_DWRITE_STOP => 530 556 dwrite_enable <= '0'; 531 state_read_data <= RD_ WAIT;557 state_read_data <= RD_5; 532 558 when CMD_SCLK_ON => 533 559 sclk_enable <= '1'; 534 state_read_data <= RD_ WAIT;560 state_read_data <= RD_5; 535 561 when CMD_SCLK_OFF => 536 562 sclk_enable <= '0'; 537 state_read_data <= RD_ WAIT;563 state_read_data <= RD_5; 538 564 when CMD_DENABLE => 539 565 denable <= '1'; 540 state_read_data <= RD_ WAIT;566 state_read_data <= RD_5; 541 567 when CMD_DDISABLE => 542 568 denable <= '0'; 543 state_read_data <= RD_ WAIT;569 state_read_data <= RD_5; 544 570 when CMD_TRIGGER_C => 545 571 trigger_stop <= '0'; 546 572 s_trigger <= '1'; 547 state_read_data <= RD_ WAIT;573 state_read_data <= RD_5; 548 574 when CMD_TRIGGER_S => 549 575 trigger_stop <= '1'; 550 state_read_data <= RD_ WAIT;576 state_read_data <= RD_5; 551 577 -- phase shift commands here: 552 578 when CMD_PS_DO => 553 579 ps_do_phase_shift <= '1'; 554 state_read_data <= RD_ WAIT;580 state_read_data <= RD_5; 555 581 when CMD_PS_DIRINC => 556 582 ps_direction <= '1'; 557 state_read_data <= RD_ WAIT;583 state_read_data <= RD_5; 558 584 when CMD_PS_RESET => 559 585 ps_reset <= '1'; 560 state_read_data <= RD_ WAIT;586 state_read_data <= RD_5; 561 587 when CMD_SRCLK_ON => 562 588 srclk_enable <= '1'; 563 state_read_data <= RD_ WAIT;589 state_read_data <= RD_5; 564 590 when CMD_SRCLK_OFF => 565 591 srclk_enable <= '0'; 566 state_read_data <= RD_ WAIT;592 state_read_data <= RD_5; 567 593 when CMD_PS_DIRDEC => 568 594 ps_direction <= '0'; 569 state_read_data <= RD_ WAIT;595 state_read_data <= RD_5; 570 596 when CMD_WRITE => 571 597 next_packet_data <= '1'; … … 586 612 end if; 587 613 when RD_WAIT => 588 state_read_data <= RD_WAIT1; 614 if (config_rw_ack = '1') then 615 state_read_data <= RD_WAIT1; 616 end if; 589 617 when RD_WAIT1 => 590 config_data <= (others => 'Z'); 591 config_wr_en <= '0'; 592 state_read_data <= RD_5; 618 if (config_rw_ready = '1') then 619 config_data <= (others => 'Z'); 620 config_wr_en <= '0'; 621 state_read_data <= RD_5; 622 end if; 593 623 when RD_END => 594 624 par_addr <= W5300_S0_CR; … … 599 629 next_state <= CONFIG; 600 630 else 601 -- busy <= '0';602 631 next_state <= MAIN; 603 632 end if; … … 619 648 if (local_write_header_flag = '1') then 620 649 local_socket_nr <= ram_data (2 downto 0); 650 -- local_socket_nr <= "000"; 621 651 end if; 622 652 next_state_tmp <= next_state; … … 640 670 state_write <= WR_04; 641 671 when WR_04 => 642 if (socket_tx_free (16 downto 0) < write_length_bytes) then 672 673 -- led <= socket_tx_free (15 downto 8); 674 675 -- if (socket_tx_free (16 downto 0) < write_length_bytes) then 676 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then 643 677 state_write <= WR_01; 644 678 else … … 751 785 state_init <= WRITE_REG; 752 786 next_state <= WRITE_DATA; 753 state_write <= WR_05 ;787 state_write <= WR_05a; 754 788 755 789 -- End Write End Package Flag 790 791 -- Wait???? 792 when WR_05a => 793 if (wait_cntr < 10) then -- 3000 works??? 794 wait_cntr <= wait_cntr + 1; 795 else 796 wait_cntr <= 0; 797 state_write <= WR_05b; 798 end if; 799 when WR_05b => 800 state_write <= WR_05; 756 801 757 802 --Send FIFO … … 773 818 state_write <= WR_08; 774 819 when others => 775 -- busy <= '0';776 820 state_init <= next_state_tmp; 777 821 state_write <= WR_START;
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