Changeset 10081 for firmware


Ignore:
Timestamp:
Jan 5, 2011, 5:19:13 PM (9 years ago)
Author:
neise
Message:
DRS write shift register & write config register
Location:
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib
Files:
17 edited

Legend:

Unmodified
Added
Removed
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd

    r10073 r10081  
    6767
    6868      drs_read_s_cell_ready : in std_logic;
    69       drs_s_cell_array : in drs_s_cell_array_type
     69      drs_s_cell_array : in drs_s_cell_array_type;
     70     
     71      drs_readout_started : out std_logic
    7072      );
    7173end data_generator ;
     
    7375architecture Behavioral of data_generator is
    7476
    75 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
     77type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
    7678                             WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
    7779                             WRITE_END_FLAG, WRITE_DATA_STOP,
     
    9395signal roi_max_int : roi_max_type;
    9496
     97signal sig_drs_readout_started : std_logic := '0';
     98
    9599begin
    96100 
     101  drs_readout_started <= sig_drs_readout_started;
    97102 
    98103        generate_data : process (clk)
     
    151156          if (drs_srin_write_ready = '1') then
    152157            roi_max_int <= roi_max;
    153             state_generate <= WRITE_DATA_IDLE;
    154           end if;
     158            state_generate <= CONFIG6;
     159          end if;
     160          when CONFIG6 =>
     161            drs_channel_id <= DRS_WRITE_CONFIG_REG;
     162            drs_srin_data <= "11111111";
     163            drs_srin_write_8b <= '1';
     164            if (drs_srin_write_ack = '1') then
     165              drs_srin_write_8b <= '0';
     166              state_generate <= CONFIG7;
     167            end if;
     168          when CONFIG7 =>
     169            if (drs_srin_write_ready = '1') then
     170              roi_max_int <= roi_max;
     171              state_generate <= WRITE_DATA_IDLE;
     172            end if;
    155173        -- end configure DRS
    156174
     
    161179--          if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then
    162180          if (ram_write_ea = '1' and trigger_flag = '1') then
     181            sig_drs_readout_started <= '1'; -- is set to '0' in state WRITE_DAC1
    163182            -- stop drs, dwrite low
    164183            drs_dwrite <= '0';
     
    193212
    194213        when WRITE_DAC1 =>
     214          sig_drs_readout_started <= '0'; -- is set to '1' in state WRITE_DATA_IDLE
    195215          data_out <= conv_std_logic_vector (dac_array (3), 16)
    196216                    & conv_std_logic_vector (dac_array (2), 16)
     
    256276                      & "000" & adc_otr(1) & adc_data_array(1)
    257277                      & "000" & adc_otr(0) & adc_data_array(0);
    258 --              data_out <= "00000" & conv_std_logic_vector (data_cntr, 11)
     278 --             data_out <= "00000" & conv_std_logic_vector (data_cntr, 11)
    259279--                          & "00010" & conv_std_logic_vector (data_cntr, 11)
    260280--                          & "00100" & conv_std_logic_vector (data_cntr, 11)
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak

    r10073 r10081  
    6767
    6868      drs_read_s_cell_ready : in std_logic;
    69       drs_s_cell_array : in drs_s_cell_array_type
     69      drs_s_cell_array : in drs_s_cell_array_type;
     70     
     71      drs_readout_started : out std_logic
    7072      );
    7173end data_generator ;
     
    7375architecture Behavioral of data_generator is
    7476
    75 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
     77type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
    7678                             WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
    7779                             WRITE_END_FLAG, WRITE_DATA_STOP,
     
    9395signal roi_max_int : roi_max_type;
    9496
     97signal sig_drs_readout_started : std_logic := '0';
     98
    9599begin
    96100 
     101  drs_readout_started <= sig_drs_readout_started;
    97102 
    98103        generate_data : process (clk)
     
    142147        when CONFIG4 =>
    143148          drs_channel_id <= DRS_WRITE_SHIFT_REG;
    144           drs_srin_data <= "10101010";
     149          drs_srin_data <= "11111111";
    145150          drs_srin_write_8b <= '1';
    146151          if (drs_srin_write_ack = '1') then
     
    151156          if (drs_srin_write_ready = '1') then
    152157            roi_max_int <= roi_max;
    153             state_generate <= WRITE_DATA_IDLE;
    154           end if;
     158            state_generate <= CONFIG6;
     159          end if;
     160          when CONFIG6 =>
     161            drs_channel_id <= DRS_WRITE_CONFIG_REG;
     162            drs_srin_data <= "11111111";
     163            drs_srin_write_8b <= '1';
     164            if (drs_srin_write_ack = '1') then
     165              drs_srin_write_8b <= '0';
     166              state_generate <= CONFIG7;
     167            end if;
     168          when CONFIG7 =>
     169            if (drs_srin_write_ready = '1') then
     170              roi_max_int <= roi_max;
     171              state_generate <= WRITE_DATA_IDLE;
     172            end if;
    155173        -- end configure DRS
    156174
     
    161179--          if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then
    162180          if (ram_write_ea = '1' and trigger_flag = '1') then
     181            sig_drs_readout_started <= '1'; -- is set to '0' in state WRITE_DAC1
    163182            -- stop drs, dwrite low
    164183            drs_dwrite <= '0';
     
    193212
    194213        when WRITE_DAC1 =>
     214          sig_drs_readout_started <= '0'; -- is set to '1' in state WRITE_DATA_IDLE
    195215          data_out <= conv_std_logic_vector (dac_array (3), 16)
    196216                    & conv_std_logic_vector (dac_array (2), 16)
     
    252272        when WRITE_ADC_DATA =>
    253273          if (data_cntr < roi_max (channel_id)) then
    254             data_out <= "000" & adc_otr(3) & adc_data_array(3)
    255                       & "000" & adc_otr(2) & adc_data_array(2)
    256                       & "000" & adc_otr(1) & adc_data_array(1)
    257                       & "000" & adc_otr(0) & adc_data_array(0);
    258 --              data_out <= "00000" & conv_std_logic_vector (data_cntr, 11)
    259 --                          & "00010" & conv_std_logic_vector (data_cntr, 11)
    260 --                          & "00100" & conv_std_logic_vector (data_cntr, 11)
    261 --                          & "00110" & conv_std_logic_vector (data_cntr, 11) ;
     274--            data_out <= "000" & adc_otr(3) & adc_data_array(3)
     275--                      & "000" & adc_otr(2) & adc_data_array(2)
     276--                      & "000" & adc_otr(1) & adc_data_array(1)
     277--                      & "000" & adc_otr(0) & adc_data_array(0);
     278              data_out <= "00000" & conv_std_logic_vector (data_cntr, 11)
     279                          & "00010" & conv_std_logic_vector (data_cntr, 11)
     280                          & "00100" & conv_std_logic_vector (data_cntr, 11)
     281                          & "00110" & conv_std_logic_vector (data_cntr, 11) ;
    262282            addr_cntr <= addr_cntr + 1;
    263283            state_generate <= WRITE_ADC_DATA;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd

    r10072 r10081  
    6161            srin_write_ack <= '1';
    6262            srin_cntr <= 0;
    63             SRCLK_EN <= '1';
     63            --SRCLK_EN <= '1';
    6464            state_main <= SRIN_WRITE_8B;
    6565          end if;
     
    7575       
    7676        when SRIN_WRITE_8B =>
     77          SRCLK_EN <= '1';
    7778          srin_out <= srin_data (7 - srin_cntr);
    7879          if (srin_cntr = 7) then
    79             SRCLK_EN <= '0';
     80            --SRCLK_EN <= '0';
    8081            state_main <= SRIN_WRITE_END;
    8182          else
     
    8384          end if;
    8485        when SRIN_WRITE_END =>
    85           srin_out <= '0';
     86          SRCLK_EN <= '0';
     87          srin_out <= '1';
    8688          srin_write_ready <= '1';
    8789          srin_write_ack <= '0';
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd

    r10078 r10081  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 12:19:07 05.01.2011
     5--          at - 17:46:34 05.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    7979-- Created:
    8080--          by - dneise.UNKNOWN (E5B-LABOR6)
    81 --          at - 12:19:08 05.01.2011
     81--          at - 17:46:35 05.01.2011
    8282--
    8383-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    124124   -- status:
    125125   SIGNAL shifting        : std_logic                    := '0';
     126
     127   -- Implicit buffer signal declarations
     128   SIGNAL SRIN_internal : std_logic;
    126129
    127130
     
    253256   -- HDL Embedded Text Block 9 eb3
    254257   -- eb3 9                         
    255    A0_T(0) <= CLK50_OUT;
    256    A0_T(1)  <= CLK25_OUT;
     258   A0_T(0) <= ready;
     259   A0_T(1) <= shifting;
    257260   A0_T(2) <= CLK25_PSOUT;
    258261   A0_T(3) <= PS_DIR_IN;
     
    262265   A0_T(7) <= DCM_locked;
    263266   
    264    A1_T(0) <= ready;
    265    A1_T(1) <= shifting;
    266    A1_T(2) <= PSDONE_extraOUT;
    267    A1_T(3) <= PSCLK_OUT;
    268    A1_T(4) <= LOCKED_extraOUT;
    269    
    270    A1_T(5) <= '0';
    271    A1_T(6) <= '0';
    272    A1_T(7) <= '0';
     267   A1_T(0) <= SRIN_internal;
     268   A1_T(1) <= PSDONE_extraOUT;
     269   A1_T(2) <= PSCLK_OUT;
     270   A1_T(3) <= LOCKED_extraOUT;
     271   
     272   A1_T(4) <= drs_channel_id(0);
     273   A1_T(5) <= drs_channel_id(1);
     274   A1_T(6) <= drs_channel_id(2);
     275   A1_T(7) <= drs_channel_id(3);
    273276
    274277
     
    311314         RSRLOAD         => RSRLOAD,
    312315         SRCLK           => SRCLK,
    313          SRIN_out        => SRIN,
     316         SRIN_out        => SRIN_internal,
    314317         adc_clk_en      => adc_clk_en,
    315318         adc_oeb         => OE_ADC,
     
    337340      );
    338341
     342   -- Implicit buffered output assignments
     343   SRIN <= SRIN_internal;
     344
    339345END struct;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd

    r10072 r10081  
    140140constant CMD_PS_RESET : std_logic_vector     := X"17";
    141141-- DRS Registers
     142  constant DRS_CONFIG_REG : std_logic_vector := "1100"; 
    142143  constant DRS_WRITE_SHIFT_REG : std_logic_vector := "1101"; 
    143  
     144  constant DRS_WRITE_CONFIG_REG : std_logic_vector := "1110"; 
     145  constant DRS_DISABLE_ALL_OUTS : std_logic_vector := "1111"; 
    144146 
    145147-- Declare functions and procedure
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd.bak

    r9912 r10081  
    2323 
    2424  -- @ ETH zurich
    25     constant NETMASK : ip_type := (255, 255, 248, 0);
    26     constant IP_ADDRESS : ip_type := (192, 33, 99, 225);
    27     constant GATEWAY : ip_type := (192, 33, 96, 1);
     25--    constant NETMASK : ip_type := (255, 255, 248, 0);
     26--    constant IP_ADDRESS : ip_type := (192, 33, 99, 225);
     27--    constant GATEWAY : ip_type := (192, 33, 96, 1);
    2828
    2929  -- @ TU Dortmund
    30 --  constant NETMASK : ip_type := (255, 255, 255, 0);
    31 --  constant IP_ADDRESS : ip_type := (129, 217, 160, 119);
    32 --  constant GATEWAY : ip_type := (129, 217, 160, 1);
     30  constant NETMASK : ip_type := (255, 255, 255, 0);
     31  constant IP_ADDRESS : ip_type := (129, 217, 160, 119);
     32  constant GATEWAY : ip_type := (129, 217, 160, 1);
    3333
    3434  constant FIRST_PORT : integer := 5000;
     
    7979
    8080--
    81   constant W5300_TX_FIFO_SIZE : integer := (15360 / 2); -- Socket TX FIFO-Size in 16 Bit Words
     81  constant W5300_TX_FIFO_SIZE_8B : integer := 15360; -- Socket TX FIFO-Size in Bytes
     82  constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words
    8283
    8384  constant LOG2_OF_RAM_SIZE_64B : integer := 15;
     
    119120  constant CMD_READ : std_logic_vector        := X"0A";
    120121  constant CMD_WRITE : std_logic_vector       := X"05";
     122-- Config-RAM
     123  constant BADDR_ROI : std_logic_vector := X"00"; -- Baseaddress ROI-Values
     124  constant BADDR_DAC : std_logic_vector := X"24"; -- Baseaddress DAC-Values
    121125
    122126  constant CMD_DENABLE : std_logic_vector     := X"06";
     
    135139
    136140constant CMD_PS_RESET : std_logic_vector     := X"17";
    137 
     141-- DRS Registers
     142  constant DRS_WRITE_SHIFT_REG : std_logic_vector := "1101"; 
    138143 
    139144 
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd

    r10078 r10081  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 12:19:06 05.01.2011
     5--          at - 17:46:33 05.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    8080-- Created:
    8181--          by - dneise.UNKNOWN (E5B-LABOR6)
    82 --          at - 12:19:07 05.01.2011
     82--          at - 17:46:34 05.01.2011
    8383--
    8484-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    137137   SIGNAL drs_read_s_cell        : std_logic                                    := '0';
    138138   SIGNAL drs_read_s_cell_ready  : std_logic;
     139   SIGNAL drs_readout_started    : std_logic;
    139140   SIGNAL drs_s_cell_array       : drs_s_cell_array_type;
    140141   SIGNAL drs_srin_data          : std_logic_vector(7 DOWNTO 0)                 := (others => '0');
     
    298299      drs_srin_write_ready  : IN     std_logic ;
    299300      drs_read_s_cell_ready : IN     std_logic ;
    300       drs_s_cell_array      : IN     drs_s_cell_array_type
     301      drs_s_cell_array      : IN     drs_s_cell_array_type ;
     302      drs_readout_started   : OUT    std_logic
    301303   );
    302304   END COMPONENT;
     
    596598         drs_srin_write_ready  => srin_write_ready,
    597599         drs_read_s_cell_ready => drs_read_s_cell_ready,
    598          drs_s_cell_array      => drs_s_cell_array
     600         drs_s_cell_array      => drs_s_cell_array,
     601         drs_readout_started   => drs_readout_started
    599602      );
    600603   I_main_drs_pulser : drs_pulser
     
    628631         amber           => amber,
    629632         red             => red,
    630          trigger         => trigger_out,
     633         trigger         => drs_readout_started,
    631634         socks_waiting   => socks_waiting,
    632635         socks_connected => socks_connected
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf

    r10075 r10081  
    265265DESIGN @f@a@d_@board
    266266VIEW struct.bd
    267 NO_GRAPHIC 126
     267GRAPHIC 13136,0 127 0
     268DESIGN @f@a@d_@board
     269VIEW struct.bd
     270NO_GRAPHIC 129
    268271LIBRARY FACT_FAD_lib
    269272DESIGN @f@a@d_main
    270273VIEW struct
    271 GRAPHIC 169,0 128 0
    272 DESIGN @f@a@d_main
    273 VIEW symbol.sb
    274 GRAPHIC 14,0 129 1
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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf

    r10075 r10081  
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     359VIEW struct.bd
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     362VIEW struct.bd
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     365VIEW struct.bd
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     368VIEW struct.bd
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     371VIEW struct.bd
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     374VIEW struct.bd
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     377VIEW struct.bd
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     398VIEW struct.bd
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     400DESIGN @f@a@d_main
     401VIEW struct.bd
     402NO_GRAPHIC 184
    400403LIBRARY FACT_FAD_lib
    401404DESIGN adc_buffer
    402405VIEW beha
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    404 DESIGN @f@a@d_main
    405 VIEW struct.bd
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     408VIEW struct.bd
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     411VIEW struct.bd
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    410413DESIGN clock_generator_var_ps
    411414VIEW symbol.sb
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     415GRAPHIC 168,0 197 0
    413416DESIGN clock_generator_var_ps
    414417VIEW symbol.sb
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     418GRAPHIC 848,0 198 0
    416419DESIGN clock_generator_var_ps
    417420VIEW symbol.sb
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     421GRAPHIC 703,0 199 0
    419422DESIGN clock_generator_var_ps
    420423VIEW symbol.sb
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     424GRAPHIC 698,0 200 0
    422425DESIGN clock_generator_var_ps
    423426VIEW symbol.sb
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     427GRAPHIC 126,0 201 0
    425428DESIGN clock_generator_var_ps
    426429VIEW symbol.sb
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     430GRAPHIC 643,0 202 0
    428431DESIGN clock_generator_var_ps
    429432VIEW symbol.sb
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     433GRAPHIC 121,0 203 0
    431434DESIGN clock_generator_var_ps
    432435VIEW symbol.sb
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     436GRAPHIC 481,0 204 0
    434437DESIGN clock_generator_var_ps
    435438VIEW symbol.sb
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     439GRAPHIC 544,0 205 0
    437440DESIGN clock_generator_var_ps
    438441VIEW symbol.sb
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     442GRAPHIC 524,0 206 0
    440443DESIGN clock_generator_var_ps
    441444VIEW symbol.sb
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     445GRAPHIC 539,0 207 0
    443446DESIGN clock_generator_var_ps
    444447VIEW symbol.sb
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     448GRAPHIC 529,0 208 0
    446449DESIGN clock_generator_var_ps
    447450VIEW symbol.sb
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     451GRAPHIC 534,0 209 0
    449452DESIGN clock_generator_var_ps
    450453VIEW symbol.sb
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     454GRAPHIC 475,0 210 0
    452455DESIGN clock_generator_var_ps
    453456VIEW symbol.sb
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     457GRAPHIC 463,0 211 0
    455458DESIGN clock_generator_var_ps
    456459VIEW symbol.sb
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    458 DESIGN @f@a@d_main
    459 VIEW struct.bd
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     460GRAPHIC 469,0 212 0
     461DESIGN @f@a@d_main
     462VIEW struct.bd
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    461464DESIGN control_unit
    462465VIEW symbol.sb
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     466GRAPHIC 130,0 218 0
    464467DESIGN control_unit
    465468VIEW symbol.sb
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     469GRAPHIC 135,0 219 0
    467470DESIGN control_unit
    468471VIEW symbol.sb
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     472GRAPHIC 170,0 220 0
    470473DESIGN control_unit
    471474VIEW symbol.sb
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     475GRAPHIC 175,0 221 0
    473476DESIGN control_unit
    474477VIEW symbol.sb
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     478GRAPHIC 160,0 222 0
    476479DESIGN control_unit
    477480VIEW symbol.sb
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     481GRAPHIC 145,0 223 0
    479482DESIGN control_unit
    480483VIEW symbol.sb
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     484GRAPHIC 140,0 224 0
    482485DESIGN control_unit
    483486VIEW symbol.sb
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     487GRAPHIC 180,0 225 0
    485488DESIGN control_unit
    486489VIEW symbol.sb
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     490GRAPHIC 558,0 226 0
    488491DESIGN control_unit
    489492VIEW symbol.sb
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    491494DESIGN control_unit
    492495VIEW symbol.sb
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    494497DESIGN control_unit
    495498VIEW symbol.sb
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     499GRAPHIC 165,0 231 0
    497500DESIGN control_unit
    498501VIEW symbol.sb
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     502GRAPHIC 155,0 232 0
    500503DESIGN control_unit
    501504VIEW symbol.sb
    502 GRAPHIC 150,0 232 0
    503 DESIGN @f@a@d_main
    504 VIEW struct.bd
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     506DESIGN @f@a@d_main
     507VIEW struct.bd
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    506509DESIGN data@r@a@m_64b_16b_width14_5
    507510VIEW data@r@a@m_64b_16b_width14_5_a
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    509512DESIGN data@r@a@m_64b_16b_width14_5
    510513VIEW data@r@a@m_64b_16b_width14_5_a
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     514GRAPHIC 53,0 239 0
    512515DESIGN data@r@a@m_64b_16b_width14_5
    513516VIEW data@r@a@m_64b_16b_width14_5_a
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     517GRAPHIC 58,0 240 0
    515518DESIGN data@r@a@m_64b_16b_width14_5
    516519VIEW data@r@a@m_64b_16b_width14_5_a
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     520GRAPHIC 63,0 241 0
    518521DESIGN data@r@a@m_64b_16b_width14_5
    519522VIEW data@r@a@m_64b_16b_width14_5_a
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    521524DESIGN data@r@a@m_64b_16b_width14_5
    522525VIEW data@r@a@m_64b_16b_width14_5_a
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    525528VIEW data@r@a@m_64b_16b_width14_5_a
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    528 VIEW struct.bd
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    530 DESIGN data_generator
    531 VIEW symbol.sb
    532 GRAPHIC 14,0 247 1
    533 DESIGN data_generator
    534 VIEW @behavioral
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    536 DESIGN data_generator
    537 VIEW @behavioral
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    539 DESIGN data_generator
    540 VIEW @behavioral
    541 GRAPHIC 58,0 254 0
    542 DESIGN data_generator
    543 VIEW @behavioral
    544 GRAPHIC 73,0 255 0
    545 DESIGN data_generator
    546 VIEW @behavioral
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    548 DESIGN data_generator
    549 VIEW @behavioral
    550 GRAPHIC 402,0 257 0
    551 DESIGN data_generator
    552 VIEW @behavioral
    553 GRAPHIC 407,0 258 0
    554 DESIGN data_generator
    555 VIEW @behavioral
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    557 DESIGN data_generator
    558 VIEW @behavioral
    559 GRAPHIC 1122,0 261 0
    560 DESIGN data_generator
    561 VIEW @behavioral
    562 GRAPHIC 963,0 263 0
    563 DESIGN data_generator
    564 VIEW @behavioral
    565 GRAPHIC 1127,0 265 0
    566 DESIGN data_generator
    567 VIEW @behavioral
    568 GRAPHIC 1048,0 267 0
    569 DESIGN data_generator
    570 VIEW @behavioral
    571 GRAPHIC 958,0 268 0
    572 DESIGN data_generator
    573 VIEW @behavioral
    574 GRAPHIC 1053,0 269 0
    575 DESIGN data_generator
    576 VIEW @behavioral
    577 GRAPHIC 1201,0 270 0
    578 DESIGN data_generator
    579 VIEW @behavioral
    580 GRAPHIC 1196,0 271 0
    581 DESIGN data_generator
    582 VIEW @behavioral
    583 GRAPHIC 1206,0 272 0
    584 DESIGN data_generator
    585 VIEW @behavioral
    586 GRAPHIC 473,0 273 0
    587 DESIGN data_generator
    588 VIEW @behavioral
    589 GRAPHIC 412,0 274 0
    590 DESIGN data_generator
    591 VIEW @behavioral
    592 GRAPHIC 1085,0 275 0
    593 DESIGN data_generator
    594 VIEW @behavioral
    595 GRAPHIC 1090,0 276 0
    596 DESIGN data_generator
    597 VIEW @behavioral
    598 GRAPHIC 1240,0 277 0
    599 DESIGN data_generator
    600 VIEW @behavioral
    601 GRAPHIC 526,0 278 0
    602 DESIGN data_generator
    603 VIEW @behavioral
    604 GRAPHIC 88,0 279 0
    605 DESIGN data_generator
    606 VIEW @behavioral
    607 GRAPHIC 285,0 280 0
    608 DESIGN data_generator
    609 VIEW @behavioral
    610 GRAPHIC 93,0 281 0
    611 DESIGN data_generator
    612 VIEW @behavioral
    613 GRAPHIC 98,0 282 0
    614 DESIGN data_generator
    615 VIEW @behavioral
    616 GRAPHIC 1164,0 283 0
    617 DESIGN data_generator
    618 VIEW @behavioral
    619 GRAPHIC 1159,0 285 0
    620 DESIGN data_generator
    621 VIEW @behavioral
    622 GRAPHIC 898,0 286 0
    623 DESIGN data_generator
    624 VIEW @behavioral
    625 GRAPHIC 637,0 287 0
    626 DESIGN data_generator
    627 VIEW @behavioral
    628 GRAPHIC 1395,0 288 0
    629 DESIGN data_generator
    630 VIEW @behavioral
    631 GRAPHIC 1427,0 289 0
    632 DESIGN data_generator
    633 VIEW @behavioral
    634 GRAPHIC 676,0 290 0
    635 DESIGN data_generator
    636 VIEW @behavioral
    637 GRAPHIC 845,0 291 0
    638 DESIGN data_generator
    639 VIEW @behavioral
    640 GRAPHIC 681,0 292 0
    641 DESIGN data_generator
    642 VIEW @behavioral
    643 GRAPHIC 801,0 293 0
    644 DESIGN data_generator
    645 VIEW @behavioral
    646 GRAPHIC 1464,0 294 0
    647 DESIGN data_generator
    648 VIEW @behavioral
    649 GRAPHIC 1469,0 295 0
    650 DESIGN data_generator
    651 VIEW @behavioral
    652 GRAPHIC 1459,0 296 0
    653 DESIGN data_generator
    654 VIEW @behavioral
    655 GRAPHIC 1474,0 297 0
    656 DESIGN data_generator
    657 VIEW @behavioral
    658 GRAPHIC 806,0 298 0
    659 DESIGN data_generator
    660 VIEW @behavioral
    661 GRAPHIC 811,0 299 0
    662 DESIGN @f@a@d_main
    663 VIEW struct.bd
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    665 DESIGN @f@a@d_main
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     533DESIGN data_generator
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     801VIEW symbol.sb
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     1534VIEW struct.bd
     1535GRAPHIC 5114,0 711 0
     1536DESIGN @f@a@d_main
     1537VIEW struct.bd
     1538GRAPHIC 5122,0 712 0
     1539DESIGN @f@a@d_main
     1540VIEW struct.bd
     1541GRAPHIC 5130,0 713 0
     1542DESIGN @f@a@d_main
     1543VIEW struct.bd
     1544GRAPHIC 10194,0 714 0
     1545DESIGN @f@a@d_main
     1546VIEW struct.bd
     1547GRAPHIC 10202,0 715 0
     1548DESIGN @f@a@d_main
     1549VIEW struct.bd
     1550GRAPHIC 5106,0 716 0
     1551DESIGN @f@a@d_main
     1552VIEW struct.bd
     1553GRAPHIC 6362,0 717 0
     1554DESIGN @f@a@d_main
     1555VIEW struct.bd
     1556GRAPHIC 6452,0 718 0
     1557DESIGN @f@a@d_main
     1558VIEW struct.bd
     1559GRAPHIC 8752,0 719 0
     1560DESIGN @f@a@d_main
     1561VIEW struct.bd
     1562GRAPHIC 9233,0 720 0
     1563DESIGN @f@a@d_main
     1564VIEW struct.bd
     1565GRAPHIC 9241,0 721 0
     1566DESIGN @f@a@d_main
     1567VIEW struct.bd
     1568GRAPHIC 9943,0 722 0
     1569DESIGN @f@a@d_main
     1570VIEW struct.bd
     1571GRAPHIC 9951,0 723 0
     1572DESIGN @f@a@d_main
     1573VIEW struct.bd
     1574GRAPHIC 10637,0 724 0
     1575DESIGN @f@a@d_main
     1576VIEW struct.bd
     1577GRAPHIC 10629,0 725 0
     1578DESIGN @f@a@d_main
     1579VIEW struct.bd
     1580GRAPHIC 6276,0 729 0
     1581DESIGN @f@a@d_main
     1582VIEW struct.bd
     1583GRAPHIC 3888,0 730 0
     1584DESIGN @f@a@d_main
     1585VIEW struct.bd
     1586NO_GRAPHIC 732
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd

    r10075 r10081  
    149149(vvPair
    150150variable "date"
    151 value "04.01.2011"
     151value "05.01.2011"
    152152)
    153153(vvPair
    154154variable "day"
    155 value "Di"
     155value "Mi"
    156156)
    157157(vvPair
    158158variable "day_long"
    159 value "Dienstag"
     159value "Mittwoch"
    160160)
    161161(vvPair
    162162variable "dd"
    163 value "04"
     163value "05"
    164164)
    165165(vvPair
     
    297297(vvPair
    298298variable "time"
    299 value "18:14:31"
     299value "17:34:20"
    300300)
    301301(vvPair
     
    27572757)
    27582758xt "39000,62400,67500,63200"
    2759 st "SIGNAL board_id        : std_logic_vector(3 downto 0)
    2760 "
     2759st "SIGNAL board_id        : std_logic_vector(3 downto 0)"
    27612760)
    27622761)
     
    27762775)
    27772776xt "39000,63200,67500,64000"
    2778 st "SIGNAL crate_id        : std_logic_vector(1 downto 0)
    2779 "
     2777st "SIGNAL crate_id        : std_logic_vector(1 downto 0)"
    27802778)
    27812779)
     
    31003098)
    31013099xt "39000,61600,63000,62400"
    3102 st "SIGNAL adc_data_array  : adc_data_array_type
    3103 "
     3100st "SIGNAL adc_data_array  : adc_data_array_type"
    31043101)
    31053102)
     
    31193116)
    31203117xt "39000,35800,67500,36600"
    3121 st "RSRLOAD         : std_logic                    := '0'
    3122 "
     3118st "RSRLOAD         : std_logic                    := '0'"
    31233119)
    31243120)
     
    31833179)
    31843180xt "39000,60000,71000,60800"
    3185 st "SIGNAL SRCLK           : std_logic                    := '0'
    3186 "
     3181st "SIGNAL SRCLK           : std_logic                    := '0'"
    31873182)
    31883183)
     
    32023197)
    32033198xt "39000,66400,67500,67200"
    3204 st "SIGNAL sensor_cs       : std_logic_vector(3 DOWNTO 0)
    3205 "
     3199st "SIGNAL sensor_cs       : std_logic_vector(3 DOWNTO 0)"
    32063200)
    32073201)
     
    32203214)
    32213215xt "39000,23000,54000,23800"
    3222 st "DAC_CS          : std_logic
    3223 "
     3216st "DAC_CS          : std_logic"
    32243217)
    32253218)
     
    32853278)
    32863279xt "39000,15800,54000,16600"
    3287 st "X_50M           : STD_LOGIC
    3288 "
     3280st "X_50M           : STD_LOGIC"
    32893281)
    32903282)
     
    33033295)
    33043296xt "39000,14200,54000,15000"
    3305 st "TRG             : STD_LOGIC
    3306 "
     3297st "TRG             : STD_LOGIC"
    33073298)
    33083299)
     
    34133404)
    34143405xt "39000,19000,64000,19800"
    3415 st "A_CLK           : std_logic_vector(3 downto 0)
    3416 "
     3406st "A_CLK           : std_logic_vector(3 downto 0)"
    34173407)
    34183408)
     
    34313421)
    34323422xt "39000,51200,57500,52000"
    3433 st "SIGNAL CLK_25_PS       : std_logic
    3434 "
     3423st "SIGNAL CLK_25_PS       : std_logic"
    34353424)
    34363425)
     
    34963485)
    34973486xt "39000,30200,54000,31000"
    3498 st "OE_ADC          : STD_LOGIC
    3499 "
     3487st "OE_ADC          : STD_LOGIC"
    35003488)
    35013489)
     
    35603548)
    35613549xt "39000,7000,64000,7800"
    3562 st "A_OTR           : std_logic_vector(3 DOWNTO 0)
    3563 "
     3550st "A_OTR           : std_logic_vector(3 DOWNTO 0)"
    35643551)
    35653552)
     
    38503837)
    38513838xt "39000,3800,64500,4600"
    3852 st "A0_D            : std_logic_vector(11 DOWNTO 0)
    3853 "
     3839st "A0_D            : std_logic_vector(11 DOWNTO 0)"
    38543840)
    38553841)
     
    38693855)
    38703856xt "39000,4600,64500,5400"
    3871 st "A1_D            : std_logic_vector(11 DOWNTO 0)
    3872 "
     3857st "A1_D            : std_logic_vector(11 DOWNTO 0)"
    38733858)
    38743859)
     
    38883873)
    38893874xt "39000,5400,64500,6200"
    3890 st "A2_D            : std_logic_vector(11 DOWNTO 0)
    3891 "
     3875st "A2_D            : std_logic_vector(11 DOWNTO 0)"
    38923876)
    38933877)
     
    39073891)
    39083892xt "39000,6200,64500,7000"
    3909 st "A3_D            : std_logic_vector(11 DOWNTO 0)
    3910 "
     3893st "A3_D            : std_logic_vector(11 DOWNTO 0)"
    39113894)
    39123895)
     
    40163999)
    40174000xt "39000,19800,54000,20600"
    4018 st "D0_SRCLK        : STD_LOGIC
    4019 "
     4001st "D0_SRCLK        : STD_LOGIC"
    40204002)
    40214003)
     
    40344016)
    40354017xt "39000,20600,54000,21400"
    4036 st "D1_SRCLK        : STD_LOGIC
    4037 "
     4018st "D1_SRCLK        : STD_LOGIC"
    40384019)
    40394020)
     
    40524033)
    40534034xt "39000,21400,54000,22200"
    4054 st "D2_SRCLK        : STD_LOGIC
    4055 "
     4035st "D2_SRCLK        : STD_LOGIC"
    40564036)
    40574037)
     
    40704050)
    40714051xt "39000,22200,54000,23000"
    4072 st "D3_SRCLK        : STD_LOGIC
    4073 "
     4052st "D3_SRCLK        : STD_LOGIC"
    40744053)
    40754054)
     
    42684247)
    42694248xt "39000,7800,54000,8600"
    4270 st "D0_SROUT        : std_logic
    4271 "
     4249st "D0_SROUT        : std_logic"
    42724250)
    42734251)
     
    42864264)
    42874265xt "39000,8600,54000,9400"
    4288 st "D1_SROUT        : std_logic
    4289 "
     4266st "D1_SROUT        : std_logic"
    42904267)
    42914268)
     
    43044281)
    43054282xt "39000,9400,54000,10200"
    4306 st "D2_SROUT        : std_logic
    4307 "
     4283st "D2_SROUT        : std_logic"
    43084284)
    43094285)
     
    43224298)
    43234299xt "39000,10200,54000,11000"
    4324 st "D3_SROUT        : std_logic
    4325 "
     4300st "D3_SROUT        : std_logic"
    43264301)
    43274302)
     
    43874362)
    43884363xt "39000,25400,73500,26200"
    4389 st "D_A             : std_logic_vector(3 DOWNTO 0) := (others => '0')
    4390 "
     4364st "D_A             : std_logic_vector(3 DOWNTO 0) := (others => '0')"
    43914365)
    43924366)
     
    44514425)
    44524426xt "39000,24600,67500,25400"
    4453 st "DWRITE          : std_logic                    := '0'
    4454 "
     4427st "DWRITE          : std_logic                    := '0'"
    44554428)
    44564429)
     
    47804753)
    47814754xt "39000,38200,54000,39000"
    4782 st "T0_CS           : std_logic
    4783 "
     4755st "T0_CS           : std_logic"
    47844756)
    47854757)
     
    47984770)
    47994771xt "39000,39000,54000,39800"
    4800 st "T1_CS           : std_logic
    4801 "
     4772st "T1_CS           : std_logic"
    48024773)
    48034774)
     
    48164787)
    48174788xt "39000,39800,54000,40600"
    4818 st "T2_CS           : std_logic
    4819 "
     4789st "T2_CS           : std_logic"
    48204790)
    48214791)
     
    48344804)
    48354805xt "39000,40600,54000,41400"
    4836 st "T3_CS           : std_logic
    4837 "
     4806st "T3_CS           : std_logic"
    48384807)
    48394808)
     
    48964865)
    48974866xt "39000,37400,54000,38200"
    4898 st "S_CLK           : std_logic
    4899 "
     4867st "S_CLK           : std_logic"
    49004868)
    49014869)
     
    49154883)
    49164884xt "39000,42200,64000,43000"
    4917 st "W_A             : std_logic_vector(9 DOWNTO 0)
    4918 "
     4885st "W_A             : std_logic_vector(9 DOWNTO 0)"
    49194886)
    49204887)
     
    49344901)
    49354902xt "39000,47000,64500,47800"
    4936 st "W_D             : std_logic_vector(15 DOWNTO 0)
    4937 "
     4903st "W_D             : std_logic_vector(15 DOWNTO 0)"
    49384904)
    49394905)
     
    49534919)
    49544920xt "39000,44600,67500,45400"
    4955 st "W_RES           : std_logic                    := '1'
    4956 "
     4921st "W_RES           : std_logic                    := '1'"
    49574922)
    49584923)
     
    49724937)
    49734938xt "39000,43800,67500,44600"
    4974 st "W_RD            : std_logic                    := '1'
    4975 "
     4939st "W_RD            : std_logic                    := '1'"
    49764940)
    49774941)
     
    49914955)
    49924956xt "39000,45400,67500,46200"
    4993 st "W_WR            : std_logic                    := '1'
    4994 "
     4957st "W_WR            : std_logic                    := '1'"
    49954958)
    49964959)
     
    50094972)
    50104973xt "39000,15000,54000,15800"
    5011 st "W_INT           : std_logic
    5012 "
     4974st "W_INT           : std_logic"
    50134975)
    50144976)
     
    50284990)
    50294991xt "39000,43000,67500,43800"
    5030 st "W_CS            : std_logic                    := '1'
    5031 "
     4992st "W_CS            : std_logic                    := '1'"
    50324993)
    50334994)
     
    50895050)
    50905051xt "39000,29400,67500,30200"
    5091 st "MOSI            : std_logic                    := '0'
    5092 "
     5052st "MOSI            : std_logic                    := '0'"
    50935053)
    50945054)
     
    51535113)
    51545114xt "39000,46200,54000,47000"
    5155 st "MISO            : std_logic
    5156 "
     5115st "MISO            : std_logic"
    51575116)
    51585117)
     
    55805539)
    55815540xt "39000,41400,54000,42200"
    5582 st "TRG_V           : std_logic
    5583 "
     5541st "TRG_V           : std_logic"
    55845542)
    55855543)
     
    55985556)
    55995557xt "39000,33400,54000,34200"
    5600 st "RS485_C_RE      : std_logic
    5601 "
     5558st "RS485_C_RE      : std_logic"
    56025559)
    56035560)
     
    56165573)
    56175574xt "39000,31800,54000,32600"
    5618 st "RS485_C_DE      : std_logic
    5619 "
     5575st "RS485_C_DE      : std_logic"
    56205576)
    56215577)
     
    56345590)
    56355591xt "39000,35000,54000,35800"
    5636 st "RS485_E_RE      : std_logic
    5637 "
     5592st "RS485_E_RE      : std_logic"
    56385593)
    56395594)
     
    56525607)
    56535608xt "39000,34200,54000,35000"
    5654 st "RS485_E_DE      : std_logic
    5655 "
     5609st "RS485_E_DE      : std_logic"
    56565610)
    56575611)
     
    56715625)
    56725626xt "39000,23800,67500,24600"
    5673 st "DENABLE         : std_logic                    := '0'
    5674 "
     5627st "DENABLE         : std_logic                    := '0'"
    56755628)
    56765629)
     
    56895642)
    56905643xt "39000,27800,54000,28600"
    5691 st "EE_CS           : std_logic
    5692 "
     5644st "EE_CS           : std_logic"
    56935645)
    56945646)
     
    59335885)
    59345886xt "39000,26200,73500,27000"
    5935 st "D_T             : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')
    5936 "
     5887st "D_T             : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
    59375888)
    59385889)
     
    59975948)
    59985949xt "39000,11000,64000,11800"
    5999 st "D_PLLLCK        : std_logic_vector(3 DOWNTO 0)
    6000 "
     5950st "D_PLLLCK        : std_logic_vector(3 DOWNTO 0)"
    60015951)
    60025952)
     
    60616011)
    60626012xt "39000,27000,73500,27800"
    6063 st "D_T2            : std_logic_vector(3 DOWNTO 0) := (others => '0')
    6064 "
     6013st "D_T2            : std_logic_vector(3 DOWNTO 0) := (others => '0')"
    60656014)
    60666015)
     
    63016250)
    63026251xt "39000,17400,73500,18200"
    6303 st "A1_T            : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')
    6304 "
     6252st "A1_T            : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
    63056253)
    63066254)
     
    63196267)
    63206268xt "39000,64800,57500,65600"
    6321 st "SIGNAL dummy           : std_logic
    6322 "
     6269st "SIGNAL dummy           : std_logic"
    63236270)
    63246271)
     
    66566603)
    66576604xt "39000,64000,77000,64800"
    6658 st "SIGNAL drs_channel_id  : std_logic_vector(3 downto 0) := (others => '0')
    6659 "
     6605st "SIGNAL drs_channel_id  : std_logic_vector(3 downto 0) := (others => '0')"
    66606606)
    66616607)
     
    66746620)
    66756621xt "39000,52800,57500,53600"
    6676 st "SIGNAL CLK_50          : std_logic
    6677 "
     6622st "SIGNAL CLK_50          : std_logic"
    66786623)
    66796624)
     
    70597004)
    70607005xt "39000,52000,57500,52800"
    7061 st "SIGNAL CLK_25_PS1      : std_logic
    7062 "
     7006st "SIGNAL CLK_25_PS1      : std_logic"
    70637007)
    70647008)
     
    70787022)
    70797023xt "39000,60800,71000,61600"
    7080 st "SIGNAL adc_clk_en      : std_logic                    := '0'
    7081 "
     7024st "SIGNAL adc_clk_en      : std_logic                    := '0'"
    70827025)
    70837026)
     
    71427085)
    71437086xt "39000,16600,73500,17400"
    7144 st "A0_T            : std_logic_vector(7 DOWNTO 0) := (others => '0')
    7145 "
     7087st "A0_T            : std_logic_vector(7 DOWNTO 0) := (others => '0')"
    71467088)
    71477089)
     
    71727114st "
    71737115-- eb3 9                         
    7174 A0_T(0) <= CLK50_OUT;
    7175 A0_T(1)  <= CLK25_OUT;
     7116A0_T(0) <= ready;
     7117A0_T(1) <= shifting;
    71767118A0_T(2) <= CLK25_PSOUT;
    71777119A0_T(3) <= PS_DIR_IN;
     
    71817123A0_T(7) <= DCM_locked;
    71827124
    7183 A1_T(0) <= ready;
    7184 A1_T(1) <= shifting;
    7185 A1_T(2) <= PSDONE_extraOUT;
    7186 A1_T(3) <= PSCLK_OUT;
    7187 A1_T(4) <= LOCKED_extraOUT;
     7125A1_T(0) <= SRIN;
     7126A1_T(1) <= PSDONE_extraOUT;
     7127A1_T(2) <= PSCLK_OUT;
     7128A1_T(3) <= LOCKED_extraOUT;
    71887129
    7189 A1_T(5) <= '0';
    7190 A1_T(6) <= '0';
    7191 A1_T(7) <= '0';
     7130A1_T(4) <= drs_channel_id(0);
     7131A1_T(5) <= drs_channel_id(1);
     7132A1_T(6) <= drs_channel_id(2);
     7133A1_T(7) <= drs_channel_id(3);
     7134
    71927135"
    71937136tm "HdlTextMgr"
     
    72077150lineWidth 2
    72087151)
    7209 xt "106000,122000,112000,136000"
     7152xt "106000,122000,112000,137000"
    72107153)
    72117154oxt "0,0,8000,10000"
     
    72447187fg "49152,49152,49152"
    72457188)
    7246 xt "106250,134250,107750,135750"
     7189xt "106250,135250,107750,136750"
    72477190iconName "TextFile.png"
    72487191iconMaskName "TextFile.msk"
     
    72657208)
    72667209xt "39000,50400,57500,51200"
    7267 st "SIGNAL CLK50_OUT       : std_logic
    7268 "
     7210st "SIGNAL CLK50_OUT       : std_logic"
    72697211)
    72707212)
     
    72837225)
    72847226xt "39000,48800,57500,49600"
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    72877228)
    72887229)
     
    73017242)
    73027243xt "39000,49600,57500,50400"
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    73057245)
    73067246)
     
    73197259)
    73207260xt "39000,58400,57500,59200"
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    73237262)
    73247263)
     
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     7278st "SIGNAL PS_DO_IN        : std_logic"
    73417279)
    73427280)
     
    73557293)
    73567294xt "39000,56800,57500,57600"
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    7358 "
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    73597296)
    73607297)
     
    73737310)
    73747311xt "39000,57600,57500,58400"
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     7312st "SIGNAL PSINCDEC_OUT    : std_logic"
    73777313)
    73787314)
     
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    73987333)
     
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    74197353)
     
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     7373SIGNAL shifting        : std_logic                    := '0'"
    74417374)
    74427375)
     
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    74597391)
    74607392)
     
    74737405)
    74747406xt "39000,55200,57500,56000"
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    74787409)
     
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    75597488)
     
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    76217549)
     
    76797607)
    76807608xt "39000,12600,54000,13400"
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     7609st "RS485_E_DI      : std_logic"
    76837610)
    76847611)
     
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    76987625xt "39000,13400,54000,14200"
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    7700 "
     7626st "RS485_E_DO      : std_logic"
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    77027628)
     
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    78097734)
     
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    79587882)
    79597883)
     
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    79737897xt "39000,28600,54000,29400"
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    7975 "
     7898st "GREEN_LED       : std_logic"
    79767899)
    79777900)
     
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    79917914xt "39000,31000,54000,31800"
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    79957917)
     
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     13018decl (Decl
    1306213019n "S_CLK"
    1306313020t "std_logic"
     
    1306813025uid 3654,0
    1306913026)
    13070 *437 (LeafLogPort
     13027*438 (LeafLogPort
    1307113028port (LogicalPort
    1307213029m 1
     
    1308113038uid 3656,0
    1308213039)
    13083 *438 (LeafLogPort
     13040*439 (LeafLogPort
    1308413041port (LogicalPort
    1308513042m 2
     
    1309413051uid 3658,0
    1309513052)
    13096 *439 (LeafLogPort
     13053*440 (LeafLogPort
    1309713054port (LogicalPort
    1309813055m 1
     
    1310713064uid 3660,0
    1310813065)
    13109 *440 (LeafLogPort
     13066*441 (LeafLogPort
    1311013067port (LogicalPort
    1311113068m 1
     
    1312013077uid 3662,0
    1312113078)
    13122 *441 (LeafLogPort
     13079*442 (LeafLogPort
    1312313080port (LogicalPort
    1312413081m 1
     
    1313313090uid 3664,0
    1313413091)
    13135 *442 (LeafLogPort
     13092*443 (LeafLogPort
    1313613093port (LogicalPort
    1313713094decl (Decl
     
    1314413101uid 3666,0
    1314513102)
    13146 *443 (LeafLogPort
     13103*444 (LeafLogPort
    1314713104port (LogicalPort
    1314813105m 1
     
    1315713114uid 3668,0
    1315813115)
    13159 *444 (LeafLogPort
     13116*445 (LeafLogPort
    1316013117port (LogicalPort
    1316113118m 1
     
    1317013127uid 3696,0
    1317113128)
    13172 *445 (LeafLogPort
     13129*446 (LeafLogPort
    1317313130port (LogicalPort
    1317413131m 2
     
    1318413141uid 3698,0
    1318513142)
    13186 *446 (LeafLogPort
    13187 port (LogicalPort
    13188 m 1
    13189 decl (Decl
    13190 n "TRG_V"
    13191 t "std_logic"
    13192 o 48
    13193 suid 126,0
    13194 )
    13195 )
    13196 uid 3886,0
    13197 )
    1319813143*447 (LeafLogPort
    1319913144port (LogicalPort
    1320013145m 1
    1320113146decl (Decl
    13202 n "RS485_C_RE"
    13203 t "std_logic"
    13204 o 38
    13205 suid 127,0
    13206 )
    13207 )
    13208 uid 3888,0
     13147n "TRG_V"
     13148t "std_logic"
     13149o 48
     13150suid 126,0
     13151)
     13152)
     13153uid 3886,0
    1320913154)
    1321013155*448 (LeafLogPort
     
    1321213157m 1
    1321313158decl (Decl
    13214 n "RS485_C_DE"
    13215 t "std_logic"
    13216 o 36
    13217 suid 128,0
    13218 )
    13219 )
    13220 uid 3890,0
     13159n "RS485_C_RE"
     13160t "std_logic"
     13161o 38
     13162suid 127,0
     13163)
     13164)
     13165uid 3888,0
    1322113166)
    1322213167*449 (LeafLogPort
     
    1322413169m 1
    1322513170decl (Decl
    13226 n "RS485_E_RE"
    13227 t "std_logic"
    13228 o 40
    13229 suid 129,0
    13230 )
    13231 )
    13232 uid 3892,0
     13171n "RS485_C_DE"
     13172t "std_logic"
     13173o 36
     13174suid 128,0
     13175)
     13176)
     13177uid 3890,0
    1323313178)
    1323413179*450 (LeafLogPort
     
    1323613181m 1
    1323713182decl (Decl
    13238 n "RS485_E_DE"
    13239 t "std_logic"
    13240 o 39
    13241 suid 130,0
    13242 )
    13243 )
    13244 uid 3894,0
     13183n "RS485_E_RE"
     13184t "std_logic"
     13185o 40
     13186suid 129,0
     13187)
     13188)
     13189uid 3892,0
    1324513190)
    1324613191*451 (LeafLogPort
     
    1324813193m 1
    1324913194decl (Decl
     13195n "RS485_E_DE"
     13196t "std_logic"
     13197o 39
     13198suid 130,0
     13199)
     13200)
     13201uid 3894,0
     13202)
     13203*452 (LeafLogPort
     13204port (LogicalPort
     13205m 1
     13206decl (Decl
    1325013207n "DENABLE"
    1325113208t "std_logic"
     
    1325713214uid 3896,0
    1325813215)
    13259 *452 (LeafLogPort
     13216*453 (LeafLogPort
    1326013217port (LogicalPort
    1326113218m 1
     
    1326913226uid 3900,0
    1327013227)
    13271 *453 (LeafLogPort
     13228*454 (LeafLogPort
    1327213229port (LogicalPort
    1327313230m 1
     
    1328313240uid 5322,0
    1328413241)
    13285 *454 (LeafLogPort
     13242*455 (LeafLogPort
    1328613243port (LogicalPort
    1328713244decl (Decl
     
    1329613253scheme 0
    1329713254)
    13298 *455 (LeafLogPort
     13255*456 (LeafLogPort
    1329913256port (LogicalPort
    1330013257m 1
     
    1331113268scheme 0
    1331213269)
    13313 *456 (LeafLogPort
     13270*457 (LeafLogPort
    1331413271port (LogicalPort
    1331513272m 1
     
    1332613283scheme 0
    1332713284)
    13328 *457 (LeafLogPort
     13285*458 (LeafLogPort
    1332913286port (LogicalPort
    1333013287m 4
     
    1333913296scheme 0
    1334013297)
    13341 *458 (LeafLogPort
     13298*459 (LeafLogPort
    1334213299port (LogicalPort
    1334313300m 4
     
    1335313310uid 8875,0
    1335413311)
    13355 *459 (LeafLogPort
    13356 port (LogicalPort
    13357 m 4
    13358 decl (Decl
    13359 n "CLK_50"
    13360 t "std_logic"
    13361 o 61
    13362 suid 163,0
    13363 )
    13364 )
    13365 uid 9516,0
    13366 )
    1336713312*460 (LeafLogPort
    1336813313port (LogicalPort
    1336913314m 4
    1337013315decl (Decl
    13371 n "CLK_25_PS1"
    13372 t "std_logic"
    13373 o 60
    13374 suid 164,0
    13375 )
    13376 )
    13377 uid 10056,0
     13316n "CLK_50"
     13317t "std_logic"
     13318o 61
     13319suid 163,0
     13320)
     13321)
     13322uid 9516,0
    1337813323)
    1337913324*461 (LeafLogPort
     
    1338113326m 4
    1338213327decl (Decl
     13328n "CLK_25_PS1"
     13329t "std_logic"
     13330o 60
     13331suid 164,0
     13332)
     13333)
     13334uid 10056,0
     13335)
     13336*462 (LeafLogPort
     13337port (LogicalPort
     13338m 4
     13339decl (Decl
    1338313340n "adc_clk_en"
    1338413341t "std_logic"
     
    1339013347uid 10058,0
    1339113348)
    13392 *462 (LeafLogPort
     13349*463 (LeafLogPort
    1339313350port (LogicalPort
    1339413351m 1
     
    1340513362scheme 0
    1340613363)
    13407 *463 (LeafLogPort
    13408 port (LogicalPort
    13409 m 4
    13410 decl (Decl
    13411 n "CLK50_OUT"
    13412 t "std_logic"
    13413 o 58
    13414 suid 184,0
    13415 )
    13416 )
    13417 uid 10704,0
    13418 )
    1341913364*464 (LeafLogPort
    1342013365port (LogicalPort
    1342113366m 4
    1342213367decl (Decl
    13423 n "CLK25_OUT"
    13424 t "std_logic"
    13425 o 56
    13426 suid 185,0
    13427 )
    13428 )
    13429 uid 10706,0
     13368n "CLK50_OUT"
     13369t "std_logic"
     13370o 58
     13371suid 184,0
     13372)
     13373)
     13374uid 10704,0
    1343013375)
    1343113376*465 (LeafLogPort
     
    1343313378m 4
    1343413379decl (Decl
    13435 n "CLK25_PSOUT"
    13436 t "std_logic"
    13437 o 57
    13438 suid 186,0
    13439 )
    13440 )
    13441 uid 10708,0
     13380n "CLK25_OUT"
     13381t "std_logic"
     13382o 56
     13383suid 185,0
     13384)
     13385)
     13386uid 10706,0
    1344213387)
    1344313388*466 (LeafLogPort
     
    1344513390m 4
    1344613391decl (Decl
    13447 n "PS_DIR_IN"
    13448 t "std_logic"
    13449 o 68
    13450 suid 187,0
    13451 )
    13452 )
    13453 uid 10710,0
     13392n "CLK25_PSOUT"
     13393t "std_logic"
     13394o 57
     13395suid 186,0
     13396)
     13397)
     13398uid 10708,0
    1345413399)
    1345513400*467 (LeafLogPort
     
    1345713402m 4
    1345813403decl (Decl
    13459 n "PS_DO_IN"
    13460 t "std_logic"
    13461 o 69
    13462 suid 188,0
    13463 )
    13464 )
    13465 uid 10712,0
     13404n "PS_DIR_IN"
     13405t "std_logic"
     13406o 68
     13407suid 187,0
     13408)
     13409)
     13410uid 10710,0
    1346613411)
    1346713412*468 (LeafLogPort
     
    1346913414m 4
    1347013415decl (Decl
    13471 n "PSEN_OUT"
    13472 t "std_logic"
    13473 o 66
    13474 suid 189,0
    13475 )
    13476 )
    13477 uid 10714,0
     13416n "PS_DO_IN"
     13417t "std_logic"
     13418o 69
     13419suid 188,0
     13420)
     13421)
     13422uid 10712,0
    1347813423)
    1347913424*469 (LeafLogPort
     
    1348113426m 4
    1348213427decl (Decl
     13428n "PSEN_OUT"
     13429t "std_logic"
     13430o 66
     13431suid 189,0
     13432)
     13433)
     13434uid 10714,0
     13435)
     13436*470 (LeafLogPort
     13437port (LogicalPort
     13438m 4
     13439decl (Decl
    1348313440n "PSINCDEC_OUT"
    1348413441t "std_logic"
     
    1348913446uid 10716,0
    1349013447)
    13491 *470 (LeafLogPort
     13448*471 (LeafLogPort
    1349213449port (LogicalPort
    1349313450m 4
     
    1350313460uid 10718,0
    1350413461)
    13505 *471 (LeafLogPort
     13462*472 (LeafLogPort
    1350613463port (LogicalPort
    1350713464m 4
     
    1351813475uid 10720,0
    1351913476)
    13520 *472 (LeafLogPort
     13477*473 (LeafLogPort
    1352113478port (LogicalPort
    1352213479m 4
     
    1353413491uid 10722,0
    1353513492)
    13536 *473 (LeafLogPort
    13537 port (LogicalPort
    13538 m 4
    13539 decl (Decl
    13540 n "PSDONE_extraOUT"
    13541 t "std_logic"
    13542 o 65
    13543 suid 194,0
    13544 )
    13545 )
    13546 uid 10724,0
    13547 )
    1354813493*474 (LeafLogPort
    1354913494port (LogicalPort
    1355013495m 4
    1355113496decl (Decl
    13552 n "PSCLK_OUT"
    13553 t "std_logic"
    13554 o 64
    13555 suid 195,0
    13556 )
    13557 )
    13558 uid 10726,0
     13497n "PSDONE_extraOUT"
     13498t "std_logic"
     13499o 65
     13500suid 194,0
     13501)
     13502)
     13503uid 10724,0
    1355913504)
    1356013505*475 (LeafLogPort
     
    1356213507m 4
    1356313508decl (Decl
     13509n "PSCLK_OUT"
     13510t "std_logic"
     13511o 64
     13512suid 195,0
     13513)
     13514)
     13515uid 10726,0
     13516)
     13517*476 (LeafLogPort
     13518port (LogicalPort
     13519m 4
     13520decl (Decl
    1356413521n "LOCKED_extraOUT"
    1356513522t "std_logic"
     
    1357013527uid 10728,0
    1357113528)
    13572 *476 (LeafLogPort
     13529*477 (LeafLogPort
    1357313530port (LogicalPort
    1357413531decl (Decl
     
    1358213539scheme 0
    1358313540)
    13584 *477 (LeafLogPort
     13541*478 (LeafLogPort
    1358513542port (LogicalPort
    1358613543m 1
     
    1359513552scheme 0
    1359613553)
    13597 *478 (LeafLogPort
     13554*479 (LeafLogPort
    1359813555port (LogicalPort
    1359913556decl (Decl
     
    1360713564scheme 0
    1360813565)
    13609 *479 (LeafLogPort
     13566*480 (LeafLogPort
    1361013567port (LogicalPort
    1361113568decl (Decl
     
    1361913576scheme 0
    1362013577)
    13621 *480 (LeafLogPort
     13578*481 (LeafLogPort
    1362213579port (LogicalPort
    1362313580m 1
     
    1363213589uid 12336,0
    1363313590)
    13634 *481 (LeafLogPort
    13635 port (LogicalPort
    13636 m 1
    13637 decl (Decl
    13638 n "AMBER_LED"
    13639 t "std_logic"
    13640 o 31
    13641 suid 207,0
    13642 )
    13643 )
    13644 uid 12768,0
    13645 )
    1364613591*482 (LeafLogPort
    1364713592port (LogicalPort
    1364813593m 1
    1364913594decl (Decl
     13595n "AMBER_LED"
     13596t "std_logic"
     13597o 31
     13598suid 207,0
     13599)
     13600)
     13601uid 12768,0
     13602)
     13603*483 (LeafLogPort
     13604port (LogicalPort
     13605m 1
     13606decl (Decl
    1365013607n "GREEN_LED"
    1365113608t "std_logic"
     
    1365613613uid 12770,0
    1365713614)
    13658 *483 (LeafLogPort
     13615*484 (LeafLogPort
    1365913616port (LogicalPort
    1366013617m 1
     
    1367513632uid 67,0
    1367613633optionalChildren [
    13677 *484 (Sheet
     13634*485 (Sheet
    1367813635sheetRow (SheetRow
    1367913636headerVa (MVa
     
    1369213649font "Tahoma,10,0"
    1369313650)
    13694 emptyMRCItem *485 (MRCItem
    13695 litem &392
     13651emptyMRCItem *486 (MRCItem
     13652litem &393
    1369613653pos 79
    1369713654dimension 20
     
    1369913656uid 69,0
    1370013657optionalChildren [
    13701 *486 (MRCItem
    13702 litem &393
     13658*487 (MRCItem
     13659litem &394
    1370313660pos 0
    1370413661dimension 20
    1370513662uid 70,0
    1370613663)
    13707 *487 (MRCItem
    13708 litem &394
     13664*488 (MRCItem
     13665litem &395
    1370913666pos 1
    1371013667dimension 23
    1371113668uid 71,0
    1371213669)
    13713 *488 (MRCItem
    13714 litem &395
     13670*489 (MRCItem
     13671litem &396
    1371513672pos 2
    1371613673hidden 1
     
    1371813675uid 72,0
    1371913676)
    13720 *489 (MRCItem
    13721 litem &405
     13677*490 (MRCItem
     13678litem &406
    1372213679pos 52
    1372313680dimension 20
    1372413681uid 328,0
    1372513682)
    13726 *490 (MRCItem
    13727 litem &406
     13683*491 (MRCItem
     13684litem &407
    1372813685pos 53
    1372913686dimension 20
    1373013687uid 330,0
    1373113688)
    13732 *491 (MRCItem
    13733 litem &407
     13689*492 (MRCItem
     13690litem &408
    1373413691pos 54
    1373513692dimension 20
    1373613693uid 1492,0
    1373713694)
    13738 *492 (MRCItem
    13739 litem &408
     13695*493 (MRCItem
     13696litem &409
    1374013697pos 0
    1374113698dimension 20
    1374213699uid 2436,0
    1374313700)
    13744 *493 (MRCItem
    13745 litem &409
     13701*494 (MRCItem
     13702litem &410
    1374613703pos 55
    1374713704dimension 20
    1374813705uid 2438,0
    1374913706)
    13750 *494 (MRCItem
    13751 litem &410
     13707*495 (MRCItem
     13708litem &411
    1375213709pos 56
    1375313710dimension 20
    1375413711uid 3038,0
    1375513712)
    13756 *495 (MRCItem
    13757 litem &411
     13713*496 (MRCItem
     13714litem &412
    1375813715pos 1
    1375913716dimension 20
    1376013717uid 3040,0
    1376113718)
    13762 *496 (MRCItem
    13763 litem &412
     13719*497 (MRCItem
     13720litem &413
    1376413721pos 2
    1376513722dimension 20
    1376613723uid 3277,0
    1376713724)
    13768 *497 (MRCItem
    13769 litem &413
     13725*498 (MRCItem
     13726litem &414
    1377013727pos 3
    1377113728dimension 20
    1377213729uid 3279,0
    1377313730)
    13774 *498 (MRCItem
    13775 litem &414
     13731*499 (MRCItem
     13732litem &415
    1377613733pos 4
    1377713734dimension 20
    1377813735uid 3281,0
    1377913736)
    13780 *499 (MRCItem
    13781 litem &415
     13737*500 (MRCItem
     13738litem &416
    1378213739pos 57
    1378313740dimension 20
    1378413741uid 3283,0
    1378513742)
    13786 *500 (MRCItem
    13787 litem &416
     13743*501 (MRCItem
     13744litem &417
    1378813745pos 5
    1378913746dimension 20
    1379013747uid 3383,0
    1379113748)
    13792 *501 (MRCItem
    13793 litem &417
     13749*502 (MRCItem
     13750litem &418
    1379413751pos 6
    1379513752dimension 20
    1379613753uid 3385,0
    1379713754)
    13798 *502 (MRCItem
    13799 litem &418
     13755*503 (MRCItem
     13756litem &419
    1380013757pos 7
    1380113758dimension 20
    1380213759uid 3387,0
    1380313760)
    13804 *503 (MRCItem
    13805 litem &419
     13761*504 (MRCItem
     13762litem &420
    1380613763pos 8
    1380713764dimension 20
    1380813765uid 3389,0
    1380913766)
    13810 *504 (MRCItem
    13811 litem &420
     13767*505 (MRCItem
     13768litem &421
    1381213769pos 9
    1381313770dimension 20
    1381413771uid 3391,0
    1381513772)
    13816 *505 (MRCItem
    13817 litem &421
     13773*506 (MRCItem
     13774litem &422
    1381813775pos 10
    1381913776dimension 20
    1382013777uid 3393,0
    1382113778)
    13822 *506 (MRCItem
    13823 litem &422
     13779*507 (MRCItem
     13780litem &423
    1382413781pos 11
    1382513782dimension 20
    1382613783uid 3469,0
    1382713784)
    13828 *507 (MRCItem
    13829 litem &423
     13785*508 (MRCItem
     13786litem &424
    1383013787pos 12
    1383113788dimension 20
    1383213789uid 3471,0
    1383313790)
    13834 *508 (MRCItem
    13835 litem &424
     13791*509 (MRCItem
     13792litem &425
    1383613793pos 13
    1383713794dimension 20
    1383813795uid 3473,0
    1383913796)
    13840 *509 (MRCItem
    13841 litem &425
     13797*510 (MRCItem
     13798litem &426
    1384213799pos 14
    1384313800dimension 20
    1384413801uid 3475,0
    1384513802)
    13846 *510 (MRCItem
    13847 litem &426
     13803*511 (MRCItem
     13804litem &427
    1384813805pos 15
    1384913806dimension 20
    1385013807uid 3525,0
    1385113808)
    13852 *511 (MRCItem
    13853 litem &427
     13809*512 (MRCItem
     13810litem &428
    1385413811pos 16
    1385513812dimension 20
    1385613813uid 3527,0
    1385713814)
    13858 *512 (MRCItem
    13859 litem &428
     13815*513 (MRCItem
     13816litem &429
    1386013817pos 17
    1386113818dimension 20
    1386213819uid 3529,0
    1386313820)
    13864 *513 (MRCItem
    13865 litem &429
     13821*514 (MRCItem
     13822litem &430
    1386613823pos 18
    1386713824dimension 20
    1386813825uid 3531,0
    1386913826)
    13870 *514 (MRCItem
    13871 litem &430
     13827*515 (MRCItem
     13828litem &431
    1387213829pos 19
    1387313830dimension 20
    1387413831uid 3533,0
    1387513832)
    13876 *515 (MRCItem
    13877 litem &431
     13833*516 (MRCItem
     13834litem &432
    1387813835pos 20
    1387913836dimension 20
    1388013837uid 3535,0
    1388113838)
    13882 *516 (MRCItem
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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak

    r10075 r10081  
    149149(vvPair
    150150variable "date"
    151 value "04.01.2011"
     151value "05.01.2011"
    152152)
    153153(vvPair
    154154variable "day"
    155 value "Di"
     155value "Mi"
    156156)
    157157(vvPair
    158158variable "day_long"
    159 value "Dienstag"
     159value "Mittwoch"
    160160)
    161161(vvPair
    162162variable "dd"
    163 value "04"
     163value "05"
    164164)
    165165(vvPair