Changeset 10366 for firmware/FTM

Timestamp:

04/13/11 15:02:49 (14 years ago)

Author:

weitzel

Message:

FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module

Location:

firmware/FTM

Files:

• FTM_central_control.vhd (modified) (5 diffs)
• FTM_top.vhd (modified) (16 diffs)
• FTM_top_tb.vhd (modified) (8 diffs)
• clock/FTM_clk_gen_2.vhd (added)
• clock/FTM_dcm_40M_to_50M_2.vhd (added)
• clock/FTM_dcm_40M_to_50M_2.xaw (added)
• clock/FTM_dcm_40M_to_50M_2_arwz.ucf (added)
• clock/FTM_dcm_50M_to_250M_2.vhd (added)
• clock/FTM_dcm_50M_to_250M_2.xaw (added)
• clock/FTM_dcm_50M_to_250M_2_arwz.ucf (added)
• ethernet/cram_control_beha.vhd (modified) (3 diffs)
• ethernet/ethernet_modul_beha.vhd (modified) (9 diffs)
• ethernet/header_modul_beha.vhd (modified) (5 diffs)
• ethernet/w5300_modul.vhd (modified) (27 diffs)
• ftm_board.ucf (modified) (4 diffs)
• ftm_definitions.vhd (modified) (8 diffs)
• trigger (added)
• trigger/assembler (added)
• trigger/assembler/FTU_trigger_generator (added)
• trigger/assembler/FTU_trigger_generator/FTU_trigger_counter.vhd (added)
• trigger/drivers (added)
• trigger/drivers/calibration_pedestal (added)
• trigger/drivers/calibration_pedestal/calibration_pedestal.vhd (added)
• trigger/drivers/deadtime_generator (added)
• trigger/drivers/deadtime_generator/deadtime_generator.vhd (added)
• trigger/drivers/detection_logic (added)
• trigger/drivers/detection_logic/adder_3_bits.ngc (added)
• trigger/drivers/detection_logic/adder_3_bits.vhd (added)
• trigger/drivers/detection_logic/adder_4_bits.ngc (added)
• trigger/drivers/detection_logic/adder_4_bits.vhd (added)
• trigger/drivers/detection_logic/adder_5_bits.ngc (added)
• trigger/drivers/detection_logic/adder_5_bits.vhd (added)
• trigger/drivers/detection_logic/trigger_sum.vhd (added)
• trigger/drivers/detection_logic/unary_to_binary.vhd (added)
• trigger/drivers/input_synch (added)
• trigger/drivers/input_synch/input_synch.vhd (added)
• trigger/drivers/interface_sync (added)
• trigger/drivers/interface_sync/interface_sync_250MHz.vhd (added)
• trigger/drivers/interface_sync/interface_sync_50MHz.vhd (added)
• trigger/drivers/time_window (added)
• trigger/drivers/time_window/time_counter.vhd (added)
• trigger/drivers/time_window/time_window.vhd (added)
• trigger/drivers/trigger_count_ID (added)
• trigger/drivers/trigger_count_ID/trigger_ID_count.vhd (added)
• trigger/drivers/trigger_delayed_pulse (added)
• trigger/drivers/trigger_delayed_pulse/delayed_pulse.vhd (added)
• trigger/ftm_trigger (added)
• trigger/ftm_trigger/trigger_manager.vhd (added)
• trigger/kernel (added)
• trigger/kernel/trigger_generator (added)
• trigger/kernel/trigger_generator/trigger_generator.vhd (added)
• trigger/readme.txt (added)

firmware/FTM/FTM_central_control.vhd

@@ -35 +35 @@
   port(
     clk                  : IN  std_logic;
+    clk_ready            : in  std_logic;
     clk_scaler           : IN  std_logic;
     new_config           : IN  std_logic;
@@ -60 +61 @@
     config_start_cc      : out std_logic := '0';
     config_started_cc    : in  std_logic;
-    config_ready_cc      : in  std_logic
+    config_ready_cc      : in  std_logic;
+    config_trigger       : out  std_logic := '0';
+    config_trigger_done  : in  std_logic
   );
 end FTM_central_control;
@@ -82 +85 @@
                                    CP_CONFIG_FTU, CP_CONFIG_FTU_01,
                                    CP_CONFIG_SCALER, CP_CONFIG_SCALER_01,
+                                   CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01,
                                    CP_IDLE, CP_PING, CP_READ_RATES, CP_READ_RATES_01,
                                    CP_SEND_START, CP_SEND_END);
@@ -94 +98 @@
 
         when CP_INIT =>
-          state_central_proc <= CP_CONFIG;
-          
+          if (clk_ready = '1') then
+            state_central_proc <= CP_CONFIG;
+          end if;
+            
         when CP_CONFIG_START =>
           if (config_started_ack = '1') then
@@ -154 +160 @@
             wait_cnt_sig <= 0;
             reset_scaler_sig <= '0';
+            state_central_proc <= CP_CONFIG_TRIGGER;
+          end if;
+
+        when CP_CONFIG_TRIGGER =>
+          --config trigger_manager block
+          config_trigger <= '1';
+          state_central_proc <= CP_CONFIG_TRIGGER_01;
+
+        when CP_CONFIG_TRIGGER_01 =>
+          config_trigger <= '0';
+          if (config_trigger_done = '1') then
             state_central_proc <= CP_IDLE;
           end if;

firmware/FTM/FTM_top.vhd

@@ -89 +89 @@
     -- on IO-Bank 2
     -------------------------------------------------------------------------------
-    -- Trig_Prim_A  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 0
-    -- Trig_Prim_B  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 1
-    -- Trig_Prim_C  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 2
-    -- Trig_Prim_D  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 3
+    Trig_Prim_A  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 0
+    Trig_Prim_B  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 1
+    Trig_Prim_C  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 2
+    Trig_Prim_D  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 3
 
   
@@ -98 +98 @@
     ------------------------------------------------------------------------------
     -- on IO-Bank 3  
-    -- ext_Trig  : in  STD_LOGIC_VECTOR(2 downto 1);      -- external trigger input
-    -- Veto      : in  STD_LOGIC;                         -- trigger veto input
+    ext_Trig  : in  STD_LOGIC_VECTOR(2 downto 1);      -- external trigger input
+    Veto      : in  STD_LOGIC;                         -- trigger veto input
     -- NIM_In    : in  STD_LOGIC_VECTOR(2 downto 0);      -- auxiliary inputs
 
@@ -186 +186 @@
     -- on IO-Bank 3
     -------------------------------------------------------------------------------
-    -- Busy0     : in STD_LOGIC;
-    -- Busy1     : in STD_LOGIC;
-    -- Busy2     : in STD_LOGIC;
-    -- Busy3     : in STD_LOGIC;
+    Busy0     : in STD_LOGIC;
+    Busy1     : in STD_LOGIC;
+    Busy2     : in STD_LOGIC;
+    Busy3     : in STD_LOGIC;
 
 
@@ -215 +215 @@
     -- RES_n      : out STD_LOGIC;   --  RES-  IO-Bank 0
 
-    -- TRG_p      : out STD_LOGIC;   -- TRG+  Trigger
-    -- TRG_n      : out STD_LOGIC;   -- TRG-  IO-Bank 0
-
-    -- TIM_Run_p  : out STD_LOGIC;   -- TIM_Run+  Time Marker
-    -- TIM_Run_n  : out STD_LOGIC;   -- TIM_Run-  IO-Bank 2
+    TRG_p      : out STD_LOGIC;   -- TRG+  Trigger
+    TRG_n      : out STD_LOGIC;   -- TRG-  IO-Bank 0
+
+    TIM_Run_p  : out STD_LOGIC;   -- TIM_Run+  Time Marker
+    TIM_Run_n  : out STD_LOGIC;   -- TIM_Run-  IO-Bank 2
     TIM_Sel    : out STD_LOGIC   -- Time Marker selector on IO-Bank 2
                                                     
@@ -336 +336 @@
   signal dd_send_ack_sig            : std_logic := '1';
   signal dd_send_ready_sig          : std_logic := '1';
+  --very new stuff
+  SIGNAL ftu_error_send_ack_sig     : std_logic                      := '1';
+  SIGNAL ftu_error_send_ready_sig   : std_logic                      := '1';
+  SIGNAL ftu_error_calls_sig        : std_logic_vector(15 DOWNTO 0)  := X"0000";
+  SIGNAL ftu_error_data_sig         : std_logic_vector(223 DOWNTO 0) := (others => '0');
+  SIGNAL ftu_error_send_sig         : std_logic                      := '0';
+  signal prescaling_FTU01_sig       : std_logic_vector (15 DOWNTO 0);
+  signal trigger_counter_sig        : std_logic_vector (31 DOWNTO 0);
+  signal trigger_counter_read_sig   : std_logic;
+  signal trigger_counter_valid_sig  : std_logic;
+  
   signal config_start_cc_sig   : std_logic := '0';
   signal config_started_cc_sig : std_logic := '0';
   signal config_ready_cc_sig   : std_logic := '0';
+
+  signal config_trigger_sig : std_logic;
+  signal config_trigger_done_sig : std_logic;
   
   signal clk_buf_sig     : std_logic;
@@ -349 +363 @@
   signal reset_sig : STD_LOGIC := '0';  -- initialize to 0 on power-up
 
+  signal trigger_signal_sig : std_logic := '0';
+  signal TIM_signal_sig : std_logic := '0';
+  
   signal led_sig : std_logic_vector(7 downto 0) := (others => '0');
   
-  component FTM_clk_gen
+--  component FTM_clk_gen
+--    port(
+--      clk        : IN  STD_LOGIC;
+--      rst        : IN  STD_LOGIC;
+--      clk_1      : OUT STD_LOGIC;
+--      clk_50     : OUT STD_LOGIC;
+--      clk_250    : OUT STD_LOGIC;
+--      clk_250_ps : OUT STD_LOGIC;
+--      ready      : OUT STD_LOGIC
+--    );
+--  end component;
+
+  component FTM_clk_gen_2
     port(
       clk        : IN  STD_LOGIC;
@@ -362 +391 @@
     );
   end component;
-
+  
+  component trigger_manager
+    port(
+      --clocks
+      clk_50MHz           : in  std_logic;
+      clk_250MHz          : in  std_logic;
+      clk_250MHz_180      : in  std_logic;
+      --trigger primitives from FTUs
+      trig_prim_0         : in  std_logic_vector(9 downto 0);  --crate 0
+      trig_prim_1         : in  std_logic_vector(9 downto 0);  --crate 1
+      trig_prim_2         : in  std_logic_vector(9 downto 0);  --crate 2
+      trig_prim_3         : in  std_logic_vector(9 downto 0);  --crate 3
+      --external signals
+      ext_trig_1          : in  std_logic;
+      ext_trig_2          : in  std_logic;
+      ext_veto            : in  std_logic;
+      FAD_busy_0          : in  std_logic;  --crate 0
+      FAD_busy_1          : in  std_logic;  --crate 1
+      FAD_busy_2          : in  std_logic;  --crate 2
+      FAD_busy_3          : in  std_logic;  --crate 3
+      --control signals from e.g. main control
+      start_run           : in  std_logic;  --enable trigger output
+      stop_run            : in  std_logic;  --disable trigger output
+      new_config          : in  std_logic;
+      --settings register (see FTM Firmware Specifications)
+      general_settings    : in  std_logic_vector(15 downto 0);
+      LP_and_PED_freq     : in  std_logic_vector(15 downto 0);
+      LP1_LP2_PED_ratio   : in  std_logic_vector(15 downto 0);
+      maj_coinc_n_phys    : in  std_logic_vector(15 downto 0);
+      maj_coinc_n_calib   : in  std_logic_vector(15 downto 0);
+      trigger_delay       : in  std_logic_vector(15 downto 0);
+      TIM_delay           : in  std_logic_vector(15 downto 0);
+      dead_time           : in  std_logic_vector(15 downto 0);
+      coinc_window_phys   : in  std_logic_vector(15 downto 0);
+      coinc_window_calib  : in  std_logic_vector(15 downto 0);
+      active_FTU_list_0   : in  std_logic_vector(15 downto 0);
+      active_FTU_list_1   : in  std_logic_vector(15 downto 0);
+      active_FTU_list_2   : in  std_logic_vector(15 downto 0);
+      active_FTU_list_3   : in  std_logic_vector(15 downto 0);
+      --control signals or information for other entities
+      trigger_ID_read     : in  std_logic;
+      trig_cnt_copy_read  : in  std_logic;
+      trigger_ID_ready    : out std_logic;
+      trigger_ID          : out std_logic_vector(55 downto 0);
+      trig_cnt_copy       : out std_logic_vector(31 downto 0);  --counter reading
+      trig_cnt_copy_valid : out std_logic;  --trigger counter reading is valid
+      trigger_active      : out std_logic;  --phys triggers are enabled/active
+      config_done         : out std_logic;
+      LP1_pulse           : out std_logic;  --send start signal to light pulser 1
+      LP2_pulse           : out std_logic;  --send start signal to light pulser 2
+      --trigger and time marker output signals to FADs
+      trigger_signal      : out std_logic;
+      TIM_signal          : out std_logic
+    );
+  end component;
+  
   component Clock_cond_interface is
     port(
@@ -390 +474 @@
     port(
       clk                  : IN  std_logic;
+      clk_ready            : in  std_logic;
       clk_scaler           : IN  std_logic;
       new_config           : IN  std_logic;
@@ -415 +500 @@
       config_start_cc      : out std_logic := '0';
       config_started_cc    : in  std_logic;
-      config_ready_cc      : in  std_logic
+      config_ready_cc      : in  std_logic;
+      config_trigger       : out std_logic;
+      config_trigger_done  : in  std_logic
     );
   end component;
@@ -536 +623 @@
       dd_send                : IN     std_logic;
       dd_send_ack            : OUT    std_logic                      := '1';
-      dd_send_ready          : OUT    std_logic                      := '1'
+      dd_send_ready          : OUT    std_logic                      := '1';
+      --very new stuff
+      ftu_error_calls        : IN     std_logic_vector (15 DOWNTO 0);
+      ftu_error_data         : IN     std_logic_vector (223 DOWNTO 0);  -- (28 * 8) - 1
+      ftu_error_send         : IN     std_logic;
+      ftu_error_send_ack     : OUT    std_logic                      := '1';
+      ftu_error_send_ready   : OUT    std_logic                      := '1';
+      prescaling_FTU01       : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
+      trigger_counter        : IN     std_logic_vector (31 DOWNTO 0) := (others => '0');
+      trigger_counter_read   : OUT    std_logic                      := '0';
+      trigger_counter_valid  : IN     std_logic
     );
   end component;
@@ -542 +639 @@
 begin
 
-  -- IBUFG: Single-ended global clock input buffer
-  --        Spartan-3A
-  -- Xilinx HDL Language Template, version 11.4
-  
-   IBUFG_inst : IBUFG
-   generic map (
-      IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, 
-                               -- "0"-"16" 
-      IOSTANDARD => "DEFAULT")
-   port map (
-      O => clk_buf_sig, -- Clock buffer output
-      I => clk      -- Clock buffer input (connect directly to top-level port)
-   );
-  
-  Inst_FTM_clk_gen : FTM_clk_gen
+--  -- IBUFG: Single-ended global clock input buffer
+--  --        Spartan-3A
+--  -- Xilinx HDL Language Template, version 11.4
+  
+--   IBUFG_inst : IBUFG
+--   generic map (
+--      IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, 
+--                               -- "0"-"16" 
+--      IOSTANDARD => "DEFAULT")
+--   port map (
+--      O => clk_buf_sig, -- Clock buffer output
+--      I => clk      -- Clock buffer input (connect directly to top-level port)
+--   );
+  
+--  Inst_FTM_clk_gen : FTM_clk_gen
+--    port map(
+--      clk        => clk_buf_sig,
+--      rst        => reset_sig,
+--      clk_1      => clk_1M_sig,
+--      clk_50     => clk_50M_sig,
+--      clk_250    => clk_250M_sig,
+--      clk_250_ps => clk_250M_ps_sig,
+--      ready      => clk_ready_sig
+--    );
+
+  Inst_FTM_clk_gen_2 : FTM_clk_gen_2
     port map(
-      clk        => clk_buf_sig,
+      clk        => clk,
       rst        => reset_sig,
       clk_1      => clk_1M_sig,
@@ -566 +674 @@
       ready      => clk_ready_sig
     );
-
+  
+   --differential output buffer for trigger signal
+   OBUFDS_LVDS_33_TRG : OBUFDS_LVDS_33
+     port map(
+       O  => TRG_p,
+       OB => TRG_n,
+       I  => trigger_signal_sig
+     );
+
+   --differential output buffer for trigger signal
+   OBUFDS_LVDS_33_TIM : OBUFDS_LVDS_33
+     port map(
+       O  => TIM_Run_p,
+       OB => TIM_Run_n,
+       I  => TIM_signal_sig
+     );
+   
+   Inst_trigger_manager : trigger_manager
+     port map(
+      --clocks
+      clk_50MHz           => clk_50M_sig,
+      clk_250MHz          => clk_250M_sig,
+      clk_250MHz_180      => clk_250M_ps_sig,
+      --trigger primitives from FTUs
+      trig_prim_0         => Trig_Prim_A,  --crate 0
+      trig_prim_1         => Trig_Prim_B,  --crate 1
+      trig_prim_2         => Trig_Prim_C,  --crate 2
+      trig_prim_3         => Trig_Prim_D,  --crate 3
+      --external signals
+      ext_trig_1          => ext_Trig(1),
+      ext_trig_2          => ext_Trig(2),
+      ext_veto            => Veto,
+      FAD_busy_0          => Busy0,  --crate 0
+      FAD_busy_1          => Busy1,  --crate 1
+      FAD_busy_2          => Busy2,  --crate 2
+      FAD_busy_3          => Busy3,  --crate 3
+      --control signals from e.g. main control
+      start_run           => '1',  --enable trigger output
+      stop_run            => '0',  --disable trigger output
+      new_config          => config_trigger_sig,
+      --settings register (see FTM Firmware Specifications)
+      general_settings    => general_settings_sig,
+      LP_and_PED_freq     => lp_pt_freq_sig,
+      LP1_LP2_PED_ratio   => lp_pt_ratio_sig,
+      maj_coinc_n_phys    => coin_n_p_sig,
+      maj_coinc_n_calib   => coin_n_c_sig,
+      trigger_delay       => trigger_delay_sig,
+      TIM_delay           => timemarker_delay_sig,
+      dead_time           => dead_time_sig,
+      coinc_window_phys   => coin_win_p_sig,
+      coinc_window_calib  => coin_win_c_sig,
+      active_FTU_list_0   => ftu_active_cr0_sig,
+      active_FTU_list_1   => ftu_active_cr1_sig,
+      active_FTU_list_2   => ftu_active_cr2_sig,
+      active_FTU_list_3   => ftu_active_cr3_sig,
+      --control signals or information for other entities
+      trigger_ID_read     => '0',
+      trig_cnt_copy_read  => trigger_counter_read_sig,
+      trigger_ID_ready    => open,
+      trigger_ID          => open,
+      trig_cnt_copy       => trigger_counter_sig,  --counter reading
+      trig_cnt_copy_valid => trigger_counter_valid_sig,  --trigger counter reading is valid
+      trigger_active      => open,  --phys triggers are enabled/active
+      config_done         => config_trigger_done_sig,
+      LP1_pulse           => open,  --send start signal to light pulser 1
+      LP2_pulse           => open,  --send start signal to light pulser 2
+      --trigger and time marker output signals to FADs
+      trigger_signal      => trigger_signal_sig,
+      TIM_signal          => TIM_signal_sig
+    );
+   
   Inst_Clock_cond_interface : Clock_cond_interface
     port map(
@@ -593 +771 @@
     port map(
       clk                  => clk_50M_sig,
+      clk_ready            => clk_ready_sig,
       clk_scaler           => clk_1M_sig,
       new_config           => new_config_sig,
@@ -612 +791 @@
       rates_started_ftu    => rates_ftu_started_sig,
       rates_ready_ftu      => rates_ftu_ready_sig,
-      prescaling_FTU01     => "00010011",
+      prescaling_FTU01     => prescaling_FTU01_sig(7 downto 0),
       dd_send              => dd_send_sig,
       dd_send_ack          => dd_send_ack_sig,
@@ -618 +797 @@
       config_start_cc      => config_start_cc_sig,
       config_started_cc    => config_started_cc_sig,
-      config_ready_cc      => config_ready_cc_sig
+      config_ready_cc      => config_ready_cc_sig,
+      config_trigger       => config_trigger_sig,
+      config_trigger_done  => config_trigger_done_sig
     );
   
@@ -737 +918 @@
       dd_send                => dd_send_sig,
       dd_send_ack            => dd_send_ack_sig,
-      dd_send_ready          => dd_send_ready_sig
+      dd_send_ready          => dd_send_ready_sig,
+      --very new stuff
+      ftu_error_calls        => ftu_error_calls_sig,
+      ftu_error_data         => ftu_error_data_sig,
+      ftu_error_send         => ftu_error_send_sig,
+      ftu_error_send_ack     => ftu_error_send_ack_sig,
+      ftu_error_send_ready   => ftu_error_send_ready_sig,
+      prescaling_FTU01       => prescaling_FTU01_sig,
+      trigger_counter        => trigger_counter_sig,  
+      trigger_counter_read   => trigger_counter_read_sig,
+      trigger_counter_valid  => trigger_counter_valid_sig
     );
 

firmware/FTM/FTM_top_tb.vhd

@@ -92 +92 @@
       -- Trigger primitives inputs
       -------------------------------------------------------------------------------
-      -- Trig_Prim_A  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 0
-      -- Trig_Prim_B  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 1
-      -- Trig_Prim_C  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 2
-      -- Trig_Prim_D  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 3
+      Trig_Prim_A  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 0
+      Trig_Prim_B  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 1
+      Trig_Prim_C  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 2
+      Trig_Prim_D  : in STD_LOGIC_VECTOR(9 downto 0);  -- crate 3
 
   
       -- NIM inputs
       ------------------------------------------------------------------------------
-      -- ext_Trig  : in  STD_LOGIC_VECTOR(2 downto 1);      -- external trigger input
-      -- Veto      : in  STD_LOGIC;                         -- trigger veto input
+      ext_Trig  : in  STD_LOGIC_VECTOR(2 downto 1);      -- external trigger input
+      Veto      : in  STD_LOGIC;                         -- trigger veto input
       -- NIM_In    : in  STD_LOGIC_VECTOR(2 downto 0);      -- auxiliary inputs
 
@@ -141 +141 @@
 
       Bus1_RxD_3    : in STD_LOGIC;   -- crate 3
-      Bus1_TxD_3    : out STD_LOGIC
+      Bus1_TxD_3    : out STD_LOGIC;
 
 
@@ -183 +183 @@
       -- Busy signals from the FAD boards
       -------------------------------------------------------------------------------
---      Busy0     : in STD_LOGIC;
---      Busy1     : in STD_LOGIC;
---      Busy2     : in STD_LOGIC;
---      Busy3     : in STD_LOGIC;
+      Busy0     : in STD_LOGIC;
+      Busy1     : in STD_LOGIC;
+      Busy2     : in STD_LOGIC;
+      Busy3     : in STD_LOGIC;
 
 
@@ -211 +211 @@
 --      RES_n      : out STD_LOGIC;   --  RES-
 
---      TRG_p      : out STD_LOGIC;   -- TRG+  Trigger
---      TRG_n      : out STD_LOGIC;   -- TRG-
-
---      TIM_Run_p  : out STD_LOGIC;   -- TIM_Run+  Time Marker
---      TIM_Run_n  : out STD_LOGIC;   -- TIM_Run-
+      TRG_p      : out STD_LOGIC;   -- TRG+  Trigger
+      TRG_n      : out STD_LOGIC;   -- TRG-
+
+      TIM_Run_p  : out STD_LOGIC;   -- TIM_Run+  Time Marker
+      TIM_Run_n  : out STD_LOGIC   -- TIM_Run-
 --      TIM_Sel    : out STD_LOGIC;   -- Time Marker selector
                                                     
@@ -368 +368 @@
 --      SIO           => SIO_sig,
 --      TS_CS         => TS_CS_sig,
---      Trig_Prim_A   => Trig_Prim_A_sig,
---      Trig_Prim_B   => Trig_Prim_B_sig,
---      Trig_Prim_C   => Trig_Prim_C_sig,
---      Trig_Prim_D   => Trig_Prim_D_sig,
---      ext_Trig      => ext_Trig_sig,
---      Veto          => Veto_sig, 
+      Trig_Prim_A   => Trig_Prim_A_sig,
+      Trig_Prim_B   => Trig_Prim_B_sig,
+      Trig_Prim_C   => Trig_Prim_C_sig,
+      Trig_Prim_D   => Trig_Prim_D_sig,
+      ext_Trig      => ext_Trig_sig,
+      Veto          => Veto_sig, 
 --      NIM_In        => NIM_In_sig, 
 --      NIM_In3_GCLK  => NIM_In3_GCLK_sig, 
@@ -393 +393 @@
       Bus1_TxD_2    => Bus1_TxD_2_sig,
       Bus1_RxD_3    => Bus1_RxD_3_sig,
-      Bus1_TxD_3    => Bus1_TxD_3_sig  
+      Bus1_TxD_3    => Bus1_TxD_3_sig,  
 --      Bus2_Tx_En    => Bus2_Tx_En_sig,                               
 --      Bus2_Rx_En    => Bus2_Rx_En_sig,
@@ -408 +408 @@
 --      Crate_Res2    => Crate_Res2_sig,
 --      Crate_Res3    => Crate_Res3_sig,
---      Busy0         => Busy0_sig,
---      Busy1         => Busy1_sig,
---      Busy2         => Busy2_sig,
---      Busy3         => Busy3_sig,
+      Busy0         => Busy0_sig,
+      Busy1         => Busy1_sig,
+      Busy2         => Busy2_sig,
+      Busy3         => Busy3_sig,
 --      RES_p         => RES_p_sig,
 --      RES_n         => RES_n_sig,
---      TRG_p         => TRG_p_sig,
---      TRG_n         => TRG_n_sig,
---      TIM_Run_p     => TIM_Run_p_sig,
---      TIM_Run_n     => TIM_Run_n_sig,
+      TRG_p         => TRG_p_sig,
+      TRG_n         => TRG_n_sig,
+      TIM_Run_p     => TIM_Run_p_sig,
+      TIM_Run_n     => TIM_Run_n_sig
 --      TIM_Sel       => TIM_Sel_sig,
 --      Cal_0_p       => Cal_0_p_sig,  
@@ -446 +446 @@
   end process clk_proc;
 
+  -- Stimulus process for busy signals
+  busy_proc: process
+  begin
+    wait for 500us;
+    Busy0_sig <= '1';
+    wait for 100us;
+    Busy0_sig <= '0';
+    wait for 1ms;
+    Busy0_sig <= '1';
+    wait for 500us;
+    Busy0_sig <= '0';
+    wait;
+  end process busy_proc;
+    
+  -- Stimulus process for trigger
+  trigger_proc: process
+  begin
+    ---------------------------------------------------------------------------
+    -- FTUs not yet initialized
+    ---------------------------------------------------------------------------
+    wait for 10us;
+    Trig_Prim_A_sig(0) <= '1';
+    wait for 100ns;
+    Trig_Prim_A_sig(0) <= '0';
+    wait for 99us;
+    Trig_Prim_B_sig(0) <= '1';
+    wait for 100ns;
+    Trig_Prim_B_sig(0) <= '0';
+    wait for 1us;
+    Trig_Prim_B_sig(0) <= '1';
+    wait for 100ns;
+    Trig_Prim_B_sig(0) <= '0';
+    ---------------------------------------------------------------------------
+    -- now FTUs are initialized
+    ---------------------------------------------------------------------------
+    wait for 2200us;
+    Trig_Prim_A_sig(0) <= '1';
+    Trig_Prim_B_sig(0) <= '1';
+    wait for 100ns;
+    Trig_Prim_A_sig(0) <= '0';
+    Trig_Prim_B_sig(0) <= '0';
+    wait for 4us;
+    Trig_Prim_A_sig(0) <= '1';
+    wait for 100ns;
+    Trig_Prim_A_sig(0) <= '0';
+    wait for 22us;
+    Trig_Prim_B_sig(0) <= '1';
+    wait for 100ns;
+    Trig_Prim_B_sig(0) <= '0';
+    wait;
+  end process trigger_proc;
+  
   -- Stimulus process for RS485 of crate 0 
   rs485_0_proc: process

firmware/FTM/ethernet/cram_control_beha.vhd

@@ -65 +65 @@
     coin_win_p       : OUT std_logic_vector (15 downto 0) := (others => '0');
     coin_win_c       : OUT std_logic_vector (15 downto 0) := (others => '0');
+    prescaling_FTU01 : OUT std_logic_vector (15 downto 0) := (others => '0');
     ftu_active_cr0   : OUT std_logic_vector (15 downto 0) := (others => '0');
     ftu_active_cr1   : OUT std_logic_vector (15 downto 0) := (others => '0');
@@ -162 +163 @@
         when CR_CONFIG_START =>
           if (addr_cnt < SD_BLOCK_SIZE) then
-            if ((addr_cnt < SD_FTU_BASE_ADDR) OR (addr_cnt >= SD_FTU_ACTIVE_BASE_ADDR)) then
+            if ((addr_cnt < SD_FTU_BASE_ADDR)
+                OR (addr_cnt = SD_ADDR_ftu_prescaling_0)
+                OR (addr_cnt >= SD_FTU_ACTIVE_BASE_ADDR)
+                ) then
               local_sd_addr <= addr_cnt;
               next_state <= CR_CONFIG_01;
               state_cram_proc <= CR_READ_START;
             elsif (addr_cnt = SD_FTU_BASE_ADDR) then
+              addr_cnt <= SD_ADDR_ftu_prescaling_0;
+            elsif (addr_cnt = (SD_ADDR_ftu_prescaling_0 + 1)) then
               addr_cnt <= SD_FTU_ACTIVE_BASE_ADDR;
             end if;
@@ -242 +248 @@
                           when SD_ADDR_coin_win_c =>
                                 coin_win_c <= local_sd_data;
+              when SD_ADDR_ftu_prescaling_0 =>
+                prescaling_FTU01 <= local_sd_data;            
               when SD_ADDR_ftu_active_cr0 =>
                 ftu_active_cr0 <= local_sd_data;

firmware/FTM/ethernet/ethernet_modul_beha.vhd

@@ -2 +2 @@
 --
 -- Created:
---          by - kai.UNKNOWN (E5PCXX)
---          at - 11:52:19 03.03.2011
+--          by - kai.users (tpkw.local.priv)
+--          at - 10:39:41 04/13/11
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
 --
-
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
@@ -16 +15 @@
 USE ftm_definitions.ftm_constants.all;
 
+
 ENTITY ethernet_modul IS
-  PORT( 
-    wiz_reset              : OUT    std_logic                      := '1';
-    wiz_addr               : OUT    std_logic_vector (9 DOWNTO 0);
-    wiz_data               : INOUT  std_logic_vector (15 DOWNTO 0);
-    wiz_cs                 : OUT    std_logic                      := '1';
-    wiz_wr                 : OUT    std_logic                      := '1';
-    wiz_rd                 : OUT    std_logic                      := '1';
-    wiz_int                : IN     std_logic;
-    clk                    : IN     std_logic;
-    sd_ready               : OUT    std_logic;
-    sd_busy                : OUT    std_logic;
-    led                    : OUT    std_logic_vector (7 DOWNTO 0);
-    sd_read_ftu            : IN     std_logic;
-    sd_started_ftu         : OUT    std_logic                      := '0';
-    cc_R0                  : OUT    std_logic_vector (31 DOWNTO 0);
-    cc_R1                  : OUT    std_logic_vector (31 DOWNTO 0);
-    cc_R11                 : OUT    std_logic_vector (31 DOWNTO 0);
-    cc_R13                 : OUT    std_logic_vector (31 DOWNTO 0);
-    cc_R14                 : OUT    std_logic_vector (31 DOWNTO 0);
-    cc_R15                 : OUT    std_logic_vector (31 DOWNTO 0);
-    cc_R8                  : OUT    std_logic_vector (31 DOWNTO 0);
-    cc_R9                  : OUT    std_logic_vector (31 DOWNTO 0);
-    coin_n_c               : OUT    std_logic_vector (15 DOWNTO 0);
-    coin_n_p               : OUT    std_logic_vector (15 DOWNTO 0);
-    dead_time              : OUT    std_logic_vector (15 DOWNTO 0);
-    -- data from config ram
-    general_settings       : OUT    std_logic_vector (15 DOWNTO 0);
-    lp1_amplitude          : OUT    std_logic_vector (15 DOWNTO 0);
-    lp1_delay              : OUT    std_logic_vector (15 DOWNTO 0);
-    lp2_amplitude          : OUT    std_logic_vector (15 DOWNTO 0);
-    lp2_delay              : OUT    std_logic_vector (15 DOWNTO 0);
-    lp_pt_freq             : OUT    std_logic_vector (15 DOWNTO 0);
-    lp_pt_ratio            : OUT    std_logic_vector (15 DOWNTO 0);
-    timemarker_delay       : OUT    std_logic_vector (15 DOWNTO 0);
-    trigger_delay          : OUT    std_logic_vector (15 DOWNTO 0);
-    sd_addr_ftu            : IN     std_logic_vector (11 DOWNTO 0);
-    sd_data_out_ftu        : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
-    ftu_active_cr0         : OUT    std_logic_vector (15 DOWNTO 0);
-    ftu_active_cr1         : OUT    std_logic_vector (15 DOWNTO 0);
-    ftu_active_cr2         : OUT    std_logic_vector (15 DOWNTO 0);
-    ftu_active_cr3         : OUT    std_logic_vector (15 DOWNTO 0);
-    new_config             : OUT    std_logic                      := '0';
-    config_started         : IN     std_logic;
-    config_start_eth       : IN     std_logic;
-    config_started_eth     : OUT    std_logic                      := '0';
-    config_ready_eth       : OUT    std_logic                      := '0';
-    config_started_ack     : OUT    std_logic                      := '0';
-    fl_busy                : OUT    std_logic;
-    fl_ready               : OUT    std_logic;
-    fl_write_ftu           : IN     std_logic;
-    fl_started_ftu         : OUT    std_logic                      := '0';
-    fl_addr_ftu            : IN     std_logic_vector (11 DOWNTO 0);
-    fl_data_in_ftu         : IN     std_logic_vector (15 DOWNTO 0) := (others => '0');
-    --
-    ping_ftu_start         : OUT    std_logic                      := '0';
-    ping_ftu_started       : IN     std_logic;
-    ping_ftu_ready         : IN     std_logic;
-    dd_write_ftu           : IN     std_logic;
-    dd_started_ftu         : OUT    std_logic                      := '0';
-    dd_data_in_ftu         : IN     std_logic_vector (15 DOWNTO 0);
-    dd_addr_ftu            : IN     std_logic_vector (11 DOWNTO 0);
-    dd_busy                : OUT    std_logic;
-    dd_ready               : OUT    std_logic;
-    coin_win_c             : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
-    coin_win_p             : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
-    dd_block_ready_ftu     : IN     std_logic;
-    dd_block_start_ack_ftu : OUT    std_logic                      := '0';
-    dd_block_start_ftu     : IN     std_logic;
-    dd_send                : IN     std_logic;
-    dd_send_ack            : OUT    std_logic                      := '1';
-    dd_send_ready          : OUT    std_logic                      := '1'
-  );
+   PORT( 
+      wiz_reset              : OUT    std_logic                      := '1';
+      wiz_addr               : OUT    std_logic_vector (9 DOWNTO 0);
+      wiz_data               : INOUT  std_logic_vector (15 DOWNTO 0);
+      wiz_cs                 : OUT    std_logic                      := '1';
+      wiz_wr                 : OUT    std_logic                      := '1';
+      wiz_rd                 : OUT    std_logic                      := '1';
+      wiz_int                : IN     std_logic;
+      clk                    : IN     std_logic;
+      sd_ready               : OUT    std_logic;
+      sd_busy                : OUT    std_logic;
+      led                    : OUT    std_logic_vector (7 DOWNTO 0);
+      sd_read_ftu            : IN     std_logic;
+      sd_started_ftu         : OUT    std_logic                      := '0';
+      cc_R0                  : OUT    std_logic_vector (31 DOWNTO 0);
+      cc_R1                  : OUT    std_logic_vector (31 DOWNTO 0);
+      cc_R11                 : OUT    std_logic_vector (31 DOWNTO 0);
+      cc_R13                 : OUT    std_logic_vector (31 DOWNTO 0);
+      cc_R14                 : OUT    std_logic_vector (31 DOWNTO 0);
+      cc_R15                 : OUT    std_logic_vector (31 DOWNTO 0);
+      cc_R8                  : OUT    std_logic_vector (31 DOWNTO 0);
+      cc_R9                  : OUT    std_logic_vector (31 DOWNTO 0);
+      coin_n_c               : OUT    std_logic_vector (15 DOWNTO 0);
+      coin_n_p               : OUT    std_logic_vector (15 DOWNTO 0);
+      dead_time              : OUT    std_logic_vector (15 DOWNTO 0);
+      -- data from config ram
+      general_settings       : OUT    std_logic_vector (15 DOWNTO 0);
+      lp1_amplitude          : OUT    std_logic_vector (15 DOWNTO 0);
+      lp1_delay              : OUT    std_logic_vector (15 DOWNTO 0);
+      lp2_amplitude          : OUT    std_logic_vector (15 DOWNTO 0);
+      lp2_delay              : OUT    std_logic_vector (15 DOWNTO 0);
+      lp_pt_freq             : OUT    std_logic_vector (15 DOWNTO 0);
+      lp_pt_ratio            : OUT    std_logic_vector (15 DOWNTO 0);
+      timemarker_delay       : OUT    std_logic_vector (15 DOWNTO 0);
+      trigger_delay          : OUT    std_logic_vector (15 DOWNTO 0);
+      sd_addr_ftu            : IN     std_logic_vector (11 DOWNTO 0);
+      sd_data_out_ftu        : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
+      ftu_active_cr0         : OUT    std_logic_vector (15 DOWNTO 0);
+      ftu_active_cr1         : OUT    std_logic_vector (15 DOWNTO 0);
+      ftu_active_cr2         : OUT    std_logic_vector (15 DOWNTO 0);
+      ftu_active_cr3         : OUT    std_logic_vector (15 DOWNTO 0);
+      new_config             : OUT    std_logic                      := '0';
+      config_started         : IN     std_logic;
+      config_start_eth       : IN     std_logic;
+      config_started_eth     : OUT    std_logic                      := '0';
+      config_ready_eth       : OUT    std_logic                      := '0';
+      config_started_ack     : OUT    std_logic                      := '0';
+      fl_busy                : OUT    std_logic;
+      fl_ready               : OUT    std_logic;
+      fl_write_ftu           : IN     std_logic;
+      fl_started_ftu         : OUT    std_logic                      := '0';
+      fl_addr_ftu            : IN     std_logic_vector (11 DOWNTO 0);
+      fl_data_in_ftu         : IN     std_logic_vector (15 DOWNTO 0) := (others => '0');
+      ping_ftu_start         : OUT    std_logic                      := '0';
+      ping_ftu_started       : IN     std_logic;
+      ping_ftu_ready         : IN     std_logic;
+      dd_write_ftu           : IN     std_logic;
+      dd_started_ftu         : OUT    std_logic                      := '0';
+      dd_data_in_ftu         : IN     std_logic_vector (15 DOWNTO 0);
+      dd_addr_ftu            : IN     std_logic_vector (11 DOWNTO 0);
+      dd_busy                : OUT    std_logic;
+      dd_ready               : OUT    std_logic;
+      coin_win_c             : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
+      coin_win_p             : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
+      dd_block_ready_ftu     : IN     std_logic;
+      dd_block_start_ack_ftu : OUT    std_logic                      := '0';
+      dd_block_start_ftu     : IN     std_logic;
+      dd_send                : IN     std_logic;
+      dd_send_ack            : OUT    std_logic                      := '1';
+      dd_send_ready          : OUT    std_logic                      := '1';
+      ftu_error_calls        : IN     std_logic_vector (15 DOWNTO 0);
+      ftu_error_data         : IN     std_logic_vector (223 DOWNTO 0);                    -- (28 * 8) - 1
+      ftu_error_send         : IN     std_logic;
+      ftu_error_send_ack     : OUT    std_logic                      := '1';
+      ftu_error_send_ready   : OUT    std_logic                      := '1';
+      prescaling_FTU01       : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
+      trigger_counter        : IN     std_logic_vector (31 DOWNTO 0) := (others => '0');
+      trigger_counter_read   : OUT    std_logic                      := '0';
+      trigger_counter_valid  : IN     std_logic
+   );
+
 END ethernet_modul ;
 
@@ -241 +250 @@
       coin_win_p        : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
       coin_win_c        : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
+      prescaling_FTU01  : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
       ftu_active_cr0    : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
       ftu_active_cr1    : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
@@ -328 +338 @@
       get_header_started       : OUT    std_logic                      := '0';
       get_header_ready         : OUT    std_logic                      := '0';
+      trigger_counter_read     : OUT    std_logic                      := '0';
+      trigger_counter_valid    : IN     std_logic ;
+      trigger_counter          : IN     std_logic_vector (31 DOWNTO 0) := (others => '0');
       header_board_id          : OUT    std_logic_vector (63 DOWNTO 0) := (others => '0');
       header_firmware_id       : OUT    std_logic_vector (15 DOWNTO 0) := (others => '0');
@@ -386 +399 @@
       fl_busy                  : IN     std_logic ;
       --
+      ftu_error_send           : IN     std_logic ;
+      ftu_error_send_ack       : OUT    std_logic                      := '1';
+      ftu_error_send_ready     : OUT    std_logic                      := '1';
+      ftu_error_calls          : IN     std_logic_vector (15 DOWNTO 0);
+      ftu_error_data           : IN     std_logic_vector (223 DOWNTO 0);                 -- (28 * 8) - 1
+      --
       get_header               : OUT    std_logic                      := '0';
       get_header_started       : IN     std_logic ;
@@ -395 +414 @@
    );
    END COMPONENT;
-
-   -- Optional embedded configurations
-   -- pragma synthesis_off
-   -- FOR ALL : CRAM_4096_16b USE ENTITY FACT_FTM_lib.CRAM_4096_16b;
-   -- FOR ALL : DRAM_4096_16b USE ENTITY FACT_FTM_lib.DRAM_4096_16b;
-   -- FOR ALL : FRAM_4096_16b USE ENTITY FACT_FTM_lib.FRAM_4096_16b;
-   -- FOR ALL : cram_control USE ENTITY FACT_FTM_lib.cram_control;
-   -- FOR ALL : dd_write_general_modul USE ENTITY FACT_FTM_lib.dd_write_general_modul;
-   -- FOR ALL : dram_control USE ENTITY FACT_FTM_lib.dram_control;
-   -- FOR ALL : eth_config_modul USE ENTITY FACT_FTM_lib.eth_config_modul;
-   -- FOR ALL : fram_control USE ENTITY FACT_FTM_lib.fram_control;
-   -- FOR ALL : header_modul USE ENTITY FACT_FTM_lib.header_modul;
-   -- FOR ALL : w5300_modul USE ENTITY FACT_FTM_lib.w5300_modul;
-   -- pragma synthesis_on
 
 BEGIN
@@ -492 +497 @@
          coin_win_p        => coin_win_p,
          coin_win_c        => coin_win_c,
+         prescaling_FTU01  => prescaling_FTU01,
          ftu_active_cr0    => ftu_active_cr0,
          ftu_active_cr1    => ftu_active_cr1,
@@ -574 +580 @@
          get_header_started       => get_header_started,
          get_header_ready         => get_header_ready,
+         trigger_counter_read     => trigger_counter_read,
+         trigger_counter_valid    => trigger_counter_valid,
+         trigger_counter          => trigger_counter,
          header_board_id          => header_board_id,
          header_firmware_id       => header_firmware_id,
@@ -626 +635 @@
          fl_ready                 => fl_ready_internal,
          fl_busy                  => fl_busy_internal,
+         ftu_error_send           => ftu_error_send,
+         ftu_error_send_ack       => ftu_error_send_ack,
+         ftu_error_send_ready     => ftu_error_send_ready,
+         ftu_error_calls          => ftu_error_calls,
+         ftu_error_data           => ftu_error_data,
          get_header               => get_header,
          get_header_started       => get_header_started,

firmware/FTM/ethernet/header_modul_beha.vhd

@@ -8 +8 @@
 -- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
 --
-
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 USE ieee.std_logic_arith.all;
 USE IEEE.STD_LOGIC_UNSIGNED.all;
--- LIBRARY FACT_FTM_lib;
--- USE FACT_FTM_lib.ftm_array_types.all;
--- USE FACT_FTM_lib.ftm_constants.all;
+--LIBRARY FACT_FTM_lib;
+--USE FACT_FTM_lib.ftm_array_types.all;
+--USE FACT_FTM_lib.ftm_constants.all;
 library ftm_definitions;
 USE ftm_definitions.ftm_array_types.all;
@@ -26 +25 @@
   get_header_started        : OUT std_logic := '0';
   get_header_ready          : OUT std_logic := '0';
+  trigger_counter_read      : OUT std_logic := '0';
+  trigger_counter_valid     : IN std_logic;
+  trigger_counter           : IN  std_logic_vector (31 DOWNTO 0) := (others => '0');
   header_board_id           : OUT std_logic_vector (63 DOWNTO 0) := (others => '0');
   header_firmware_id        : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
@@ -36 +38 @@
 ARCHITECTURE beha OF header_modul IS
 
-  type state_header_proc_type is (HP_INIT, HP_CONFIG, HP_IDLE, HP_START, HP_END);
+  type state_header_proc_type is (HP_INIT, HP_CONFIG, HP_IDLE, HP_START, HP_TRG_CNT, HP_END);
   
   signal state_header_proc : state_header_proc_type := HP_INIT;
@@ -62 +64 @@
         header_board_id <= to_stdlogicvector (DNA_FOR_SIM);
         header_firmware_id <= X"00" & FIRMWARE_ID;
-        header_trigger_counter <= X"22221111";
         header_timestamp_counter <= X"333322221111";
-        state_header_proc <= HP_END;
+        
+        trigger_counter_read <= '1';
+        state_header_proc <= HP_TRG_CNT;
+        
+      when HP_TRG_CNT =>
+        trigger_counter_read <= '0';
+        if (trigger_counter_valid = '1') then
+          header_trigger_counter <= trigger_counter;
+          state_header_proc <= HP_END;
+        end if;
         
       when HP_END =>
@@ -78 +88 @@
 
 END ARCHITECTURE beha;
+

firmware/FTM/ethernet/w5300_modul.vhd

@@ -23 +23 @@
 USE IEEE.STD_LOGIC_ARITH.all;
 USE IEEE.STD_LOGIC_UNSIGNED.all;
--- LIBRARY FACT_FTM_lib;
--- USE FACT_FTM_lib.ftm_array_types.all;
--- USE FACT_FTM_lib.ftm_constants.all;
+
+--LIBRARY FACT_FTM_lib;
+--USE FACT_FTM_lib.ftm_array_types.all;
+--USE FACT_FTM_lib.ftm_constants.all;
 library ftm_definitions;
 USE ftm_definitions.ftm_array_types.all;
@@ -34 +35 @@
 library UNISIM;
 use UNISIM.VComponents.all;
-
 
 ENTITY w5300_modul IS
@@ -88 +88 @@
     fl_busy        : IN     std_logic;
     --
+    ftu_error_send        : IN  std_logic;
+    ftu_error_send_ack    : OUT std_logic := '1';
+    ftu_error_send_ready  : OUT std_logic := '1';
+    ftu_error_calls       : IN  std_logic_vector (15 DOWNTO 0);
+    ftu_error_data        : IN  std_logic_vector (223 DOWNTO 0);  -- (28 * 8) - 1
+    --
     get_header                : OUT std_logic := '0';
     get_header_started        : IN  std_logic;
@@ -95 +101 @@
     header_trigger_counter    : IN  std_logic_vector (31 DOWNTO 0);
     header_timestamp_counter  : IN  std_logic_vector (47 DOWNTO 0)
+
   );
 
@@ -103 +110 @@
   type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
                            INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
-                           SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED,
-                           READ_DATA, WRITE_TO_SD_ADDR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL);
+                           SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR,
+                           READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL);
   type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08,
                             WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01); 
@@ -116 +123 @@
   type state_read_dd_type is (READ_DD_START, READ_DD_WAIT, READ_DD_END);
   type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE_GENERAL, READ_DD_BLOCK_WRITE, READ_DD_BLOCK_END, READ_DD_BLOCK_INTERN);
+  type state_send_ftu_error_type is (SFE_START, SFE_END);
 
   signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
@@ -137 +145 @@
   signal state_read_dd                           : state_read_dd_type            := READ_DD_START;
   signal state_read_dd_block                     : state_read_dd_block_type      := READ_DD_BLOCK_START;
+  signal state_send_ftu_error                    : state_send_ftu_error_type     := SFE_START;
 
 
@@ -144 +153 @@
   signal zaehler     : std_logic_vector (19 downto 0) := (others => '0');
   signal data_cnt    : integer                        := 0;
-  signal header_cnt  : integer                        := 0;
+  signal header_cnt  : std_logic_vector (7 DOWNTO 0)  := X"00";
   signal socket_cnt  : std_logic_vector (2 downto 0)  := "000";
 
@@ -164 +173 @@
   signal internal_cmd : std_logic := '0';
 
+  signal autosend_flag : std_logic := '1';
+  
   -- -- --
   signal led_int : std_logic_vector (7 downto 0) := X"00";
@@ -289 +300 @@
               state_read_dd         <= READ_DD_START;
               state_read_dd_block   <= READ_DD_BLOCK_START;
+              state_send_ftu_error  <= SFE_START;
               -- reset output signals 
               new_config <= '0';
@@ -302 +314 @@
               dd_write_general <= '0';
               fl_read <= '0';
+              ftu_error_send_ack <= '1';
+              ftu_error_send_ready <= '1';
               -- set internal signals
               new_config_flag <= '0';
@@ -312 +326 @@
             end if;
 
-                                        -- Init
+          -- Init
           when INIT =>
             par_addr   <= W5300_MR;
@@ -319 +333 @@
             next_state <= IM;
 
-                                        -- Interrupt Mask
+          -- Interrupt Mask
           when IM =>
             par_addr   <= W5300_IMR;
@@ -326 +340 @@
             next_state <= MT;
 
-                                        -- Memory Type
+          -- Memory Type
           when MT =>
             par_addr   <= W5300_MTYPER;
@@ -333 +347 @@
             next_state <= STX;
 
-                                        -- Socket TX Memory Size
+          -- Socket TX Memory Size
           when STX =>
             par_data <= X"4000";        -- 64K TX for socket 0, others 0
@@ -375 +389 @@
             next_state <= MAC;
 
-                                        -- MAC
+          -- MAC
           when MAC =>
             par_addr   <= W5300_SHAR;
@@ -392 +406 @@
             next_state <= GW;
 
-                                        -- Gateway
+          -- Gateway
           when GW =>
             par_addr               <= W5300_GAR;
@@ -406 +420 @@
             next_state             <= SNM;
 
-                                                      -- Subnet Mask
+          -- Subnet Mask
           when SNM =>
             par_addr               <= W5300_SUBR;
@@ -419 +433 @@
             state_init             <= WRITE_REG;
             next_state             <= IP;
-                                                      -- Own IP-Address
+          -- Own IP-Address
           when IP =>
             par_addr               <= W5300_SIPR;
@@ -432 +446 @@
             state_init             <= WRITE_REG;
             next_state             <= SI;
-                                                      -- Socket Init
+          -- Socket Init
           when SI =>
             par_addr   <= W5300_S0_MR + socket_cnt * W5300_S_INC;
@@ -438 +452 @@
             state_init <= WRITE_REG;
             next_state <= SI1;
-                                                      -- Sx Interrupt Mask
+          -- Sx Interrupt Mask
           when SI1 =>
             par_addr   <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
@@ -493 +507 @@
                   dd_send_ack <= '0';
                   dd_send_ready <= '0';
+                  ftu_error_send_ack <= '0';
+                  ftu_error_send_ready <= '0';
                   led_int <= X"00";
                   -- -- --
@@ -538 +554 @@
               dd_send_ack <= '1';
               dd_send_ready <= '0';
-              -- "simulate" command read dynamic data block
-              cmd_array (0) <= CMD_START_DELIMITER;
-              cmd_array (1) <= CMD_READ;
-              cmd_array (2) <= PAR_READ_DD;
-              state_read_data <= RD_CMD_PARSE;
+              if (autosend_flag = '0') then
+                state_read_dd_block <= READ_DD_BLOCK_END;
+              end if;
+              state_read_data <= RD_READ_DD_BLOCK;
               state_init <= READ_DATA;
+            elsif (ftu_error_send = '1') then
+              ftu_error_send_ack <= '1';
+              ftu_error_send_ready <= '0';
+              if (autosend_flag = '0') then
+                state_send_ftu_error <= SFE_END;
+              end if;
+              state_init <= SEND_FTU_ERROR;
             end if;
 
 
+          -- send FTU error message
+          when SEND_FTU_ERROR =>
+            case state_send_ftu_error is
+              when SFE_START =>
+                next_state <= SEND_FTU_ERROR;
+                read_addr_state <= READ_FTU_ERROR;
+                local_sd_addr <= X"000";
+                local_write_length <= "00000" & FTU_ERROR_LENGTH;
+                state_send_ftu_error <=  SFE_END;
+                state_init <= WRITE_DATA;
+              when SFE_END =>
+                if (ftu_error_send = '0') then
+                  ftu_error_send_ack <= '0';
+                  ftu_error_send_ready <= '1';
+                  state_send_ftu_error <= SFE_START;
+                  state_init <= MAIN;
+                end if;
+             end case;
+            
+            
           -- read data from socket 0  
           when READ_DATA =>
@@ -664 +706 @@
                     state_ping <= PING_START;
                     state_read_data <= RD_PING;
+                    
+                  when CMD_AUTOSEND =>
+                    state_read_data <= RD_5;
+                    case cmd_array (2) is
+                      when PAR_AUTOSEND_EA =>
+                        autosend_flag <= '1';
+                      when PAR_AUTOSEND_DA =>
+                        autosend_flag <= '0';
+                      when others =>
+                        null;
+                      end case;
                     
                   when others =>
@@ -791 +844 @@
             end case;  -- state_read_data
             
-
+          
+          -- read FTU errors
+          when READ_FTU_ERROR =>
+            state_init <= next_state;
+            if (data_cnt = 0) then
+              local_sd_data <= ftu_error_calls;
+            else
+              local_sd_data <= X"00" & ftu_error_data (((data_cnt * 8) - 1) DOWNTO ((data_cnt * 8) - 8));
+            end if;
+          
+          
           -- read from header modul
           when READ_FROM_HEADER_MODUL =>
             state_init <= next_state;
             case header_cnt is
-              when 0 =>
+              when X"00" =>
                 local_sd_data <= header_board_id (63 DOWNTO 48);
-              when 1 =>
+              when X"01" =>
                 local_sd_data <= header_board_id (47 DOWNTO 32);
-              when 2 =>
+              when X"02" =>
                 local_sd_data <= header_board_id (31 DOWNTO 16);
-              when 3 =>
+              when X"03" =>
                 local_sd_data <= header_board_id (15 DOWNTO 0);
-              when 4 =>
+              when X"04" =>
                 local_sd_data <= header_firmware_id;
-              when 5 =>
+              when X"05" =>
                 local_sd_data <= header_trigger_counter (31 DOWNTO 16);
-              when 6 =>
+              when X"06" =>
                 local_sd_data <= header_trigger_counter (15 DOWNTO 0);
-              when 7 =>
+              when X"07" =>
                 local_sd_data <= header_timestamp_counter (47 DOWNTO 32);
-              when 8 =>
+              when X"08" =>
                 local_sd_data <= header_timestamp_counter (31 DOWNTO 16);
-              when 9 =>
+              when X"09" =>
                 local_sd_data <= header_timestamp_counter (15 DOWNTO 0);
-              when 10 =>
+              when X"0A" =>
                 local_sd_data <= X"FFFF"; -- spare
               when others =>
@@ -920 +983 @@
                 write_length_bytes <= (FTM_HEADER_LENGTH + local_write_length (15 downto 0)) & '0';  -- shift left (*2)
                 data_cnt           <= 0;
-                header_cnt         <= 0;
+                header_cnt         <= X"00";
                 state_write        <= WR_01;
               -- Check FIFO Size
@@ -1074 +1137 @@
 
 end Behavioral;
-

firmware/FTM/ftm_board.ucf

@@ -98 +98 @@
 # crate 0 
 # crate A
-# NET Trig_Prim_A<0>  LOC  = AC6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>      
-# NET Trig_Prim_A<1>  LOC  = AD6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>
-# NET Trig_Prim_A<2>  LOC  = AF3  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>
-# NET Trig_Prim_A<3>  LOC  = AE4  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>
-# NET Trig_Prim_A<4>  LOC  = AE6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>
-# NET Trig_Prim_A<5>  LOC  = AE7  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>
-# NET Trig_Prim_A<6>  LOC  = AE8  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>
-# NET Trig_Prim_A<7>  LOC  = AC8  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>
-# NET Trig_Prim_A<8>  LOC  = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>
-# NET Trig_Prim_A<9>  LOC  = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>
+NET Trig_Prim_A<0>  LOC  = AC6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>        
+NET Trig_Prim_A<1>  LOC  = AD6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>
+NET Trig_Prim_A<2>  LOC  = AF3  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>
+NET Trig_Prim_A<3>  LOC  = AE4  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>
+NET Trig_Prim_A<4>  LOC  = AE6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>
+NET Trig_Prim_A<5>  LOC  = AE7  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>
+NET Trig_Prim_A<6>  LOC  = AE8  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>
+NET Trig_Prim_A<7>  LOC  = AC8  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>
+NET Trig_Prim_A<8>  LOC  = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>
+NET Trig_Prim_A<9>  LOC  = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>
 
 # crate 1
 # crate B
-# NET Trig_Prim_B<0>  LOC  = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>      
-# NET Trig_Prim_B<1>  LOC  = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>
-# NET Trig_Prim_B<2>  LOC  = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>
-# NET Trig_Prim_B<3>  LOC  = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>
-# NET Trig_Prim_B<4>  LOC  = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>
-# NET Trig_Prim_B<5>  LOC  = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>
-# NET Trig_Prim_B<6>  LOC  = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>
-# NET Trig_Prim_B<7>  LOC  = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>
-# NET Trig_Prim_B<8>  LOC  = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>
-# NET Trig_Prim_B<9>  LOC  = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>
+NET Trig_Prim_B<0>  LOC  = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>        
+NET Trig_Prim_B<1>  LOC  = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>
+NET Trig_Prim_B<2>  LOC  = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>
+NET Trig_Prim_B<3>  LOC  = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>
+NET Trig_Prim_B<4>  LOC  = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>
+NET Trig_Prim_B<5>  LOC  = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>
+NET Trig_Prim_B<6>  LOC  = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>
+NET Trig_Prim_B<7>  LOC  = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>
+NET Trig_Prim_B<8>  LOC  = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>
+NET Trig_Prim_B<9>  LOC  = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>
 
 # crate 2
 # crate C
-# NET Trig_Prim_C<0>  LOC  = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>      
-# NET Trig_Prim_C<1>  LOC  = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>
-# NET Trig_Prim_C<2>  LOC  = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>
-# NET Trig_Prim_C<3>  LOC  = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>
-# NET Trig_Prim_C<4>  LOC  = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>
-# NET Trig_Prim_C<5>  LOC  = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>
-# NET Trig_Prim_C<6>  LOC  = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>
-# NET Trig_Prim_C<7>  LOC  = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>
-# NET Trig_Prim_C<8>  LOC  = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>
-# NET Trig_Prim_C<9>  LOC  = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>
+NET Trig_Prim_C<0>  LOC  = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>        
+NET Trig_Prim_C<1>  LOC  = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>
+NET Trig_Prim_C<2>  LOC  = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>
+NET Trig_Prim_C<3>  LOC  = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>
+NET Trig_Prim_C<4>  LOC  = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>
+NET Trig_Prim_C<5>  LOC  = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>
+NET Trig_Prim_C<6>  LOC  = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>
+NET Trig_Prim_C<7>  LOC  = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>
+NET Trig_Prim_C<8>  LOC  = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>
+NET Trig_Prim_C<9>  LOC  = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>
 
 # crate 3
 # crate D
-# NET Trig_Prim_D<0>  LOC  = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>      
-# NET Trig_Prim_D<1>  LOC  = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>
-# NET Trig_Prim_D<2>  LOC  = AC9  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>
-# NET Trig_Prim_D<3>  LOC  = AB9  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>
-# NET Trig_Prim_D<4>  LOC  = AB7  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>
-# NET Trig_Prim_D<5>  LOC  = AF8  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>
-# NET Trig_Prim_D<6>  LOC  = AF4  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>
-# NET Trig_Prim_D<7>  LOC  = AF5  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>
-# NET Trig_Prim_D<8>  LOC  = AD7  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>
-# NET Trig_Prim_D<9>  LOC  = AE3  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>
+NET Trig_Prim_D<0>  LOC  = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>        
+NET Trig_Prim_D<1>  LOC  = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>
+NET Trig_Prim_D<2>  LOC  = AC9  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>
+NET Trig_Prim_D<3>  LOC  = AB9  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>
+NET Trig_Prim_D<4>  LOC  = AB7  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>
+NET Trig_Prim_D<5>  LOC  = AF8  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>
+NET Trig_Prim_D<6>  LOC  = AF4  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>
+NET Trig_Prim_D<7>  LOC  = AF5  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>
+NET Trig_Prim_D<8>  LOC  = AD7  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>
+NET Trig_Prim_D<9>  LOC  = AE3  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>
 
 
@@ -152 +152 @@
 #######################################################
 # on IO-Bank 3
-# NET ext_Trig<1>  LOC  = B1  | IOSTANDARD=LVCMOS33; #  
-# NET ext_Trig<2>  LOC  = B2  | IOSTANDARD=LVCMOS33; #
-# NET Veto         LOC  = E4  | IOSTANDARD=LVCMOS33; #
+NET ext_Trig<1>  LOC  = B1  | IOSTANDARD=LVCMOS33; #    
+NET ext_Trig<2>  LOC  = B2  | IOSTANDARD=LVCMOS33; #
+NET Veto         LOC  = E4  | IOSTANDARD=LVCMOS33; #
 # NET NIM_In<0>    LOC  = D3  | IOSTANDARD=LVCMOS33; #
 # NET NIM_In<1>    LOC  = F4  | IOSTANDARD=LVCMOS33; #
@@ -260 +260 @@
 # on IO-Bank 3
 #######################################################
-# NET Busy0    LOC  = M4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-# NET Busy1    LOC  = P2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-# NET Busy2    LOC  = R4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-# NET Busy3    LOC  = U1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
+NET Busy0    LOC  = M4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
+NET Busy1    LOC  = P2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
+NET Busy2    LOC  = R4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
+NET Busy3    LOC  = U1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
 
 
@@ -291 +291 @@
 # NET RES_n       LOC  = C15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0
 
-# NET TRG_p       LOC  = B15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger
-# NET TRG_n       LOC  = A15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0
-
-# NET TIM_Run_p   LOC  = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker
-# NET TIM_Run_n   LOC  = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2
+NET TRG_p       LOC  = B15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger
+NET TRG_n       LOC  = A15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0
+
+NET TIM_Run_p   LOC  = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker
+NET TIM_Run_n   LOC  = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2
 
 NET TIM_Sel     LOC  = AD22 | IOSTANDARD=LVCMOS33;  # Time Marker selector IO-Bank 2

firmware/FTM/ftm_definitions.vhd

@@ -29 +29 @@
 -- kw 03.03.: added FTM_HEADER_LENGTH
 --
+-- modified:   Quirin Weitzel, March 14 2011
+-- third merger with library file from dortmund (changes below)
+-- kw 22.03.: added FTU_ERROR_LENGTH
+-- kw 30.03.: added CMD_AUTOSEND, PAR_AUTOSEND_EA, PAR_AUTOSEND_DA
+--
+---kw 11.04.: added SD_ADDR_ftu_prescaling_0
+--
 ----------------------------------------------------------------------------------
 
@@ -72 +79 @@
 use ftm_definitions.ftm_array_types.all;
 use IEEE.NUMERIC_STD.ALL;
+use ieee.math_real.all;
 
 package ftm_constants is
@@ -191 +199 @@
   -- ping all FTUs
   constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs
+  -- turn automatic sending of dd-block and ftu-error-list on or off
+  constant CMD_AUTOSEND : std_logic_vector := X"0020";
+  constant PAR_AUTOSEND_EA : std_logic_vector := X"0001"; -- enable automatic sending
+  constant PAR_AUTOSEND_DA : std_logic_vector := X"0000"; -- disable automatic sending
 
   -- header length of data packages
   constant FTM_HEADER_LENGTH : std_logic_vector (7 DOWNTO 0) := X"0B";
+  
+  -- FTU error message
+  constant FTU_ERROR_LENGTH       : std_logic_vector (11 downto 0) := X"01D"; --(number of unsuccessful calls) + (28 * data) = 29
   
   -- FTU-list parameters
@@ -249 +264 @@
   constant SD_ADDR_coin_win_p       : std_logic_vector := X"01D";
   constant SD_ADDR_coin_win_c       : std_logic_vector := X"01E";
+  constant SD_ADDR_ftu_prescaling_0 : std_logic_vector := X"029";
   constant SD_ADDR_ftu_active_cr0   : std_logic_vector := X"1B0";
   constant SD_ADDR_ftu_active_cr1   : std_logic_vector := X"1B1";
@@ -264 +280 @@
   -- !!! to be defined !!!
   constant sd_block_default_array : sd_block_default_array_type := (
-      X"0000", -- SD_ADDR_general_settings  -- general settings
+      --X"0080", -- SD_ADDR_general_settings  -- general settings
+      X"0060", -- SD_ADDR_general_settings  -- general settings
       X"0000", -- SD_ADDR_led               -- on-board status LEDs
-      X"0002", -- SD_ADDR_lp_pt_freq        -- light pulser and pedestal trigger frequency
-      X"0003", -- SD_ADDR_lp_pt_ratio...    -- ratio between LP1, LP2 and pedestal triggers
+      --X"0400", -- SD_ADDR_lp_pt_freq        -- light pulser and pedestal trigger frequency
+      X"0001", -- SD_ADDR_lp_pt_freq        -- light pulser and pedestal trigger frequency
+      --X"0001", -- SD_ADDR_lp_pt_ratio...    -- ratio between LP1, LP2 and pedestal triggers
+      X"0420", -- SD_ADDR_lp_pt_ratio...    -- ratio between LP1, LP2 and pedestal triggers
       X"0004", -- SD_ADDR_lp1_amplitude     -- light pulser 1 amplitude
       X"0005", -- SD_ADDR_lp2_amplitude     -- light pulser 2 amplitude
       X"0006", -- SD_ADDR_lp1_delay         -- light pulser 1 delay
       X"0007", -- SD_ADDR_lp2_delay         -- light pulser 2 delay
-      X"0008", -- SD_ADDR_coin_n_p          -- majority coincidence n (for physics)
-      X"0009", -- SD_ADDR_coin_n_c          -- majority coincidence n (for calibration)
-      X"000A", -- SD_ADDR_trigger_delay     -- trigger delay
-      X"000B", -- SD_ADDR_timemarker_delay  -- timemarker delay
-      X"000C", -- SD_ADDR_dead_time         -- dead time
+      X"0001", -- SD_ADDR_coin_n_p          -- majority coincidence n (for physics)
+      X"001E", -- SD_ADDR_coin_n_c          -- majority coincidence n (for calibration)
+      X"0000", -- SD_ADDR_trigger_delay     -- trigger delay
+      X"0000", -- SD_ADDR_timemarker_delay  -- timemarker delay
+      --X"0019", -- SD_ADDR_dead_time         -- dead time, 8ns + 4x25ns = 108ns
+      X"0000", -- SD_ADDR_dead_time         -- dead time, 8ns + 4x25ns = 108ns
       X"0003", -- SD_ADDR_cc_R0_HI          -- clock conditioner R0 bits 31...16
       X"8000", -- SD_ADDR_cc_R0_LO          -- clock conditioner R0 bits 15...0
@@ -293 +313 @@
       X"1400", -- SD_ADDR_cc_R15_HI         -- clock conditioner R15 bits 31...16
       X"FA0F", -- SD_ADDR_cc_R15_LO         -- clock conditioner R15 bits 15...0
-      X"001D", -- SD_ADDR_coin_win_p        -- majority coincidence window (for physics)
-      X"001E", -- SD_ADDR_coin_win_c        -- majority coincidence window (for calibration)
+      X"0001", -- SD_ADDR_coin_win_p        -- majority coincidence window (for physics), 8ns + 4x1ns = 12ns
+      X"0001", -- SD_ADDR_coin_win_c        -- majority coincidence window (for calibration), 8ns + 4x1ns = 12ns
       X"001F"  --                           -- Spare
   );
@@ -314 +334 @@
   --default values for active FTU lists
   constant sd_block_default_ftu_active_list : sd_block_default_ftu_active_list_type := (
-    X"0001",
+    X"0000",
     X"0000",
     X"0000",
@@ -325 +345 @@
 
   -- Timing counter
---  constant tc_width : integer := 48;    -- width (number of bits) of timing counter
---  constant zero : unsigned (tc_width - 1 downto 0) := (others => '0');  
-
+  --  constant tc_width : integer := 48;    -- width (number of bits) of timing counter
+  --  constant zero : unsigned (tc_width - 1 downto 0) := (others => '0');  
+
+  --======================================================================================
+  -- Constants for calibration and pedestal triggers generation
+  --======================================================================================
+  constant LOW_SPEED_CLOCK_FREQ   : real          := 50000000.0;
+  constant LOW_SPEED_CLOCK_PERIOD : real          := 1.0/LOW_SPEED_CLOCK_FREQ;
+  constant MS_PERIOD              : real          := 0.001;
+  constant MAX_MS_COUNTER_WIDTH   : integer       := integer(ceil(log2(real(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD))));
+  constant MAX_MS_COUNTER_VAL     : integer       := integer(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD);
+  --======================================================================================
+  
+  --======================================================================================
+  -- Constants for trigger and TIM signals width (8ns+value*4ns)
+  --======================================================================================
+  constant TRIG_SIGNAL_PULSE_WIDTH        : integer range 0 to 15 := 10;
+  constant TIM_SIGNAL_PULSE_WIDTH         : integer range 0 to 15 := 0;
+  --======================================================================================
+  
 end ftm_constants;